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add leon3ft into leon3_soc (and option IS_RADHARD to use leon3 or leon3ft)
pellion -
r524:cca844e6506f JC
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@@ -379,7 +379,7 BEGIN -- beh
379 379 pirq_ms => 6,
380 380 pirq_wfp => 14,
381 381 hindex => 2,
382 top_lfr_version => X"010135") -- aa.bb.cc version
382 top_lfr_version => X"010138") -- aa.bb.cc version
383 383 -- AA : BOARD NUMBER
384 384 -- 0 => MINI_LFR
385 385 -- 1 => EM
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@@ -330,10 +330,8 BEGIN -- beh
330 330 nCTS2 <= '1';
331 331 nDCD2 <= '1';
332 332
333 --EXT CONNECTOR
334
335 --SPACE WIRE
336
333 --
334
337 335 leon3_soc_1 : leon3_soc
338 336 GENERIC MAP (
339 337 fabtech => apa3e,
@@ -344,6 +342,7 BEGIN -- beh
344 342 dbguart => 0,
345 343 pclow => 2,
346 344 clk_freq => 25000,
345 IS_RADHARD => 1,
347 346 NB_CPU => 1,
348 347 ENABLE_FPU => 1,
349 348 FPU_NETLIST => 0,
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@@ -41,41 +41,43 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 43 LIBRARY iap;
44 USE iap.memctrl.all;
44 USE iap.memctrl.ALL;
45 45
46 46
47 47 ENTITY leon3_soc IS
48 48 GENERIC (
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
56 56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
59 IS_RADHARD : INTEGER := 0;
58 60 --
59 NB_CPU : INTEGER := 1;
60 ENABLE_FPU : INTEGER := 1;
61 FPU_NETLIST : INTEGER := 1;
62 ENABLE_DSU : INTEGER := 1;
63 ENABLE_AHB_UART : INTEGER := 1;
64 ENABLE_APB_UART : INTEGER := 1;
65 ENABLE_IRQMP : INTEGER := 1;
66 ENABLE_GPT : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
67 69 --
68 NB_AHB_MASTER : INTEGER := 1;
69 NB_AHB_SLAVE : INTEGER := 1;
70 NB_APB_SLAVE : INTEGER := 1;
70 NB_AHB_MASTER : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
71 73 --
72 74 ADDRESS_SIZE : INTEGER := 20;
73 75 USES_IAP_MEMCTRLR : INTEGER := 0
74 76
75 77 );
76 78 PORT (
77 clk : IN STD_ULOGIC;
78 reset : IN STD_ULOGIC;
79 clk : IN STD_ULOGIC;
80 reset : IN STD_ULOGIC;
79 81
80 82 errorn : OUT STD_ULOGIC;
81 83
@@ -95,20 +97,20 ENTITY leon3_soc IS
95 97 nSRAM_BE2 : OUT STD_LOGIC;
96 98 nSRAM_BE3 : OUT STD_LOGIC;
97 99 nSRAM_WE : OUT STD_LOGIC;
98 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
100 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
99 101 nSRAM_OE : OUT STD_LOGIC;
100 102 nSRAM_READY : IN STD_LOGIC;
101 103 SRAM_MBE : INOUT STD_LOGIC;
102 104 -- APB --------------------------------------------------------------------
103 apbi_ext : OUT apb_slv_in_type;
104 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
105 apbi_ext : OUT apb_slv_in_type;
106 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
105 107 -- AHB_Slave --------------------------------------------------------------
106 ahbi_s_ext : OUT ahb_slv_in_type;
107 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
108 ahbi_s_ext : OUT ahb_slv_in_type;
109 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
108 110 -- AHB_Master -------------------------------------------------------------
109 ahbi_m_ext : OUT AHB_Mst_In_Type;
110 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
111
111 ahbi_m_ext : OUT AHB_Mst_In_Type;
112 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
113
112 114 );
113 115 END;
114 116
@@ -119,132 +121,132 ARCHITECTURE Behavioral OF leon3_soc IS
119 121 -----------------------------------------------------------------------------
120 122
121 123 -- Clock generator
122 constant CFG_CLKMUL : integer := (1);
123 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
124 constant CFG_OCLKDIV : integer := (1);
125 constant CFG_CLK_NOFB : integer := 0;
124 CONSTANT CFG_CLKMUL : INTEGER := (1);
125 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
126 CONSTANT CFG_OCLKDIV : INTEGER := (1);
127 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
126 128 -- LEON3 processor core
127 constant CFG_LEON3 : integer := 1;
128 constant CFG_NCPU : integer := NB_CPU;
129 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
130 constant CFG_V8 : integer := 0;
131 constant CFG_MAC : integer := 0;
132 constant CFG_SVT : integer := 0;
133 constant CFG_RSTADDR : integer := 16#00000#;
134 constant CFG_LDDEL : integer := (1);
135 constant CFG_NWP : integer := (0);
136 constant CFG_PWD : integer := 1*2;
137 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
129 CONSTANT CFG_LEON3 : INTEGER := 1;
130 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
131 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
132 CONSTANT CFG_V8 : INTEGER := 0;
133 CONSTANT CFG_MAC : INTEGER := 0;
134 CONSTANT CFG_SVT : INTEGER := 0;
135 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
136 CONSTANT CFG_LDDEL : INTEGER := (1);
137 CONSTANT CFG_NWP : INTEGER := (0);
138 CONSTANT CFG_PWD : INTEGER := 1*2;
139 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
138 140 -- 1*(8 + 16 * 0) => grfpu-light
139 141 -- 1*(8 + 16 * 1) => netlist
140 142 -- 0*(8 + 16 * 0) => No FPU
141 143 -- 0*(8 + 16 * 1) => No FPU;
142 constant CFG_ICEN : integer := 1;
143 constant CFG_ISETS : integer := 1;
144 constant CFG_ISETSZ : integer := 4;
145 constant CFG_ILINE : integer := 4;
146 constant CFG_IREPL : integer := 0;
147 constant CFG_ILOCK : integer := 0;
148 constant CFG_ILRAMEN : integer := 0;
149 constant CFG_ILRAMADDR: integer := 16#8E#;
150 constant CFG_ILRAMSZ : integer := 1;
151 constant CFG_DCEN : integer := 1;
152 constant CFG_DSETS : integer := 1;
153 constant CFG_DSETSZ : integer := 4;
154 constant CFG_DLINE : integer := 4;
155 constant CFG_DREPL : integer := 0;
156 constant CFG_DLOCK : integer := 0;
157 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
158 constant CFG_DLRAMEN : integer := 0;
159 constant CFG_DLRAMADDR: integer := 16#8F#;
160 constant CFG_DLRAMSZ : integer := 1;
161 constant CFG_MMUEN : integer := 0;
162 constant CFG_ITLBNUM : integer := 2;
163 constant CFG_DTLBNUM : integer := 2;
164 constant CFG_TLB_TYPE : integer := 1 + 0*2;
165 constant CFG_TLB_REP : integer := 1;
166
167 constant CFG_DSU : integer := ENABLE_DSU;
168 constant CFG_ITBSZ : integer := 0;
169 constant CFG_ATBSZ : integer := 0;
144 CONSTANT CFG_ICEN : INTEGER := 1;
145 CONSTANT CFG_ISETS : INTEGER := 1;
146 CONSTANT CFG_ISETSZ : INTEGER := 4;
147 CONSTANT CFG_ILINE : INTEGER := 4;
148 CONSTANT CFG_IREPL : INTEGER := 0;
149 CONSTANT CFG_ILOCK : INTEGER := 0;
150 CONSTANT CFG_ILRAMEN : INTEGER := 0;
151 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
152 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
153 CONSTANT CFG_DCEN : INTEGER := 1;
154 CONSTANT CFG_DSETS : INTEGER := 1;
155 CONSTANT CFG_DSETSZ : INTEGER := 4;
156 CONSTANT CFG_DLINE : INTEGER := 4;
157 CONSTANT CFG_DREPL : INTEGER := 0;
158 CONSTANT CFG_DLOCK : INTEGER := 0;
159 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
160 CONSTANT CFG_DLRAMEN : INTEGER := 0;
161 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
162 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
163 CONSTANT CFG_MMUEN : INTEGER := 0;
164 CONSTANT CFG_ITLBNUM : INTEGER := 2;
165 CONSTANT CFG_DTLBNUM : INTEGER := 2;
166 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
167 CONSTANT CFG_TLB_REP : INTEGER := 1;
168
169 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
170 CONSTANT CFG_ITBSZ : INTEGER := 0;
171 CONSTANT CFG_ATBSZ : INTEGER := 0;
170 172
171 173 -- AMBA settings
172 constant CFG_DEFMST : integer := (0);
173 constant CFG_RROBIN : integer := 1;
174 constant CFG_SPLIT : integer := 0;
175 constant CFG_AHBIO : integer := 16#FFF#;
176 constant CFG_APBADDR : integer := 16#800#;
174 CONSTANT CFG_DEFMST : INTEGER := (0);
175 CONSTANT CFG_RROBIN : INTEGER := 1;
176 CONSTANT CFG_SPLIT : INTEGER := 0;
177 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
178 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
177 179
178 180 -- DSU UART
179 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
181 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
180 182
181 183 -- LEON2 memory controller
182 constant CFG_MCTRL_SDEN : integer := 0;
183
184 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
185
184 186 -- UART 1
185 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
186 constant CFG_UART1_FIFO : integer := 1;
187 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
188 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
187 189
188 190 -- LEON3 interrupt controller
189 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
191 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
190 192
191 193 -- Modular timer
192 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
193 constant CFG_GPT_NTIM : integer := (2);
194 constant CFG_GPT_SW : integer := (8);
195 constant CFG_GPT_TW : integer := (32);
196 constant CFG_GPT_IRQ : integer := (8);
197 constant CFG_GPT_SEPIRQ : integer := 1;
198 constant CFG_GPT_WDOGEN : integer := 0;
199 constant CFG_GPT_WDOG : integer := 16#0#;
194 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
195 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
196 CONSTANT CFG_GPT_SW : INTEGER := (8);
197 CONSTANT CFG_GPT_TW : INTEGER := (32);
198 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
199 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
200 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
201 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
200 202 -----------------------------------------------------------------------------
201 203
202 204 -----------------------------------------------------------------------------
203 205 -- SIGNALs
204 206 -----------------------------------------------------------------------------
205 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
207 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
206 208 -- CLK & RST --
207 SIGNAL clk2x : STD_ULOGIC;
208 SIGNAL clkmn : STD_ULOGIC;
209 SIGNAL clkm : STD_ULOGIC;
210 SIGNAL rstn : STD_ULOGIC;
211 SIGNAL rstraw : STD_ULOGIC;
212 SIGNAL pciclk : STD_ULOGIC;
213 SIGNAL sdclkl : STD_ULOGIC;
214 SIGNAL cgi : clkgen_in_type;
215 SIGNAL cgo : clkgen_out_type;
209 SIGNAL clk2x : STD_ULOGIC;
210 SIGNAL clkmn : STD_ULOGIC;
211 SIGNAL clkm : STD_ULOGIC;
212 SIGNAL rstn : STD_ULOGIC;
213 SIGNAL rstraw : STD_ULOGIC;
214 SIGNAL pciclk : STD_ULOGIC;
215 SIGNAL sdclkl : STD_ULOGIC;
216 SIGNAL cgi : clkgen_in_type;
217 SIGNAL cgo : clkgen_out_type;
216 218 --- AHB / APB
217 SIGNAL apbi : apb_slv_in_type;
218 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
219 SIGNAL ahbsi : ahb_slv_in_type;
220 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
221 SIGNAL ahbmi : ahb_mst_in_type;
222 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
219 SIGNAL apbi : apb_slv_in_type;
220 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
221 SIGNAL ahbsi : ahb_slv_in_type;
222 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
223 SIGNAL ahbmi : ahb_mst_in_type;
224 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
223 225 --UART
224 SIGNAL ahbuarti : uart_in_type;
225 SIGNAL ahbuarto : uart_out_type;
226 SIGNAL apbuarti : uart_in_type;
227 SIGNAL apbuarto : uart_out_type;
226 SIGNAL ahbuarti : uart_in_type;
227 SIGNAL ahbuarto : uart_out_type;
228 SIGNAL apbuarti : uart_in_type;
229 SIGNAL apbuarto : uart_out_type;
228 230 --MEM CTRLR
229 SIGNAL memi : memory_in_type;
230 SIGNAL memo : memory_out_type;
231 SIGNAL wpo : wprot_out_type;
232 SIGNAL sdo : sdram_out_type;
233 SIGNAl mbe : std_logic; -- enable memory programming
234 SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal
235 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0);
236 SIGNAL nSRAM_OE_s : STD_LOGIC;
231 SIGNAL memi : memory_in_type;
232 SIGNAL memo : memory_out_type;
233 SIGNAL wpo : wprot_out_type;
234 SIGNAL sdo : sdram_out_type;
235 SIGNAL mbe : STD_LOGIC; -- enable memory programming
236 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
237 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
238 SIGNAL nSRAM_OE_s : STD_LOGIC;
237 239 --IRQ
238 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
239 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
240 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
241 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
240 242 --Timer
241 SIGNAL gpti : gptimer_in_type;
242 SIGNAL gpto : gptimer_out_type;
243 SIGNAL gpti : gptimer_in_type;
244 SIGNAL gpto : gptimer_out_type;
243 245 --DSU
244 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
245 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
246 SIGNAL dsui : dsu_in_type;
247 SIGNAL dsuo : dsu_out_type;
246 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
247 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
248 SIGNAL dsui : dsu_in_type;
249 SIGNAL dsuo : dsu_out_type;
248 250 -----------------------------------------------------------------------------
249 251
250 252
@@ -271,15 +273,88 BEGIN
271 273
272 274 l3 : IF CFG_LEON3 = 1 GENERATE
273 275 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
274 u0 : leon3s -- LEON3 processor
275 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
276 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
277 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
278 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
279 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
280 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
281 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
282 irqi(i), irqo(i), dbgi(i), dbgo(i));
276 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
277 u0 : leon3s -- LEON3 processor
278 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
279 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
280 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
281 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
282 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
283 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
284 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
285 irqi(i), irqo(i), dbgi(i), dbgo(i));
286 END GENERATE leon3_non_radhard;
287 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
288 cpu : ENTITY gaisler.leon3ft
289 GENERIC MAP (
290 HINDEX => i, --: integer; --CPU_HINDEX,
291 FABTECH => fabtech, --CFG_TECH,
292 MEMTECH => memtech, --CFG_TECH,
293 NWINDOWS => CFG_NWIN, --CFG_NWIN,
294 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
295 FPU => CFG_FPU, --CFG_FPU,
296 V8 => CFG_V8, --CFG_V8,
297 CP => 0, --CFG_CP,
298 MAC => CFG_MAC, --CFG_MAC,
299 PCLOW => pclow, --CFG_PCLOW,
300 NOTAG => 0, --CFG_NOTAG,
301 NWP => CFG_NWP, --CFG_NWP,
302 ICEN => CFG_ICEN, --CFG_ICEN,
303 IREPL => CFG_IREPL, --CFG_IREPL,
304 ISETS => CFG_ISETS, --CFG_ISETS,
305 ILINESIZE => CFG_ILINE, --CFG_ILINE,
306 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
307 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
308 DCEN => CFG_DCEN, --CFG_DCEN,
309 DREPL => CFG_DREPL, --CFG_DREPL,
310 DSETS => CFG_DSETS, --CFG_DSETS,
311 DLINESIZE => CFG_DLINE, --CFG_DLINE,
312 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
313 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
314 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
315 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
316 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
317 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
318 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
319 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
320 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
321 MMUEN => CFG_MMUEN, --CFG_MMUEN,
322 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
323 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
324 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
325 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
326 LDDEL => CFG_LDDEL, --CFG_LDDEL,
327 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
328 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
329 PWD => CFG_PWD, --CFG_PWD,
330 SVT => CFG_SVT, --CFG_SVT,
331 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
332 SMP => CFG_NCPU-1, --CFG_NCPU-1,
333 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
334 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
335 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
336 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
337 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
338 CACHED => 0, --: integer; --CFG_DFIXED,
339 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
340 SCANTEST => 0, --: integer; --CFG_SCANTEST,
341 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
342 BP => 1) --CFG_BP
343 PORT MAP ( --
344 rstn => rstn, --rst_n,
345 clk => clkm, --clk,
346 ahbi => ahbmi, --ahbmi,
347 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
348 ahbsi => ahbsi, --ahbsi,
349 ahbso => ahbso, --ahbso,
350 irqi => irqi(i), --irqi(CPU_HINDEX),
351 irqo => irqo(i), --irqo(CPU_HINDEX),
352 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
353 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
354 gclk => clkm --clk
355 );
356 END GENERATE leon3_radhard_i;
357
283 358 END GENERATE;
284 359 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
285 360
@@ -294,8 +369,8 BEGIN
294 369 END GENERATE;
295 370
296 371 nodsu : IF CFG_DSU = 0 GENERATE
297 ahbso(2) <= ahbs_none;
298 dsuo.tstop <= '0';
372 ahbso(2) <= ahbs_none;
373 dsuo.tstop <= '0';
299 374 dsuo.active <= '0';
300 375 END GENERATE;
301 376
@@ -314,66 +389,66 BEGIN
314 389 ----------------------------------------------------------------------
315 390 --- Memory controllers ---------------------------------------------
316 391 ----------------------------------------------------------------------
317 ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
318 memctrlr : mctrl GENERIC MAP (
319 hindex => 0,
320 pindex => 0,
321 paddr => 0,
322 srbanks => 1
323 )
324 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
325 memi.bexcn <= '1';
326 memi.brdyn <= '1';
392 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
393 memctrlr : mctrl GENERIC MAP (
394 hindex => 0,
395 pindex => 0,
396 paddr => 0,
397 srbanks => 1
398 )
399 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
400 memi.bexcn <= '1';
401 memi.brdyn <= '1';
327 402
328 nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0));
329 nSRAM_OE_s <= memo.ramoen(0);
330 END GENERATE;
403 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
404 nSRAM_OE_s <= memo.ramoen(0);
405 END GENERATE;
331 406
332 IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
333 memctrlr : srctrle_0ws
334 GENERIC MAP(
335 hindex => 0,
336 pindex => 0,
337 paddr => 0,
338 srbanks => 2,
339 banksz => 8, --512k * 32
340 rmw => 1,
341 --Aeroflex memory generics:
342 mprog => 1, -- program memory by default values after reset
343 mpsrate => 12, -- default scrub rate period
344 mpb2s => 4, -- default busy to scrub delay
345 mpapb => 1, -- instantiate apb register
346 mchipcnt => 2,
347 mpenall => 1 -- when 0 program only E1 chip, else program all dies
348 )
349 PORT MAP (
350 rst => rstn,
351 clk => clkm,
352 ahbsi => ahbsi,
353 ahbso => ahbso(0),
354 apbi => apbi,
355 apbo => apbo(0),
356 sri => memi,
357 sro => memo,
358 --Aeroflex memory signals:
359 ucerr => open, -- uncorrectable error signal
360 mbe => mbe, -- enable memory programming
361 mbe_drive => mbe_drive -- drive the MBE memory signal
362 );
407 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
408 memctrlr : srctrle_0ws
409 GENERIC MAP(
410 hindex => 0,
411 pindex => 0,
412 paddr => 0,
413 srbanks => 2,
414 banksz => 8, --512k * 32
415 rmw => 1,
416 --Aeroflex memory generics:
417 mprog => 1, -- program memory by default values after reset
418 mpsrate => 12, -- default scrub rate period
419 mpb2s => 4, -- default busy to scrub delay
420 mpapb => 1, -- instantiate apb register
421 mchipcnt => 2,
422 mpenall => 1 -- when 0 program only E1 chip, else program all dies
423 )
424 PORT MAP (
425 rst => rstn,
426 clk => clkm,
427 ahbsi => ahbsi,
428 ahbso => ahbso(0),
429 apbi => apbi,
430 apbo => apbo(0),
431 sri => memi,
432 sro => memo,
433 --Aeroflex memory signals:
434 ucerr => OPEN, -- uncorrectable error signal
435 mbe => mbe, -- enable memory programming
436 mbe_drive => mbe_drive -- drive the MBE memory signal
437 );
363 438
364 memi.brdyn <= nSRAM_READY;
439 memi.brdyn <= nSRAM_READY;
365 440
366 mbe_pad : iopad
367 GENERIC MAP(tech => padtech)
368 PORT MAP(pad => SRAM_MBE,
369 i => mbe,
370 en => mbe_drive,
371 o => memi.bexcn );
441 mbe_pad : iopad
442 GENERIC MAP(tech => padtech)
443 PORT MAP(pad => SRAM_MBE,
444 i => mbe,
445 en => mbe_drive,
446 o => memi.bexcn);
372 447
373 nSRAM_CE_s <= (memo.ramsn(1 downto 0));
374 nSRAM_OE_s <= memo.oen;
375
376 END GENERATE;
448 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
449 nSRAM_OE_s <= memo.oen;
450
451 END GENERATE;
377 452
378 453
379 454 memi.writen <= '1';
@@ -381,7 +456,7 END GENERATE;
381 456 memi.bwidth <= "10";
382 457
383 458 bdr : FOR i IN 0 TO 3 GENERATE
384 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
459 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
385 460 PORT MAP (
386 461 data(31-i*8 DOWNTO 24-i*8),
387 462 memo.data(31-i*8 DOWNTO 24-i*8),
@@ -391,13 +466,13 END GENERATE;
391 466
392 467 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
393 468 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
394 rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
395 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
396 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
397 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
398 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
399 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
400 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
469 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
470 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
471 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
472 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
473 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
474 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
475 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
401 476
402 477
403 478
@@ -464,27 +539,27 END GENERATE;
464 539 -------------------------------------------------------------------------------
465 540
466 541 -- APB --------------------------------------------------------------------
467 apbi_ext <= apbi;
468 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
469 max_16_apb: IF I + 5 < 16 GENERATE
470 apbo(I+5)<= apbo_ext(I+5);
542 apbi_ext <= apbi;
543 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
544 max_16_apb : IF I + 5 < 16 GENERATE
545 apbo(I+5) <= apbo_ext(I+5);
471 546 END GENERATE max_16_apb;
472 547 END GENERATE all_apb;
473 548 -- AHB_Slave --------------------------------------------------------------
474 549 ahbi_s_ext <= ahbsi;
475 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
476 max_16_ahbs: IF I + 3 < 16 GENERATE
550 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
551 max_16_ahbs : IF I + 3 < 16 GENERATE
477 552 ahbso(I+3) <= ahbo_s_ext(I+3);
478 553 END GENERATE max_16_ahbs;
479 554 END GENERATE all_ahbs;
480 555 -- AHB_Master -------------------------------------------------------------
481 556 ahbi_m_ext <= ahbmi;
482 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
483 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
557 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
558 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
484 559 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
485 560 END GENERATE max_16_ahbm;
486 561 END GENERATE all_ahbm;
487 562
488 563
489 564
490 END Behavioral; No newline at end of file
565 END Behavioral;
Show file before | Show file after | Hide comments
@@ -257,76 +257,145 BEGIN
257 257 --- LEON3 processor / DSU / IRQ ------------------------------------
258 258 ----------------------------------------------------------------------
259 259
260 l3 : IF CFG_LEON3 = 1 GENERATE
261 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
262 u0 : leon3ft
263 GENERIC MAP (
264 hindex => i, --: integer;
265 fabtech => fabtech,
266 memtech => memtech,
267 nwindows => CFG_NWIN,
268 dsu => CFG_DSU,
269 fpu => CFG_FPU,
270 v8 => CFG_V8,
271 cp => 0,
272 mac => CFG_MAC,
273 pclow => pclow,
274 notag => 0,
275 nwp => CFG_NWP,
276 icen => CFG_ICEN,
277 irepl => CFG_IREPL,
278 isets => CFG_ISETS,
279 ilinesize => CFG_ILINE,
280 isetsize => CFG_ISETSZ,
281 isetlock => CFG_ILOCK,
282 dcen => CFG_DCEN,
283 drepl => CFG_DREPL,
284 dsets => CFG_DSETS,
285 dlinesize => CFG_DLINE,
286 dsetsize => CFG_DSETSZ,
287 dsetlock => CFG_DLOCK,
288 dsnoop => CFG_DSNOOP,
289 ilram => CFG_ILRAMEN,
290 ilramsize => CFG_ILRAMSZ,
291 ilramstart => CFG_ILRAMADDR,
292 dlram => CFG_DLRAMEN,
293 dlramsize => CFG_DLRAMSZ,
294 dlramstart => CFG_DLRAMADDR,
295 mmuen => CFG_MMUEN,
296 itlbnum => CFG_ITLBNUM,
297 dtlbnum => CFG_DTLBNUM,
298 tlb_type => CFG_TLB_TYPE,
299 tlb_rep => CFG_TLB_REP,
300 lddel => CFG_LDDEL,
301 disas => disas,
302 tbuf => CFG_ITBSZ,
303 pwd => CFG_PWD,
304 svt => CFG_SVT,
305 rstaddr => CFG_RSTADDR,
306 smp => CFG_NCPU-1,
307 iuft => 2, --: integer range 0 to 4;
308 fpft => 1, --: integer range 0 to 4;
309 cmft => 1, --: integer range 0 to 1;
310 iuinj => 0, --: integer;
311 ceinj => 0, --: integer range 0 to 3;
312 cached => 0, --: integer;
313 netlist => 0, --: integer;
314 scantest => 0, --: integer;
315 mmupgsz => 0, --: integer range 0 to 5;
316 bp => 1) --: integer);
317 PORT MAP (
318 clk => clkm,
319 rstn => rstn,
320 ahbi => ahbmi,
321 ahbo => ahbmo(i),
322 ahbsi => ahbsi,
323 ahbso => ahbso,
324 irqi => irqi(i),
325 irqo => irqo(i),
326 dbgi => dbgi(i),
327 dbgo => dbgo(i),
328 gclk => clkm
329 );
260 l3 : IF CFG_LEON3 = 1 GENERATE
261 cpu: entity gaisler.leon3ft
262 generic map (
263 HINDEX => i, --: integer; --CPU_HINDEX,
264 FABTECH => fabtech, --CFG_TECH,
265 MEMTECH => memtech, --CFG_TECH,
266 NWINDOWS => CFG_NWIN, --CFG_NWIN,
267 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
268 FPU => CFG_FPU, --CFG_FPU,
269 V8 => CFG_V8, --CFG_V8,
270 CP => 0, --CFG_CP,
271 MAC => CFG_MAC, --CFG_MAC,
272 PCLOW => pclow, --CFG_PCLOW,
273 NOTAG => 0, --CFG_NOTAG,
274 NWP => CFG_NWP, --CFG_NWP,
275 ICEN => CFG_ICEN, --CFG_ICEN,
276 IREPL => CFG_IREPL, --CFG_IREPL,
277 ISETS => CFG_ISETS, --CFG_ISETS,
278 ILINESIZE => CFG_ILINE, --CFG_ILINE,
279 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
280 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
281 DCEN => CFG_DCEN, --CFG_DCEN,
282 DREPL => CFG_DREPL, --CFG_DREPL,
283 DSETS => CFG_DSETS, --CFG_DSETS,
284 DLINESIZE => CFG_DLINE, --CFG_DLINE,
285 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
286 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
287 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
288 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
289 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
290 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
291 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
292 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
293 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
294 MMUEN => CFG_MMUEN, --CFG_MMUEN,
295 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
296 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
297 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
298 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
299 LDDEL => CFG_LDDEL, --CFG_LDDEL,
300 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
301 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
302 PWD => CFG_PWD, --CFG_PWD,
303 SVT => CFG_SVT, --CFG_SVT,
304 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
305 SMP => CFG_NCPU-1, --CFG_NCPU-1,
306 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
307 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
308 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
309 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
310 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
311 CACHED => 0, --: integer; --CFG_DFIXED,
312 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
313 SCANTEST => 0, --: integer; --CFG_SCANTEST,
314 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
315 BP => 1)--CFG_BP
316 ) --
317 port map ( --
318 rstn => clkm, --rst_n,
319 clk => rstn, --clk,
320 ahbi => ahbmi, --ahbmi,
321 ahbo => ahbmo(i)--ahbmo(CPU_HINDEX),
322 ahbsi => ahbsi, --ahbsi,
323 ahbso => ahbso, --ahbso,
324 irqi => irqi(i),--irqi(CPU_HINDEX),
325 irqo => irqo(i),--irqo(CPU_HINDEX),
326 dbgi => dbgi(i),--dbgi(CPU_HINDEX),
327 dbgo => dbgo(i),--dbgo(CPU_HINDEX),
328 gclk => clkm--clk
329 );
330 --cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
331 -- u0 : leon3ft
332 -- GENERIC MAP (
333 -- hindex => i, --: integer;
334 -- fabtech => fabtech,
335 -- memtech => memtech,
336 -- nwindows => CFG_NWIN,
337 -- dsu => CFG_DSU,
338 -- fpu => CFG_FPU,
339 -- v8 => CFG_V8,
340 -- cp => 0,
341 -- mac => CFG_MAC,
342 -- pclow => pclow,
343 -- notag => 0,
344 -- nwp => CFG_NWP,
345 -- icen => CFG_ICEN,
346 -- irepl => CFG_IREPL,
347 -- isets => CFG_ISETS,
348 -- ilinesize => CFG_ILINE,
349 -- isetsize => CFG_ISETSZ,
350 -- isetlock => CFG_ILOCK,
351 -- dcen => CFG_DCEN,
352 -- drepl => CFG_DREPL,
353 -- dsets => CFG_DSETS,
354 -- dlinesize => CFG_DLINE,
355 -- dsetsize => CFG_DSETSZ,
356 -- dsetlock => CFG_DLOCK,
357 -- dsnoop => CFG_DSNOOP,
358 -- ilram => CFG_ILRAMEN,
359 -- ilramsize => CFG_ILRAMSZ,
360 -- ilramstart => CFG_ILRAMADDR,
361 -- dlram => CFG_DLRAMEN,
362 -- dlramsize => CFG_DLRAMSZ,
363 -- dlramstart => CFG_DLRAMADDR,
364 -- mmuen => CFG_MMUEN,
365 -- itlbnum => CFG_ITLBNUM,
366 -- dtlbnum => CFG_DTLBNUM,
367 -- tlb_type => CFG_TLB_TYPE,
368 -- tlb_rep => CFG_TLB_REP,
369 -- lddel => CFG_LDDEL,
370 -- disas => disas,
371 -- tbuf => CFG_ITBSZ,
372 -- pwd => CFG_PWD,
373 -- svt => CFG_SVT,
374 -- rstaddr => CFG_RSTADDR,
375 -- smp => CFG_NCPU-1,
376 -- iuft => 2, --: integer range 0 to 4;
377 -- fpft => 1, --: integer range 0 to 4;
378 -- cmft => 1, --: integer range 0 to 1;
379 -- iuinj => 0, --: integer;
380 -- ceinj => 0, --: integer range 0 to 3;
381 -- cached => 0, --: integer;
382 -- netlist => 0, --: integer;
383 -- scantest => 0, --: integer;
384 -- mmupgsz => 0, --: integer range 0 to 5;
385 -- bp => 1) --: integer);
386 -- PORT MAP (
387 -- clk => clkm,
388 -- rstn => rstn,
389 -- ahbi => ahbmi,
390 -- ahbo => ahbmo(i),
391 -- ahbsi => ahbsi,
392 -- ahbso => ahbso,
393 -- irqi => irqi(i),
394 -- irqo => irqo(i),
395 -- dbgi => dbgi(i),
396 -- dbgo => dbgo(i),
397 -- gclk => clkm
398 -- );
330 399
331 400 END GENERATE;
332 401
@@ -484,4 +553,4 BEGIN
484 553
485 554
486 555
487 END Behavioral; No newline at end of file
556 END Behavioral;
Show file before | Show file after | Hide comments
@@ -41,6 +41,7 PACKAGE lpp_leon3_soc_pkg IS
41 41 dbguart : INTEGER;
42 42 pclow : INTEGER;
43 43 clk_freq : INTEGER;
44 IS_RADHARD : INTEGER;
44 45 NB_CPU : INTEGER;
45 46 ENABLE_FPU : INTEGER;
46 47 FPU_NETLIST : INTEGER;
@@ -93,50 +94,50 PACKAGE lpp_leon3_soc_pkg IS
93 94 END COMPONENT;
94 95
95 96
96 COMPONENT leon3ft_soc
97 GENERIC (
98 fabtech : INTEGER;
99 memtech : INTEGER;
100 padtech : INTEGER;
101 clktech : INTEGER;
102 disas : INTEGER;
103 dbguart : INTEGER;
104 pclow : INTEGER;
105 clk_freq : INTEGER;
106 NB_CPU : INTEGER;
107 ENABLE_FPU : INTEGER;
108 FPU_NETLIST : INTEGER;
109 ENABLE_DSU : INTEGER;
110 ENABLE_AHB_UART : INTEGER;
111 ENABLE_APB_UART : INTEGER;
112 ENABLE_IRQMP : INTEGER;
113 ENABLE_GPT : INTEGER;
114 NB_AHB_MASTER : INTEGER;
115 NB_AHB_SLAVE : INTEGER;
116 NB_APB_SLAVE : INTEGER);
117 PORT (
118 clk : IN STD_ULOGIC;
119 reset : IN STD_ULOGIC;
120 errorn : OUT STD_ULOGIC;
121 ahbrxd : IN STD_ULOGIC;
122 ahbtxd : OUT STD_ULOGIC;
123 urxd1 : IN STD_ULOGIC;
124 utxd1 : OUT STD_ULOGIC;
125 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
126 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 nSRAM_BE0 : OUT STD_LOGIC;
128 nSRAM_BE1 : OUT STD_LOGIC;
129 nSRAM_BE2 : OUT STD_LOGIC;
130 nSRAM_BE3 : OUT STD_LOGIC;
131 nSRAM_WE : OUT STD_LOGIC;
132 nSRAM_CE : OUT STD_LOGIC;
133 nSRAM_OE : OUT STD_LOGIC;
134 apbi_ext : OUT apb_slv_in_type;
135 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
136 ahbi_s_ext : OUT ahb_slv_in_type;
137 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
138 ahbi_m_ext : OUT AHB_Mst_In_Type;
139 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
140 END COMPONENT;
97 --COMPONENT leon3ft_soc
98 -- GENERIC (
99 -- fabtech : INTEGER;
100 -- memtech : INTEGER;
101 -- padtech : INTEGER;
102 -- clktech : INTEGER;
103 -- disas : INTEGER;
104 -- dbguart : INTEGER;
105 -- pclow : INTEGER;
106 -- clk_freq : INTEGER;
107 -- NB_CPU : INTEGER;
108 -- ENABLE_FPU : INTEGER;
109 -- FPU_NETLIST : INTEGER;
110 -- ENABLE_DSU : INTEGER;
111 -- ENABLE_AHB_UART : INTEGER;
112 -- ENABLE_APB_UART : INTEGER;
113 -- ENABLE_IRQMP : INTEGER;
114 -- ENABLE_GPT : INTEGER;
115 -- NB_AHB_MASTER : INTEGER;
116 -- NB_AHB_SLAVE : INTEGER;
117 -- NB_APB_SLAVE : INTEGER);
118 -- PORT (
119 -- clk : IN STD_ULOGIC;
120 -- reset : IN STD_ULOGIC;
121 -- errorn : OUT STD_ULOGIC;
122 -- ahbrxd : IN STD_ULOGIC;
123 -- ahbtxd : OUT STD_ULOGIC;
124 -- urxd1 : IN STD_ULOGIC;
125 -- utxd1 : OUT STD_ULOGIC;
126 -- address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
127 -- data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -- nSRAM_BE0 : OUT STD_LOGIC;
129 -- nSRAM_BE1 : OUT STD_LOGIC;
130 -- nSRAM_BE2 : OUT STD_LOGIC;
131 -- nSRAM_BE3 : OUT STD_LOGIC;
132 -- nSRAM_WE : OUT STD_LOGIC;
133 -- nSRAM_CE : OUT STD_LOGIC;
134 -- nSRAM_OE : OUT STD_LOGIC;
135 -- apbi_ext : OUT apb_slv_in_type;
136 -- apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
137 -- ahbi_s_ext : OUT ahb_slv_in_type;
138 -- ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
139 -- ahbi_m_ext : OUT AHB_Mst_In_Type;
140 -- ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
141 --END COMPONENT;
141 142
142 END; No newline at end of file
143 END;
Show file before | Show file after | Hide comments
@@ -1,3 +1,2
1 1 lpp_leon3_soc_pkg.vhd
2 2 leon3_soc.vhd
3 leon3ft_soc.vhd
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