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1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
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23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
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24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
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25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
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26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
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27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
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28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
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29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
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30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
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31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
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32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
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33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
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34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
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35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
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36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
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37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
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38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
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39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
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40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
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43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
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44 | USE lpp.general_purpose.ALL; | |
45 |
USE lpp.lpp_lfr_ |
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45 | USE lpp.lpp_lfr_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
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47 | |||
48 | ENTITY LFR_em IS |
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48 | ENTITY LFR_em IS | |
49 |
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49 | |||
50 | PORT ( |
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50 | PORT ( | |
51 | clk100MHz : IN STD_ULOGIC; |
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51 | clk100MHz : IN STD_ULOGIC; | |
52 | clk49_152MHz : IN STD_ULOGIC; |
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52 | clk49_152MHz : IN STD_ULOGIC; | |
53 | reset : IN STD_ULOGIC; |
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53 | reset : IN STD_ULOGIC; | |
54 |
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54 | |||
55 | -- TAG -------------------------------------------------------------------- |
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55 | -- TAG -------------------------------------------------------------------- | |
56 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
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56 | TAG1 : IN STD_ULOGIC; -- DSU rx data | |
57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
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57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data | |
58 | -- UART APB --------------------------------------------------------------- |
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58 | -- UART APB --------------------------------------------------------------- | |
59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data | |
60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data | |
61 | -- RAM -------------------------------------------------------------------- |
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61 | -- RAM -------------------------------------------------------------------- | |
62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
64 | nSRAM_BE0 : OUT STD_LOGIC; |
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64 | nSRAM_BE0 : OUT STD_LOGIC; | |
65 | nSRAM_BE1 : OUT STD_LOGIC; |
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65 | nSRAM_BE1 : OUT STD_LOGIC; | |
66 | nSRAM_BE2 : OUT STD_LOGIC; |
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66 | nSRAM_BE2 : OUT STD_LOGIC; | |
67 | nSRAM_BE3 : OUT STD_LOGIC; |
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67 | nSRAM_BE3 : OUT STD_LOGIC; | |
68 | nSRAM_WE : OUT STD_LOGIC; |
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68 | nSRAM_WE : OUT STD_LOGIC; | |
69 | nSRAM_CE : OUT STD_LOGIC; |
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69 | nSRAM_CE : OUT STD_LOGIC; | |
70 | nSRAM_OE : OUT STD_LOGIC; |
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70 | nSRAM_OE : OUT STD_LOGIC; | |
71 | -- SPW -------------------------------------------------------------------- |
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71 | -- SPW -------------------------------------------------------------------- | |
72 | spw1_din : IN STD_LOGIC; |
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72 | spw1_din : IN STD_LOGIC; | |
73 | spw1_sin : IN STD_LOGIC; |
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73 | spw1_sin : IN STD_LOGIC; | |
74 | spw1_dout : OUT STD_LOGIC; |
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74 | spw1_dout : OUT STD_LOGIC; | |
75 | spw1_sout : OUT STD_LOGIC; |
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75 | spw1_sout : OUT STD_LOGIC; | |
76 | spw2_din : IN STD_LOGIC; |
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76 | spw2_din : IN STD_LOGIC; | |
77 | spw2_sin : IN STD_LOGIC; |
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77 | spw2_sin : IN STD_LOGIC; | |
78 | spw2_dout : OUT STD_LOGIC; |
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78 | spw2_dout : OUT STD_LOGIC; | |
79 | spw2_sout : OUT STD_LOGIC; |
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79 | spw2_sout : OUT STD_LOGIC; | |
80 | -- ADC -------------------------------------------------------------------- |
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80 | -- ADC -------------------------------------------------------------------- | |
81 | bias_fail_sw : OUT STD_LOGIC; |
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81 | bias_fail_sw : OUT STD_LOGIC; | |
82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
83 | ADC_smpclk : OUT STD_LOGIC; |
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83 | ADC_smpclk : OUT STD_LOGIC; | |
84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |
85 | -- HK --------------------------------------------------------------------- |
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85 | -- HK --------------------------------------------------------------------- | |
86 | HK_smpclk : OUT STD_LOGIC; |
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86 | HK_smpclk : OUT STD_LOGIC; | |
87 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
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87 | ADC_OEB_bar_HK : OUT STD_LOGIC; | |
88 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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88 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
89 | --------------------------------------------------------------------------- |
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89 | --------------------------------------------------------------------------- | |
90 | TAG8 : OUT STD_LOGIC; |
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90 | TAG8 : OUT STD_LOGIC; | |
91 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
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91 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) | |
92 | ); |
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92 | ); | |
93 |
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93 | |||
94 | END LFR_em; |
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94 | END LFR_em; | |
95 |
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95 | |||
96 |
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96 | |||
97 | ARCHITECTURE beh OF LFR_em IS |
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97 | ARCHITECTURE beh OF LFR_em IS | |
98 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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98 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
99 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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99 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
100 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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100 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
101 | ----------------------------------------------------------------------------- |
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101 | ----------------------------------------------------------------------------- | |
102 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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102 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
103 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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103 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
104 |
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104 | |||
105 | -- CONSTANTS |
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105 | -- CONSTANTS | |
106 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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106 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
107 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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107 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
108 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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108 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
109 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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109 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
110 |
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110 | |||
111 | SIGNAL apbi_ext : apb_slv_in_type; |
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111 | SIGNAL apbi_ext : apb_slv_in_type; | |
112 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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112 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
113 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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113 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
114 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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114 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
115 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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115 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
116 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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116 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
117 |
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117 | |||
118 | -- Spacewire signals |
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118 | -- Spacewire signals | |
119 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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119 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
120 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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120 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
121 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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121 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
122 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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122 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
123 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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123 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
124 | SIGNAL spw_clk : STD_LOGIC; |
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124 | SIGNAL spw_clk : STD_LOGIC; | |
125 | SIGNAL swni : grspw_in_type; |
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125 | SIGNAL swni : grspw_in_type; | |
126 | SIGNAL swno : grspw_out_type; |
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126 | SIGNAL swno : grspw_out_type; | |
127 |
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127 | |||
128 | --GPIO |
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128 | --GPIO | |
129 | SIGNAL gpioi : gpio_in_type; |
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129 | SIGNAL gpioi : gpio_in_type; | |
130 | SIGNAL gpioo : gpio_out_type; |
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130 | SIGNAL gpioo : gpio_out_type; | |
131 |
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131 | |||
132 | -- AD Converter ADS7886 |
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132 | -- AD Converter ADS7886 | |
133 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
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133 | SIGNAL sample : Samples14v(8 DOWNTO 0); | |
134 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
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134 | SIGNAL sample_s : Samples(8 DOWNTO 0); | |
135 | SIGNAL sample_val : STD_LOGIC; |
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135 | SIGNAL sample_val : STD_LOGIC; | |
136 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
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136 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); | |
137 |
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137 | |||
138 | ----------------------------------------------------------------------------- |
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138 | ----------------------------------------------------------------------------- | |
139 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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139 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
140 |
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140 | |||
141 | ----------------------------------------------------------------------------- |
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141 | ----------------------------------------------------------------------------- | |
142 | SIGNAL rstn : STD_LOGIC; |
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142 | SIGNAL rstn : STD_LOGIC; | |
143 |
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143 | |||
144 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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144 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
145 | SIGNAL LFR_rstn : STD_LOGIC; |
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145 | SIGNAL LFR_rstn : STD_LOGIC; | |
146 |
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146 | |||
147 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
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147 | SIGNAL ADC_smpclk_s : STD_LOGIC; | |
148 | ----------------------------------------------------------------------------- |
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148 | ----------------------------------------------------------------------------- | |
149 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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149 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
150 |
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150 | |||
151 | BEGIN -- beh |
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151 | BEGIN -- beh | |
152 |
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152 | |||
153 | ----------------------------------------------------------------------------- |
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153 | ----------------------------------------------------------------------------- | |
154 | -- CLK |
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154 | -- CLK | |
155 | ----------------------------------------------------------------------------- |
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155 | ----------------------------------------------------------------------------- | |
156 | rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); |
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156 | rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); | |
157 |
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157 | |||
158 | PROCESS(clk100MHz) |
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158 | PROCESS(clk100MHz) | |
159 | BEGIN |
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159 | BEGIN | |
160 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN |
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160 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN | |
161 | clk_50_s <= NOT clk_50_s; |
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161 | clk_50_s <= NOT clk_50_s; | |
162 | END IF; |
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162 | END IF; | |
163 | END PROCESS; |
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163 | END PROCESS; | |
164 |
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164 | |||
165 | PROCESS(clk_50_s) |
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165 | PROCESS(clk_50_s) | |
166 | BEGIN |
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166 | BEGIN | |
167 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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167 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
168 | clk_25 <= NOT clk_25; |
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168 | clk_25 <= NOT clk_25; | |
169 | END IF; |
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169 | END IF; | |
170 | END PROCESS; |
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170 | END PROCESS; | |
171 |
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171 | |||
172 | PROCESS(clk49_152MHz) |
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172 | PROCESS(clk49_152MHz) | |
173 | BEGIN |
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173 | BEGIN | |
174 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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174 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN | |
175 | clk_24 <= NOT clk_24; |
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175 | clk_24 <= NOT clk_24; | |
176 | END IF; |
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176 | END IF; | |
177 | END PROCESS; |
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177 | END PROCESS; | |
178 |
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178 | |||
179 | ----------------------------------------------------------------------------- |
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179 | ----------------------------------------------------------------------------- | |
180 |
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180 | |||
181 | PROCESS (clk_25, rstn) |
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181 | PROCESS (clk_25, rstn) | |
182 | BEGIN -- PROCESS |
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182 | BEGIN -- PROCESS | |
183 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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183 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
184 | led(0) <= '0'; |
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184 | led(0) <= '0'; | |
185 | led(1) <= '0'; |
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185 | led(1) <= '0'; | |
186 | led(2) <= '0'; |
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186 | led(2) <= '0'; | |
187 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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187 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
188 | led(0) <= '0'; |
|
188 | led(0) <= '0'; | |
189 | led(1) <= '1'; |
|
189 | led(1) <= '1'; | |
190 | led(2) <= '1'; |
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190 | led(2) <= '1'; | |
191 | END IF; |
|
191 | END IF; | |
192 | END PROCESS; |
|
192 | END PROCESS; | |
193 |
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193 | |||
194 | -- |
|
194 | -- | |
195 | leon3_soc_1 : leon3_soc |
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195 | leon3_soc_1 : leon3_soc | |
196 | GENERIC MAP ( |
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196 | GENERIC MAP ( | |
197 | fabtech => apa3e, |
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197 | fabtech => apa3e, | |
198 | memtech => apa3e, |
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198 | memtech => apa3e, | |
199 | padtech => inferred, |
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199 | padtech => inferred, | |
200 | clktech => inferred, |
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200 | clktech => inferred, | |
201 | disas => 0, |
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201 | disas => 0, | |
202 | dbguart => 0, |
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202 | dbguart => 0, | |
203 | pclow => 2, |
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203 | pclow => 2, | |
204 | clk_freq => 25000, |
|
204 | clk_freq => 25000, | |
205 | NB_CPU => 1, |
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205 | NB_CPU => 1, | |
206 | ENABLE_FPU => 1, |
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206 | ENABLE_FPU => 1, | |
207 | FPU_NETLIST => 0, |
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207 | FPU_NETLIST => 0, | |
208 | ENABLE_DSU => 1, |
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208 | ENABLE_DSU => 1, | |
209 | ENABLE_AHB_UART => 1, |
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209 | ENABLE_AHB_UART => 1, | |
210 | ENABLE_APB_UART => 1, |
|
210 | ENABLE_APB_UART => 1, | |
211 | ENABLE_IRQMP => 1, |
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211 | ENABLE_IRQMP => 1, | |
212 | ENABLE_GPT => 1, |
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212 | ENABLE_GPT => 1, | |
213 | NB_AHB_MASTER => NB_AHB_MASTER, |
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213 | NB_AHB_MASTER => NB_AHB_MASTER, | |
214 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
214 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
215 | NB_APB_SLAVE => NB_APB_SLAVE, |
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215 | NB_APB_SLAVE => NB_APB_SLAVE, | |
216 | ADDRESS_SIZE => 20, |
|
216 | ADDRESS_SIZE => 20, | |
217 | USES_IAP_MEMCTRLR => 0) |
|
217 | USES_IAP_MEMCTRLR => 0) | |
218 | PORT MAP ( |
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218 | PORT MAP ( | |
219 | clk => clk_25, |
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219 | clk => clk_25, | |
220 | reset => rstn, |
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220 | reset => rstn, | |
221 | errorn => OPEN, |
|
221 | errorn => OPEN, | |
222 |
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222 | |||
223 | ahbrxd => TAG1, |
|
223 | ahbrxd => TAG1, | |
224 | ahbtxd => TAG3, |
|
224 | ahbtxd => TAG3, | |
225 | urxd1 => TAG2, |
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225 | urxd1 => TAG2, | |
226 | utxd1 => TAG4, |
|
226 | utxd1 => TAG4, | |
227 |
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227 | |||
228 | address => address, |
|
228 | address => address, | |
229 | data => data, |
|
229 | data => data, | |
230 | nSRAM_BE0 => nSRAM_BE0, |
|
230 | nSRAM_BE0 => nSRAM_BE0, | |
231 | nSRAM_BE1 => nSRAM_BE1, |
|
231 | nSRAM_BE1 => nSRAM_BE1, | |
232 | nSRAM_BE2 => nSRAM_BE2, |
|
232 | nSRAM_BE2 => nSRAM_BE2, | |
233 | nSRAM_BE3 => nSRAM_BE3, |
|
233 | nSRAM_BE3 => nSRAM_BE3, | |
234 | nSRAM_WE => nSRAM_WE, |
|
234 | nSRAM_WE => nSRAM_WE, | |
235 | nSRAM_CE => nSRAM_CE_s, |
|
235 | nSRAM_CE => nSRAM_CE_s, | |
236 | nSRAM_OE => nSRAM_OE, |
|
236 | nSRAM_OE => nSRAM_OE, | |
237 | nSRAM_READY => '0', |
|
237 | nSRAM_READY => '0', | |
238 | SRAM_MBE => OPEN, |
|
238 | SRAM_MBE => OPEN, | |
239 |
|
239 | |||
240 | apbi_ext => apbi_ext, |
|
240 | apbi_ext => apbi_ext, | |
241 | apbo_ext => apbo_ext, |
|
241 | apbo_ext => apbo_ext, | |
242 | ahbi_s_ext => ahbi_s_ext, |
|
242 | ahbi_s_ext => ahbi_s_ext, | |
243 | ahbo_s_ext => ahbo_s_ext, |
|
243 | ahbo_s_ext => ahbo_s_ext, | |
244 | ahbi_m_ext => ahbi_m_ext, |
|
244 | ahbi_m_ext => ahbi_m_ext, | |
245 | ahbo_m_ext => ahbo_m_ext); |
|
245 | ahbo_m_ext => ahbo_m_ext); | |
246 |
|
246 | |||
247 |
|
247 | |||
248 | nSRAM_CE <= nSRAM_CE_s(0); |
|
248 | nSRAM_CE <= nSRAM_CE_s(0); | |
249 |
|
249 | |||
250 | ------------------------------------------------------------------------------- |
|
250 | ------------------------------------------------------------------------------- | |
251 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
251 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
252 | ------------------------------------------------------------------------------- |
|
252 | ------------------------------------------------------------------------------- | |
253 |
apb_lfr_ |
|
253 | apb_lfr_management_1 : apb_lfr_management | |
254 | GENERIC MAP ( |
|
254 | GENERIC MAP ( | |
255 | pindex => 6, |
|
255 | pindex => 6, | |
256 | paddr => 6, |
|
256 | paddr => 6, | |
257 | pmask => 16#fff#, |
|
257 | pmask => 16#fff#, | |
258 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
258 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
259 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
259 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
260 | PORT MAP ( |
|
260 | PORT MAP ( | |
261 | clk25MHz => clk_25, |
|
261 | clk25MHz => clk_25, | |
262 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
262 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
263 | resetn => rstn, |
|
263 | resetn => rstn, | |
264 | grspw_tick => swno.tickout, |
|
264 | grspw_tick => swno.tickout, | |
265 | apbi => apbi_ext, |
|
265 | apbi => apbi_ext, | |
266 | apbo => apbo_ext(6), |
|
266 | apbo => apbo_ext(6), | |
|
267 | ||||
|
268 | HK_sample => sample_s(8), | |||
|
269 | HK_val => sample_val, | |||
|
270 | HK_sel => HK_SEL, | |||
|
271 | ||||
267 |
|
|
272 | coarse_time => coarse_time, | |
268 | fine_time => fine_time, |
|
273 | fine_time => fine_time, | |
269 | LFR_soft_rstn => LFR_soft_rstn |
|
274 | LFR_soft_rstn => LFR_soft_rstn | |
270 | ); |
|
275 | ); | |
271 |
|
276 | |||
272 | ----------------------------------------------------------------------- |
|
277 | ----------------------------------------------------------------------- | |
273 | --- SpaceWire -------------------------------------------------------- |
|
278 | --- SpaceWire -------------------------------------------------------- | |
274 | ----------------------------------------------------------------------- |
|
279 | ----------------------------------------------------------------------- | |
275 |
|
280 | |||
276 | -- SPW_EN <= '1'; |
|
281 | -- SPW_EN <= '1'; | |
277 |
|
282 | |||
278 | spw_clk <= clk_50_s; |
|
283 | spw_clk <= clk_50_s; | |
279 | spw_rxtxclk <= spw_clk; |
|
284 | spw_rxtxclk <= spw_clk; | |
280 | spw_rxclkn <= NOT spw_rxtxclk; |
|
285 | spw_rxclkn <= NOT spw_rxtxclk; | |
281 |
|
286 | |||
282 | -- PADS for SPW1 |
|
287 | -- PADS for SPW1 | |
283 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
288 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
284 | PORT MAP (spw1_din, dtmp(0)); |
|
289 | PORT MAP (spw1_din, dtmp(0)); | |
285 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
290 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
286 | PORT MAP (spw1_sin, stmp(0)); |
|
291 | PORT MAP (spw1_sin, stmp(0)); | |
287 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
292 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
288 | PORT MAP (spw1_dout, swno.d(0)); |
|
293 | PORT MAP (spw1_dout, swno.d(0)); | |
289 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
294 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
290 | PORT MAP (spw1_sout, swno.s(0)); |
|
295 | PORT MAP (spw1_sout, swno.s(0)); | |
291 | -- PADS FOR SPW2 |
|
296 | -- PADS FOR SPW2 | |
292 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
297 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
293 | PORT MAP (spw2_din, dtmp(1)); |
|
298 | PORT MAP (spw2_din, dtmp(1)); | |
294 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
299 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
295 | PORT MAP (spw2_sin, stmp(1)); |
|
300 | PORT MAP (spw2_sin, stmp(1)); | |
296 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
301 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
297 | PORT MAP (spw2_dout, swno.d(1)); |
|
302 | PORT MAP (spw2_dout, swno.d(1)); | |
298 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
303 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
299 | PORT MAP (spw2_sout, swno.s(1)); |
|
304 | PORT MAP (spw2_sout, swno.s(1)); | |
300 |
|
305 | |||
301 | -- GRSPW PHY |
|
306 | -- GRSPW PHY | |
302 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
307 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
303 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
308 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
304 | spw_phy0 : grspw_phy |
|
309 | spw_phy0 : grspw_phy | |
305 | GENERIC MAP( |
|
310 | GENERIC MAP( | |
306 | tech => apa3e, |
|
311 | tech => apa3e, | |
307 | rxclkbuftype => 1, |
|
312 | rxclkbuftype => 1, | |
308 | scantest => 0) |
|
313 | scantest => 0) | |
309 | PORT MAP( |
|
314 | PORT MAP( | |
310 | rxrst => swno.rxrst, |
|
315 | rxrst => swno.rxrst, | |
311 | di => dtmp(j), |
|
316 | di => dtmp(j), | |
312 | si => stmp(j), |
|
317 | si => stmp(j), | |
313 | rxclko => spw_rxclk(j), |
|
318 | rxclko => spw_rxclk(j), | |
314 | do => swni.d(j), |
|
319 | do => swni.d(j), | |
315 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
320 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
316 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
321 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
317 | END GENERATE spw_inputloop; |
|
322 | END GENERATE spw_inputloop; | |
318 |
|
323 | |||
319 | -- SPW core |
|
324 | -- SPW core | |
320 | sw0 : grspwm GENERIC MAP( |
|
325 | sw0 : grspwm GENERIC MAP( | |
321 | tech => apa3e, |
|
326 | tech => apa3e, | |
322 | hindex => 1, |
|
327 | hindex => 1, | |
323 | pindex => 5, |
|
328 | pindex => 5, | |
324 | paddr => 5, |
|
329 | paddr => 5, | |
325 | pirq => 11, |
|
330 | pirq => 11, | |
326 | sysfreq => 25000, -- CPU_FREQ |
|
331 | sysfreq => 25000, -- CPU_FREQ | |
327 | rmap => 1, |
|
332 | rmap => 1, | |
328 | rmapcrc => 1, |
|
333 | rmapcrc => 1, | |
329 | fifosize1 => 16, |
|
334 | fifosize1 => 16, | |
330 | fifosize2 => 16, |
|
335 | fifosize2 => 16, | |
331 | rxclkbuftype => 1, |
|
336 | rxclkbuftype => 1, | |
332 | rxunaligned => 0, |
|
337 | rxunaligned => 0, | |
333 | rmapbufs => 4, |
|
338 | rmapbufs => 4, | |
334 | ft => 0, |
|
339 | ft => 0, | |
335 | netlist => 0, |
|
340 | netlist => 0, | |
336 | ports => 2, |
|
341 | ports => 2, | |
337 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
342 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
338 | memtech => apa3e, |
|
343 | memtech => apa3e, | |
339 | destkey => 2, |
|
344 | destkey => 2, | |
340 | spwcore => 1 |
|
345 | spwcore => 1 | |
341 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
346 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
342 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
347 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
343 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
348 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
344 | ) |
|
349 | ) | |
345 | PORT MAP(rstn, clk_25, spw_rxclk(0), |
|
350 | PORT MAP(rstn, clk_25, spw_rxclk(0), | |
346 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
351 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
347 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
352 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
348 | swni, swno); |
|
353 | swni, swno); | |
349 |
|
354 | |||
350 | swni.tickin <= '0'; |
|
355 | swni.tickin <= '0'; | |
351 | swni.rmapen <= '1'; |
|
356 | swni.rmapen <= '1'; | |
352 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
357 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
353 | swni.tickinraw <= '0'; |
|
358 | swni.tickinraw <= '0'; | |
354 | swni.timein <= (OTHERS => '0'); |
|
359 | swni.timein <= (OTHERS => '0'); | |
355 | swni.dcrstval <= (OTHERS => '0'); |
|
360 | swni.dcrstval <= (OTHERS => '0'); | |
356 | swni.timerrstval <= (OTHERS => '0'); |
|
361 | swni.timerrstval <= (OTHERS => '0'); | |
357 |
|
362 | |||
358 | ------------------------------------------------------------------------------- |
|
363 | ------------------------------------------------------------------------------- | |
359 | -- LFR ------------------------------------------------------------------------ |
|
364 | -- LFR ------------------------------------------------------------------------ | |
360 | ------------------------------------------------------------------------------- |
|
365 | ------------------------------------------------------------------------------- | |
361 | LFR_rstn <= LFR_soft_rstn AND rstn; |
|
366 | LFR_rstn <= LFR_soft_rstn AND rstn; | |
362 |
|
367 | |||
363 | lpp_lfr_1 : lpp_lfr |
|
368 | lpp_lfr_1 : lpp_lfr | |
364 | GENERIC MAP ( |
|
369 | GENERIC MAP ( | |
365 | Mem_use => use_RAM, |
|
370 | Mem_use => use_RAM, | |
366 | nb_data_by_buffer_size => 32, |
|
371 | nb_data_by_buffer_size => 32, | |
367 | --nb_word_by_buffer_size => 30, |
|
372 | --nb_word_by_buffer_size => 30, | |
368 | nb_snapshot_param_size => 32, |
|
373 | nb_snapshot_param_size => 32, | |
369 | delta_vector_size => 32, |
|
374 | delta_vector_size => 32, | |
370 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
375 | delta_vector_size_f0_2 => 7, -- log2(96) | |
371 | pindex => 15, |
|
376 | pindex => 15, | |
372 | paddr => 15, |
|
377 | paddr => 15, | |
373 | pmask => 16#fff#, |
|
378 | pmask => 16#fff#, | |
374 | pirq_ms => 6, |
|
379 | pirq_ms => 6, | |
375 | pirq_wfp => 14, |
|
380 | pirq_wfp => 14, | |
376 | hindex => 2, |
|
381 | hindex => 2, | |
377 |
top_lfr_version => X"0101 |
|
382 | top_lfr_version => X"010131") -- aa.bb.cc version | |
378 | -- AA : BOARD NUMBER |
|
383 | -- AA : BOARD NUMBER | |
379 | -- 0 => MINI_LFR |
|
384 | -- 0 => MINI_LFR | |
380 | -- 1 => EM |
|
385 | -- 1 => EM | |
381 | PORT MAP ( |
|
386 | PORT MAP ( | |
382 | clk => clk_25, |
|
387 | clk => clk_25, | |
383 | rstn => LFR_rstn, |
|
388 | rstn => LFR_rstn, | |
384 | sample_B => sample_s(2 DOWNTO 0), |
|
389 | sample_B => sample_s(2 DOWNTO 0), | |
385 | sample_E => sample_s(7 DOWNTO 3), |
|
390 | sample_E => sample_s(7 DOWNTO 3), | |
386 | sample_val => sample_val, |
|
391 | sample_val => sample_val, | |
387 | apbi => apbi_ext, |
|
392 | apbi => apbi_ext, | |
388 | apbo => apbo_ext(15), |
|
393 | apbo => apbo_ext(15), | |
389 | ahbi => ahbi_m_ext, |
|
394 | ahbi => ahbi_m_ext, | |
390 | ahbo => ahbo_m_ext(2), |
|
395 | ahbo => ahbo_m_ext(2), | |
391 | coarse_time => coarse_time, |
|
396 | coarse_time => coarse_time, | |
392 | fine_time => fine_time, |
|
397 | fine_time => fine_time, | |
393 | data_shaping_BW => bias_fail_sw, |
|
398 | data_shaping_BW => bias_fail_sw, | |
394 | debug_vector => OPEN, |
|
399 | debug_vector => OPEN, | |
395 | debug_vector_ms => OPEN); --, |
|
400 | debug_vector_ms => OPEN); --, | |
396 | --observation_vector_0 => OPEN, |
|
401 | --observation_vector_0 => OPEN, | |
397 | --observation_vector_1 => OPEN, |
|
402 | --observation_vector_1 => OPEN, | |
398 | --observation_reg => observation_reg); |
|
403 | --observation_reg => observation_reg); | |
399 |
|
404 | |||
400 |
|
405 | |||
401 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
406 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
402 | sample_s(I) <= sample(I) & '0' & '0'; |
|
407 | sample_s(I) <= sample(I) & '0' & '0'; | |
403 | END GENERATE all_sample; |
|
408 | END GENERATE all_sample; | |
404 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
409 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); | |
405 |
|
410 | |||
406 | ----------------------------------------------------------------------------- |
|
411 | ----------------------------------------------------------------------------- | |
407 | -- |
|
412 | -- | |
408 | ----------------------------------------------------------------------------- |
|
413 | ----------------------------------------------------------------------------- | |
409 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
414 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
410 | GENERIC MAP ( |
|
415 | GENERIC MAP ( | |
411 | ChanelCount => 9, |
|
416 | ChanelCount => 9, | |
412 | ncycle_cnv_high => 13, |
|
417 | ncycle_cnv_high => 13, | |
413 | ncycle_cnv => 25, |
|
418 | ncycle_cnv => 25, | |
414 | FILTER_ENABLED => 16#FF#) |
|
419 | FILTER_ENABLED => 16#FF#) | |
415 | PORT MAP ( |
|
420 | PORT MAP ( | |
416 | cnv_clk => clk_24, |
|
421 | cnv_clk => clk_24, | |
417 | cnv_rstn => rstn, |
|
422 | cnv_rstn => rstn, | |
418 | cnv => ADC_smpclk_s, |
|
423 | cnv => ADC_smpclk_s, | |
419 | clk => clk_25, |
|
424 | clk => clk_25, | |
420 | rstn => rstn, |
|
425 | rstn => rstn, | |
421 | ADC_data => ADC_data, |
|
426 | ADC_data => ADC_data, | |
422 | ADC_nOE => ADC_OEB_bar_CH_s, |
|
427 | ADC_nOE => ADC_OEB_bar_CH_s, | |
423 | sample => sample, |
|
428 | sample => sample, | |
424 | sample_val => sample_val); |
|
429 | sample_val => sample_val); | |
425 |
|
430 | |||
426 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
431 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); | |
427 |
|
432 | |||
428 | ADC_smpclk <= ADC_smpclk_s; |
|
433 | ADC_smpclk <= ADC_smpclk_s; | |
429 | HK_smpclk <= ADC_smpclk_s; |
|
434 | HK_smpclk <= ADC_smpclk_s; | |
430 |
|
435 | |||
431 | TAG8 <= ADC_smpclk_s; |
|
436 | TAG8 <= ADC_smpclk_s; | |
432 |
|
437 | |||
433 | ----------------------------------------------------------------------------- |
|
438 | ----------------------------------------------------------------------------- | |
434 | -- HK |
|
439 | -- HK | |
435 | ----------------------------------------------------------------------------- |
|
440 | ----------------------------------------------------------------------------- | |
436 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
441 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); | |
437 |
|
442 | |||
438 | lpp_lfr_hk_1: lpp_lfr_hk |
|
|||
439 | GENERIC MAP ( |
|
|||
440 | pindex => 7, |
|
|||
441 | paddr => 7, |
|
|||
442 | pmask => 16#fff#) |
|
|||
443 | PORT MAP ( |
|
|||
444 | clk => clk_25, |
|
|||
445 | rstn => rstn, |
|
|||
446 |
|
||||
447 | apbi => apbi_ext, |
|
|||
448 | apbo => apbo_ext(7), |
|
|||
449 |
|
||||
450 | sample_val => sample_val, |
|
|||
451 | sample => sample_s(8), |
|
|||
452 | HK_SEL => HK_SEL); |
|
|||
453 |
|
||||
454 | END beh; |
|
443 | END beh; |
@@ -1,746 +1,733 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
|
31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
|
32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
|
33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
|
34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
|
35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
|
36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
|
37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
|
38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
|
43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
|
44 | USE lpp.general_purpose.ALL; | |
45 |
USE lpp.lpp_lfr_ |
|
45 | USE lpp.lpp_lfr_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
|
47 | |||
48 | ENTITY MINI_LFR_top IS |
|
48 | ENTITY MINI_LFR_top IS | |
49 |
|
49 | |||
50 | PORT ( |
|
50 | PORT ( | |
51 | clk_50 : IN STD_LOGIC; |
|
51 | clk_50 : IN STD_LOGIC; | |
52 | clk_49 : IN STD_LOGIC; |
|
52 | clk_49 : IN STD_LOGIC; | |
53 | reset : IN STD_LOGIC; |
|
53 | reset : IN STD_LOGIC; | |
54 | --BPs |
|
54 | --BPs | |
55 | BP0 : IN STD_LOGIC; |
|
55 | BP0 : IN STD_LOGIC; | |
56 | BP1 : IN STD_LOGIC; |
|
56 | BP1 : IN STD_LOGIC; | |
57 | --LEDs |
|
57 | --LEDs | |
58 | LED0 : OUT STD_LOGIC; |
|
58 | LED0 : OUT STD_LOGIC; | |
59 | LED1 : OUT STD_LOGIC; |
|
59 | LED1 : OUT STD_LOGIC; | |
60 | LED2 : OUT STD_LOGIC; |
|
60 | LED2 : OUT STD_LOGIC; | |
61 | --UARTs |
|
61 | --UARTs | |
62 | TXD1 : IN STD_LOGIC; |
|
62 | TXD1 : IN STD_LOGIC; | |
63 | RXD1 : OUT STD_LOGIC; |
|
63 | RXD1 : OUT STD_LOGIC; | |
64 | nCTS1 : OUT STD_LOGIC; |
|
64 | nCTS1 : OUT STD_LOGIC; | |
65 | nRTS1 : IN STD_LOGIC; |
|
65 | nRTS1 : IN STD_LOGIC; | |
66 |
|
66 | |||
67 | TXD2 : IN STD_LOGIC; |
|
67 | TXD2 : IN STD_LOGIC; | |
68 | RXD2 : OUT STD_LOGIC; |
|
68 | RXD2 : OUT STD_LOGIC; | |
69 | nCTS2 : OUT STD_LOGIC; |
|
69 | nCTS2 : OUT STD_LOGIC; | |
70 | nDTR2 : IN STD_LOGIC; |
|
70 | nDTR2 : IN STD_LOGIC; | |
71 | nRTS2 : IN STD_LOGIC; |
|
71 | nRTS2 : IN STD_LOGIC; | |
72 | nDCD2 : OUT STD_LOGIC; |
|
72 | nDCD2 : OUT STD_LOGIC; | |
73 |
|
73 | |||
74 | --EXT CONNECTOR |
|
74 | --EXT CONNECTOR | |
75 | IO0 : INOUT STD_LOGIC; |
|
75 | IO0 : INOUT STD_LOGIC; | |
76 | IO1 : INOUT STD_LOGIC; |
|
76 | IO1 : INOUT STD_LOGIC; | |
77 | IO2 : INOUT STD_LOGIC; |
|
77 | IO2 : INOUT STD_LOGIC; | |
78 | IO3 : INOUT STD_LOGIC; |
|
78 | IO3 : INOUT STD_LOGIC; | |
79 | IO4 : INOUT STD_LOGIC; |
|
79 | IO4 : INOUT STD_LOGIC; | |
80 | IO5 : INOUT STD_LOGIC; |
|
80 | IO5 : INOUT STD_LOGIC; | |
81 | IO6 : INOUT STD_LOGIC; |
|
81 | IO6 : INOUT STD_LOGIC; | |
82 | IO7 : INOUT STD_LOGIC; |
|
82 | IO7 : INOUT STD_LOGIC; | |
83 | IO8 : INOUT STD_LOGIC; |
|
83 | IO8 : INOUT STD_LOGIC; | |
84 | IO9 : INOUT STD_LOGIC; |
|
84 | IO9 : INOUT STD_LOGIC; | |
85 | IO10 : INOUT STD_LOGIC; |
|
85 | IO10 : INOUT STD_LOGIC; | |
86 | IO11 : INOUT STD_LOGIC; |
|
86 | IO11 : INOUT STD_LOGIC; | |
87 |
|
87 | |||
88 | --SPACE WIRE |
|
88 | --SPACE WIRE | |
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
91 | SPW_NOM_SIN : IN STD_LOGIC; | |
92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
95 | SPW_RED_SIN : IN STD_LOGIC; |
|
95 | SPW_RED_SIN : IN STD_LOGIC; | |
96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
98 | -- MINI LFR ADC INPUTS |
|
98 | -- MINI LFR ADC INPUTS | |
99 | ADC_nCS : OUT STD_LOGIC; |
|
99 | ADC_nCS : OUT STD_LOGIC; | |
100 | ADC_CLK : OUT STD_LOGIC; |
|
100 | ADC_CLK : OUT STD_LOGIC; | |
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 |
|
102 | |||
103 | -- SRAM |
|
103 | -- SRAM | |
104 | SRAM_nWE : OUT STD_LOGIC; |
|
104 | SRAM_nWE : OUT STD_LOGIC; | |
105 | SRAM_CE : OUT STD_LOGIC; |
|
105 | SRAM_CE : OUT STD_LOGIC; | |
106 | SRAM_nOE : OUT STD_LOGIC; |
|
106 | SRAM_nOE : OUT STD_LOGIC; | |
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
110 | ); |
|
110 | ); | |
111 |
|
111 | |||
112 | END MINI_LFR_top; |
|
112 | END MINI_LFR_top; | |
113 |
|
113 | |||
114 |
|
114 | |||
115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
119 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
122 | -- |
|
122 | -- | |
123 | SIGNAL errorn : STD_LOGIC; |
|
123 | SIGNAL errorn : STD_LOGIC; | |
124 | -- UART AHB --------------------------------------------------------------- |
|
124 | -- UART AHB --------------------------------------------------------------- | |
125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
127 |
|
127 | |||
128 | -- UART APB --------------------------------------------------------------- |
|
128 | -- UART APB --------------------------------------------------------------- | |
129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
131 | -- |
|
131 | -- | |
132 | SIGNAL I00_s : STD_LOGIC; |
|
132 | SIGNAL I00_s : STD_LOGIC; | |
133 |
|
133 | |||
134 | -- CONSTANTS |
|
134 | -- CONSTANTS | |
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
136 | -- |
|
136 | -- | |
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
140 |
|
140 | |||
141 | SIGNAL apbi_ext : apb_slv_in_type; |
|
141 | SIGNAL apbi_ext : apb_slv_in_type; | |
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); |
|
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); | |
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); |
|
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); | |
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); |
|
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); | |
147 |
|
147 | |||
148 | -- Spacewire signals |
|
148 | -- Spacewire signals | |
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
154 | SIGNAL spw_clk : STD_LOGIC; |
|
154 | SIGNAL spw_clk : STD_LOGIC; | |
155 | SIGNAL swni : grspw_in_type; |
|
155 | SIGNAL swni : grspw_in_type; | |
156 | SIGNAL swno : grspw_out_type; |
|
156 | SIGNAL swno : grspw_out_type; | |
157 | -- SIGNAL clkmn : STD_ULOGIC; |
|
157 | -- SIGNAL clkmn : STD_ULOGIC; | |
158 | -- SIGNAL txclk : STD_ULOGIC; |
|
158 | -- SIGNAL txclk : STD_ULOGIC; | |
159 |
|
159 | |||
160 | --GPIO |
|
160 | --GPIO | |
161 | SIGNAL gpioi : gpio_in_type; |
|
161 | SIGNAL gpioi : gpio_in_type; | |
162 | SIGNAL gpioo : gpio_out_type; |
|
162 | SIGNAL gpioo : gpio_out_type; | |
163 |
|
163 | |||
164 | -- AD Converter ADS7886 |
|
164 | -- AD Converter ADS7886 | |
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
|
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
167 | SIGNAL sample_val : STD_LOGIC; |
|
167 | SIGNAL sample_val : STD_LOGIC; | |
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
171 |
|
171 | |||
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
173 |
|
173 | |||
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
177 | ----------------------------------------------------------------------------- |
|
177 | ----------------------------------------------------------------------------- | |
178 |
|
178 | |||
179 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
|
179 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
180 | SIGNAL LFR_rstn : STD_LOGIC; |
|
180 | SIGNAL LFR_rstn : STD_LOGIC; | |
181 |
|
181 | |||
182 |
|
182 | |||
183 | SIGNAL rstn_25 : STD_LOGIC; |
|
183 | SIGNAL rstn_25 : STD_LOGIC; | |
184 | SIGNAL rstn_25_d1 : STD_LOGIC; |
|
184 | SIGNAL rstn_25_d1 : STD_LOGIC; | |
185 | SIGNAL rstn_25_d2 : STD_LOGIC; |
|
185 | SIGNAL rstn_25_d2 : STD_LOGIC; | |
186 | SIGNAL rstn_25_d3 : STD_LOGIC; |
|
186 | SIGNAL rstn_25_d3 : STD_LOGIC; | |
187 |
|
187 | |||
188 | SIGNAL rstn_50 : STD_LOGIC; |
|
188 | SIGNAL rstn_50 : STD_LOGIC; | |
189 | SIGNAL rstn_50_d1 : STD_LOGIC; |
|
189 | SIGNAL rstn_50_d1 : STD_LOGIC; | |
190 | SIGNAL rstn_50_d2 : STD_LOGIC; |
|
190 | SIGNAL rstn_50_d2 : STD_LOGIC; | |
191 | SIGNAL rstn_50_d3 : STD_LOGIC; |
|
191 | SIGNAL rstn_50_d3 : STD_LOGIC; | |
192 |
|
192 | |||
193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
195 |
|
195 | |||
196 | -- |
|
196 | -- | |
197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
198 |
|
198 | |||
199 | -- |
|
199 | -- | |
200 | SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
200 | SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
201 | SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0); |
|
201 | SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0); | |
202 |
|
202 | |||
203 | BEGIN -- beh |
|
203 | BEGIN -- beh | |
204 |
|
204 | |||
205 | ----------------------------------------------------------------------------- |
|
205 | ----------------------------------------------------------------------------- | |
206 | -- CLK |
|
206 | -- CLK | |
207 | ----------------------------------------------------------------------------- |
|
207 | ----------------------------------------------------------------------------- | |
208 |
|
208 | |||
209 | --PROCESS(clk_50) |
|
209 | --PROCESS(clk_50) | |
210 | --BEGIN |
|
210 | --BEGIN | |
211 | -- IF clk_50'EVENT AND clk_50 = '1' THEN |
|
211 | -- IF clk_50'EVENT AND clk_50 = '1' THEN | |
212 | -- clk_50_s <= NOT clk_50_s; |
|
212 | -- clk_50_s <= NOT clk_50_s; | |
213 | -- END IF; |
|
213 | -- END IF; | |
214 | --END PROCESS; |
|
214 | --END PROCESS; | |
215 |
|
215 | |||
216 | --PROCESS(clk_50_s) |
|
216 | --PROCESS(clk_50_s) | |
217 | --BEGIN |
|
217 | --BEGIN | |
218 | -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
218 | -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
219 | -- clk_25 <= NOT clk_25; |
|
219 | -- clk_25 <= NOT clk_25; | |
220 | -- END IF; |
|
220 | -- END IF; | |
221 | --END PROCESS; |
|
221 | --END PROCESS; | |
222 |
|
222 | |||
223 | --PROCESS(clk_49) |
|
223 | --PROCESS(clk_49) | |
224 | --BEGIN |
|
224 | --BEGIN | |
225 | -- IF clk_49'EVENT AND clk_49 = '1' THEN |
|
225 | -- IF clk_49'EVENT AND clk_49 = '1' THEN | |
226 | -- clk_24 <= NOT clk_24; |
|
226 | -- clk_24 <= NOT clk_24; | |
227 | -- END IF; |
|
227 | -- END IF; | |
228 | --END PROCESS; |
|
228 | --END PROCESS; | |
229 |
|
229 | |||
230 | --PROCESS(clk_25) |
|
230 | --PROCESS(clk_25) | |
231 | --BEGIN |
|
231 | --BEGIN | |
232 | -- IF clk_25'EVENT AND clk_25 = '1' THEN |
|
232 | -- IF clk_25'EVENT AND clk_25 = '1' THEN | |
233 | -- rstn_25 <= reset; |
|
233 | -- rstn_25 <= reset; | |
234 | -- END IF; |
|
234 | -- END IF; | |
235 | --END PROCESS; |
|
235 | --END PROCESS; | |
236 |
|
236 | |||
237 | PROCESS (clk_50, reset) |
|
237 | PROCESS (clk_50, reset) | |
238 | BEGIN -- PROCESS |
|
238 | BEGIN -- PROCESS | |
239 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
239 | IF reset = '0' THEN -- asynchronous reset (active low) | |
240 | clk_50_s <= '0'; |
|
240 | clk_50_s <= '0'; | |
241 | rstn_50 <= '0'; |
|
241 | rstn_50 <= '0'; | |
242 | rstn_50_d1 <= '0'; |
|
242 | rstn_50_d1 <= '0'; | |
243 | rstn_50_d2 <= '0'; |
|
243 | rstn_50_d2 <= '0'; | |
244 | rstn_50_d3 <= '0'; |
|
244 | rstn_50_d3 <= '0'; | |
245 |
|
245 | |||
246 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge |
|
246 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge | |
247 | clk_50_s <= NOT clk_50_s; |
|
247 | clk_50_s <= NOT clk_50_s; | |
248 | rstn_50_d1 <= '1'; |
|
248 | rstn_50_d1 <= '1'; | |
249 | rstn_50_d2 <= rstn_50_d1; |
|
249 | rstn_50_d2 <= rstn_50_d1; | |
250 | rstn_50_d3 <= rstn_50_d2; |
|
250 | rstn_50_d3 <= rstn_50_d2; | |
251 | rstn_50 <= rstn_50_d3; |
|
251 | rstn_50 <= rstn_50_d3; | |
252 | END IF; |
|
252 | END IF; | |
253 | END PROCESS; |
|
253 | END PROCESS; | |
254 |
|
254 | |||
255 | PROCESS (clk_50_s, rstn_50) |
|
255 | PROCESS (clk_50_s, rstn_50) | |
256 | BEGIN -- PROCESS |
|
256 | BEGIN -- PROCESS | |
257 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
|
257 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |
258 | clk_25 <= '0'; |
|
258 | clk_25 <= '0'; | |
259 | rstn_25 <= '0'; |
|
259 | rstn_25 <= '0'; | |
260 | rstn_25_d1 <= '0'; |
|
260 | rstn_25_d1 <= '0'; | |
261 | rstn_25_d2 <= '0'; |
|
261 | rstn_25_d2 <= '0'; | |
262 | rstn_25_d3 <= '0'; |
|
262 | rstn_25_d3 <= '0'; | |
263 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge |
|
263 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge | |
264 | clk_25 <= NOT clk_25; |
|
264 | clk_25 <= NOT clk_25; | |
265 | rstn_25_d1 <= '1'; |
|
265 | rstn_25_d1 <= '1'; | |
266 | rstn_25_d2 <= rstn_25_d1; |
|
266 | rstn_25_d2 <= rstn_25_d1; | |
267 | rstn_25_d3 <= rstn_25_d2; |
|
267 | rstn_25_d3 <= rstn_25_d2; | |
268 | rstn_25 <= rstn_25_d3; |
|
268 | rstn_25 <= rstn_25_d3; | |
269 | END IF; |
|
269 | END IF; | |
270 | END PROCESS; |
|
270 | END PROCESS; | |
271 |
|
271 | |||
272 | PROCESS (clk_49, reset) |
|
272 | PROCESS (clk_49, reset) | |
273 | BEGIN -- PROCESS |
|
273 | BEGIN -- PROCESS | |
274 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
274 | IF reset = '0' THEN -- asynchronous reset (active low) | |
275 | clk_24 <= '0'; |
|
275 | clk_24 <= '0'; | |
276 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge |
|
276 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
277 | clk_24 <= NOT clk_24; |
|
277 | clk_24 <= NOT clk_24; | |
278 | END IF; |
|
278 | END IF; | |
279 | END PROCESS; |
|
279 | END PROCESS; | |
280 |
|
280 | |||
281 | ----------------------------------------------------------------------------- |
|
281 | ----------------------------------------------------------------------------- | |
282 |
|
282 | |||
283 | PROCESS (clk_25, rstn_25) |
|
283 | PROCESS (clk_25, rstn_25) | |
284 | BEGIN -- PROCESS |
|
284 | BEGIN -- PROCESS | |
285 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
285 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
286 | LED0 <= '0'; |
|
286 | LED0 <= '0'; | |
287 | LED1 <= '0'; |
|
287 | LED1 <= '0'; | |
288 | LED2 <= '0'; |
|
288 | LED2 <= '0'; | |
289 | --IO1 <= '0'; |
|
289 | --IO1 <= '0'; | |
290 | --IO2 <= '1'; |
|
290 | --IO2 <= '1'; | |
291 | --IO3 <= '0'; |
|
291 | --IO3 <= '0'; | |
292 | --IO4 <= '0'; |
|
292 | --IO4 <= '0'; | |
293 | --IO5 <= '0'; |
|
293 | --IO5 <= '0'; | |
294 | --IO6 <= '0'; |
|
294 | --IO6 <= '0'; | |
295 | --IO7 <= '0'; |
|
295 | --IO7 <= '0'; | |
296 | --IO8 <= '0'; |
|
296 | --IO8 <= '0'; | |
297 | --IO9 <= '0'; |
|
297 | --IO9 <= '0'; | |
298 | --IO10 <= '0'; |
|
298 | --IO10 <= '0'; | |
299 | --IO11 <= '0'; |
|
299 | --IO11 <= '0'; | |
300 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
300 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
301 | LED0 <= '0'; |
|
301 | LED0 <= '0'; | |
302 | LED1 <= '1'; |
|
302 | LED1 <= '1'; | |
303 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
303 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
304 | --IO1 <= '1'; |
|
304 | --IO1 <= '1'; | |
305 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
305 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
306 | --IO3 <= ADC_SDO(0); |
|
306 | --IO3 <= ADC_SDO(0); | |
307 | --IO4 <= ADC_SDO(1); |
|
307 | --IO4 <= ADC_SDO(1); | |
308 | --IO5 <= ADC_SDO(2); |
|
308 | --IO5 <= ADC_SDO(2); | |
309 | --IO6 <= ADC_SDO(3); |
|
309 | --IO6 <= ADC_SDO(3); | |
310 | --IO7 <= ADC_SDO(4); |
|
310 | --IO7 <= ADC_SDO(4); | |
311 | --IO8 <= ADC_SDO(5); |
|
311 | --IO8 <= ADC_SDO(5); | |
312 | --IO9 <= ADC_SDO(6); |
|
312 | --IO9 <= ADC_SDO(6); | |
313 | --IO10 <= ADC_SDO(7); |
|
313 | --IO10 <= ADC_SDO(7); | |
314 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
314 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
315 | END IF; |
|
315 | END IF; | |
316 | END PROCESS; |
|
316 | END PROCESS; | |
317 |
|
317 | |||
318 | PROCESS (clk_24, rstn_25) |
|
318 | PROCESS (clk_24, rstn_25) | |
319 | BEGIN -- PROCESS |
|
319 | BEGIN -- PROCESS | |
320 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
320 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
321 | I00_s <= '0'; |
|
321 | I00_s <= '0'; | |
322 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
322 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |
323 | I00_s <= NOT I00_s; |
|
323 | I00_s <= NOT I00_s; | |
324 | END IF; |
|
324 | END IF; | |
325 | END PROCESS; |
|
325 | END PROCESS; | |
326 | -- IO0 <= I00_s; |
|
326 | -- IO0 <= I00_s; | |
327 |
|
327 | |||
328 | --UARTs |
|
328 | --UARTs | |
329 | nCTS1 <= '1'; |
|
329 | nCTS1 <= '1'; | |
330 | nCTS2 <= '1'; |
|
330 | nCTS2 <= '1'; | |
331 | nDCD2 <= '1'; |
|
331 | nDCD2 <= '1'; | |
332 |
|
332 | |||
333 | --EXT CONNECTOR |
|
333 | --EXT CONNECTOR | |
334 |
|
334 | |||
335 | --SPACE WIRE |
|
335 | --SPACE WIRE | |
336 |
|
336 | |||
337 | leon3_soc_1 : leon3_soc |
|
337 | leon3_soc_1 : leon3_soc | |
338 | GENERIC MAP ( |
|
338 | GENERIC MAP ( | |
339 | fabtech => apa3e, |
|
339 | fabtech => apa3e, | |
340 | memtech => apa3e, |
|
340 | memtech => apa3e, | |
341 | padtech => inferred, |
|
341 | padtech => inferred, | |
342 | clktech => inferred, |
|
342 | clktech => inferred, | |
343 | disas => 0, |
|
343 | disas => 0, | |
344 | dbguart => 0, |
|
344 | dbguart => 0, | |
345 | pclow => 2, |
|
345 | pclow => 2, | |
346 | clk_freq => 25000, |
|
346 | clk_freq => 25000, | |
347 | NB_CPU => 1, |
|
347 | NB_CPU => 1, | |
348 | ENABLE_FPU => 1, |
|
348 | ENABLE_FPU => 1, | |
349 | FPU_NETLIST => 0, |
|
349 | FPU_NETLIST => 0, | |
350 | ENABLE_DSU => 1, |
|
350 | ENABLE_DSU => 1, | |
351 | ENABLE_AHB_UART => 1, |
|
351 | ENABLE_AHB_UART => 1, | |
352 | ENABLE_APB_UART => 1, |
|
352 | ENABLE_APB_UART => 1, | |
353 | ENABLE_IRQMP => 1, |
|
353 | ENABLE_IRQMP => 1, | |
354 | ENABLE_GPT => 1, |
|
354 | ENABLE_GPT => 1, | |
355 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
355 | NB_AHB_MASTER => NB_AHB_MASTER, | |
356 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
356 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
357 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
357 | NB_APB_SLAVE => NB_APB_SLAVE, | |
358 | ADDRESS_SIZE => 20, |
|
358 | ADDRESS_SIZE => 20, | |
359 | USES_IAP_MEMCTRLR => 0) |
|
359 | USES_IAP_MEMCTRLR => 0) | |
360 | PORT MAP ( |
|
360 | PORT MAP ( | |
361 | clk => clk_25, |
|
361 | clk => clk_25, | |
362 | reset => rstn_25, |
|
362 | reset => rstn_25, | |
363 | errorn => errorn, |
|
363 | errorn => errorn, | |
364 | ahbrxd => TXD1, |
|
364 | ahbrxd => TXD1, | |
365 | ahbtxd => RXD1, |
|
365 | ahbtxd => RXD1, | |
366 | urxd1 => TXD2, |
|
366 | urxd1 => TXD2, | |
367 | utxd1 => RXD2, |
|
367 | utxd1 => RXD2, | |
368 | address => SRAM_A, |
|
368 | address => SRAM_A, | |
369 | data => SRAM_DQ, |
|
369 | data => SRAM_DQ, | |
370 | nSRAM_BE0 => SRAM_nBE(0), |
|
370 | nSRAM_BE0 => SRAM_nBE(0), | |
371 | nSRAM_BE1 => SRAM_nBE(1), |
|
371 | nSRAM_BE1 => SRAM_nBE(1), | |
372 | nSRAM_BE2 => SRAM_nBE(2), |
|
372 | nSRAM_BE2 => SRAM_nBE(2), | |
373 | nSRAM_BE3 => SRAM_nBE(3), |
|
373 | nSRAM_BE3 => SRAM_nBE(3), | |
374 | nSRAM_WE => SRAM_nWE, |
|
374 | nSRAM_WE => SRAM_nWE, | |
375 | nSRAM_CE => SRAM_CE_s, |
|
375 | nSRAM_CE => SRAM_CE_s, | |
376 | nSRAM_OE => SRAM_nOE, |
|
376 | nSRAM_OE => SRAM_nOE, | |
377 | nSRAM_READY => '0', |
|
377 | nSRAM_READY => '0', | |
378 | SRAM_MBE => OPEN, |
|
378 | SRAM_MBE => OPEN, | |
379 | apbi_ext => apbi_ext, |
|
379 | apbi_ext => apbi_ext, | |
380 | apbo_ext => apbo_ext, |
|
380 | apbo_ext => apbo_ext, | |
381 | ahbi_s_ext => ahbi_s_ext, |
|
381 | ahbi_s_ext => ahbi_s_ext, | |
382 | ahbo_s_ext => ahbo_s_ext, |
|
382 | ahbo_s_ext => ahbo_s_ext, | |
383 | ahbi_m_ext => ahbi_m_ext, |
|
383 | ahbi_m_ext => ahbi_m_ext, | |
384 | ahbo_m_ext => ahbo_m_ext); |
|
384 | ahbo_m_ext => ahbo_m_ext); | |
385 |
|
385 | |||
386 | SRAM_CE <= SRAM_CE_s(0); |
|
386 | SRAM_CE <= SRAM_CE_s(0); | |
387 | ------------------------------------------------------------------------------- |
|
387 | ------------------------------------------------------------------------------- | |
388 |
-- APB_LFR_ |
|
388 | -- APB_LFR_MANAGEMENT --------------------------------------------------------- | |
389 | ------------------------------------------------------------------------------- |
|
389 | ------------------------------------------------------------------------------- | |
390 |
apb_lfr_ |
|
390 | apb_lfr_management_1 : apb_lfr_management | |
391 | GENERIC MAP ( |
|
391 | GENERIC MAP ( | |
392 | pindex => 6, |
|
392 | pindex => 6, | |
393 | paddr => 6, |
|
393 | paddr => 6, | |
394 | pmask => 16#fff#, |
|
394 | pmask => 16#fff#, | |
395 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
395 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
396 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
396 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
397 | PORT MAP ( |
|
397 | PORT MAP ( | |
398 | clk25MHz => clk_25, |
|
398 | clk25MHz => clk_25, | |
399 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
399 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
400 | resetn => rstn_25, |
|
400 | resetn => rstn_25, | |
401 | grspw_tick => swno.tickout, |
|
401 | grspw_tick => swno.tickout, | |
402 | apbi => apbi_ext, |
|
402 | apbi => apbi_ext, | |
403 | apbo => apbo_ext(6), |
|
403 | apbo => apbo_ext(6), | |
|
404 | HK_sample => sample_hk, | |||
|
405 | HK_val => sample_val, | |||
|
406 | HK_sel => HK_SEL, | |||
404 |
|
|
407 | coarse_time => coarse_time, | |
405 | fine_time => fine_time, |
|
408 | fine_time => fine_time, | |
406 | LFR_soft_rstn => LFR_soft_rstn |
|
409 | LFR_soft_rstn => LFR_soft_rstn | |
407 | ); |
|
410 | ); | |
408 |
|
411 | |||
409 | ----------------------------------------------------------------------- |
|
412 | ----------------------------------------------------------------------- | |
410 | --- SpaceWire -------------------------------------------------------- |
|
413 | --- SpaceWire -------------------------------------------------------- | |
411 | ----------------------------------------------------------------------- |
|
414 | ----------------------------------------------------------------------- | |
412 |
|
415 | |||
413 | SPW_EN <= '1'; |
|
416 | SPW_EN <= '1'; | |
414 |
|
417 | |||
415 | spw_clk <= clk_50_s; |
|
418 | spw_clk <= clk_50_s; | |
416 | spw_rxtxclk <= spw_clk; |
|
419 | spw_rxtxclk <= spw_clk; | |
417 | spw_rxclkn <= NOT spw_rxtxclk; |
|
420 | spw_rxclkn <= NOT spw_rxtxclk; | |
418 |
|
421 | |||
419 | -- PADS for SPW1 |
|
422 | -- PADS for SPW1 | |
420 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
423 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
421 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
424 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
422 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
425 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
423 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
426 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
424 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
427 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
425 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
428 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
426 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
429 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
427 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
430 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
428 | -- PADS FOR SPW2 |
|
431 | -- PADS FOR SPW2 | |
429 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
432 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
430 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
433 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
431 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
434 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
432 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
435 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
433 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
436 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
434 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
437 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
435 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
438 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
436 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
439 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
437 |
|
440 | |||
438 | -- GRSPW PHY |
|
441 | -- GRSPW PHY | |
439 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
442 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
440 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
443 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
441 | spw_phy0 : grspw_phy |
|
444 | spw_phy0 : grspw_phy | |
442 | GENERIC MAP( |
|
445 | GENERIC MAP( | |
443 | tech => apa3e, |
|
446 | tech => apa3e, | |
444 | rxclkbuftype => 1, |
|
447 | rxclkbuftype => 1, | |
445 | scantest => 0) |
|
448 | scantest => 0) | |
446 | PORT MAP( |
|
449 | PORT MAP( | |
447 | rxrst => swno.rxrst, |
|
450 | rxrst => swno.rxrst, | |
448 | di => dtmp(j), |
|
451 | di => dtmp(j), | |
449 | si => stmp(j), |
|
452 | si => stmp(j), | |
450 | rxclko => spw_rxclk(j), |
|
453 | rxclko => spw_rxclk(j), | |
451 | do => swni.d(j), |
|
454 | do => swni.d(j), | |
452 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
455 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
453 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
456 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
454 | END GENERATE spw_inputloop; |
|
457 | END GENERATE spw_inputloop; | |
455 |
|
458 | |||
456 | swni.rmapnodeaddr <= (OTHERS => '0'); |
|
459 | swni.rmapnodeaddr <= (OTHERS => '0'); | |
457 |
|
460 | |||
458 | -- SPW core |
|
461 | -- SPW core | |
459 | sw0 : grspwm GENERIC MAP( |
|
462 | sw0 : grspwm GENERIC MAP( | |
460 | tech => apa3e, |
|
463 | tech => apa3e, | |
461 | hindex => 1, |
|
464 | hindex => 1, | |
462 | pindex => 5, |
|
465 | pindex => 5, | |
463 | paddr => 5, |
|
466 | paddr => 5, | |
464 | pirq => 11, |
|
467 | pirq => 11, | |
465 | sysfreq => 25000, -- CPU_FREQ |
|
468 | sysfreq => 25000, -- CPU_FREQ | |
466 | rmap => 1, |
|
469 | rmap => 1, | |
467 | rmapcrc => 1, |
|
470 | rmapcrc => 1, | |
468 | fifosize1 => 16, |
|
471 | fifosize1 => 16, | |
469 | fifosize2 => 16, |
|
472 | fifosize2 => 16, | |
470 | rxclkbuftype => 1, |
|
473 | rxclkbuftype => 1, | |
471 | rxunaligned => 0, |
|
474 | rxunaligned => 0, | |
472 | rmapbufs => 4, |
|
475 | rmapbufs => 4, | |
473 | ft => 0, |
|
476 | ft => 0, | |
474 | netlist => 0, |
|
477 | netlist => 0, | |
475 | ports => 2, |
|
478 | ports => 2, | |
476 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
479 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
477 | memtech => apa3e, |
|
480 | memtech => apa3e, | |
478 | destkey => 2, |
|
481 | destkey => 2, | |
479 | spwcore => 1 |
|
482 | spwcore => 1 | |
480 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
483 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
481 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
484 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
482 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
485 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
483 | ) |
|
486 | ) | |
484 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
487 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
485 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
488 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
486 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
489 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
487 | swni, swno); |
|
490 | swni, swno); | |
488 |
|
491 | |||
489 | swni.tickin <= '0'; |
|
492 | swni.tickin <= '0'; | |
490 | swni.rmapen <= '1'; |
|
493 | swni.rmapen <= '1'; | |
491 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
494 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
492 | swni.tickinraw <= '0'; |
|
495 | swni.tickinraw <= '0'; | |
493 | swni.timein <= (OTHERS => '0'); |
|
496 | swni.timein <= (OTHERS => '0'); | |
494 | swni.dcrstval <= (OTHERS => '0'); |
|
497 | swni.dcrstval <= (OTHERS => '0'); | |
495 | swni.timerrstval <= (OTHERS => '0'); |
|
498 | swni.timerrstval <= (OTHERS => '0'); | |
496 |
|
499 | |||
497 | ------------------------------------------------------------------------------- |
|
500 | ------------------------------------------------------------------------------- | |
498 | -- LFR ------------------------------------------------------------------------ |
|
501 | -- LFR ------------------------------------------------------------------------ | |
499 | ------------------------------------------------------------------------------- |
|
502 | ------------------------------------------------------------------------------- | |
500 |
|
503 | |||
501 |
|
504 | |||
502 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
505 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
503 | --LFR_rstn <= rstn_25; |
|
506 | --LFR_rstn <= rstn_25; | |
504 |
|
507 | |||
505 | lpp_lfr_1 : lpp_lfr |
|
508 | lpp_lfr_1 : lpp_lfr | |
506 | GENERIC MAP ( |
|
509 | GENERIC MAP ( | |
507 | Mem_use => use_RAM, |
|
510 | Mem_use => use_RAM, | |
508 | nb_data_by_buffer_size => 32, |
|
511 | nb_data_by_buffer_size => 32, | |
509 | nb_snapshot_param_size => 32, |
|
512 | nb_snapshot_param_size => 32, | |
510 | delta_vector_size => 32, |
|
513 | delta_vector_size => 32, | |
511 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
514 | delta_vector_size_f0_2 => 7, -- log2(96) | |
512 | pindex => 15, |
|
515 | pindex => 15, | |
513 | paddr => 15, |
|
516 | paddr => 15, | |
514 | pmask => 16#fff#, |
|
517 | pmask => 16#fff#, | |
515 | pirq_ms => 6, |
|
518 | pirq_ms => 6, | |
516 | pirq_wfp => 14, |
|
519 | pirq_wfp => 14, | |
517 | hindex => 2, |
|
520 | hindex => 2, | |
518 |
top_lfr_version => X"0001 |
|
521 | top_lfr_version => X"000131") -- aa.bb.cc version | |
519 | PORT MAP ( |
|
522 | PORT MAP ( | |
520 | clk => clk_25, |
|
523 | clk => clk_25, | |
521 | rstn => LFR_rstn, |
|
524 | rstn => LFR_rstn, | |
522 | sample_B => sample_s(2 DOWNTO 0), |
|
525 | sample_B => sample_s(2 DOWNTO 0), | |
523 | sample_E => sample_s(7 DOWNTO 3), |
|
526 | sample_E => sample_s(7 DOWNTO 3), | |
524 | sample_val => sample_val, |
|
527 | sample_val => sample_val, | |
525 | apbi => apbi_ext, |
|
528 | apbi => apbi_ext, | |
526 | apbo => apbo_ext(15), |
|
529 | apbo => apbo_ext(15), | |
527 | ahbi => ahbi_m_ext, |
|
530 | ahbi => ahbi_m_ext, | |
528 | ahbo => ahbo_m_ext(2), |
|
531 | ahbo => ahbo_m_ext(2), | |
529 | coarse_time => coarse_time, |
|
532 | coarse_time => coarse_time, | |
530 | fine_time => fine_time, |
|
533 | fine_time => fine_time, | |
531 | data_shaping_BW => bias_fail_sw_sig, |
|
534 | data_shaping_BW => bias_fail_sw_sig, | |
532 | debug_vector => lfr_debug_vector, |
|
535 | debug_vector => lfr_debug_vector, | |
533 | debug_vector_ms => lfr_debug_vector_ms |
|
536 | debug_vector_ms => lfr_debug_vector_ms | |
534 | ); |
|
537 | ); | |
535 |
|
538 | |||
536 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; |
|
539 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; | |
537 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); |
|
540 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); | |
538 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; |
|
541 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; | |
539 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; |
|
542 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; | |
540 | IO0 <= rstn_25; |
|
543 | IO0 <= rstn_25; | |
541 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid |
|
544 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid | |
542 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready |
|
545 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready | |
543 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full |
|
546 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full | |
544 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full |
|
547 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full | |
545 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 |
|
548 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 | |
546 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 |
|
549 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 | |
547 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 |
|
550 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 | |
548 |
|
551 | |||
549 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
552 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
550 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
553 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
551 | END GENERATE all_sample; |
|
554 | END GENERATE all_sample; | |
552 |
|
555 | |||
553 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
556 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
554 | GENERIC MAP( |
|
557 | GENERIC MAP( | |
555 | ChannelCount => 8, |
|
558 | ChannelCount => 8, | |
556 | SampleNbBits => 14, |
|
559 | SampleNbBits => 14, | |
557 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
560 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
558 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
561 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
559 | PORT MAP ( |
|
562 | PORT MAP ( | |
560 | -- CONV |
|
563 | -- CONV | |
561 | cnv_clk => clk_24, |
|
564 | cnv_clk => clk_24, | |
562 | cnv_rstn => rstn_25, |
|
565 | cnv_rstn => rstn_25, | |
563 | cnv => ADC_nCS_sig, |
|
566 | cnv => ADC_nCS_sig, | |
564 | -- DATA |
|
567 | -- DATA | |
565 | clk => clk_25, |
|
568 | clk => clk_25, | |
566 | rstn => rstn_25, |
|
569 | rstn => rstn_25, | |
567 | sck => ADC_CLK_sig, |
|
570 | sck => ADC_CLK_sig, | |
568 | sdo => ADC_SDO_sig, |
|
571 | sdo => ADC_SDO_sig, | |
569 | -- SAMPLE |
|
572 | -- SAMPLE | |
570 | sample => sample, |
|
573 | sample => sample, | |
571 | sample_val => sample_val); |
|
574 | sample_val => sample_val); | |
572 |
|
575 | |||
573 | --IO10 <= ADC_SDO_sig(5); |
|
576 | --IO10 <= ADC_SDO_sig(5); | |
574 | --IO9 <= ADC_SDO_sig(4); |
|
577 | --IO9 <= ADC_SDO_sig(4); | |
575 | --IO8 <= ADC_SDO_sig(3); |
|
578 | --IO8 <= ADC_SDO_sig(3); | |
576 |
|
579 | |||
577 | ADC_nCS <= ADC_nCS_sig; |
|
580 | ADC_nCS <= ADC_nCS_sig; | |
578 | ADC_CLK <= ADC_CLK_sig; |
|
581 | ADC_CLK <= ADC_CLK_sig; | |
579 | ADC_SDO_sig <= ADC_SDO; |
|
582 | ADC_SDO_sig <= ADC_SDO; | |
580 |
|
583 | |||
581 | lpp_lfr_hk_1: lpp_lfr_hk |
|
|||
582 | GENERIC MAP ( |
|
|||
583 | pindex => 7, |
|
|||
584 | paddr => 7, |
|
|||
585 | pmask => 16#fff#) |
|
|||
586 | PORT MAP ( |
|
|||
587 | clk => clk_25, |
|
|||
588 | rstn => rstn_25, |
|
|||
589 |
|
||||
590 | apbi => apbi_ext, |
|
|||
591 | apbo => apbo_ext(7), |
|
|||
592 |
|
||||
593 | sample_val => sample_val, |
|
|||
594 | sample => sample_hk, |
|
|||
595 | HK_SEL => HK_SEL); |
|
|||
596 |
|
||||
597 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE |
|
584 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE | |
598 | "0010001000100010" WHEN HK_SEL = "10" ELSE |
|
585 | "0010001000100010" WHEN HK_SEL = "10" ELSE | |
599 | "0100010001000100" WHEN HK_SEL = "10" ELSE |
|
586 | "0100010001000100" WHEN HK_SEL = "10" ELSE | |
600 | (OTHERS => '0'); |
|
587 | (OTHERS => '0'); | |
601 |
|
588 | |||
602 |
|
589 | |||
603 | ---------------------------------------------------------------------- |
|
590 | ---------------------------------------------------------------------- | |
604 | --- GPIO ----------------------------------------------------------- |
|
591 | --- GPIO ----------------------------------------------------------- | |
605 | ---------------------------------------------------------------------- |
|
592 | ---------------------------------------------------------------------- | |
606 |
|
593 | |||
607 | grgpio0 : grgpio |
|
594 | grgpio0 : grgpio | |
608 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
595 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
609 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
596 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
610 |
|
597 | |||
611 | gpioi.sig_en <= (OTHERS => '0'); |
|
598 | gpioi.sig_en <= (OTHERS => '0'); | |
612 | gpioi.sig_in <= (OTHERS => '0'); |
|
599 | gpioi.sig_in <= (OTHERS => '0'); | |
613 | gpioi.din <= (OTHERS => '0'); |
|
600 | gpioi.din <= (OTHERS => '0'); | |
614 | --pio_pad_0 : iopad |
|
601 | --pio_pad_0 : iopad | |
615 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
602 | -- GENERIC MAP (tech => CFG_PADTECH) | |
616 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
603 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
617 | --pio_pad_1 : iopad |
|
604 | --pio_pad_1 : iopad | |
618 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
605 | -- GENERIC MAP (tech => CFG_PADTECH) | |
619 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
606 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
620 | --pio_pad_2 : iopad |
|
607 | --pio_pad_2 : iopad | |
621 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
608 | -- GENERIC MAP (tech => CFG_PADTECH) | |
622 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
609 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
623 | --pio_pad_3 : iopad |
|
610 | --pio_pad_3 : iopad | |
624 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
611 | -- GENERIC MAP (tech => CFG_PADTECH) | |
625 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
612 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
626 | --pio_pad_4 : iopad |
|
613 | --pio_pad_4 : iopad | |
627 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
614 | -- GENERIC MAP (tech => CFG_PADTECH) | |
628 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
615 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
629 | --pio_pad_5 : iopad |
|
616 | --pio_pad_5 : iopad | |
630 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
617 | -- GENERIC MAP (tech => CFG_PADTECH) | |
631 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
618 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
632 | --pio_pad_6 : iopad |
|
619 | --pio_pad_6 : iopad | |
633 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
620 | -- GENERIC MAP (tech => CFG_PADTECH) | |
634 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
621 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
635 | --pio_pad_7 : iopad |
|
622 | --pio_pad_7 : iopad | |
636 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
623 | -- GENERIC MAP (tech => CFG_PADTECH) | |
637 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
624 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
638 |
|
625 | |||
639 | PROCESS (clk_25, rstn_25) |
|
626 | PROCESS (clk_25, rstn_25) | |
640 | BEGIN -- PROCESS |
|
627 | BEGIN -- PROCESS | |
641 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
628 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
642 | -- --IO0 <= '0'; |
|
629 | -- --IO0 <= '0'; | |
643 | -- IO1 <= '0'; |
|
630 | -- IO1 <= '0'; | |
644 | -- IO2 <= '0'; |
|
631 | -- IO2 <= '0'; | |
645 | -- IO3 <= '0'; |
|
632 | -- IO3 <= '0'; | |
646 | -- IO4 <= '0'; |
|
633 | -- IO4 <= '0'; | |
647 | -- IO5 <= '0'; |
|
634 | -- IO5 <= '0'; | |
648 | -- IO6 <= '0'; |
|
635 | -- IO6 <= '0'; | |
649 | -- IO7 <= '0'; |
|
636 | -- IO7 <= '0'; | |
650 | IO8 <= '0'; |
|
637 | IO8 <= '0'; | |
651 | IO9 <= '0'; |
|
638 | IO9 <= '0'; | |
652 | IO10 <= '0'; |
|
639 | IO10 <= '0'; | |
653 | IO11 <= '0'; |
|
640 | IO11 <= '0'; | |
654 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
641 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
655 | CASE gpioo.dout(2 DOWNTO 0) IS |
|
642 | CASE gpioo.dout(2 DOWNTO 0) IS | |
656 | WHEN "011" => |
|
643 | WHEN "011" => | |
657 | -- --IO0 <= observation_reg(0 ); |
|
644 | -- --IO0 <= observation_reg(0 ); | |
658 | -- IO1 <= observation_reg(1 ); |
|
645 | -- IO1 <= observation_reg(1 ); | |
659 | -- IO2 <= observation_reg(2 ); |
|
646 | -- IO2 <= observation_reg(2 ); | |
660 | -- IO3 <= observation_reg(3 ); |
|
647 | -- IO3 <= observation_reg(3 ); | |
661 | -- IO4 <= observation_reg(4 ); |
|
648 | -- IO4 <= observation_reg(4 ); | |
662 | -- IO5 <= observation_reg(5 ); |
|
649 | -- IO5 <= observation_reg(5 ); | |
663 | -- IO6 <= observation_reg(6 ); |
|
650 | -- IO6 <= observation_reg(6 ); | |
664 | -- IO7 <= observation_reg(7 ); |
|
651 | -- IO7 <= observation_reg(7 ); | |
665 | IO8 <= observation_reg(8); |
|
652 | IO8 <= observation_reg(8); | |
666 | IO9 <= observation_reg(9); |
|
653 | IO9 <= observation_reg(9); | |
667 | IO10 <= observation_reg(10); |
|
654 | IO10 <= observation_reg(10); | |
668 | IO11 <= observation_reg(11); |
|
655 | IO11 <= observation_reg(11); | |
669 | WHEN "001" => |
|
656 | WHEN "001" => | |
670 | -- --IO0 <= observation_reg(0 + 12); |
|
657 | -- --IO0 <= observation_reg(0 + 12); | |
671 | -- IO1 <= observation_reg(1 + 12); |
|
658 | -- IO1 <= observation_reg(1 + 12); | |
672 | -- IO2 <= observation_reg(2 + 12); |
|
659 | -- IO2 <= observation_reg(2 + 12); | |
673 | -- IO3 <= observation_reg(3 + 12); |
|
660 | -- IO3 <= observation_reg(3 + 12); | |
674 | -- IO4 <= observation_reg(4 + 12); |
|
661 | -- IO4 <= observation_reg(4 + 12); | |
675 | -- IO5 <= observation_reg(5 + 12); |
|
662 | -- IO5 <= observation_reg(5 + 12); | |
676 | -- IO6 <= observation_reg(6 + 12); |
|
663 | -- IO6 <= observation_reg(6 + 12); | |
677 | -- IO7 <= observation_reg(7 + 12); |
|
664 | -- IO7 <= observation_reg(7 + 12); | |
678 | IO8 <= observation_reg(8 + 12); |
|
665 | IO8 <= observation_reg(8 + 12); | |
679 | IO9 <= observation_reg(9 + 12); |
|
666 | IO9 <= observation_reg(9 + 12); | |
680 | IO10 <= observation_reg(10 + 12); |
|
667 | IO10 <= observation_reg(10 + 12); | |
681 | IO11 <= observation_reg(11 + 12); |
|
668 | IO11 <= observation_reg(11 + 12); | |
682 | WHEN "010" => |
|
669 | WHEN "010" => | |
683 | -- --IO0 <= observation_reg(0 + 12 + 12); |
|
670 | -- --IO0 <= observation_reg(0 + 12 + 12); | |
684 | -- IO1 <= observation_reg(1 + 12 + 12); |
|
671 | -- IO1 <= observation_reg(1 + 12 + 12); | |
685 | -- IO2 <= observation_reg(2 + 12 + 12); |
|
672 | -- IO2 <= observation_reg(2 + 12 + 12); | |
686 | -- IO3 <= observation_reg(3 + 12 + 12); |
|
673 | -- IO3 <= observation_reg(3 + 12 + 12); | |
687 | -- IO4 <= observation_reg(4 + 12 + 12); |
|
674 | -- IO4 <= observation_reg(4 + 12 + 12); | |
688 | -- IO5 <= observation_reg(5 + 12 + 12); |
|
675 | -- IO5 <= observation_reg(5 + 12 + 12); | |
689 | -- IO6 <= observation_reg(6 + 12 + 12); |
|
676 | -- IO6 <= observation_reg(6 + 12 + 12); | |
690 | -- IO7 <= observation_reg(7 + 12 + 12); |
|
677 | -- IO7 <= observation_reg(7 + 12 + 12); | |
691 | IO8 <= '0'; |
|
678 | IO8 <= '0'; | |
692 | IO9 <= '0'; |
|
679 | IO9 <= '0'; | |
693 | IO10 <= '0'; |
|
680 | IO10 <= '0'; | |
694 | IO11 <= '0'; |
|
681 | IO11 <= '0'; | |
695 | WHEN "000" => |
|
682 | WHEN "000" => | |
696 | -- --IO0 <= observation_vector_0(0 ); |
|
683 | -- --IO0 <= observation_vector_0(0 ); | |
697 | -- IO1 <= observation_vector_0(1 ); |
|
684 | -- IO1 <= observation_vector_0(1 ); | |
698 | -- IO2 <= observation_vector_0(2 ); |
|
685 | -- IO2 <= observation_vector_0(2 ); | |
699 | -- IO3 <= observation_vector_0(3 ); |
|
686 | -- IO3 <= observation_vector_0(3 ); | |
700 | -- IO4 <= observation_vector_0(4 ); |
|
687 | -- IO4 <= observation_vector_0(4 ); | |
701 | -- IO5 <= observation_vector_0(5 ); |
|
688 | -- IO5 <= observation_vector_0(5 ); | |
702 | -- IO6 <= observation_vector_0(6 ); |
|
689 | -- IO6 <= observation_vector_0(6 ); | |
703 | -- IO7 <= observation_vector_0(7 ); |
|
690 | -- IO7 <= observation_vector_0(7 ); | |
704 | IO8 <= observation_vector_0(8); |
|
691 | IO8 <= observation_vector_0(8); | |
705 | IO9 <= observation_vector_0(9); |
|
692 | IO9 <= observation_vector_0(9); | |
706 | IO10 <= observation_vector_0(10); |
|
693 | IO10 <= observation_vector_0(10); | |
707 | IO11 <= observation_vector_0(11); |
|
694 | IO11 <= observation_vector_0(11); | |
708 | WHEN "100" => |
|
695 | WHEN "100" => | |
709 | -- --IO0 <= observation_vector_1(0 ); |
|
696 | -- --IO0 <= observation_vector_1(0 ); | |
710 | -- IO1 <= observation_vector_1(1 ); |
|
697 | -- IO1 <= observation_vector_1(1 ); | |
711 | -- IO2 <= observation_vector_1(2 ); |
|
698 | -- IO2 <= observation_vector_1(2 ); | |
712 | -- IO3 <= observation_vector_1(3 ); |
|
699 | -- IO3 <= observation_vector_1(3 ); | |
713 | -- IO4 <= observation_vector_1(4 ); |
|
700 | -- IO4 <= observation_vector_1(4 ); | |
714 | -- IO5 <= observation_vector_1(5 ); |
|
701 | -- IO5 <= observation_vector_1(5 ); | |
715 | -- IO6 <= observation_vector_1(6 ); |
|
702 | -- IO6 <= observation_vector_1(6 ); | |
716 | -- IO7 <= observation_vector_1(7 ); |
|
703 | -- IO7 <= observation_vector_1(7 ); | |
717 | IO8 <= observation_vector_1(8); |
|
704 | IO8 <= observation_vector_1(8); | |
718 | IO9 <= observation_vector_1(9); |
|
705 | IO9 <= observation_vector_1(9); | |
719 | IO10 <= observation_vector_1(10); |
|
706 | IO10 <= observation_vector_1(10); | |
720 | IO11 <= observation_vector_1(11); |
|
707 | IO11 <= observation_vector_1(11); | |
721 | WHEN OTHERS => NULL; |
|
708 | WHEN OTHERS => NULL; | |
722 | END CASE; |
|
709 | END CASE; | |
723 |
|
710 | |||
724 | END IF; |
|
711 | END IF; | |
725 | END PROCESS; |
|
712 | END PROCESS; | |
726 | ----------------------------------------------------------------------------- |
|
713 | ----------------------------------------------------------------------------- | |
727 | -- |
|
714 | -- | |
728 | ----------------------------------------------------------------------------- |
|
715 | ----------------------------------------------------------------------------- | |
729 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE |
|
716 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
730 |
apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= |
|
717 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
731 | apbo_ext(I) <= apb_none; |
|
718 | apbo_ext(I) <= apb_none; | |
732 | END GENERATE apbo_ext_not_used; |
|
719 | END GENERATE apbo_ext_not_used; | |
733 | END GENERATE all_apbo_ext; |
|
720 | END GENERATE all_apbo_ext; | |
734 |
|
721 | |||
735 |
|
722 | |||
736 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE |
|
723 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE | |
737 | ahbo_s_ext(I) <= ahbs_none; |
|
724 | ahbo_s_ext(I) <= ahbs_none; | |
738 | END GENERATE all_ahbo_ext; |
|
725 | END GENERATE all_ahbo_ext; | |
739 |
|
726 | |||
740 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE |
|
727 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE | |
741 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE |
|
728 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE | |
742 | ahbo_m_ext(I) <= ahbm_none; |
|
729 | ahbo_m_ext(I) <= ahbm_none; | |
743 | END GENERATE ahbo_m_ext_not_used; |
|
730 | END GENERATE ahbo_m_ext_not_used; | |
744 | END GENERATE all_ahbo_m_ext; |
|
731 | END GENERATE all_ahbo_m_ext; | |
745 |
|
732 | |||
746 | END beh; |
|
733 | END beh; |
@@ -1,31 +1,31 | |||||
1 | ./amba_lcd_16x2_ctrlr |
|
1 | ./amba_lcd_16x2_ctrlr | |
2 | ./general_purpose |
|
2 | ./general_purpose | |
3 | ./general_purpose/lpp_AMR |
|
3 | ./general_purpose/lpp_AMR | |
4 | ./general_purpose/lpp_balise |
|
4 | ./general_purpose/lpp_balise | |
5 | ./general_purpose/lpp_delay |
|
5 | ./general_purpose/lpp_delay | |
6 | ./lpp_amba |
|
6 | ./lpp_amba | |
7 | ./dsp/chirp |
|
7 | ./dsp/chirp | |
8 | ./dsp/iir_filter |
|
8 | ./dsp/iir_filter | |
9 | ./dsp/cic |
|
9 | ./dsp/cic | |
10 | ./dsp/lpp_downsampling |
|
10 | ./dsp/lpp_downsampling | |
11 | ./dsp/lpp_fft_rtax |
|
11 | ./dsp/lpp_fft_rtax | |
12 | ./lpp_memory |
|
12 | ./lpp_memory | |
13 | ./dsp/lpp_fft |
|
13 | ./dsp/lpp_fft | |
14 |
./lfr_ |
|
14 | ./lfr_management | |
15 | ./lpp_ad_Conv |
|
15 | ./lpp_ad_Conv | |
16 | ./lpp_bootloader |
|
16 | ./lpp_bootloader | |
17 | ./lpp_cna |
|
17 | ./lpp_cna | |
18 | ./lpp_spectral_matrix |
|
18 | ./lpp_spectral_matrix | |
19 | ./lpp_demux |
|
19 | ./lpp_demux | |
20 | ./lpp_Header |
|
20 | ./lpp_Header | |
21 | ./lpp_matrix |
|
21 | ./lpp_matrix | |
22 | ./lpp_uart |
|
22 | ./lpp_uart | |
23 | ./lpp_usb |
|
23 | ./lpp_usb | |
24 | ./lpp_dma |
|
24 | ./lpp_dma | |
25 | ./lpp_waveform |
|
25 | ./lpp_waveform | |
26 | ./lpp_top_lfr |
|
26 | ./lpp_top_lfr | |
27 | ./lpp_Header |
|
27 | ./lpp_Header | |
28 | ./lpp_leon3_soc |
|
28 | ./lpp_leon3_soc | |
29 | ./lpp_debug_lfr |
|
29 | ./lpp_debug_lfr | |
30 | ./lpp_sim/CY7C1061DV33 |
|
30 | ./lpp_sim/CY7C1061DV33 | |
31 | ./lpp_sim |
|
31 | ./lpp_sim |
@@ -1,329 +1,380 | |||||
1 | ---------------------------------------------------------------------------------- |
|
1 | ---------------------------------------------------------------------------------- | |
2 | -- Company: |
|
2 | -- Company: | |
3 | -- Engineer: |
|
3 | -- Engineer: | |
4 | -- |
|
4 | -- | |
5 | -- Create Date: 11:17:05 07/02/2012 |
|
5 | -- Create Date: 11:17:05 07/02/2012 | |
6 | -- Design Name: |
|
6 | -- Design Name: | |
7 | -- Module Name: apb_lfr_time_management - Behavioral |
|
7 | -- Module Name: apb_lfr_time_management - Behavioral | |
8 | -- Project Name: |
|
8 | -- Project Name: | |
9 | -- Target Devices: |
|
9 | -- Target Devices: | |
10 | -- Tool versions: |
|
10 | -- Tool versions: | |
11 | -- Description: |
|
11 | -- Description: | |
12 | -- |
|
12 | -- | |
13 | -- Dependencies: |
|
13 | -- Dependencies: | |
14 | -- |
|
14 | -- | |
15 | -- Revision: |
|
15 | -- Revision: | |
16 | -- Revision 0.01 - File Created |
|
16 | -- Revision 0.01 - File Created | |
17 | -- Additional Comments: |
|
17 | -- Additional Comments: | |
18 | -- |
|
18 | -- | |
19 | ---------------------------------------------------------------------------------- |
|
19 | ---------------------------------------------------------------------------------- | |
20 | LIBRARY IEEE; |
|
20 | LIBRARY IEEE; | |
21 | USE IEEE.STD_LOGIC_1164.ALL; |
|
21 | USE IEEE.STD_LOGIC_1164.ALL; | |
22 | USE IEEE.NUMERIC_STD.ALL; |
|
22 | USE IEEE.NUMERIC_STD.ALL; | |
23 | LIBRARY grlib; |
|
23 | LIBRARY grlib; | |
24 | USE grlib.amba.ALL; |
|
24 | USE grlib.amba.ALL; | |
25 | USE grlib.stdlib.ALL; |
|
25 | USE grlib.stdlib.ALL; | |
26 | USE grlib.devices.ALL; |
|
26 | USE grlib.devices.ALL; | |
27 | LIBRARY lpp; |
|
27 | LIBRARY lpp; | |
28 | USE lpp.apb_devices_list.ALL; |
|
28 | USE lpp.apb_devices_list.ALL; | |
29 | USE lpp.general_purpose.ALL; |
|
29 | USE lpp.general_purpose.ALL; | |
30 |
USE lpp.lpp_lfr_ |
|
30 | USE lpp.lpp_lfr_management.ALL; | |
31 |
USE lpp.lpp_lfr_ |
|
31 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; | |
32 |
|
32 | |||
33 |
|
33 | |||
34 |
ENTITY apb_lfr_ |
|
34 | ENTITY apb_lfr_management IS | |
35 |
|
35 | |||
36 | GENERIC( |
|
36 | GENERIC( | |
37 | pindex : INTEGER := 0; --! APB slave index |
|
37 | pindex : INTEGER := 0; --! APB slave index | |
38 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
|
38 | paddr : INTEGER := 0; --! ADDR field of the APB BAR | |
39 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
|
39 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR | |
40 | FIRST_DIVISION : INTEGER := 374; |
|
40 | FIRST_DIVISION : INTEGER := 374; | |
41 | NB_SECOND_DESYNC : INTEGER := 60 |
|
41 | NB_SECOND_DESYNC : INTEGER := 60 | |
42 | ); |
|
42 | ); | |
43 |
|
43 | |||
44 | PORT ( |
|
44 | PORT ( | |
45 | clk25MHz : IN STD_LOGIC; --! Clock |
|
45 | clk25MHz : IN STD_LOGIC; --! Clock | |
46 | clk24_576MHz : IN STD_LOGIC; --! secondary clock |
|
46 | clk24_576MHz : IN STD_LOGIC; --! secondary clock | |
47 | resetn : IN STD_LOGIC; --! Reset |
|
47 | resetn : IN STD_LOGIC; --! Reset | |
48 |
|
48 | |||
49 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
|
49 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
50 |
|
50 | |||
51 | apbi : IN apb_slv_in_type; --! APB slave input signals |
|
51 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
52 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
|
52 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
53 |
|
53 | --------------------------------------------------------------------------- | ||
|
54 | HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
55 | HK_val : IN STD_LOGIC; | |||
|
56 | HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
57 | --------------------------------------------------------------------------- | |||
54 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
|
58 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
55 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME |
|
59 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME | |
56 | --------------------------------------------------------------------------- |
|
60 | --------------------------------------------------------------------------- | |
57 | LFR_soft_rstn : OUT STD_LOGIC |
|
61 | LFR_soft_rstn : OUT STD_LOGIC | |
58 | ); |
|
62 | ); | |
59 |
|
63 | |||
60 |
END apb_lfr_ |
|
64 | END apb_lfr_management; | |
61 |
|
65 | |||
62 |
ARCHITECTURE Behavioral OF apb_lfr_ |
|
66 | ARCHITECTURE Behavioral OF apb_lfr_management IS | |
63 |
|
67 | |||
64 | CONSTANT REVISION : INTEGER := 1; |
|
68 | CONSTANT REVISION : INTEGER := 1; | |
65 | CONSTANT pconfig : apb_config_type := ( |
|
69 | CONSTANT pconfig : apb_config_type := ( | |
66 | 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0), |
|
70 | 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0), | |
67 | 1 => apb_iobar(paddr, pmask) |
|
71 | 1 => apb_iobar(paddr, pmask) | |
68 | ); |
|
72 | ); | |
69 |
|
73 | |||
70 | TYPE apb_lfr_time_management_Reg IS RECORD |
|
74 | TYPE apb_lfr_time_management_Reg IS RECORD | |
71 | ctrl : STD_LOGIC; |
|
75 | ctrl : STD_LOGIC; | |
72 | soft_reset : STD_LOGIC; |
|
76 | soft_reset : STD_LOGIC; | |
73 | coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
77 | coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
74 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
78 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
75 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
79 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
76 | LFR_soft_reset : STD_LOGIC; |
|
80 | LFR_soft_reset : STD_LOGIC; | |
|
81 | HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
82 | HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
83 | HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
77 | END RECORD; |
|
84 | END RECORD; | |
78 | SIGNAL r : apb_lfr_time_management_Reg; |
|
85 | SIGNAL r : apb_lfr_time_management_Reg; | |
79 |
|
86 | |||
80 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
81 | SIGNAL force_tick : STD_LOGIC; |
|
88 | SIGNAL force_tick : STD_LOGIC; | |
82 | SIGNAL previous_force_tick : STD_LOGIC; |
|
89 | SIGNAL previous_force_tick : STD_LOGIC; | |
83 | SIGNAL soft_tick : STD_LOGIC; |
|
90 | SIGNAL soft_tick : STD_LOGIC; | |
84 |
|
91 | |||
85 | SIGNAL coarsetime_reg_updated : STD_LOGIC; |
|
92 | SIGNAL coarsetime_reg_updated : STD_LOGIC; | |
86 | SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
93 | SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
87 |
|
94 | |||
88 | --SIGNAL coarse_time_new : STD_LOGIC; |
|
95 | --SIGNAL coarse_time_new : STD_LOGIC; | |
89 | SIGNAL coarse_time_new_49 : STD_LOGIC; |
|
96 | SIGNAL coarse_time_new_49 : STD_LOGIC; | |
90 | SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
91 | SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
98 | SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
92 |
|
99 | |||
93 | --SIGNAL fine_time_new : STD_LOGIC; |
|
100 | --SIGNAL fine_time_new : STD_LOGIC; | |
94 | --SIGNAL fine_time_new_temp : STD_LOGIC; |
|
101 | --SIGNAL fine_time_new_temp : STD_LOGIC; | |
95 | SIGNAL fine_time_new_49 : STD_LOGIC; |
|
102 | SIGNAL fine_time_new_49 : STD_LOGIC; | |
96 | SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
103 | SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
97 | SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
104 | SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
98 | SIGNAL tick : STD_LOGIC; |
|
105 | SIGNAL tick : STD_LOGIC; | |
99 | SIGNAL new_timecode : STD_LOGIC; |
|
106 | SIGNAL new_timecode : STD_LOGIC; | |
100 | SIGNAL new_coarsetime : STD_LOGIC; |
|
107 | SIGNAL new_coarsetime : STD_LOGIC; | |
101 |
|
108 | |||
102 | SIGNAL time_new_49 : STD_LOGIC; |
|
109 | SIGNAL time_new_49 : STD_LOGIC; | |
103 | SIGNAL time_new : STD_LOGIC; |
|
110 | SIGNAL time_new : STD_LOGIC; | |
104 |
|
111 | |||
105 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
106 | SIGNAL force_reset : STD_LOGIC; |
|
113 | SIGNAL force_reset : STD_LOGIC; | |
107 | SIGNAL previous_force_reset : STD_LOGIC; |
|
114 | SIGNAL previous_force_reset : STD_LOGIC; | |
108 | SIGNAL soft_reset : STD_LOGIC; |
|
115 | SIGNAL soft_reset : STD_LOGIC; | |
109 | SIGNAL soft_reset_sync : STD_LOGIC; |
|
116 | SIGNAL soft_reset_sync : STD_LOGIC; | |
110 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
|
118 | SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
119 | SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
120 | SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
121 | SIGNAL HK_sel_s : STD_LOGIC_VECTOR( 1 DOWNTO 0); | |||
111 |
|
122 | |||
112 | SIGNAL rstn_LFR_TM : STD_LOGIC; |
|
123 | SIGNAL rstn_LFR_TM : STD_LOGIC; | |
113 |
|
124 | |||
114 | BEGIN |
|
125 | BEGIN | |
115 |
|
126 | |||
116 | LFR_soft_rstn <= NOT r.LFR_soft_reset; |
|
127 | LFR_soft_rstn <= NOT r.LFR_soft_reset; | |
117 |
|
128 | |||
118 | PROCESS(resetn, clk25MHz) |
|
129 | PROCESS(resetn, clk25MHz) | |
119 | BEGIN |
|
130 | BEGIN | |
120 |
|
131 | |||
121 | IF resetn = '0' THEN |
|
132 | IF resetn = '0' THEN | |
122 | Rdata <= (OTHERS => '0'); |
|
133 | Rdata <= (OTHERS => '0'); | |
123 | r.coarse_time_load <= (OTHERS => '0'); |
|
134 | r.coarse_time_load <= (OTHERS => '0'); | |
124 | r.soft_reset <= '0'; |
|
135 | r.soft_reset <= '0'; | |
125 | r.ctrl <= '0'; |
|
136 | r.ctrl <= '0'; | |
126 | r.LFR_soft_reset <= '1'; |
|
137 | r.LFR_soft_reset <= '1'; | |
127 |
|
138 | |||
128 | force_tick <= '0'; |
|
139 | force_tick <= '0'; | |
129 | previous_force_tick <= '0'; |
|
140 | previous_force_tick <= '0'; | |
130 | soft_tick <= '0'; |
|
141 | soft_tick <= '0'; | |
131 |
|
142 | |||
132 | coarsetime_reg_updated <= '0'; |
|
143 | coarsetime_reg_updated <= '0'; | |
133 |
|
144 | |||
134 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN |
|
145 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN | |
135 | coarsetime_reg_updated <= '0'; |
|
146 | coarsetime_reg_updated <= '0'; | |
136 |
|
147 | |||
137 | force_tick <= r.ctrl; |
|
148 | force_tick <= r.ctrl; | |
138 | previous_force_tick <= force_tick; |
|
149 | previous_force_tick <= force_tick; | |
139 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN |
|
150 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN | |
140 | soft_tick <= '1'; |
|
151 | soft_tick <= '1'; | |
141 | ELSE |
|
152 | ELSE | |
142 | soft_tick <= '0'; |
|
153 | soft_tick <= '0'; | |
143 | END IF; |
|
154 | END IF; | |
144 |
|
155 | |||
145 | force_reset <= r.soft_reset; |
|
156 | force_reset <= r.soft_reset; | |
146 | previous_force_reset <= force_reset; |
|
157 | previous_force_reset <= force_reset; | |
147 | IF (previous_force_reset = '0') AND (force_reset = '1') THEN |
|
158 | IF (previous_force_reset = '0') AND (force_reset = '1') THEN | |
148 | soft_reset <= '1'; |
|
159 | soft_reset <= '1'; | |
149 | ELSE |
|
160 | ELSE | |
150 | soft_reset <= '0'; |
|
161 | soft_reset <= '0'; | |
151 | END IF; |
|
162 | END IF; | |
152 |
|
163 | |||
153 | --APB Write OP |
|
164 | --APB Write OP | |
154 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN |
|
165 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN | |
155 | CASE apbi.paddr(7 DOWNTO 2) IS |
|
166 | CASE apbi.paddr(7 DOWNTO 2) IS | |
156 |
WHEN ADDR_LFR_ |
|
167 | WHEN ADDR_LFR_MANAGMENT_CONTROL => | |
157 | r.ctrl <= apbi.pwdata(0); |
|
168 | r.ctrl <= apbi.pwdata(0); | |
158 | r.soft_reset <= apbi.pwdata(1); |
|
169 | r.soft_reset <= apbi.pwdata(1); | |
159 | r.LFR_soft_reset <= apbi.pwdata(2); |
|
170 | r.LFR_soft_reset <= apbi.pwdata(2); | |
160 |
WHEN ADDR_LFR_ |
|
171 | WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => | |
161 | r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); |
|
172 | r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); | |
162 | coarsetime_reg_updated <= '1'; |
|
173 | coarsetime_reg_updated <= '1'; | |
163 | WHEN OTHERS => |
|
174 | WHEN OTHERS => | |
164 | NULL; |
|
175 | NULL; | |
165 | END CASE; |
|
176 | END CASE; | |
166 | ELSE |
|
177 | ELSE | |
167 | IF r.ctrl = '1' THEN |
|
178 | IF r.ctrl = '1' THEN | |
168 | r.ctrl <= '0'; |
|
179 | r.ctrl <= '0'; | |
169 | END if; |
|
180 | END if; | |
170 | IF r.soft_reset = '1' THEN |
|
181 | IF r.soft_reset = '1' THEN | |
171 | r.soft_reset <= '0'; |
|
182 | r.soft_reset <= '0'; | |
172 | END if; |
|
183 | END if; | |
173 | END IF; |
|
184 | END IF; | |
174 |
|
185 | |||
175 | --APB READ OP |
|
186 | --APB READ OP | |
176 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN |
|
187 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN | |
177 | CASE apbi.paddr(7 DOWNTO 2) IS |
|
188 | CASE apbi.paddr(7 DOWNTO 2) IS | |
178 |
WHEN ADDR_LFR_ |
|
189 | WHEN ADDR_LFR_MANAGMENT_CONTROL => | |
179 | Rdata(0) <= r.ctrl; |
|
190 | Rdata(0) <= r.ctrl; | |
180 | Rdata(1) <= r.soft_reset; |
|
191 | Rdata(1) <= r.soft_reset; | |
181 | Rdata(2) <= r.LFR_soft_reset; |
|
192 | Rdata(2) <= r.LFR_soft_reset; | |
182 | Rdata(31 DOWNTO 3) <= (others => '0'); |
|
193 | Rdata(31 DOWNTO 3) <= (others => '0'); | |
183 |
WHEN ADDR_LFR_ |
|
194 | WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => | |
184 | Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); |
|
195 | Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); | |
185 |
WHEN ADDR_LFR_ |
|
196 | WHEN ADDR_LFR_MANAGMENT_TIME_COARSE => | |
186 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); |
|
197 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); | |
187 |
WHEN ADDR_LFR_ |
|
198 | WHEN ADDR_LFR_MANAGMENT_TIME_FINE => | |
188 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
199 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
189 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); |
|
200 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); | |
|
201 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 => | |||
|
202 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); | |||
|
203 | Rdata(15 DOWNTO 0) <= r.HK_temp_0; | |||
|
204 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 => | |||
|
205 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); | |||
|
206 | Rdata(15 DOWNTO 0) <= r.HK_temp_1; | |||
|
207 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 => | |||
|
208 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); | |||
|
209 | Rdata(15 DOWNTO 0) <= r.HK_temp_2; | |||
190 | WHEN OTHERS => |
|
210 | WHEN OTHERS => | |
191 | Rdata(31 DOWNTO 0) <= (others => '0'); |
|
211 | Rdata(31 DOWNTO 0) <= (others => '0'); | |
192 | END CASE; |
|
212 | END CASE; | |
193 | END IF; |
|
213 | END IF; | |
194 |
|
214 | |||
195 | END IF; |
|
215 | END IF; | |
196 | END PROCESS; |
|
216 | END PROCESS; | |
197 |
|
217 | |||
198 | apbo.pirq <= (OTHERS => '0'); |
|
218 | apbo.pirq <= (OTHERS => '0'); | |
199 | apbo.prdata <= Rdata; |
|
219 | apbo.prdata <= Rdata; | |
200 | apbo.pconfig <= pconfig; |
|
220 | apbo.pconfig <= pconfig; | |
201 | apbo.pindex <= pindex; |
|
221 | apbo.pindex <= pindex; | |
202 |
|
222 | |||
203 | ----------------------------------------------------------------------------- |
|
223 | ----------------------------------------------------------------------------- | |
204 | -- IN |
|
224 | -- IN | |
205 | coarse_time <= r.coarse_time; |
|
225 | coarse_time <= r.coarse_time; | |
206 | fine_time <= r.fine_time; |
|
226 | fine_time <= r.fine_time; | |
207 | coarsetime_reg <= r.coarse_time_load; |
|
227 | coarsetime_reg <= r.coarse_time_load; | |
208 | ----------------------------------------------------------------------------- |
|
228 | ----------------------------------------------------------------------------- | |
209 |
|
229 | |||
210 | ----------------------------------------------------------------------------- |
|
230 | ----------------------------------------------------------------------------- | |
211 | -- OUT |
|
231 | -- OUT | |
212 | r.coarse_time <= coarse_time_s; |
|
232 | r.coarse_time <= coarse_time_s; | |
213 | r.fine_time <= fine_time_s; |
|
233 | r.fine_time <= fine_time_s; | |
214 | ----------------------------------------------------------------------------- |
|
234 | ----------------------------------------------------------------------------- | |
215 |
|
235 | |||
216 | ----------------------------------------------------------------------------- |
|
236 | ----------------------------------------------------------------------------- | |
217 | tick <= grspw_tick OR soft_tick; |
|
237 | tick <= grspw_tick OR soft_tick; | |
218 |
|
238 | |||
219 | SYNC_VALID_BIT_1 : SYNC_VALID_BIT |
|
239 | SYNC_VALID_BIT_1 : SYNC_VALID_BIT | |
220 | GENERIC MAP ( |
|
240 | GENERIC MAP ( | |
221 | NB_FF_OF_SYNC => 2) |
|
241 | NB_FF_OF_SYNC => 2) | |
222 | PORT MAP ( |
|
242 | PORT MAP ( | |
223 | clk_in => clk25MHz, |
|
243 | clk_in => clk25MHz, | |
224 | clk_out => clk24_576MHz, |
|
244 | clk_out => clk24_576MHz, | |
225 | rstn => resetn, |
|
245 | rstn => resetn, | |
226 | sin => tick, |
|
246 | sin => tick, | |
227 | sout => new_timecode); |
|
247 | sout => new_timecode); | |
228 |
|
248 | |||
229 | SYNC_VALID_BIT_2 : SYNC_VALID_BIT |
|
249 | SYNC_VALID_BIT_2 : SYNC_VALID_BIT | |
230 | GENERIC MAP ( |
|
250 | GENERIC MAP ( | |
231 | NB_FF_OF_SYNC => 2) |
|
251 | NB_FF_OF_SYNC => 2) | |
232 | PORT MAP ( |
|
252 | PORT MAP ( | |
233 | clk_in => clk25MHz, |
|
253 | clk_in => clk25MHz, | |
234 | clk_out => clk24_576MHz, |
|
254 | clk_out => clk24_576MHz, | |
235 | rstn => resetn, |
|
255 | rstn => resetn, | |
236 | sin => coarsetime_reg_updated, |
|
256 | sin => coarsetime_reg_updated, | |
237 | sout => new_coarsetime); |
|
257 | sout => new_coarsetime); | |
238 |
|
258 | |||
239 | SYNC_VALID_BIT_3 : SYNC_VALID_BIT |
|
259 | SYNC_VALID_BIT_3 : SYNC_VALID_BIT | |
240 | GENERIC MAP ( |
|
260 | GENERIC MAP ( | |
241 | NB_FF_OF_SYNC => 2) |
|
261 | NB_FF_OF_SYNC => 2) | |
242 | PORT MAP ( |
|
262 | PORT MAP ( | |
243 | clk_in => clk25MHz, |
|
263 | clk_in => clk25MHz, | |
244 | clk_out => clk24_576MHz, |
|
264 | clk_out => clk24_576MHz, | |
245 | rstn => resetn, |
|
265 | rstn => resetn, | |
246 | sin => soft_reset, |
|
266 | sin => soft_reset, | |
247 | sout => soft_reset_sync); |
|
267 | sout => soft_reset_sync); | |
248 |
|
268 | |||
249 | ----------------------------------------------------------------------------- |
|
269 | ----------------------------------------------------------------------------- | |
250 | --SYNC_FF_1 : SYNC_FF |
|
270 | --SYNC_FF_1 : SYNC_FF | |
251 | -- GENERIC MAP ( |
|
271 | -- GENERIC MAP ( | |
252 | -- NB_FF_OF_SYNC => 2) |
|
272 | -- NB_FF_OF_SYNC => 2) | |
253 | -- PORT MAP ( |
|
273 | -- PORT MAP ( | |
254 | -- clk => clk25MHz, |
|
274 | -- clk => clk25MHz, | |
255 | -- rstn => resetn, |
|
275 | -- rstn => resetn, | |
256 | -- A => fine_time_new_49, |
|
276 | -- A => fine_time_new_49, | |
257 | -- A_sync => fine_time_new_temp); |
|
277 | -- A_sync => fine_time_new_temp); | |
258 |
|
278 | |||
259 | --lpp_front_detection_1 : lpp_front_detection |
|
279 | --lpp_front_detection_1 : lpp_front_detection | |
260 | -- PORT MAP ( |
|
280 | -- PORT MAP ( | |
261 | -- clk => clk25MHz, |
|
281 | -- clk => clk25MHz, | |
262 | -- rstn => resetn, |
|
282 | -- rstn => resetn, | |
263 | -- sin => fine_time_new_temp, |
|
283 | -- sin => fine_time_new_temp, | |
264 | -- sout => fine_time_new); |
|
284 | -- sout => fine_time_new); | |
265 |
|
285 | |||
266 | --SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
|
286 | --SYNC_VALID_BIT_4 : SYNC_VALID_BIT | |
267 | -- GENERIC MAP ( |
|
287 | -- GENERIC MAP ( | |
268 | -- NB_FF_OF_SYNC => 2) |
|
288 | -- NB_FF_OF_SYNC => 2) | |
269 | -- PORT MAP ( |
|
289 | -- PORT MAP ( | |
270 | -- clk_in => clk24_576MHz, |
|
290 | -- clk_in => clk24_576MHz, | |
271 | -- clk_out => clk25MHz, |
|
291 | -- clk_out => clk25MHz, | |
272 | -- rstn => resetn, |
|
292 | -- rstn => resetn, | |
273 | -- sin => coarse_time_new_49, |
|
293 | -- sin => coarse_time_new_49, | |
274 | -- sout => coarse_time_new); |
|
294 | -- sout => coarse_time_new); | |
275 |
|
295 | |||
276 | time_new_49 <= coarse_time_new_49 OR fine_time_new_49; |
|
296 | time_new_49 <= coarse_time_new_49 OR fine_time_new_49; | |
277 |
|
297 | |||
278 | SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
|
298 | SYNC_VALID_BIT_4 : SYNC_VALID_BIT | |
279 | GENERIC MAP ( |
|
299 | GENERIC MAP ( | |
280 | NB_FF_OF_SYNC => 2) |
|
300 | NB_FF_OF_SYNC => 2) | |
281 | PORT MAP ( |
|
301 | PORT MAP ( | |
282 | clk_in => clk24_576MHz, |
|
302 | clk_in => clk24_576MHz, | |
283 | clk_out => clk25MHz, |
|
303 | clk_out => clk25MHz, | |
284 | rstn => resetn, |
|
304 | rstn => resetn, | |
285 | sin => time_new_49, |
|
305 | sin => time_new_49, | |
286 | sout => time_new); |
|
306 | sout => time_new); | |
287 |
|
307 | |||
288 |
|
308 | |||
289 |
|
309 | |||
290 | PROCESS (clk25MHz, resetn) |
|
310 | PROCESS (clk25MHz, resetn) | |
291 | BEGIN -- PROCESS |
|
311 | BEGIN -- PROCESS | |
292 | IF resetn = '0' THEN -- asynchronous reset (active low) |
|
312 | IF resetn = '0' THEN -- asynchronous reset (active low) | |
293 | fine_time_s <= (OTHERS => '0'); |
|
313 | fine_time_s <= (OTHERS => '0'); | |
294 | coarse_time_s <= (OTHERS => '0'); |
|
314 | coarse_time_s <= (OTHERS => '0'); | |
295 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
315 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge | |
296 | IF time_new = '1' THEN |
|
316 | IF time_new = '1' THEN | |
297 | fine_time_s <= fine_time_49; |
|
317 | fine_time_s <= fine_time_49; | |
298 | coarse_time_s <= coarse_time_49; |
|
318 | coarse_time_s <= coarse_time_49; | |
299 | END IF; |
|
319 | END IF; | |
300 | END IF; |
|
320 | END IF; | |
301 | END PROCESS; |
|
321 | END PROCESS; | |
302 |
|
322 | |||
303 |
|
323 | |||
304 | rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE |
|
324 | rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE | |
305 | '0' WHEN soft_reset_sync = '1' ELSE |
|
325 | '0' WHEN soft_reset_sync = '1' ELSE | |
306 | '1'; |
|
326 | '1'; | |
307 |
|
327 | |||
308 |
|
328 | |||
309 | ----------------------------------------------------------------------------- |
|
329 | ----------------------------------------------------------------------------- | |
310 | -- LFR_TIME_MANAGMENT |
|
330 | -- LFR_TIME_MANAGMENT | |
311 | ----------------------------------------------------------------------------- |
|
331 | ----------------------------------------------------------------------------- | |
312 | lfr_time_management_1 : lfr_time_management |
|
332 | lfr_time_management_1 : lfr_time_management | |
313 | GENERIC MAP ( |
|
333 | GENERIC MAP ( | |
314 | FIRST_DIVISION => FIRST_DIVISION, |
|
334 | FIRST_DIVISION => FIRST_DIVISION, | |
315 | NB_SECOND_DESYNC => NB_SECOND_DESYNC) |
|
335 | NB_SECOND_DESYNC => NB_SECOND_DESYNC) | |
316 | PORT MAP ( |
|
336 | PORT MAP ( | |
317 | clk => clk24_576MHz, |
|
337 | clk => clk24_576MHz, | |
318 | rstn => rstn_LFR_TM, |
|
338 | rstn => rstn_LFR_TM, | |
319 |
|
339 | |||
320 | tick => new_timecode, |
|
340 | tick => new_timecode, | |
321 | new_coarsetime => new_coarsetime, |
|
341 | new_coarsetime => new_coarsetime, | |
322 | coarsetime_reg => coarsetime_reg(30 DOWNTO 0), |
|
342 | coarsetime_reg => coarsetime_reg(30 DOWNTO 0), | |
323 |
|
343 | |||
324 | fine_time => fine_time_49, |
|
344 | fine_time => fine_time_49, | |
325 | fine_time_new => fine_time_new_49, |
|
345 | fine_time_new => fine_time_new_49, | |
326 | coarse_time => coarse_time_49, |
|
346 | coarse_time => coarse_time_49, | |
327 | coarse_time_new => coarse_time_new_49); |
|
347 | coarse_time_new => coarse_time_new_49); | |
328 |
|
348 | |||
329 | END Behavioral; |
|
349 | ----------------------------------------------------------------------------- | |
|
350 | -- HK | |||
|
351 | ----------------------------------------------------------------------------- | |||
|
352 | ||||
|
353 | PROCESS (clk25MHz, resetn) | |||
|
354 | BEGIN -- PROCESS | |||
|
355 | IF resetn = '0' THEN -- asynchronous reset (active low) | |||
|
356 | ||||
|
357 | r.HK_temp_0 <= (OTHERS => '0'); | |||
|
358 | r.HK_temp_1 <= (OTHERS => '0'); | |||
|
359 | r.HK_temp_2 <= (OTHERS => '0'); | |||
|
360 | ||||
|
361 | HK_sel_s <= "00"; | |||
|
362 | ||||
|
363 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge | |||
|
364 | ||||
|
365 | IF HK_val = '1' THEN | |||
|
366 | CASE HK_sel_s IS | |||
|
367 | WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01"; | |||
|
368 | WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10"; | |||
|
369 | WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00"; | |||
|
370 | WHEN OTHERS => NULL; | |||
|
371 | END CASE; | |||
|
372 | ||||
|
373 | END IF; | |||
|
374 | ||||
|
375 | END IF; | |||
|
376 | END PROCESS; | |||
|
377 | ||||
|
378 | HK_sel <= HK_sel_s; | |||
|
379 | ||||
|
380 | END Behavioral; No newline at end of file |
1 | NO CONTENT: file renamed from lib/lpp/lfr_time_management/coarse_time_counter.vhd to lib/lpp/lfr_management/coarse_time_counter.vhd |
|
NO CONTENT: file renamed from lib/lpp/lfr_time_management/coarse_time_counter.vhd to lib/lpp/lfr_management/coarse_time_counter.vhd |
1 | NO CONTENT: file renamed from lib/lpp/lfr_time_management/fine_time_counter.vhd to lib/lpp/lfr_management/fine_time_counter.vhd |
|
NO CONTENT: file renamed from lib/lpp/lfr_time_management/fine_time_counter.vhd to lib/lpp/lfr_management/fine_time_counter.vhd |
@@ -1,174 +1,174 | |||||
1 | ---------------------------------------------------------------------------------- |
|
1 | ---------------------------------------------------------------------------------- | |
2 | -- Company: |
|
2 | -- Company: | |
3 | -- Engineer: |
|
3 | -- Engineer: | |
4 | -- |
|
4 | -- | |
5 | -- Create Date: 11:14:05 07/02/2012 |
|
5 | -- Create Date: 11:14:05 07/02/2012 | |
6 | -- Design Name: |
|
6 | -- Design Name: | |
7 | -- Module Name: lfr_time_management - Behavioral |
|
7 | -- Module Name: lfr_time_management - Behavioral | |
8 | -- Project Name: |
|
8 | -- Project Name: | |
9 | -- Target Devices: |
|
9 | -- Target Devices: | |
10 | -- Tool versions: |
|
10 | -- Tool versions: | |
11 | -- Description: |
|
11 | -- Description: | |
12 | -- |
|
12 | -- | |
13 | -- Dependencies: |
|
13 | -- Dependencies: | |
14 | -- |
|
14 | -- | |
15 | -- Revision: |
|
15 | -- Revision: | |
16 | -- Revision 0.01 - File Created |
|
16 | -- Revision 0.01 - File Created | |
17 | -- Additional Comments: |
|
17 | -- Additional Comments: | |
18 | -- |
|
18 | -- | |
19 | ---------------------------------------------------------------------------------- |
|
19 | ---------------------------------------------------------------------------------- | |
20 | LIBRARY IEEE; |
|
20 | LIBRARY IEEE; | |
21 | USE IEEE.STD_LOGIC_1164.ALL; |
|
21 | USE IEEE.STD_LOGIC_1164.ALL; | |
22 | USE IEEE.NUMERIC_STD.ALL; |
|
22 | USE IEEE.NUMERIC_STD.ALL; | |
23 | LIBRARY lpp; |
|
23 | LIBRARY lpp; | |
24 |
USE lpp.lpp_lfr_ |
|
24 | USE lpp.lpp_lfr_management.ALL; | |
25 |
|
25 | |||
26 | ENTITY lfr_time_management IS |
|
26 | ENTITY lfr_time_management IS | |
27 | GENERIC ( |
|
27 | GENERIC ( | |
28 | FIRST_DIVISION : INTEGER := 374; |
|
28 | FIRST_DIVISION : INTEGER := 374; | |
29 | NB_SECOND_DESYNC : INTEGER := 60); |
|
29 | NB_SECOND_DESYNC : INTEGER := 60); | |
30 | PORT ( |
|
30 | PORT ( | |
31 | clk : IN STD_LOGIC; |
|
31 | clk : IN STD_LOGIC; | |
32 | rstn : IN STD_LOGIC; |
|
32 | rstn : IN STD_LOGIC; | |
33 |
|
33 | |||
34 | tick : IN STD_LOGIC; -- transition signal information |
|
34 | tick : IN STD_LOGIC; -- transition signal information | |
35 |
|
35 | |||
36 | new_coarsetime : IN STD_LOGIC; -- transition signal information |
|
36 | new_coarsetime : IN STD_LOGIC; -- transition signal information | |
37 | coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
37 | coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
38 |
|
38 | |||
39 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
39 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
40 | fine_time_new : OUT STD_LOGIC; |
|
40 | fine_time_new : OUT STD_LOGIC; | |
41 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
41 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
42 | coarse_time_new : OUT STD_LOGIC |
|
42 | coarse_time_new : OUT STD_LOGIC | |
43 | ); |
|
43 | ); | |
44 | END lfr_time_management; |
|
44 | END lfr_time_management; | |
45 |
|
45 | |||
46 | ARCHITECTURE Behavioral OF lfr_time_management IS |
|
46 | ARCHITECTURE Behavioral OF lfr_time_management IS | |
47 |
|
47 | |||
48 | SIGNAL FT_max : STD_LOGIC; |
|
48 | SIGNAL FT_max : STD_LOGIC; | |
49 | SIGNAL FT_half : STD_LOGIC; |
|
49 | SIGNAL FT_half : STD_LOGIC; | |
50 | SIGNAL FT_wait : STD_LOGIC; |
|
50 | SIGNAL FT_wait : STD_LOGIC; | |
51 |
|
51 | |||
52 | TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC); |
|
52 | TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC); | |
53 | SIGNAL state : state_fsm_time_management; |
|
53 | SIGNAL state : state_fsm_time_management; | |
54 |
|
54 | |||
55 | SIGNAL fsm_desync : STD_LOGIC; |
|
55 | SIGNAL fsm_desync : STD_LOGIC; | |
56 | SIGNAL fsm_transition : STD_LOGIC; |
|
56 | SIGNAL fsm_transition : STD_LOGIC; | |
57 |
|
57 | |||
58 | SIGNAL set_TCU : STD_LOGIC; |
|
58 | SIGNAL set_TCU : STD_LOGIC; | |
59 | SIGNAL CT_add1 : STD_LOGIC; |
|
59 | SIGNAL CT_add1 : STD_LOGIC; | |
60 |
|
60 | |||
61 | SIGNAL new_coarsetime_reg : STD_LOGIC; |
|
61 | SIGNAL new_coarsetime_reg : STD_LOGIC; | |
62 |
|
62 | |||
63 | BEGIN |
|
63 | BEGIN | |
64 |
|
64 | |||
65 | ----------------------------------------------------------------------------- |
|
65 | ----------------------------------------------------------------------------- | |
66 | -- |
|
66 | -- | |
67 | ----------------------------------------------------------------------------- |
|
67 | ----------------------------------------------------------------------------- | |
68 | PROCESS (clk, rstn) |
|
68 | PROCESS (clk, rstn) | |
69 | BEGIN -- PROCESS |
|
69 | BEGIN -- PROCESS | |
70 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
70 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
71 | new_coarsetime_reg <= '0'; |
|
71 | new_coarsetime_reg <= '0'; | |
72 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
72 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
73 | IF new_coarsetime = '1' THEN |
|
73 | IF new_coarsetime = '1' THEN | |
74 | new_coarsetime_reg <= '1'; |
|
74 | new_coarsetime_reg <= '1'; | |
75 | ELSIF tick = '1' THEN |
|
75 | ELSIF tick = '1' THEN | |
76 | new_coarsetime_reg <= '0'; |
|
76 | new_coarsetime_reg <= '0'; | |
77 | END IF; |
|
77 | END IF; | |
78 | END IF; |
|
78 | END IF; | |
79 | END PROCESS; |
|
79 | END PROCESS; | |
80 |
|
80 | |||
81 | ----------------------------------------------------------------------------- |
|
81 | ----------------------------------------------------------------------------- | |
82 | -- FINE_TIME |
|
82 | -- FINE_TIME | |
83 | ----------------------------------------------------------------------------- |
|
83 | ----------------------------------------------------------------------------- | |
84 | fine_time_counter_1: fine_time_counter |
|
84 | fine_time_counter_1: fine_time_counter | |
85 | GENERIC MAP ( |
|
85 | GENERIC MAP ( | |
86 | WAITING_TIME => X"0040", |
|
86 | WAITING_TIME => X"0040", | |
87 | FIRST_DIVISION => FIRST_DIVISION) |
|
87 | FIRST_DIVISION => FIRST_DIVISION) | |
88 | PORT MAP ( |
|
88 | PORT MAP ( | |
89 | clk => clk, |
|
89 | clk => clk, | |
90 | rstn => rstn, |
|
90 | rstn => rstn, | |
91 | tick => tick, |
|
91 | tick => tick, | |
92 | fsm_transition => fsm_transition, -- todo |
|
92 | fsm_transition => fsm_transition, -- todo | |
93 | FT_max => FT_max, |
|
93 | FT_max => FT_max, | |
94 | FT_half => FT_half, |
|
94 | FT_half => FT_half, | |
95 | FT_wait => FT_wait, |
|
95 | FT_wait => FT_wait, | |
96 | fine_time => fine_time, |
|
96 | fine_time => fine_time, | |
97 | fine_time_new => fine_time_new); |
|
97 | fine_time_new => fine_time_new); | |
98 |
|
98 | |||
99 | ----------------------------------------------------------------------------- |
|
99 | ----------------------------------------------------------------------------- | |
100 | -- COARSE_TIME |
|
100 | -- COARSE_TIME | |
101 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
102 | coarse_time_counter_1: coarse_time_counter |
|
102 | coarse_time_counter_1: coarse_time_counter | |
103 | GENERIC MAP( |
|
103 | GENERIC MAP( | |
104 | NB_SECOND_DESYNC => NB_SECOND_DESYNC ) |
|
104 | NB_SECOND_DESYNC => NB_SECOND_DESYNC ) | |
105 | PORT MAP ( |
|
105 | PORT MAP ( | |
106 | clk => clk, |
|
106 | clk => clk, | |
107 | rstn => rstn, |
|
107 | rstn => rstn, | |
108 | tick => tick, |
|
108 | tick => tick, | |
109 | set_TCU => set_TCU, -- todo |
|
109 | set_TCU => set_TCU, -- todo | |
110 | new_TCU => new_coarsetime_reg, |
|
110 | new_TCU => new_coarsetime_reg, | |
111 | set_TCU_value => coarsetime_reg, -- todo |
|
111 | set_TCU_value => coarsetime_reg, -- todo | |
112 | CT_add1 => CT_add1, -- todo |
|
112 | CT_add1 => CT_add1, -- todo | |
113 | fsm_desync => fsm_desync, -- todo |
|
113 | fsm_desync => fsm_desync, -- todo | |
114 | FT_max => FT_max, |
|
114 | FT_max => FT_max, | |
115 | coarse_time => coarse_time, |
|
115 | coarse_time => coarse_time, | |
116 | coarse_time_new => coarse_time_new); |
|
116 | coarse_time_new => coarse_time_new); | |
117 |
|
117 | |||
118 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
119 | -- FSM |
|
119 | -- FSM | |
120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
121 | fsm_desync <= '1' WHEN state = DESYNC ELSE '0'; |
|
121 | fsm_desync <= '1' WHEN state = DESYNC ELSE '0'; | |
122 | fsm_transition <= '1' WHEN state = TRANSITION ELSE '0'; |
|
122 | fsm_transition <= '1' WHEN state = TRANSITION ELSE '0'; | |
123 |
|
123 | |||
124 | PROCESS (clk, rstn) |
|
124 | PROCESS (clk, rstn) | |
125 | BEGIN -- PROCESS |
|
125 | BEGIN -- PROCESS | |
126 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
126 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
127 | state <= DESYNC; |
|
127 | state <= DESYNC; | |
128 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
128 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
129 | --CT_add1 <= '0'; |
|
129 | --CT_add1 <= '0'; | |
130 | set_TCU <= '0'; |
|
130 | set_TCU <= '0'; | |
131 | CASE state IS |
|
131 | CASE state IS | |
132 | WHEN DESYNC => |
|
132 | WHEN DESYNC => | |
133 | IF tick = '1' THEN |
|
133 | IF tick = '1' THEN | |
134 | state <= SYNC; |
|
134 | state <= SYNC; | |
135 | set_TCU <= new_coarsetime_reg; |
|
135 | set_TCU <= new_coarsetime_reg; | |
136 | --IF new_coarsetime = '0' AND FT_half = '1' THEN |
|
136 | --IF new_coarsetime = '0' AND FT_half = '1' THEN | |
137 | -- CT_add1 <= '1'; |
|
137 | -- CT_add1 <= '1'; | |
138 | --END IF; |
|
138 | --END IF; | |
139 | --ELSIF FT_max = '1' THEN |
|
139 | --ELSIF FT_max = '1' THEN | |
140 | -- CT_add1 <= '1'; |
|
140 | -- CT_add1 <= '1'; | |
141 | END IF; |
|
141 | END IF; | |
142 | WHEN TRANSITION => |
|
142 | WHEN TRANSITION => | |
143 | IF tick = '1' THEN |
|
143 | IF tick = '1' THEN | |
144 | state <= SYNC; |
|
144 | state <= SYNC; | |
145 | set_TCU <= new_coarsetime_reg; |
|
145 | set_TCU <= new_coarsetime_reg; | |
146 | --IF new_coarsetime = '0' THEN |
|
146 | --IF new_coarsetime = '0' THEN | |
147 | -- CT_add1 <= '1'; |
|
147 | -- CT_add1 <= '1'; | |
148 | --END IF; |
|
148 | --END IF; | |
149 | ELSIF FT_wait = '1' THEN |
|
149 | ELSIF FT_wait = '1' THEN | |
150 | --CT_add1 <= '1'; |
|
150 | --CT_add1 <= '1'; | |
151 | state <= DESYNC; |
|
151 | state <= DESYNC; | |
152 | END IF; |
|
152 | END IF; | |
153 | WHEN SYNC => |
|
153 | WHEN SYNC => | |
154 | IF tick = '1' THEN |
|
154 | IF tick = '1' THEN | |
155 | set_TCU <= new_coarsetime_reg; |
|
155 | set_TCU <= new_coarsetime_reg; | |
156 | --IF new_coarsetime = '0' THEN |
|
156 | --IF new_coarsetime = '0' THEN | |
157 | -- CT_add1 <= '1'; |
|
157 | -- CT_add1 <= '1'; | |
158 | --END IF; |
|
158 | --END IF; | |
159 | ELSIF FT_max = '1' THEN |
|
159 | ELSIF FT_max = '1' THEN | |
160 | state <= TRANSITION; |
|
160 | state <= TRANSITION; | |
161 | END IF; |
|
161 | END IF; | |
162 | WHEN OTHERS => NULL; |
|
162 | WHEN OTHERS => NULL; | |
163 | END CASE; |
|
163 | END CASE; | |
164 | END IF; |
|
164 | END IF; | |
165 | END PROCESS; |
|
165 | END PROCESS; | |
166 |
|
166 | |||
167 |
|
167 | |||
168 | CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE |
|
168 | CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE | |
169 | '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE |
|
169 | '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE | |
170 | '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE |
|
170 | '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE | |
171 | '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE |
|
171 | '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE | |
172 | '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE |
|
172 | '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE | |
173 | '0'; |
|
173 | '0'; | |
174 | END Behavioral; |
|
174 | END Behavioral; |
@@ -1,103 +1,105 | |||||
1 | ---------------------------------------------------------------------------------- |
|
1 | ---------------------------------------------------------------------------------- | |
2 | -- Company: |
|
2 | -- Company: | |
3 | -- Engineer: |
|
3 | -- Engineer: | |
4 | -- |
|
4 | -- | |
5 | -- Create Date: 13:04:01 07/02/2012 |
|
5 | -- Create Date: 13:04:01 07/02/2012 | |
6 | -- Design Name: |
|
6 | -- Design Name: | |
7 | -- Module Name: lpp_lfr_time_management - Behavioral |
|
7 | -- Module Name: lpp_lfr_time_management - Behavioral | |
8 | -- Project Name: |
|
8 | -- Project Name: | |
9 | -- Target Devices: |
|
9 | -- Target Devices: | |
10 | -- Tool versions: |
|
10 | -- Tool versions: | |
11 | -- Description: |
|
11 | -- Description: | |
12 | -- |
|
12 | -- | |
13 | -- Dependencies: |
|
13 | -- Dependencies: | |
14 | -- |
|
14 | -- | |
15 | -- Revision: |
|
15 | -- Revision: | |
16 | -- Revision 0.01 - File Created |
|
16 | -- Revision 0.01 - File Created | |
17 | -- Additional Comments: |
|
17 | -- Additional Comments: | |
18 | -- |
|
18 | -- | |
19 | ---------------------------------------------------------------------------------- |
|
19 | ---------------------------------------------------------------------------------- | |
20 | LIBRARY IEEE; |
|
20 | LIBRARY IEEE; | |
21 | USE IEEE.STD_LOGIC_1164.ALL; |
|
21 | USE IEEE.STD_LOGIC_1164.ALL; | |
22 | LIBRARY grlib; |
|
22 | LIBRARY grlib; | |
23 | USE grlib.amba.ALL; |
|
23 | USE grlib.amba.ALL; | |
24 | USE grlib.stdlib.ALL; |
|
24 | USE grlib.stdlib.ALL; | |
25 | USE grlib.devices.ALL; |
|
25 | USE grlib.devices.ALL; | |
26 |
|
26 | |||
27 |
PACKAGE lpp_lfr_ |
|
27 | PACKAGE lpp_lfr_management IS | |
28 |
|
28 | |||
29 | --*************************** |
|
29 | --*************************** | |
30 |
-- APB_LFR_ |
|
30 | -- APB_LFR_MANAGEMENT | |
31 |
|
31 | |||
32 |
COMPONENT apb_lfr_ |
|
32 | COMPONENT apb_lfr_management | |
33 | GENERIC( |
|
33 | GENERIC ( | |
34 |
pindex |
|
34 | pindex : INTEGER; | |
35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
|
35 | paddr : INTEGER; | |
36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
|
36 | pmask : INTEGER; | |
37 |
FIRST_DIVISION |
|
37 | FIRST_DIVISION : INTEGER; | |
38 |
NB_SECOND_DESYNC |
|
38 | NB_SECOND_DESYNC : INTEGER); | |
39 | PORT ( |
|
39 | PORT ( | |
40 |
clk25MHz : IN STD_LOGIC; |
|
40 | clk25MHz : IN STD_LOGIC; | |
41 |
clk24_576MHz : IN STD_LOGIC; |
|
41 | clk24_576MHz : IN STD_LOGIC; | |
42 |
resetn : IN STD_LOGIC; |
|
42 | resetn : IN STD_LOGIC; | |
43 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
|
43 | grspw_tick : IN STD_LOGIC; | |
44 |
apbi : IN apb_slv_in_type; |
|
44 | apbi : IN apb_slv_in_type; | |
45 |
apbo : OUT apb_slv_out_type; |
|
45 | apbo : OUT apb_slv_out_type; | |
46 |
|
|
46 | HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
47 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME |
|
47 | HK_val : IN STD_LOGIC; | |
48 | LFR_soft_rstn : OUT STD_LOGIC |
|
48 | HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |
49 | ); |
|
49 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
50 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
|
51 | LFR_soft_rstn : OUT STD_LOGIC); | |||
50 | END COMPONENT; |
|
52 | END COMPONENT; | |
51 |
|
53 | |||
52 | COMPONENT lfr_time_management |
|
54 | COMPONENT lfr_time_management | |
53 | GENERIC ( |
|
55 | GENERIC ( | |
54 | FIRST_DIVISION : INTEGER; |
|
56 | FIRST_DIVISION : INTEGER; | |
55 | NB_SECOND_DESYNC : INTEGER); |
|
57 | NB_SECOND_DESYNC : INTEGER); | |
56 | PORT ( |
|
58 | PORT ( | |
57 | clk : IN STD_LOGIC; |
|
59 | clk : IN STD_LOGIC; | |
58 | rstn : IN STD_LOGIC; |
|
60 | rstn : IN STD_LOGIC; | |
59 | tick : IN STD_LOGIC; |
|
61 | tick : IN STD_LOGIC; | |
60 | new_coarsetime : IN STD_LOGIC; |
|
62 | new_coarsetime : IN STD_LOGIC; | |
61 | coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
63 | coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
62 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
64 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
63 | fine_time_new : OUT STD_LOGIC; |
|
65 | fine_time_new : OUT STD_LOGIC; | |
64 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
66 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
65 | coarse_time_new : OUT STD_LOGIC); |
|
67 | coarse_time_new : OUT STD_LOGIC); | |
66 | END COMPONENT; |
|
68 | END COMPONENT; | |
67 |
|
69 | |||
68 | COMPONENT coarse_time_counter |
|
70 | COMPONENT coarse_time_counter | |
69 | GENERIC ( |
|
71 | GENERIC ( | |
70 | NB_SECOND_DESYNC : INTEGER ); |
|
72 | NB_SECOND_DESYNC : INTEGER ); | |
71 | PORT ( |
|
73 | PORT ( | |
72 | clk : IN STD_LOGIC; |
|
74 | clk : IN STD_LOGIC; | |
73 | rstn : IN STD_LOGIC; |
|
75 | rstn : IN STD_LOGIC; | |
74 | tick : IN STD_LOGIC; |
|
76 | tick : IN STD_LOGIC; | |
75 | set_TCU : IN STD_LOGIC; |
|
77 | set_TCU : IN STD_LOGIC; | |
76 | new_TCU : IN STD_LOGIC; |
|
78 | new_TCU : IN STD_LOGIC; | |
77 | set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
79 | set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
78 | CT_add1 : IN STD_LOGIC; |
|
80 | CT_add1 : IN STD_LOGIC; | |
79 | fsm_desync : IN STD_LOGIC; |
|
81 | fsm_desync : IN STD_LOGIC; | |
80 | FT_max : IN STD_LOGIC; |
|
82 | FT_max : IN STD_LOGIC; | |
81 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
82 | coarse_time_new : OUT STD_LOGIC); |
|
84 | coarse_time_new : OUT STD_LOGIC); | |
83 | END COMPONENT; |
|
85 | END COMPONENT; | |
84 |
|
86 | |||
85 | COMPONENT fine_time_counter |
|
87 | COMPONENT fine_time_counter | |
86 | GENERIC ( |
|
88 | GENERIC ( | |
87 | WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
89 | WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
88 | FIRST_DIVISION : INTEGER ); |
|
90 | FIRST_DIVISION : INTEGER ); | |
89 | PORT ( |
|
91 | PORT ( | |
90 | clk : IN STD_LOGIC; |
|
92 | clk : IN STD_LOGIC; | |
91 | rstn : IN STD_LOGIC; |
|
93 | rstn : IN STD_LOGIC; | |
92 | tick : IN STD_LOGIC; |
|
94 | tick : IN STD_LOGIC; | |
93 | fsm_transition : IN STD_LOGIC; |
|
95 | fsm_transition : IN STD_LOGIC; | |
94 | FT_max : OUT STD_LOGIC; |
|
96 | FT_max : OUT STD_LOGIC; | |
95 | FT_half : OUT STD_LOGIC; |
|
97 | FT_half : OUT STD_LOGIC; | |
96 | FT_wait : OUT STD_LOGIC; |
|
98 | FT_wait : OUT STD_LOGIC; | |
97 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
99 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
98 | fine_time_new : OUT STD_LOGIC); |
|
100 | fine_time_new : OUT STD_LOGIC); | |
99 | END COMPONENT; |
|
101 | END COMPONENT; | |
100 |
|
102 | |||
101 |
|
103 | |||
102 |
END lpp_lfr_ |
|
104 | END lpp_lfr_management; | |
103 |
|
105 |
@@ -1,12 +1,15 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 |
PACKAGE lpp_lfr_ |
|
5 | PACKAGE lpp_lfr_management_apbreg_pkg IS | |
6 |
|
6 | |||
7 |
CONSTANT ADDR_LFR_ |
|
7 | CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000"; | |
8 |
CONSTANT ADDR_LFR_ |
|
8 | CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001"; | |
9 |
CONSTANT ADDR_LFR_ |
|
9 | CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010"; | |
10 |
CONSTANT ADDR_LFR_ |
|
10 | CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011"; | |
|
11 | CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100"; | |||
|
12 | CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101"; | |||
|
13 | CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110"; | |||
11 |
|
14 | |||
12 |
END lpp_lfr_ |
|
15 | END lpp_lfr_management_apbreg_pkg; |
@@ -1,6 +1,6 | |||||
1 |
lpp_lfr_ |
|
1 | lpp_lfr_management.vhd | |
2 |
lpp_lfr_ |
|
2 | lpp_lfr_management_apbreg_pkg.vhd | |
3 |
apb_lfr_ |
|
3 | apb_lfr_management.vhd | |
4 | lfr_time_management.vhd |
|
4 | lfr_time_management.vhd | |
5 | fine_time_counter.vhd |
|
5 | fine_time_counter.vhd | |
6 | coarse_time_counter.vhd |
|
6 | coarse_time_counter.vhd |
@@ -1,491 +1,490 | |||||
1 | ----------------------------------------------------------------------------- |
|
1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
|
2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
|
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
|
7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 |
|
19 | |||
20 |
|
20 | |||
21 | LIBRARY ieee; |
|
21 | LIBRARY ieee; | |
22 | USE ieee.std_logic_1164.ALL; |
|
22 | USE ieee.std_logic_1164.ALL; | |
23 | LIBRARY grlib; |
|
23 | LIBRARY grlib; | |
24 | USE grlib.amba.ALL; |
|
24 | USE grlib.amba.ALL; | |
25 | USE grlib.stdlib.ALL; |
|
25 | USE grlib.stdlib.ALL; | |
26 | LIBRARY techmap; |
|
26 | LIBRARY techmap; | |
27 | USE techmap.gencomp.ALL; |
|
27 | USE techmap.gencomp.ALL; | |
28 | LIBRARY gaisler; |
|
28 | LIBRARY gaisler; | |
29 | USE gaisler.memctrl.ALL; |
|
29 | USE gaisler.memctrl.ALL; | |
30 | USE gaisler.leon3.ALL; |
|
30 | USE gaisler.leon3.ALL; | |
31 | USE gaisler.uart.ALL; |
|
31 | USE gaisler.uart.ALL; | |
32 | USE gaisler.misc.ALL; |
|
32 | USE gaisler.misc.ALL; | |
33 | USE gaisler.spacewire.ALL; -- PLE |
|
33 | USE gaisler.spacewire.ALL; -- PLE | |
34 | LIBRARY esa; |
|
34 | LIBRARY esa; | |
35 | USE esa.memoryctrl.ALL; |
|
35 | USE esa.memoryctrl.ALL; | |
36 | LIBRARY lpp; |
|
36 | LIBRARY lpp; | |
37 | USE lpp.lpp_memory.ALL; |
|
37 | USE lpp.lpp_memory.ALL; | |
38 | USE lpp.lpp_ad_conv.ALL; |
|
38 | USE lpp.lpp_ad_conv.ALL; | |
39 | USE lpp.lpp_lfr_pkg.ALL; |
|
39 | USE lpp.lpp_lfr_pkg.ALL; | |
40 | USE lpp.iir_filter.ALL; |
|
40 | USE lpp.iir_filter.ALL; | |
41 | USE lpp.general_purpose.ALL; |
|
41 | USE lpp.general_purpose.ALL; | |
42 | USE lpp.lpp_lfr_time_management.ALL; |
|
|||
43 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
42 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
44 | LIBRARY iap; |
|
43 | LIBRARY iap; | |
45 | USE iap.memctrl.all; |
|
44 | USE iap.memctrl.all; | |
46 |
|
45 | |||
47 |
|
46 | |||
48 | ENTITY leon3_soc IS |
|
47 | ENTITY leon3_soc IS | |
49 | GENERIC ( |
|
48 | GENERIC ( | |
50 | fabtech : INTEGER := apa3e; |
|
49 | fabtech : INTEGER := apa3e; | |
51 | memtech : INTEGER := apa3e; |
|
50 | memtech : INTEGER := apa3e; | |
52 | padtech : INTEGER := inferred; |
|
51 | padtech : INTEGER := inferred; | |
53 | clktech : INTEGER := inferred; |
|
52 | clktech : INTEGER := inferred; | |
54 | disas : INTEGER := 0; -- Enable disassembly to console |
|
53 | disas : INTEGER := 0; -- Enable disassembly to console | |
55 | dbguart : INTEGER := 0; -- Print UART on console |
|
54 | dbguart : INTEGER := 0; -- Print UART on console | |
56 | pclow : INTEGER := 2; |
|
55 | pclow : INTEGER := 2; | |
57 | -- |
|
56 | -- | |
58 | clk_freq : INTEGER := 25000; --kHz |
|
57 | clk_freq : INTEGER := 25000; --kHz | |
59 | -- |
|
58 | -- | |
60 | NB_CPU : INTEGER := 1; |
|
59 | NB_CPU : INTEGER := 1; | |
61 | ENABLE_FPU : INTEGER := 1; |
|
60 | ENABLE_FPU : INTEGER := 1; | |
62 | FPU_NETLIST : INTEGER := 1; |
|
61 | FPU_NETLIST : INTEGER := 1; | |
63 | ENABLE_DSU : INTEGER := 1; |
|
62 | ENABLE_DSU : INTEGER := 1; | |
64 | ENABLE_AHB_UART : INTEGER := 1; |
|
63 | ENABLE_AHB_UART : INTEGER := 1; | |
65 | ENABLE_APB_UART : INTEGER := 1; |
|
64 | ENABLE_APB_UART : INTEGER := 1; | |
66 | ENABLE_IRQMP : INTEGER := 1; |
|
65 | ENABLE_IRQMP : INTEGER := 1; | |
67 | ENABLE_GPT : INTEGER := 1; |
|
66 | ENABLE_GPT : INTEGER := 1; | |
68 | -- |
|
67 | -- | |
69 | NB_AHB_MASTER : INTEGER := 1; |
|
68 | NB_AHB_MASTER : INTEGER := 1; | |
70 | NB_AHB_SLAVE : INTEGER := 1; |
|
69 | NB_AHB_SLAVE : INTEGER := 1; | |
71 | NB_APB_SLAVE : INTEGER := 1; |
|
70 | NB_APB_SLAVE : INTEGER := 1; | |
72 | -- |
|
71 | -- | |
73 | ADDRESS_SIZE : INTEGER := 20; |
|
72 | ADDRESS_SIZE : INTEGER := 20; | |
74 | USES_IAP_MEMCTRLR : INTEGER := 0 |
|
73 | USES_IAP_MEMCTRLR : INTEGER := 0 | |
75 |
|
74 | |||
76 | ); |
|
75 | ); | |
77 | PORT ( |
|
76 | PORT ( | |
78 | clk : IN STD_ULOGIC; |
|
77 | clk : IN STD_ULOGIC; | |
79 | reset : IN STD_ULOGIC; |
|
78 | reset : IN STD_ULOGIC; | |
80 |
|
79 | |||
81 | errorn : OUT STD_ULOGIC; |
|
80 | errorn : OUT STD_ULOGIC; | |
82 |
|
81 | |||
83 | -- UART AHB --------------------------------------------------------------- |
|
82 | -- UART AHB --------------------------------------------------------------- | |
84 | ahbrxd : IN STD_ULOGIC; -- DSU rx data |
|
83 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
85 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data |
|
84 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
86 |
|
85 | |||
87 | -- UART APB --------------------------------------------------------------- |
|
86 | -- UART APB --------------------------------------------------------------- | |
88 | urxd1 : IN STD_ULOGIC; -- UART1 rx data |
|
87 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
89 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data |
|
88 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
90 |
|
89 | |||
91 | -- RAM -------------------------------------------------------------------- |
|
90 | -- RAM -------------------------------------------------------------------- | |
92 | address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0); |
|
91 | address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0); | |
93 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
94 | nSRAM_BE0 : OUT STD_LOGIC; |
|
93 | nSRAM_BE0 : OUT STD_LOGIC; | |
95 | nSRAM_BE1 : OUT STD_LOGIC; |
|
94 | nSRAM_BE1 : OUT STD_LOGIC; | |
96 | nSRAM_BE2 : OUT STD_LOGIC; |
|
95 | nSRAM_BE2 : OUT STD_LOGIC; | |
97 | nSRAM_BE3 : OUT STD_LOGIC; |
|
96 | nSRAM_BE3 : OUT STD_LOGIC; | |
98 | nSRAM_WE : OUT STD_LOGIC; |
|
97 | nSRAM_WE : OUT STD_LOGIC; | |
99 | nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0); |
|
98 | nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0); | |
100 | nSRAM_OE : OUT STD_LOGIC; |
|
99 | nSRAM_OE : OUT STD_LOGIC; | |
101 | nSRAM_READY : IN STD_LOGIC; |
|
100 | nSRAM_READY : IN STD_LOGIC; | |
102 | SRAM_MBE : INOUT STD_LOGIC; |
|
101 | SRAM_MBE : INOUT STD_LOGIC; | |
103 | -- APB -------------------------------------------------------------------- |
|
102 | -- APB -------------------------------------------------------------------- | |
104 | apbi_ext : OUT apb_slv_in_type; |
|
103 | apbi_ext : OUT apb_slv_in_type; | |
105 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); |
|
104 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); | |
106 | -- AHB_Slave -------------------------------------------------------------- |
|
105 | -- AHB_Slave -------------------------------------------------------------- | |
107 | ahbi_s_ext : OUT ahb_slv_in_type; |
|
106 | ahbi_s_ext : OUT ahb_slv_in_type; | |
108 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); |
|
107 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); | |
109 | -- AHB_Master ------------------------------------------------------------- |
|
108 | -- AHB_Master ------------------------------------------------------------- | |
110 | ahbi_m_ext : OUT AHB_Mst_In_Type; |
|
109 | ahbi_m_ext : OUT AHB_Mst_In_Type; | |
111 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) |
|
110 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) | |
112 |
|
111 | |||
113 | ); |
|
112 | ); | |
114 | END; |
|
113 | END; | |
115 |
|
114 | |||
116 | ARCHITECTURE Behavioral OF leon3_soc IS |
|
115 | ARCHITECTURE Behavioral OF leon3_soc IS | |
117 |
|
116 | |||
118 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
119 | -- CONFIG ------------------------------------------------------------------- |
|
118 | -- CONFIG ------------------------------------------------------------------- | |
120 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
121 |
|
120 | |||
122 | -- Clock generator |
|
121 | -- Clock generator | |
123 | constant CFG_CLKMUL : integer := (1); |
|
122 | constant CFG_CLKMUL : integer := (1); | |
124 | constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz |
|
123 | constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz | |
125 | constant CFG_OCLKDIV : integer := (1); |
|
124 | constant CFG_OCLKDIV : integer := (1); | |
126 | constant CFG_CLK_NOFB : integer := 0; |
|
125 | constant CFG_CLK_NOFB : integer := 0; | |
127 | -- LEON3 processor core |
|
126 | -- LEON3 processor core | |
128 | constant CFG_LEON3 : integer := 1; |
|
127 | constant CFG_LEON3 : integer := 1; | |
129 | constant CFG_NCPU : integer := NB_CPU; |
|
128 | constant CFG_NCPU : integer := NB_CPU; | |
130 | constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC |
|
129 | constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC | |
131 | constant CFG_V8 : integer := 0; |
|
130 | constant CFG_V8 : integer := 0; | |
132 | constant CFG_MAC : integer := 0; |
|
131 | constant CFG_MAC : integer := 0; | |
133 | constant CFG_SVT : integer := 0; |
|
132 | constant CFG_SVT : integer := 0; | |
134 | constant CFG_RSTADDR : integer := 16#00000#; |
|
133 | constant CFG_RSTADDR : integer := 16#00000#; | |
135 | constant CFG_LDDEL : integer := (1); |
|
134 | constant CFG_LDDEL : integer := (1); | |
136 | constant CFG_NWP : integer := (0); |
|
135 | constant CFG_NWP : integer := (0); | |
137 | constant CFG_PWD : integer := 1*2; |
|
136 | constant CFG_PWD : integer := 1*2; | |
138 | constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); |
|
137 | constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST); | |
139 | -- 1*(8 + 16 * 0) => grfpu-light |
|
138 | -- 1*(8 + 16 * 0) => grfpu-light | |
140 | -- 1*(8 + 16 * 1) => netlist |
|
139 | -- 1*(8 + 16 * 1) => netlist | |
141 | -- 0*(8 + 16 * 0) => No FPU |
|
140 | -- 0*(8 + 16 * 0) => No FPU | |
142 | -- 0*(8 + 16 * 1) => No FPU; |
|
141 | -- 0*(8 + 16 * 1) => No FPU; | |
143 | constant CFG_ICEN : integer := 1; |
|
142 | constant CFG_ICEN : integer := 1; | |
144 | constant CFG_ISETS : integer := 1; |
|
143 | constant CFG_ISETS : integer := 1; | |
145 | constant CFG_ISETSZ : integer := 4; |
|
144 | constant CFG_ISETSZ : integer := 4; | |
146 | constant CFG_ILINE : integer := 4; |
|
145 | constant CFG_ILINE : integer := 4; | |
147 | constant CFG_IREPL : integer := 0; |
|
146 | constant CFG_IREPL : integer := 0; | |
148 | constant CFG_ILOCK : integer := 0; |
|
147 | constant CFG_ILOCK : integer := 0; | |
149 | constant CFG_ILRAMEN : integer := 0; |
|
148 | constant CFG_ILRAMEN : integer := 0; | |
150 | constant CFG_ILRAMADDR: integer := 16#8E#; |
|
149 | constant CFG_ILRAMADDR: integer := 16#8E#; | |
151 | constant CFG_ILRAMSZ : integer := 1; |
|
150 | constant CFG_ILRAMSZ : integer := 1; | |
152 | constant CFG_DCEN : integer := 1; |
|
151 | constant CFG_DCEN : integer := 1; | |
153 | constant CFG_DSETS : integer := 1; |
|
152 | constant CFG_DSETS : integer := 1; | |
154 | constant CFG_DSETSZ : integer := 4; |
|
153 | constant CFG_DSETSZ : integer := 4; | |
155 | constant CFG_DLINE : integer := 4; |
|
154 | constant CFG_DLINE : integer := 4; | |
156 | constant CFG_DREPL : integer := 0; |
|
155 | constant CFG_DREPL : integer := 0; | |
157 | constant CFG_DLOCK : integer := 0; |
|
156 | constant CFG_DLOCK : integer := 0; | |
158 | constant CFG_DSNOOP : integer := 0 + 0 + 4*0; |
|
157 | constant CFG_DSNOOP : integer := 0 + 0 + 4*0; | |
159 | constant CFG_DLRAMEN : integer := 0; |
|
158 | constant CFG_DLRAMEN : integer := 0; | |
160 | constant CFG_DLRAMADDR: integer := 16#8F#; |
|
159 | constant CFG_DLRAMADDR: integer := 16#8F#; | |
161 | constant CFG_DLRAMSZ : integer := 1; |
|
160 | constant CFG_DLRAMSZ : integer := 1; | |
162 | constant CFG_MMUEN : integer := 0; |
|
161 | constant CFG_MMUEN : integer := 0; | |
163 | constant CFG_ITLBNUM : integer := 2; |
|
162 | constant CFG_ITLBNUM : integer := 2; | |
164 | constant CFG_DTLBNUM : integer := 2; |
|
163 | constant CFG_DTLBNUM : integer := 2; | |
165 | constant CFG_TLB_TYPE : integer := 1 + 0*2; |
|
164 | constant CFG_TLB_TYPE : integer := 1 + 0*2; | |
166 | constant CFG_TLB_REP : integer := 1; |
|
165 | constant CFG_TLB_REP : integer := 1; | |
167 |
|
166 | |||
168 | constant CFG_DSU : integer := ENABLE_DSU; |
|
167 | constant CFG_DSU : integer := ENABLE_DSU; | |
169 | constant CFG_ITBSZ : integer := 0; |
|
168 | constant CFG_ITBSZ : integer := 0; | |
170 | constant CFG_ATBSZ : integer := 0; |
|
169 | constant CFG_ATBSZ : integer := 0; | |
171 |
|
170 | |||
172 | -- AMBA settings |
|
171 | -- AMBA settings | |
173 | constant CFG_DEFMST : integer := (0); |
|
172 | constant CFG_DEFMST : integer := (0); | |
174 | constant CFG_RROBIN : integer := 1; |
|
173 | constant CFG_RROBIN : integer := 1; | |
175 | constant CFG_SPLIT : integer := 0; |
|
174 | constant CFG_SPLIT : integer := 0; | |
176 | constant CFG_AHBIO : integer := 16#FFF#; |
|
175 | constant CFG_AHBIO : integer := 16#FFF#; | |
177 | constant CFG_APBADDR : integer := 16#800#; |
|
176 | constant CFG_APBADDR : integer := 16#800#; | |
178 |
|
177 | |||
179 | -- DSU UART |
|
178 | -- DSU UART | |
180 | constant CFG_AHB_UART : integer := ENABLE_AHB_UART; |
|
179 | constant CFG_AHB_UART : integer := ENABLE_AHB_UART; | |
181 |
|
180 | |||
182 | -- LEON2 memory controller |
|
181 | -- LEON2 memory controller | |
183 | constant CFG_MCTRL_SDEN : integer := 0; |
|
182 | constant CFG_MCTRL_SDEN : integer := 0; | |
184 |
|
183 | |||
185 | -- UART 1 |
|
184 | -- UART 1 | |
186 | constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; |
|
185 | constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART; | |
187 | constant CFG_UART1_FIFO : integer := 1; |
|
186 | constant CFG_UART1_FIFO : integer := 1; | |
188 |
|
187 | |||
189 | -- LEON3 interrupt controller |
|
188 | -- LEON3 interrupt controller | |
190 | constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; |
|
189 | constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP; | |
191 |
|
190 | |||
192 | -- Modular timer |
|
191 | -- Modular timer | |
193 | constant CFG_GPT_ENABLE : integer := ENABLE_GPT; |
|
192 | constant CFG_GPT_ENABLE : integer := ENABLE_GPT; | |
194 | constant CFG_GPT_NTIM : integer := (2); |
|
193 | constant CFG_GPT_NTIM : integer := (2); | |
195 | constant CFG_GPT_SW : integer := (8); |
|
194 | constant CFG_GPT_SW : integer := (8); | |
196 | constant CFG_GPT_TW : integer := (32); |
|
195 | constant CFG_GPT_TW : integer := (32); | |
197 | constant CFG_GPT_IRQ : integer := (8); |
|
196 | constant CFG_GPT_IRQ : integer := (8); | |
198 | constant CFG_GPT_SEPIRQ : integer := 1; |
|
197 | constant CFG_GPT_SEPIRQ : integer := 1; | |
199 | constant CFG_GPT_WDOGEN : integer := 0; |
|
198 | constant CFG_GPT_WDOGEN : integer := 0; | |
200 | constant CFG_GPT_WDOG : integer := 16#0#; |
|
199 | constant CFG_GPT_WDOG : integer := 16#0#; | |
201 | ----------------------------------------------------------------------------- |
|
200 | ----------------------------------------------------------------------------- | |
202 |
|
201 | |||
203 | ----------------------------------------------------------------------------- |
|
202 | ----------------------------------------------------------------------------- | |
204 | -- SIGNALs |
|
203 | -- SIGNALs | |
205 | ----------------------------------------------------------------------------- |
|
204 | ----------------------------------------------------------------------------- | |
206 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; |
|
205 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; | |
207 | -- CLK & RST -- |
|
206 | -- CLK & RST -- | |
208 | SIGNAL clk2x : STD_ULOGIC; |
|
207 | SIGNAL clk2x : STD_ULOGIC; | |
209 | SIGNAL clkmn : STD_ULOGIC; |
|
208 | SIGNAL clkmn : STD_ULOGIC; | |
210 | SIGNAL clkm : STD_ULOGIC; |
|
209 | SIGNAL clkm : STD_ULOGIC; | |
211 | SIGNAL rstn : STD_ULOGIC; |
|
210 | SIGNAL rstn : STD_ULOGIC; | |
212 | SIGNAL rstraw : STD_ULOGIC; |
|
211 | SIGNAL rstraw : STD_ULOGIC; | |
213 | SIGNAL pciclk : STD_ULOGIC; |
|
212 | SIGNAL pciclk : STD_ULOGIC; | |
214 | SIGNAL sdclkl : STD_ULOGIC; |
|
213 | SIGNAL sdclkl : STD_ULOGIC; | |
215 | SIGNAL cgi : clkgen_in_type; |
|
214 | SIGNAL cgi : clkgen_in_type; | |
216 | SIGNAL cgo : clkgen_out_type; |
|
215 | SIGNAL cgo : clkgen_out_type; | |
217 | --- AHB / APB |
|
216 | --- AHB / APB | |
218 | SIGNAL apbi : apb_slv_in_type; |
|
217 | SIGNAL apbi : apb_slv_in_type; | |
219 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
|
218 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
220 | SIGNAL ahbsi : ahb_slv_in_type; |
|
219 | SIGNAL ahbsi : ahb_slv_in_type; | |
221 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
|
220 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
222 | SIGNAL ahbmi : ahb_mst_in_type; |
|
221 | SIGNAL ahbmi : ahb_mst_in_type; | |
223 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
|
222 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
224 | --UART |
|
223 | --UART | |
225 | SIGNAL ahbuarti : uart_in_type; |
|
224 | SIGNAL ahbuarti : uart_in_type; | |
226 | SIGNAL ahbuarto : uart_out_type; |
|
225 | SIGNAL ahbuarto : uart_out_type; | |
227 | SIGNAL apbuarti : uart_in_type; |
|
226 | SIGNAL apbuarti : uart_in_type; | |
228 | SIGNAL apbuarto : uart_out_type; |
|
227 | SIGNAL apbuarto : uart_out_type; | |
229 | --MEM CTRLR |
|
228 | --MEM CTRLR | |
230 | SIGNAL memi : memory_in_type; |
|
229 | SIGNAL memi : memory_in_type; | |
231 | SIGNAL memo : memory_out_type; |
|
230 | SIGNAL memo : memory_out_type; | |
232 | SIGNAL wpo : wprot_out_type; |
|
231 | SIGNAL wpo : wprot_out_type; | |
233 | SIGNAL sdo : sdram_out_type; |
|
232 | SIGNAL sdo : sdram_out_type; | |
234 | SIGNAl mbe : std_logic; -- enable memory programming |
|
233 | SIGNAl mbe : std_logic; -- enable memory programming | |
235 | SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal |
|
234 | SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal | |
236 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0); |
|
235 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0); | |
237 | SIGNAL nSRAM_OE_s : STD_LOGIC; |
|
236 | SIGNAL nSRAM_OE_s : STD_LOGIC; | |
238 | --IRQ |
|
237 | --IRQ | |
239 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
|
238 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
240 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
|
239 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
241 | --Timer |
|
240 | --Timer | |
242 | SIGNAL gpti : gptimer_in_type; |
|
241 | SIGNAL gpti : gptimer_in_type; | |
243 | SIGNAL gpto : gptimer_out_type; |
|
242 | SIGNAL gpto : gptimer_out_type; | |
244 | --DSU |
|
243 | --DSU | |
245 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); |
|
244 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
246 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); |
|
245 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
247 | SIGNAL dsui : dsu_in_type; |
|
246 | SIGNAL dsui : dsu_in_type; | |
248 | SIGNAL dsuo : dsu_out_type; |
|
247 | SIGNAL dsuo : dsu_out_type; | |
249 | ----------------------------------------------------------------------------- |
|
248 | ----------------------------------------------------------------------------- | |
250 |
|
249 | |||
251 |
|
250 | |||
252 | BEGIN |
|
251 | BEGIN | |
253 |
|
252 | |||
254 |
|
253 | |||
255 | ---------------------------------------------------------------------- |
|
254 | ---------------------------------------------------------------------- | |
256 | --- Reset and Clock generation ------------------------------------- |
|
255 | --- Reset and Clock generation ------------------------------------- | |
257 | ---------------------------------------------------------------------- |
|
256 | ---------------------------------------------------------------------- | |
258 |
|
257 | |||
259 | cgi.pllctrl <= "00"; |
|
258 | cgi.pllctrl <= "00"; | |
260 | cgi.pllrst <= rstraw; |
|
259 | cgi.pllrst <= rstraw; | |
261 |
|
260 | |||
262 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); |
|
261 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); | |
263 |
|
262 | |||
264 | clkgen0 : clkgen -- clock generator |
|
263 | clkgen0 : clkgen -- clock generator | |
265 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
264 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
266 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) |
|
265 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) | |
267 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); |
|
266 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
268 |
|
267 | |||
269 | ---------------------------------------------------------------------- |
|
268 | ---------------------------------------------------------------------- | |
270 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
269 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
271 | ---------------------------------------------------------------------- |
|
270 | ---------------------------------------------------------------------- | |
272 |
|
271 | |||
273 | l3 : IF CFG_LEON3 = 1 GENERATE |
|
272 | l3 : IF CFG_LEON3 = 1 GENERATE | |
274 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
273 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
275 | u0 : leon3s -- LEON3 processor |
|
274 | u0 : leon3s -- LEON3 processor | |
276 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
|
275 | GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, | |
277 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
|
276 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, | |
278 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
|
277 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, | |
279 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
|
278 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, | |
280 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
|
279 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, | |
281 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
|
280 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) | |
282 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
|
281 | PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, | |
283 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
|
282 | irqi(i), irqo(i), dbgi(i), dbgo(i)); | |
284 | END GENERATE; |
|
283 | END GENERATE; | |
285 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
|
284 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
286 |
|
285 | |||
287 | dsugen : IF CFG_DSU = 1 GENERATE |
|
286 | dsugen : IF CFG_DSU = 1 GENERATE | |
288 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
287 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
289 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
288 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
290 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
289 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
291 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
290 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
292 | dsui.enable <= '1'; |
|
291 | dsui.enable <= '1'; | |
293 | dsui.break <= '0'; |
|
292 | dsui.break <= '0'; | |
294 | END GENERATE; |
|
293 | END GENERATE; | |
295 | END GENERATE; |
|
294 | END GENERATE; | |
296 |
|
295 | |||
297 | nodsu : IF CFG_DSU = 0 GENERATE |
|
296 | nodsu : IF CFG_DSU = 0 GENERATE | |
298 | ahbso(2) <= ahbs_none; |
|
297 | ahbso(2) <= ahbs_none; | |
299 | dsuo.tstop <= '0'; |
|
298 | dsuo.tstop <= '0'; | |
300 | dsuo.active <= '0'; |
|
299 | dsuo.active <= '0'; | |
301 | END GENERATE; |
|
300 | END GENERATE; | |
302 |
|
301 | |||
303 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
|
302 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
304 | irqctrl0 : irqmp -- interrupt controller |
|
303 | irqctrl0 : irqmp -- interrupt controller | |
305 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
304 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
306 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
305 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
307 | END GENERATE; |
|
306 | END GENERATE; | |
308 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
|
307 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
309 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
308 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
310 | irqi(i).irl <= "0000"; |
|
309 | irqi(i).irl <= "0000"; | |
311 | END GENERATE; |
|
310 | END GENERATE; | |
312 | apbo(2) <= apb_none; |
|
311 | apbo(2) <= apb_none; | |
313 | END GENERATE; |
|
312 | END GENERATE; | |
314 |
|
313 | |||
315 | ---------------------------------------------------------------------- |
|
314 | ---------------------------------------------------------------------- | |
316 | --- Memory controllers --------------------------------------------- |
|
315 | --- Memory controllers --------------------------------------------- | |
317 | ---------------------------------------------------------------------- |
|
316 | ---------------------------------------------------------------------- | |
318 | ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE |
|
317 | ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE | |
319 | memctrlr : mctrl GENERIC MAP ( |
|
318 | memctrlr : mctrl GENERIC MAP ( | |
320 | hindex => 0, |
|
319 | hindex => 0, | |
321 | pindex => 0, |
|
320 | pindex => 0, | |
322 | paddr => 0, |
|
321 | paddr => 0, | |
323 | srbanks => 1 |
|
322 | srbanks => 1 | |
324 | ) |
|
323 | ) | |
325 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
324 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
326 | memi.bexcn <= '1'; |
|
325 | memi.bexcn <= '1'; | |
327 | memi.brdyn <= '1'; |
|
326 | memi.brdyn <= '1'; | |
328 |
|
327 | |||
329 | nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0)); |
|
328 | nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0)); | |
330 | nSRAM_OE_s <= memo.ramoen(0); |
|
329 | nSRAM_OE_s <= memo.ramoen(0); | |
331 | END GENERATE; |
|
330 | END GENERATE; | |
332 |
|
331 | |||
333 | IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE |
|
332 | IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE | |
334 | memctrlr : srctrle_0ws |
|
333 | memctrlr : srctrle_0ws | |
335 | GENERIC MAP( |
|
334 | GENERIC MAP( | |
336 | hindex => 0, |
|
335 | hindex => 0, | |
337 | pindex => 0, |
|
336 | pindex => 0, | |
338 | paddr => 0, |
|
337 | paddr => 0, | |
339 | srbanks => 2, |
|
338 | srbanks => 2, | |
340 | banksz => 8, --512k * 32 |
|
339 | banksz => 8, --512k * 32 | |
341 | rmw => 1, |
|
340 | rmw => 1, | |
342 | --Aeroflex memory generics: |
|
341 | --Aeroflex memory generics: | |
343 | mprog => 1, -- program memory by default values after reset |
|
342 | mprog => 1, -- program memory by default values after reset | |
344 | mpsrate => 12, -- default scrub rate period |
|
343 | mpsrate => 12, -- default scrub rate period | |
345 | mpb2s => 4, -- default busy to scrub delay |
|
344 | mpb2s => 4, -- default busy to scrub delay | |
346 | mpapb => 1, -- instantiate apb register |
|
345 | mpapb => 1, -- instantiate apb register | |
347 | mchipcnt => 2, |
|
346 | mchipcnt => 2, | |
348 | mpenall => 1 -- when 0 program only E1 chip, else program all dies |
|
347 | mpenall => 1 -- when 0 program only E1 chip, else program all dies | |
349 | ) |
|
348 | ) | |
350 | PORT MAP ( |
|
349 | PORT MAP ( | |
351 | rst => rstn, |
|
350 | rst => rstn, | |
352 | clk => clkm, |
|
351 | clk => clkm, | |
353 | ahbsi => ahbsi, |
|
352 | ahbsi => ahbsi, | |
354 | ahbso => ahbso(0), |
|
353 | ahbso => ahbso(0), | |
355 | apbi => apbi, |
|
354 | apbi => apbi, | |
356 | apbo => apbo(0), |
|
355 | apbo => apbo(0), | |
357 | sri => memi, |
|
356 | sri => memi, | |
358 | sro => memo, |
|
357 | sro => memo, | |
359 | --Aeroflex memory signals: |
|
358 | --Aeroflex memory signals: | |
360 | ucerr => open, -- uncorrectable error signal |
|
359 | ucerr => open, -- uncorrectable error signal | |
361 | mbe => mbe, -- enable memory programming |
|
360 | mbe => mbe, -- enable memory programming | |
362 | mbe_drive => mbe_drive -- drive the MBE memory signal |
|
361 | mbe_drive => mbe_drive -- drive the MBE memory signal | |
363 | ); |
|
362 | ); | |
364 |
|
363 | |||
365 | memi.brdyn <= nSRAM_READY; |
|
364 | memi.brdyn <= nSRAM_READY; | |
366 |
|
365 | |||
367 | mbe_pad : iopad |
|
366 | mbe_pad : iopad | |
368 | GENERIC MAP(tech => padtech) |
|
367 | GENERIC MAP(tech => padtech) | |
369 | PORT MAP(pad => SRAM_MBE, |
|
368 | PORT MAP(pad => SRAM_MBE, | |
370 | i => mbe, |
|
369 | i => mbe, | |
371 | en => mbe_drive, |
|
370 | en => mbe_drive, | |
372 | o => memi.bexcn ); |
|
371 | o => memi.bexcn ); | |
373 |
|
372 | |||
374 | nSRAM_CE_s <= (memo.ramsn(1 downto 0)); |
|
373 | nSRAM_CE_s <= (memo.ramsn(1 downto 0)); | |
375 | nSRAM_OE_s <= memo.oen; |
|
374 | nSRAM_OE_s <= memo.oen; | |
376 |
|
375 | |||
377 | END GENERATE; |
|
376 | END GENERATE; | |
378 |
|
377 | |||
379 |
|
378 | |||
380 | memi.writen <= '1'; |
|
379 | memi.writen <= '1'; | |
381 | memi.wrn <= "1111"; |
|
380 | memi.wrn <= "1111"; | |
382 | memi.bwidth <= "10"; |
|
381 | memi.bwidth <= "10"; | |
383 |
|
382 | |||
384 | bdr : FOR i IN 0 TO 3 GENERATE |
|
383 | bdr : FOR i IN 0 TO 3 GENERATE | |
385 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR) |
|
384 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR) | |
386 | PORT MAP ( |
|
385 | PORT MAP ( | |
387 | data(31-i*8 DOWNTO 24-i*8), |
|
386 | data(31-i*8 DOWNTO 24-i*8), | |
388 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
387 | memo.data(31-i*8 DOWNTO 24-i*8), | |
389 | memo.bdrive(i), |
|
388 | memo.bdrive(i), | |
390 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
389 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
391 | END GENERATE; |
|
390 | END GENERATE; | |
392 |
|
391 | |||
393 | addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech) |
|
392 | addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech) | |
394 | PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); |
|
393 | PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); | |
395 | rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s); |
|
394 | rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
396 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s); |
|
395 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s); | |
397 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
396 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
398 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
397 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
399 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
398 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
400 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
399 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
401 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
400 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
402 |
|
401 | |||
403 |
|
402 | |||
404 |
|
403 | |||
405 | ---------------------------------------------------------------------- |
|
404 | ---------------------------------------------------------------------- | |
406 | --- AHB CONTROLLER ------------------------------------------------- |
|
405 | --- AHB CONTROLLER ------------------------------------------------- | |
407 | ---------------------------------------------------------------------- |
|
406 | ---------------------------------------------------------------------- | |
408 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
407 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
409 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
408 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
410 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
409 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
411 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) |
|
410 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) | |
412 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
411 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
413 |
|
412 | |||
414 | ---------------------------------------------------------------------- |
|
413 | ---------------------------------------------------------------------- | |
415 | --- AHB UART ------------------------------------------------------- |
|
414 | --- AHB UART ------------------------------------------------------- | |
416 | ---------------------------------------------------------------------- |
|
415 | ---------------------------------------------------------------------- | |
417 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
|
416 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
418 | dcom0 : ahbuart |
|
417 | dcom0 : ahbuart | |
419 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) |
|
418 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) | |
420 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); |
|
419 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); | |
421 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); |
|
420 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
422 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); |
|
421 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
423 | END GENERATE; |
|
422 | END GENERATE; | |
424 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
423 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
425 |
|
424 | |||
426 | ---------------------------------------------------------------------- |
|
425 | ---------------------------------------------------------------------- | |
427 | --- APB Bridge ----------------------------------------------------- |
|
426 | --- APB Bridge ----------------------------------------------------- | |
428 | ---------------------------------------------------------------------- |
|
427 | ---------------------------------------------------------------------- | |
429 | apb0 : apbctrl -- AHB/APB bridge |
|
428 | apb0 : apbctrl -- AHB/APB bridge | |
430 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
|
429 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
431 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
|
430 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
432 |
|
431 | |||
433 | ---------------------------------------------------------------------- |
|
432 | ---------------------------------------------------------------------- | |
434 | --- GPT Timer ------------------------------------------------------ |
|
433 | --- GPT Timer ------------------------------------------------------ | |
435 | ---------------------------------------------------------------------- |
|
434 | ---------------------------------------------------------------------- | |
436 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
|
435 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
437 | timer0 : gptimer -- timer unit |
|
436 | timer0 : gptimer -- timer unit | |
438 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
437 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
439 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
438 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
440 | nbits => CFG_GPT_TW) |
|
439 | nbits => CFG_GPT_TW) | |
441 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
440 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
442 | gpti.dhalt <= dsuo.tstop; |
|
441 | gpti.dhalt <= dsuo.tstop; | |
443 | gpti.extclk <= '0'; |
|
442 | gpti.extclk <= '0'; | |
444 | END GENERATE; |
|
443 | END GENERATE; | |
445 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
444 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
446 |
|
445 | |||
447 |
|
446 | |||
448 | ---------------------------------------------------------------------- |
|
447 | ---------------------------------------------------------------------- | |
449 | --- APB UART ------------------------------------------------------- |
|
448 | --- APB UART ------------------------------------------------------- | |
450 | ---------------------------------------------------------------------- |
|
449 | ---------------------------------------------------------------------- | |
451 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
450 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
452 | uart1 : apbuart -- UART 1 |
|
451 | uart1 : apbuart -- UART 1 | |
453 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
452 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
454 | fifosize => CFG_UART1_FIFO) |
|
453 | fifosize => CFG_UART1_FIFO) | |
455 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
|
454 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
456 | apbuarti.rxd <= urxd1; |
|
455 | apbuarti.rxd <= urxd1; | |
457 | apbuarti.extclk <= '0'; |
|
456 | apbuarti.extclk <= '0'; | |
458 | utxd1 <= apbuarto.txd; |
|
457 | utxd1 <= apbuarto.txd; | |
459 | apbuarti.ctsn <= '0'; |
|
458 | apbuarti.ctsn <= '0'; | |
460 | END GENERATE; |
|
459 | END GENERATE; | |
461 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
|
460 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
462 |
|
461 | |||
463 | ------------------------------------------------------------------------------- |
|
462 | ------------------------------------------------------------------------------- | |
464 | -- AMBA BUS ------------------------------------------------------------------- |
|
463 | -- AMBA BUS ------------------------------------------------------------------- | |
465 | ------------------------------------------------------------------------------- |
|
464 | ------------------------------------------------------------------------------- | |
466 |
|
465 | |||
467 | -- APB -------------------------------------------------------------------- |
|
466 | -- APB -------------------------------------------------------------------- | |
468 | apbi_ext <= apbi; |
|
467 | apbi_ext <= apbi; | |
469 | all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE |
|
468 | all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE | |
470 | max_16_apb: IF I + 5 < 16 GENERATE |
|
469 | max_16_apb: IF I + 5 < 16 GENERATE | |
471 | apbo(I+5)<= apbo_ext(I+5); |
|
470 | apbo(I+5)<= apbo_ext(I+5); | |
472 | END GENERATE max_16_apb; |
|
471 | END GENERATE max_16_apb; | |
473 | END GENERATE all_apb; |
|
472 | END GENERATE all_apb; | |
474 | -- AHB_Slave -------------------------------------------------------------- |
|
473 | -- AHB_Slave -------------------------------------------------------------- | |
475 | ahbi_s_ext <= ahbsi; |
|
474 | ahbi_s_ext <= ahbsi; | |
476 | all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE |
|
475 | all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE | |
477 | max_16_ahbs: IF I + 3 < 16 GENERATE |
|
476 | max_16_ahbs: IF I + 3 < 16 GENERATE | |
478 | ahbso(I+3) <= ahbo_s_ext(I+3); |
|
477 | ahbso(I+3) <= ahbo_s_ext(I+3); | |
479 | END GENERATE max_16_ahbs; |
|
478 | END GENERATE max_16_ahbs; | |
480 | END GENERATE all_ahbs; |
|
479 | END GENERATE all_ahbs; | |
481 | -- AHB_Master ------------------------------------------------------------- |
|
480 | -- AHB_Master ------------------------------------------------------------- | |
482 | ahbi_m_ext <= ahbmi; |
|
481 | ahbi_m_ext <= ahbmi; | |
483 | all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE |
|
482 | all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE | |
484 | max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE |
|
483 | max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE | |
485 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); |
|
484 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); | |
486 | END GENERATE max_16_ahbm; |
|
485 | END GENERATE max_16_ahbm; | |
487 | END GENERATE all_ahbm; |
|
486 | END GENERATE all_ahbm; | |
488 |
|
487 | |||
489 |
|
488 | |||
490 |
|
489 | |||
491 | END Behavioral; No newline at end of file |
|
490 | END Behavioral; |
@@ -1,488 +1,487 | |||||
1 | ----------------------------------------------------------------------------- |
|
1 | ----------------------------------------------------------------------------- | |
2 | -- LEON3 Demonstration design |
|
2 | -- LEON3 Demonstration design | |
3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 2 of the License, or |
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7 | -- the Free Software Foundation; either version 2 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
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18 | ------------------------------------------------------------------------------ | |
19 |
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19 | |||
20 |
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20 | |||
21 | LIBRARY ieee; |
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21 | LIBRARY ieee; | |
22 | USE ieee.std_logic_1164.ALL; |
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22 | USE ieee.std_logic_1164.ALL; | |
23 | LIBRARY grlib; |
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23 | LIBRARY grlib; | |
24 | USE grlib.amba.ALL; |
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24 | USE grlib.amba.ALL; | |
25 | USE grlib.stdlib.ALL; |
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25 | USE grlib.stdlib.ALL; | |
26 | LIBRARY techmap; |
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26 | LIBRARY techmap; | |
27 | USE techmap.gencomp.ALL; |
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27 | USE techmap.gencomp.ALL; | |
28 | LIBRARY gaisler; |
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28 | LIBRARY gaisler; | |
29 | USE gaisler.memctrl.ALL; |
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29 | USE gaisler.memctrl.ALL; | |
30 | USE gaisler.leon3.ALL; |
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30 | USE gaisler.leon3.ALL; | |
31 | USE gaisler.uart.ALL; |
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31 | USE gaisler.uart.ALL; | |
32 | USE gaisler.misc.ALL; |
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32 | USE gaisler.misc.ALL; | |
33 | USE gaisler.spacewire.ALL; -- PLE |
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33 | USE gaisler.spacewire.ALL; -- PLE | |
34 | LIBRARY esa; |
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34 | LIBRARY esa; | |
35 | USE esa.memoryctrl.ALL; |
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35 | USE esa.memoryctrl.ALL; | |
36 | LIBRARY lpp; |
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36 | LIBRARY lpp; | |
37 | USE lpp.lpp_memory.ALL; |
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37 | USE lpp.lpp_memory.ALL; | |
38 | USE lpp.lpp_ad_conv.ALL; |
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38 | USE lpp.lpp_ad_conv.ALL; | |
39 | USE lpp.lpp_lfr_pkg.ALL; |
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39 | USE lpp.lpp_lfr_pkg.ALL; | |
40 | USE lpp.iir_filter.ALL; |
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40 | USE lpp.iir_filter.ALL; | |
41 | USE lpp.general_purpose.ALL; |
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41 | USE lpp.general_purpose.ALL; | |
42 | USE lpp.lpp_lfr_time_management.ALL; |
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43 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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42 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
44 |
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43 | |||
45 | ENTITY leon3ft_soc IS |
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44 | ENTITY leon3ft_soc IS | |
46 | GENERIC ( |
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45 | GENERIC ( | |
47 | fabtech : INTEGER := apa3e; |
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46 | fabtech : INTEGER := apa3e; | |
48 | memtech : INTEGER := apa3e; |
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47 | memtech : INTEGER := apa3e; | |
49 | padtech : INTEGER := inferred; |
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48 | padtech : INTEGER := inferred; | |
50 | clktech : INTEGER := inferred; |
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49 | clktech : INTEGER := inferred; | |
51 | disas : INTEGER := 0; -- Enable disassembly to console |
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50 | disas : INTEGER := 0; -- Enable disassembly to console | |
52 | dbguart : INTEGER := 0; -- Print UART on console |
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51 | dbguart : INTEGER := 0; -- Print UART on console | |
53 | pclow : INTEGER := 2; |
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52 | pclow : INTEGER := 2; | |
54 | -- |
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53 | -- | |
55 | clk_freq : INTEGER := 25000; --kHz |
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54 | clk_freq : INTEGER := 25000; --kHz | |
56 | -- |
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55 | -- | |
57 | NB_CPU : INTEGER := 1; |
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56 | NB_CPU : INTEGER := 1; | |
58 | ENABLE_FPU : INTEGER := 1; |
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57 | ENABLE_FPU : INTEGER := 1; | |
59 | FPU_NETLIST : INTEGER := 1; |
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58 | FPU_NETLIST : INTEGER := 1; | |
60 | ENABLE_DSU : INTEGER := 1; |
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59 | ENABLE_DSU : INTEGER := 1; | |
61 | ENABLE_AHB_UART : INTEGER := 1; |
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60 | ENABLE_AHB_UART : INTEGER := 1; | |
62 | ENABLE_APB_UART : INTEGER := 1; |
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61 | ENABLE_APB_UART : INTEGER := 1; | |
63 | ENABLE_IRQMP : INTEGER := 1; |
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62 | ENABLE_IRQMP : INTEGER := 1; | |
64 | ENABLE_GPT : INTEGER := 1; |
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63 | ENABLE_GPT : INTEGER := 1; | |
65 | -- |
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64 | -- | |
66 | NB_AHB_MASTER : INTEGER := 11; |
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65 | NB_AHB_MASTER : INTEGER := 11; | |
67 | NB_AHB_SLAVE : INTEGER := 1; |
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66 | NB_AHB_SLAVE : INTEGER := 1; | |
68 | NB_APB_SLAVE : INTEGER := 2 |
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67 | NB_APB_SLAVE : INTEGER := 2 | |
69 | ); |
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68 | ); | |
70 | PORT ( |
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69 | PORT ( | |
71 | clk : IN STD_ULOGIC; |
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70 | clk : IN STD_ULOGIC; | |
72 | reset : IN STD_ULOGIC; |
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71 | reset : IN STD_ULOGIC; | |
73 |
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72 | |||
74 | errorn : OUT STD_ULOGIC; |
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73 | errorn : OUT STD_ULOGIC; | |
75 |
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74 | |||
76 | -- UART AHB --------------------------------------------------------------- |
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75 | -- UART AHB --------------------------------------------------------------- | |
77 | ahbrxd : IN STD_ULOGIC; -- DSU rx data |
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76 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
78 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data |
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77 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
79 |
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78 | |||
80 | -- UART APB --------------------------------------------------------------- |
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79 | -- UART APB --------------------------------------------------------------- | |
81 | urxd1 : IN STD_ULOGIC; -- UART1 rx data |
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80 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
82 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data |
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81 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
83 |
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82 | |||
84 | -- RAM -------------------------------------------------------------------- |
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83 | -- RAM -------------------------------------------------------------------- | |
85 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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84 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
86 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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85 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
87 | nSRAM_BE0 : OUT STD_LOGIC; |
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86 | nSRAM_BE0 : OUT STD_LOGIC; | |
88 | nSRAM_BE1 : OUT STD_LOGIC; |
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87 | nSRAM_BE1 : OUT STD_LOGIC; | |
89 | nSRAM_BE2 : OUT STD_LOGIC; |
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88 | nSRAM_BE2 : OUT STD_LOGIC; | |
90 | nSRAM_BE3 : OUT STD_LOGIC; |
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89 | nSRAM_BE3 : OUT STD_LOGIC; | |
91 | nSRAM_WE : OUT STD_LOGIC; |
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90 | nSRAM_WE : OUT STD_LOGIC; | |
92 | nSRAM_CE : OUT STD_LOGIC; |
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91 | nSRAM_CE : OUT STD_LOGIC; | |
93 | nSRAM_OE : OUT STD_LOGIC; |
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92 | nSRAM_OE : OUT STD_LOGIC; | |
94 |
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93 | |||
95 | -- APB -------------------------------------------------------------------- |
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94 | -- APB -------------------------------------------------------------------- | |
96 | apbi_ext : OUT apb_slv_in_type; |
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95 | apbi_ext : OUT apb_slv_in_type; | |
97 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); |
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96 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); | |
98 | -- AHB_Slave -------------------------------------------------------------- |
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97 | -- AHB_Slave -------------------------------------------------------------- | |
99 | ahbi_s_ext : OUT ahb_slv_in_type; |
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98 | ahbi_s_ext : OUT ahb_slv_in_type; | |
100 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); |
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99 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); | |
101 | -- AHB_Master ------------------------------------------------------------- |
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100 | -- AHB_Master ------------------------------------------------------------- | |
102 | ahbi_m_ext : OUT AHB_Mst_In_Type; |
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101 | ahbi_m_ext : OUT AHB_Mst_In_Type; | |
103 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) |
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102 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) | |
104 |
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103 | |||
105 | ); |
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104 | ); | |
106 | END; |
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105 | END; | |
107 |
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106 | |||
108 | ARCHITECTURE Behavioral OF leon3ft_soc IS |
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107 | ARCHITECTURE Behavioral OF leon3ft_soc IS | |
109 |
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108 | |||
110 | ----------------------------------------------------------------------------- |
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109 | ----------------------------------------------------------------------------- | |
111 | -- CONFIG ------------------------------------------------------------------- |
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110 | -- CONFIG ------------------------------------------------------------------- | |
112 | ----------------------------------------------------------------------------- |
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111 | ----------------------------------------------------------------------------- | |
113 |
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112 | |||
114 | -- Clock generator |
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113 | -- Clock generator | |
115 | CONSTANT CFG_CLKMUL : INTEGER := (1); |
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114 | CONSTANT CFG_CLKMUL : INTEGER := (1); | |
116 | CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz |
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115 | CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz | |
117 | CONSTANT CFG_OCLKDIV : INTEGER := (1); |
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116 | CONSTANT CFG_OCLKDIV : INTEGER := (1); | |
118 | CONSTANT CFG_CLK_NOFB : INTEGER := 0; |
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117 | CONSTANT CFG_CLK_NOFB : INTEGER := 0; | |
119 | -- LEON3 processor core |
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118 | -- LEON3 processor core | |
120 | CONSTANT CFG_LEON3 : INTEGER := 1; |
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119 | CONSTANT CFG_LEON3 : INTEGER := 1; | |
121 | CONSTANT CFG_NCPU : INTEGER := NB_CPU; |
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120 | CONSTANT CFG_NCPU : INTEGER := NB_CPU; | |
122 | CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC |
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121 | CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC | |
123 | CONSTANT CFG_V8 : INTEGER := 0; |
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122 | CONSTANT CFG_V8 : INTEGER := 0; | |
124 | CONSTANT CFG_MAC : INTEGER := 0; |
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123 | CONSTANT CFG_MAC : INTEGER := 0; | |
125 | CONSTANT CFG_SVT : INTEGER := 0; |
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124 | CONSTANT CFG_SVT : INTEGER := 0; | |
126 | CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; |
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125 | CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; | |
127 | CONSTANT CFG_LDDEL : INTEGER := (1); |
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126 | CONSTANT CFG_LDDEL : INTEGER := (1); | |
128 | CONSTANT CFG_NWP : INTEGER := (0); |
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127 | CONSTANT CFG_NWP : INTEGER := (0); | |
129 | CONSTANT CFG_PWD : INTEGER := 1*2; |
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128 | CONSTANT CFG_PWD : INTEGER := 1*2; | |
130 | CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST); |
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129 | CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST); | |
131 | -- 1*(8 + 16 * 0) => grfpu-light |
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130 | -- 1*(8 + 16 * 0) => grfpu-light | |
132 | -- 1*(8 + 16 * 1) => netlist |
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131 | -- 1*(8 + 16 * 1) => netlist | |
133 | -- 0*(8 + 16 * 0) => No FPU |
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132 | -- 0*(8 + 16 * 0) => No FPU | |
134 | -- 0*(8 + 16 * 1) => No FPU; |
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133 | -- 0*(8 + 16 * 1) => No FPU; | |
135 | CONSTANT CFG_ICEN : INTEGER := 1; |
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134 | CONSTANT CFG_ICEN : INTEGER := 1; | |
136 | CONSTANT CFG_ISETS : INTEGER := 1; |
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135 | CONSTANT CFG_ISETS : INTEGER := 1; | |
137 | CONSTANT CFG_ISETSZ : INTEGER := 4; |
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136 | CONSTANT CFG_ISETSZ : INTEGER := 4; | |
138 | CONSTANT CFG_ILINE : INTEGER := 4; |
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137 | CONSTANT CFG_ILINE : INTEGER := 4; | |
139 | CONSTANT CFG_IREPL : INTEGER := 0; |
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138 | CONSTANT CFG_IREPL : INTEGER := 0; | |
140 | CONSTANT CFG_ILOCK : INTEGER := 0; |
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139 | CONSTANT CFG_ILOCK : INTEGER := 0; | |
141 | CONSTANT CFG_ILRAMEN : INTEGER := 0; |
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140 | CONSTANT CFG_ILRAMEN : INTEGER := 0; | |
142 | CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; |
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141 | CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; | |
143 | CONSTANT CFG_ILRAMSZ : INTEGER := 1; |
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142 | CONSTANT CFG_ILRAMSZ : INTEGER := 1; | |
144 | CONSTANT CFG_DCEN : INTEGER := 1; |
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143 | CONSTANT CFG_DCEN : INTEGER := 1; | |
145 | CONSTANT CFG_DSETS : INTEGER := 1; |
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144 | CONSTANT CFG_DSETS : INTEGER := 1; | |
146 | CONSTANT CFG_DSETSZ : INTEGER := 4; |
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145 | CONSTANT CFG_DSETSZ : INTEGER := 4; | |
147 | CONSTANT CFG_DLINE : INTEGER := 4; |
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146 | CONSTANT CFG_DLINE : INTEGER := 4; | |
148 | CONSTANT CFG_DREPL : INTEGER := 0; |
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147 | CONSTANT CFG_DREPL : INTEGER := 0; | |
149 | CONSTANT CFG_DLOCK : INTEGER := 0; |
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148 | CONSTANT CFG_DLOCK : INTEGER := 0; | |
150 | CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; |
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149 | CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; | |
151 | CONSTANT CFG_DLRAMEN : INTEGER := 0; |
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150 | CONSTANT CFG_DLRAMEN : INTEGER := 0; | |
152 | CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; |
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151 | CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; | |
153 | CONSTANT CFG_DLRAMSZ : INTEGER := 1; |
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152 | CONSTANT CFG_DLRAMSZ : INTEGER := 1; | |
154 | CONSTANT CFG_MMUEN : INTEGER := 0; |
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153 | CONSTANT CFG_MMUEN : INTEGER := 0; | |
155 | CONSTANT CFG_ITLBNUM : INTEGER := 2; |
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154 | CONSTANT CFG_ITLBNUM : INTEGER := 2; | |
156 | CONSTANT CFG_DTLBNUM : INTEGER := 2; |
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155 | CONSTANT CFG_DTLBNUM : INTEGER := 2; | |
157 | CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2; |
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156 | CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2; | |
158 | CONSTANT CFG_TLB_REP : INTEGER := 1; |
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157 | CONSTANT CFG_TLB_REP : INTEGER := 1; | |
159 |
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158 | |||
160 | CONSTANT CFG_DSU : INTEGER := ENABLE_DSU; |
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159 | CONSTANT CFG_DSU : INTEGER := ENABLE_DSU; | |
161 | CONSTANT CFG_ITBSZ : INTEGER := 0; |
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160 | CONSTANT CFG_ITBSZ : INTEGER := 0; | |
162 | CONSTANT CFG_ATBSZ : INTEGER := 0; |
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161 | CONSTANT CFG_ATBSZ : INTEGER := 0; | |
163 |
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162 | |||
164 | -- AMBA settings |
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163 | -- AMBA settings | |
165 | CONSTANT CFG_DEFMST : INTEGER := (0); |
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164 | CONSTANT CFG_DEFMST : INTEGER := (0); | |
166 | CONSTANT CFG_RROBIN : INTEGER := 1; |
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165 | CONSTANT CFG_RROBIN : INTEGER := 1; | |
167 | CONSTANT CFG_SPLIT : INTEGER := 0; |
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166 | CONSTANT CFG_SPLIT : INTEGER := 0; | |
168 | CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; |
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167 | CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; | |
169 | CONSTANT CFG_APBADDR : INTEGER := 16#800#; |
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168 | CONSTANT CFG_APBADDR : INTEGER := 16#800#; | |
170 |
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169 | |||
171 | -- DSU UART |
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170 | -- DSU UART | |
172 | CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART; |
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171 | CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART; | |
173 |
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172 | |||
174 | -- LEON2 memory controller |
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173 | -- LEON2 memory controller | |
175 | CONSTANT CFG_MCTRL_SDEN : INTEGER := 0; |
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174 | CONSTANT CFG_MCTRL_SDEN : INTEGER := 0; | |
176 |
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175 | |||
177 | -- UART 1 |
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176 | -- UART 1 | |
178 | CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART; |
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177 | CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART; | |
179 | CONSTANT CFG_UART1_FIFO : INTEGER := 1; |
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178 | CONSTANT CFG_UART1_FIFO : INTEGER := 1; | |
180 |
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179 | |||
181 | -- LEON3 interrupt controller |
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180 | -- LEON3 interrupt controller | |
182 | CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP; |
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181 | CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP; | |
183 |
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182 | |||
184 | -- Modular timer |
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183 | -- Modular timer | |
185 | CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT; |
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184 | CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT; | |
186 | CONSTANT CFG_GPT_NTIM : INTEGER := (2); |
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185 | CONSTANT CFG_GPT_NTIM : INTEGER := (2); | |
187 | CONSTANT CFG_GPT_SW : INTEGER := (8); |
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186 | CONSTANT CFG_GPT_SW : INTEGER := (8); | |
188 | CONSTANT CFG_GPT_TW : INTEGER := (32); |
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187 | CONSTANT CFG_GPT_TW : INTEGER := (32); | |
189 | CONSTANT CFG_GPT_IRQ : INTEGER := (8); |
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188 | CONSTANT CFG_GPT_IRQ : INTEGER := (8); | |
190 | CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; |
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189 | CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; | |
191 | CONSTANT CFG_GPT_WDOGEN : INTEGER := 0; |
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190 | CONSTANT CFG_GPT_WDOGEN : INTEGER := 0; | |
192 | CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#; |
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191 | CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#; | |
193 | ----------------------------------------------------------------------------- |
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192 | ----------------------------------------------------------------------------- | |
194 |
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193 | |||
195 | ----------------------------------------------------------------------------- |
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194 | ----------------------------------------------------------------------------- | |
196 | -- SIGNALs |
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195 | -- SIGNALs | |
197 | ----------------------------------------------------------------------------- |
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196 | ----------------------------------------------------------------------------- | |
198 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; |
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197 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; | |
199 | -- CLK & RST -- |
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198 | -- CLK & RST -- | |
200 | SIGNAL clk2x : STD_ULOGIC; |
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199 | SIGNAL clk2x : STD_ULOGIC; | |
201 | SIGNAL clkmn : STD_ULOGIC; |
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200 | SIGNAL clkmn : STD_ULOGIC; | |
202 | SIGNAL clkm : STD_ULOGIC; |
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201 | SIGNAL clkm : STD_ULOGIC; | |
203 | SIGNAL rstn : STD_ULOGIC; |
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202 | SIGNAL rstn : STD_ULOGIC; | |
204 | SIGNAL rstraw : STD_ULOGIC; |
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203 | SIGNAL rstraw : STD_ULOGIC; | |
205 | SIGNAL pciclk : STD_ULOGIC; |
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204 | SIGNAL pciclk : STD_ULOGIC; | |
206 | SIGNAL sdclkl : STD_ULOGIC; |
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205 | SIGNAL sdclkl : STD_ULOGIC; | |
207 | SIGNAL cgi : clkgen_in_type; |
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206 | SIGNAL cgi : clkgen_in_type; | |
208 | SIGNAL cgo : clkgen_out_type; |
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207 | SIGNAL cgo : clkgen_out_type; | |
209 | --- AHB / APB |
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208 | --- AHB / APB | |
210 | SIGNAL apbi : apb_slv_in_type; |
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209 | SIGNAL apbi : apb_slv_in_type; | |
211 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); |
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210 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
212 | SIGNAL ahbsi : ahb_slv_in_type; |
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211 | SIGNAL ahbsi : ahb_slv_in_type; | |
213 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); |
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212 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
214 | SIGNAL ahbmi : ahb_mst_in_type; |
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213 | SIGNAL ahbmi : ahb_mst_in_type; | |
215 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); |
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214 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
216 | --UART |
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215 | --UART | |
217 | SIGNAL ahbuarti : uart_in_type; |
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216 | SIGNAL ahbuarti : uart_in_type; | |
218 | SIGNAL ahbuarto : uart_out_type; |
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217 | SIGNAL ahbuarto : uart_out_type; | |
219 | SIGNAL apbuarti : uart_in_type; |
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218 | SIGNAL apbuarti : uart_in_type; | |
220 | SIGNAL apbuarto : uart_out_type; |
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219 | SIGNAL apbuarto : uart_out_type; | |
221 | --MEM CTRLR |
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220 | --MEM CTRLR | |
222 | SIGNAL memi : memory_in_type; |
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221 | SIGNAL memi : memory_in_type; | |
223 | SIGNAL memo : memory_out_type; |
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222 | SIGNAL memo : memory_out_type; | |
224 | SIGNAL wpo : wprot_out_type; |
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223 | SIGNAL wpo : wprot_out_type; | |
225 | SIGNAL sdo : sdram_out_type; |
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224 | SIGNAL sdo : sdram_out_type; | |
226 | --IRQ |
|
225 | --IRQ | |
227 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); |
|
226 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
228 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); |
|
227 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
229 | --Timer |
|
228 | --Timer | |
230 | SIGNAL gpti : gptimer_in_type; |
|
229 | SIGNAL gpti : gptimer_in_type; | |
231 | SIGNAL gpto : gptimer_out_type; |
|
230 | SIGNAL gpto : gptimer_out_type; | |
232 | --DSU |
|
231 | --DSU | |
233 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); |
|
232 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
234 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); |
|
233 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
235 | SIGNAL dsui : dsu_in_type; |
|
234 | SIGNAL dsui : dsu_in_type; | |
236 | SIGNAL dsuo : dsu_out_type; |
|
235 | SIGNAL dsuo : dsu_out_type; | |
237 | ----------------------------------------------------------------------------- |
|
236 | ----------------------------------------------------------------------------- | |
238 |
|
237 | |||
239 | SIGNAL nSRAM_CE_s : STD_LOGIC; |
|
238 | SIGNAL nSRAM_CE_s : STD_LOGIC; | |
240 | BEGIN |
|
239 | BEGIN | |
241 |
|
240 | |||
242 |
|
241 | |||
243 | ---------------------------------------------------------------------- |
|
242 | ---------------------------------------------------------------------- | |
244 | --- Reset and Clock generation ------------------------------------- |
|
243 | --- Reset and Clock generation ------------------------------------- | |
245 | ---------------------------------------------------------------------- |
|
244 | ---------------------------------------------------------------------- | |
246 |
|
245 | |||
247 | cgi.pllctrl <= "00"; |
|
246 | cgi.pllctrl <= "00"; | |
248 | cgi.pllrst <= rstraw; |
|
247 | cgi.pllrst <= rstraw; | |
249 |
|
248 | |||
250 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); |
|
249 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); | |
251 |
|
250 | |||
252 | clkgen0 : clkgen -- clock generator |
|
251 | clkgen0 : clkgen -- clock generator | |
253 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
|
252 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
254 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) |
|
253 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) | |
255 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); |
|
254 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
256 |
|
255 | |||
257 | ---------------------------------------------------------------------- |
|
256 | ---------------------------------------------------------------------- | |
258 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
|
257 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
259 | ---------------------------------------------------------------------- |
|
258 | ---------------------------------------------------------------------- | |
260 |
|
259 | |||
261 | l3 : IF CFG_LEON3 = 1 GENERATE |
|
260 | l3 : IF CFG_LEON3 = 1 GENERATE | |
262 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
261 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
263 | u0 : leon3ft |
|
262 | u0 : leon3ft | |
264 | GENERIC MAP ( |
|
263 | GENERIC MAP ( | |
265 | hindex => i, --: integer; |
|
264 | hindex => i, --: integer; | |
266 | fabtech => fabtech, |
|
265 | fabtech => fabtech, | |
267 | memtech => memtech, |
|
266 | memtech => memtech, | |
268 | nwindows => CFG_NWIN, |
|
267 | nwindows => CFG_NWIN, | |
269 | dsu => CFG_DSU, |
|
268 | dsu => CFG_DSU, | |
270 | fpu => CFG_FPU, |
|
269 | fpu => CFG_FPU, | |
271 | v8 => CFG_V8, |
|
270 | v8 => CFG_V8, | |
272 | cp => 0, |
|
271 | cp => 0, | |
273 | mac => CFG_MAC, |
|
272 | mac => CFG_MAC, | |
274 | pclow => pclow, |
|
273 | pclow => pclow, | |
275 | notag => 0, |
|
274 | notag => 0, | |
276 | nwp => CFG_NWP, |
|
275 | nwp => CFG_NWP, | |
277 | icen => CFG_ICEN, |
|
276 | icen => CFG_ICEN, | |
278 | irepl => CFG_IREPL, |
|
277 | irepl => CFG_IREPL, | |
279 | isets => CFG_ISETS, |
|
278 | isets => CFG_ISETS, | |
280 | ilinesize => CFG_ILINE, |
|
279 | ilinesize => CFG_ILINE, | |
281 | isetsize => CFG_ISETSZ, |
|
280 | isetsize => CFG_ISETSZ, | |
282 | isetlock => CFG_ILOCK, |
|
281 | isetlock => CFG_ILOCK, | |
283 | dcen => CFG_DCEN, |
|
282 | dcen => CFG_DCEN, | |
284 | drepl => CFG_DREPL, |
|
283 | drepl => CFG_DREPL, | |
285 | dsets => CFG_DSETS, |
|
284 | dsets => CFG_DSETS, | |
286 | dlinesize => CFG_DLINE, |
|
285 | dlinesize => CFG_DLINE, | |
287 | dsetsize => CFG_DSETSZ, |
|
286 | dsetsize => CFG_DSETSZ, | |
288 | dsetlock => CFG_DLOCK, |
|
287 | dsetlock => CFG_DLOCK, | |
289 | dsnoop => CFG_DSNOOP, |
|
288 | dsnoop => CFG_DSNOOP, | |
290 | ilram => CFG_ILRAMEN, |
|
289 | ilram => CFG_ILRAMEN, | |
291 | ilramsize => CFG_ILRAMSZ, |
|
290 | ilramsize => CFG_ILRAMSZ, | |
292 | ilramstart => CFG_ILRAMADDR, |
|
291 | ilramstart => CFG_ILRAMADDR, | |
293 | dlram => CFG_DLRAMEN, |
|
292 | dlram => CFG_DLRAMEN, | |
294 | dlramsize => CFG_DLRAMSZ, |
|
293 | dlramsize => CFG_DLRAMSZ, | |
295 | dlramstart => CFG_DLRAMADDR, |
|
294 | dlramstart => CFG_DLRAMADDR, | |
296 | mmuen => CFG_MMUEN, |
|
295 | mmuen => CFG_MMUEN, | |
297 | itlbnum => CFG_ITLBNUM, |
|
296 | itlbnum => CFG_ITLBNUM, | |
298 | dtlbnum => CFG_DTLBNUM, |
|
297 | dtlbnum => CFG_DTLBNUM, | |
299 | tlb_type => CFG_TLB_TYPE, |
|
298 | tlb_type => CFG_TLB_TYPE, | |
300 | tlb_rep => CFG_TLB_REP, |
|
299 | tlb_rep => CFG_TLB_REP, | |
301 | lddel => CFG_LDDEL, |
|
300 | lddel => CFG_LDDEL, | |
302 | disas => disas, |
|
301 | disas => disas, | |
303 | tbuf => CFG_ITBSZ, |
|
302 | tbuf => CFG_ITBSZ, | |
304 | pwd => CFG_PWD, |
|
303 | pwd => CFG_PWD, | |
305 | svt => CFG_SVT, |
|
304 | svt => CFG_SVT, | |
306 | rstaddr => CFG_RSTADDR, |
|
305 | rstaddr => CFG_RSTADDR, | |
307 | smp => CFG_NCPU-1, |
|
306 | smp => CFG_NCPU-1, | |
308 | iuft => 2, --: integer range 0 to 4; |
|
307 | iuft => 2, --: integer range 0 to 4; | |
309 | fpft => 1, --: integer range 0 to 4; |
|
308 | fpft => 1, --: integer range 0 to 4; | |
310 | cmft => 1, --: integer range 0 to 1; |
|
309 | cmft => 1, --: integer range 0 to 1; | |
311 | iuinj => 0, --: integer; |
|
310 | iuinj => 0, --: integer; | |
312 | ceinj => 0, --: integer range 0 to 3; |
|
311 | ceinj => 0, --: integer range 0 to 3; | |
313 | cached => 0, --: integer; |
|
312 | cached => 0, --: integer; | |
314 | netlist => 0, --: integer; |
|
313 | netlist => 0, --: integer; | |
315 | scantest => 0, --: integer; |
|
314 | scantest => 0, --: integer; | |
316 | mmupgsz => 0, --: integer range 0 to 5; |
|
315 | mmupgsz => 0, --: integer range 0 to 5; | |
317 | bp => 1) --: integer); |
|
316 | bp => 1) --: integer); | |
318 | PORT MAP ( |
|
317 | PORT MAP ( | |
319 | clk => clkm, |
|
318 | clk => clkm, | |
320 | rstn => rstn, |
|
319 | rstn => rstn, | |
321 | ahbi => ahbmi, |
|
320 | ahbi => ahbmi, | |
322 | ahbo => ahbmo(i), |
|
321 | ahbo => ahbmo(i), | |
323 | ahbsi => ahbsi, |
|
322 | ahbsi => ahbsi, | |
324 | ahbso => ahbso, |
|
323 | ahbso => ahbso, | |
325 | irqi => irqi(i), |
|
324 | irqi => irqi(i), | |
326 | irqo => irqo(i), |
|
325 | irqo => irqo(i), | |
327 | dbgi => dbgi(i), |
|
326 | dbgi => dbgi(i), | |
328 | dbgo => dbgo(i), |
|
327 | dbgo => dbgo(i), | |
329 | gclk => clkm |
|
328 | gclk => clkm | |
330 | ); |
|
329 | ); | |
331 |
|
330 | |||
332 | END GENERATE; |
|
331 | END GENERATE; | |
333 |
|
332 | |||
334 |
|
333 | |||
335 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); |
|
334 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
336 |
|
335 | |||
337 | dsugen : IF CFG_DSU = 1 GENERATE |
|
336 | dsugen : IF CFG_DSU = 1 GENERATE | |
338 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
|
337 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
339 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
|
338 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
340 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
|
339 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
341 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
|
340 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
342 | dsui.enable <= '1'; |
|
341 | dsui.enable <= '1'; | |
343 | dsui.break <= '0'; |
|
342 | dsui.break <= '0'; | |
344 | END GENERATE; |
|
343 | END GENERATE; | |
345 | END GENERATE; |
|
344 | END GENERATE; | |
346 |
|
345 | |||
347 | nodsu : IF CFG_DSU = 0 GENERATE |
|
346 | nodsu : IF CFG_DSU = 0 GENERATE | |
348 | ahbso(2) <= ahbs_none; |
|
347 | ahbso(2) <= ahbs_none; | |
349 | dsuo.tstop <= '0'; |
|
348 | dsuo.tstop <= '0'; | |
350 | dsuo.active <= '0'; |
|
349 | dsuo.active <= '0'; | |
351 | END GENERATE; |
|
350 | END GENERATE; | |
352 |
|
351 | |||
353 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE |
|
352 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
354 | irqctrl0 : irqmp -- interrupt controller |
|
353 | irqctrl0 : irqmp -- interrupt controller | |
355 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
|
354 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
356 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); |
|
355 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
357 | END GENERATE; |
|
356 | END GENERATE; | |
358 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE |
|
357 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
359 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE |
|
358 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
360 | irqi(i).irl <= "0000"; |
|
359 | irqi(i).irl <= "0000"; | |
361 | END GENERATE; |
|
360 | END GENERATE; | |
362 | apbo(2) <= apb_none; |
|
361 | apbo(2) <= apb_none; | |
363 | END GENERATE; |
|
362 | END GENERATE; | |
364 |
|
363 | |||
365 | ---------------------------------------------------------------------- |
|
364 | ---------------------------------------------------------------------- | |
366 | --- Memory controllers --------------------------------------------- |
|
365 | --- Memory controllers --------------------------------------------- | |
367 | ---------------------------------------------------------------------- |
|
366 | ---------------------------------------------------------------------- | |
368 | memctrlr : mctrl GENERIC MAP ( |
|
367 | memctrlr : mctrl GENERIC MAP ( | |
369 | hindex => 0, |
|
368 | hindex => 0, | |
370 | pindex => 0, |
|
369 | pindex => 0, | |
371 | paddr => 0, |
|
370 | paddr => 0, | |
372 | srbanks => 1 |
|
371 | srbanks => 1 | |
373 | ) |
|
372 | ) | |
374 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); |
|
373 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
375 |
|
374 | |||
376 | memi.brdyn <= '1'; |
|
375 | memi.brdyn <= '1'; | |
377 | memi.bexcn <= '1'; |
|
376 | memi.bexcn <= '1'; | |
378 | memi.writen <= '1'; |
|
377 | memi.writen <= '1'; | |
379 | memi.wrn <= "1111"; |
|
378 | memi.wrn <= "1111"; | |
380 | memi.bwidth <= "10"; |
|
379 | memi.bwidth <= "10"; | |
381 |
|
380 | |||
382 | bdr : FOR i IN 0 TO 3 GENERATE |
|
381 | bdr : FOR i IN 0 TO 3 GENERATE | |
383 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) |
|
382 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
384 | PORT MAP ( |
|
383 | PORT MAP ( | |
385 | data(31-i*8 DOWNTO 24-i*8), |
|
384 | data(31-i*8 DOWNTO 24-i*8), | |
386 | memo.data(31-i*8 DOWNTO 24-i*8), |
|
385 | memo.data(31-i*8 DOWNTO 24-i*8), | |
387 | memo.bdrive(i), |
|
386 | memo.bdrive(i), | |
388 | memi.data(31-i*8 DOWNTO 24-i*8)); |
|
387 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
389 | END GENERATE; |
|
388 | END GENERATE; | |
390 |
|
389 | |||
391 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) |
|
390 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
392 | PORT MAP (address, memo.address(21 DOWNTO 2)); |
|
391 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
393 | nSRAM_CE_s <= NOT(memo.ramsn(0)); |
|
392 | nSRAM_CE_s <= NOT(memo.ramsn(0)); | |
394 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); |
|
393 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
395 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); |
|
394 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
396 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); |
|
395 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
397 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); |
|
396 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
398 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); |
|
397 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
399 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
|
398 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
400 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
|
399 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
401 |
|
400 | |||
402 | ---------------------------------------------------------------------- |
|
401 | ---------------------------------------------------------------------- | |
403 | --- AHB CONTROLLER ------------------------------------------------- |
|
402 | --- AHB CONTROLLER ------------------------------------------------- | |
404 | ---------------------------------------------------------------------- |
|
403 | ---------------------------------------------------------------------- | |
405 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
|
404 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
406 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, |
|
405 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
407 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
|
406 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
408 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) |
|
407 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) | |
409 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
|
408 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
410 |
|
409 | |||
411 | ---------------------------------------------------------------------- |
|
410 | ---------------------------------------------------------------------- | |
412 | --- AHB UART ------------------------------------------------------- |
|
411 | --- AHB UART ------------------------------------------------------- | |
413 | ---------------------------------------------------------------------- |
|
412 | ---------------------------------------------------------------------- | |
414 | dcomgen : IF CFG_AHB_UART = 1 GENERATE |
|
413 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
415 | dcom0 : ahbuart |
|
414 | dcom0 : ahbuart | |
416 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) |
|
415 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) | |
417 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); |
|
416 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); | |
418 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); |
|
417 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
419 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); |
|
418 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
420 | END GENERATE; |
|
419 | END GENERATE; | |
421 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; |
|
420 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
422 |
|
421 | |||
423 | ---------------------------------------------------------------------- |
|
422 | ---------------------------------------------------------------------- | |
424 | --- APB Bridge ----------------------------------------------------- |
|
423 | --- APB Bridge ----------------------------------------------------- | |
425 | ---------------------------------------------------------------------- |
|
424 | ---------------------------------------------------------------------- | |
426 | apb0 : apbctrl -- AHB/APB bridge |
|
425 | apb0 : apbctrl -- AHB/APB bridge | |
427 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) |
|
426 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
428 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); |
|
427 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
429 |
|
428 | |||
430 | ---------------------------------------------------------------------- |
|
429 | ---------------------------------------------------------------------- | |
431 | --- GPT Timer ------------------------------------------------------ |
|
430 | --- GPT Timer ------------------------------------------------------ | |
432 | ---------------------------------------------------------------------- |
|
431 | ---------------------------------------------------------------------- | |
433 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE |
|
432 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
434 | timer0 : gptimer -- timer unit |
|
433 | timer0 : gptimer -- timer unit | |
435 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
|
434 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
436 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
|
435 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
437 | nbits => CFG_GPT_TW) |
|
436 | nbits => CFG_GPT_TW) | |
438 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); |
|
437 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
439 | gpti.dhalt <= dsuo.tstop; |
|
438 | gpti.dhalt <= dsuo.tstop; | |
440 | gpti.extclk <= '0'; |
|
439 | gpti.extclk <= '0'; | |
441 | END GENERATE; |
|
440 | END GENERATE; | |
442 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; |
|
441 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
443 |
|
442 | |||
444 |
|
443 | |||
445 | ---------------------------------------------------------------------- |
|
444 | ---------------------------------------------------------------------- | |
446 | --- APB UART ------------------------------------------------------- |
|
445 | --- APB UART ------------------------------------------------------- | |
447 | ---------------------------------------------------------------------- |
|
446 | ---------------------------------------------------------------------- | |
448 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE |
|
447 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
449 | uart1 : apbuart -- UART 1 |
|
448 | uart1 : apbuart -- UART 1 | |
450 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
|
449 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
451 | fifosize => CFG_UART1_FIFO) |
|
450 | fifosize => CFG_UART1_FIFO) | |
452 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); |
|
451 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
453 | apbuarti.rxd <= urxd1; |
|
452 | apbuarti.rxd <= urxd1; | |
454 | apbuarti.extclk <= '0'; |
|
453 | apbuarti.extclk <= '0'; | |
455 | utxd1 <= apbuarto.txd; |
|
454 | utxd1 <= apbuarto.txd; | |
456 | apbuarti.ctsn <= '0'; |
|
455 | apbuarti.ctsn <= '0'; | |
457 | END GENERATE; |
|
456 | END GENERATE; | |
458 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; |
|
457 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
459 |
|
458 | |||
460 | ------------------------------------------------------------------------------- |
|
459 | ------------------------------------------------------------------------------- | |
461 | -- AMBA BUS ------------------------------------------------------------------- |
|
460 | -- AMBA BUS ------------------------------------------------------------------- | |
462 | ------------------------------------------------------------------------------- |
|
461 | ------------------------------------------------------------------------------- | |
463 |
|
462 | |||
464 | -- APB -------------------------------------------------------------------- |
|
463 | -- APB -------------------------------------------------------------------- | |
465 | apbi_ext <= apbi; |
|
464 | apbi_ext <= apbi; | |
466 | all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE |
|
465 | all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE | |
467 | max_16_apb : IF I + 5 < 16 GENERATE |
|
466 | max_16_apb : IF I + 5 < 16 GENERATE | |
468 | apbo(I+5) <= apbo_ext(I+5); |
|
467 | apbo(I+5) <= apbo_ext(I+5); | |
469 | END GENERATE max_16_apb; |
|
468 | END GENERATE max_16_apb; | |
470 | END GENERATE all_apb; |
|
469 | END GENERATE all_apb; | |
471 | -- AHB_Slave -------------------------------------------------------------- |
|
470 | -- AHB_Slave -------------------------------------------------------------- | |
472 | ahbi_s_ext <= ahbsi; |
|
471 | ahbi_s_ext <= ahbsi; | |
473 | all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE |
|
472 | all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE | |
474 | max_16_ahbs : IF I + 3 < 16 GENERATE |
|
473 | max_16_ahbs : IF I + 3 < 16 GENERATE | |
475 | ahbso(I+3) <= ahbo_s_ext(I+3); |
|
474 | ahbso(I+3) <= ahbo_s_ext(I+3); | |
476 | END GENERATE max_16_ahbs; |
|
475 | END GENERATE max_16_ahbs; | |
477 | END GENERATE all_ahbs; |
|
476 | END GENERATE all_ahbs; | |
478 | -- AHB_Master ------------------------------------------------------------- |
|
477 | -- AHB_Master ------------------------------------------------------------- | |
479 | ahbi_m_ext <= ahbmi; |
|
478 | ahbi_m_ext <= ahbmi; | |
480 | all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE |
|
479 | all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE | |
481 | max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE |
|
480 | max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE | |
482 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); |
|
481 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); | |
483 | END GENERATE max_16_ahbm; |
|
482 | END GENERATE max_16_ahbm; | |
484 | END GENERATE all_ahbm; |
|
483 | END GENERATE all_ahbm; | |
485 |
|
484 | |||
486 |
|
485 | |||
487 |
|
486 | |||
488 |
END Behavioral; |
|
487 | END Behavioral; No newline at end of file |
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