diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -42,7 +42,7 @@ USE lpp.lpp_lfr_pkg.ALL; -- contains lp USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker USE lpp.iir_filter.ALL; USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_lfr_management.ALL; USE lpp.lpp_leon3_soc_pkg.ALL; ENTITY LFR_em IS @@ -250,7 +250,7 @@ BEGIN -- beh ------------------------------------------------------------------------------- -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- ------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management + apb_lfr_management_1 : apb_lfr_management GENERIC MAP ( pindex => 6, paddr => 6, @@ -264,6 +264,11 @@ BEGIN -- beh grspw_tick => swno.tickout, apbi => apbi_ext, apbo => apbo_ext(6), + + HK_sample => sample_s(8), + HK_val => sample_val, + HK_sel => HK_SEL, + coarse_time => coarse_time, fine_time => fine_time, LFR_soft_rstn => LFR_soft_rstn @@ -374,7 +379,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"01012F") -- aa.bb.cc version + top_lfr_version => X"010131") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM @@ -435,20 +440,4 @@ BEGIN -- beh ----------------------------------------------------------------------------- ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); - lpp_lfr_hk_1: lpp_lfr_hk - GENERIC MAP ( - pindex => 7, - paddr => 7, - pmask => 16#fff#) - PORT MAP ( - clk => clk_25, - rstn => rstn, - - apbi => apbi_ext, - apbo => apbo_ext(7), - - sample_val => sample_val, - sample => sample_s(8), - HK_SEL => HK_SEL); - END beh; diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -42,7 +42,7 @@ USE lpp.lpp_lfr_pkg.ALL; -- contains lp USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker USE lpp.iir_filter.ALL; USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_lfr_management.ALL; USE lpp.lpp_leon3_soc_pkg.ALL; ENTITY MINI_LFR_top IS @@ -385,9 +385,9 @@ BEGIN -- beh SRAM_CE <= SRAM_CE_s(0); ------------------------------------------------------------------------------- --- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- +-- APB_LFR_MANAGEMENT --------------------------------------------------------- ------------------------------------------------------------------------------- - apb_lfr_time_management_1 : apb_lfr_time_management + apb_lfr_management_1 : apb_lfr_management GENERIC MAP ( pindex => 6, paddr => 6, @@ -401,6 +401,9 @@ BEGIN -- beh grspw_tick => swno.tickout, apbi => apbi_ext, apbo => apbo_ext(6), + HK_sample => sample_hk, + HK_val => sample_val, + HK_sel => HK_SEL, coarse_time => coarse_time, fine_time => fine_time, LFR_soft_rstn => LFR_soft_rstn @@ -515,7 +518,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"00012E") -- aa.bb.cc version + top_lfr_version => X"000131") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, @@ -578,22 +581,6 @@ BEGIN -- beh ADC_CLK <= ADC_CLK_sig; ADC_SDO_sig <= ADC_SDO; - lpp_lfr_hk_1: lpp_lfr_hk - GENERIC MAP ( - pindex => 7, - paddr => 7, - pmask => 16#fff#) - PORT MAP ( - clk => clk_25, - rstn => rstn_25, - - apbi => apbi_ext, - apbo => apbo_ext(7), - - sample_val => sample_val, - sample => sample_hk, - HK_SEL => HK_SEL); - sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE "0010001000100010" WHEN HK_SEL = "10" ELSE "0100010001000100" WHEN HK_SEL = "10" ELSE @@ -727,7 +714,7 @@ BEGIN -- beh -- ----------------------------------------------------------------------------- all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE - apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 7 AND I /= 11 AND I /= 15 GENERATE + apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE apbo_ext(I) <= apb_none; END GENERATE apbo_ext_not_used; END GENERATE all_apbo_ext; diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -11,7 +11,7 @@ ./dsp/lpp_fft_rtax ./lpp_memory ./dsp/lpp_fft -./lfr_time_management +./lfr_management ./lpp_ad_Conv ./lpp_bootloader ./lpp_cna diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_management/apb_lfr_management.vhd rename from lib/lpp/lfr_time_management/apb_lfr_time_management.vhd rename to lib/lpp/lfr_management/apb_lfr_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_management/apb_lfr_management.vhd @@ -27,11 +27,11 @@ USE grlib.devices.ALL; LIBRARY lpp; USE lpp.apb_devices_list.ALL; USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; +USE lpp.lpp_lfr_management.ALL; +USE lpp.lpp_lfr_management_apbreg_pkg.ALL; -ENTITY apb_lfr_time_management IS +ENTITY apb_lfr_management IS GENERIC( pindex : INTEGER := 0; --! APB slave index @@ -50,16 +50,20 @@ ENTITY apb_lfr_time_management IS apbi : IN apb_slv_in_type; --! APB slave input signals apbo : OUT apb_slv_out_type; --! APB slave output signals - + --------------------------------------------------------------------------- + HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_val : IN STD_LOGIC; + HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + --------------------------------------------------------------------------- coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME --------------------------------------------------------------------------- LFR_soft_rstn : OUT STD_LOGIC ); -END apb_lfr_time_management; +END apb_lfr_management; -ARCHITECTURE Behavioral OF apb_lfr_time_management IS +ARCHITECTURE Behavioral OF apb_lfr_management IS CONSTANT REVISION : INTEGER := 1; CONSTANT pconfig : apb_config_type := ( @@ -74,6 +78,9 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); LFR_soft_reset : STD_LOGIC; + HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); END RECORD; SIGNAL r : apb_lfr_time_management_Reg; @@ -108,6 +115,10 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ SIGNAL soft_reset : STD_LOGIC; SIGNAL soft_reset_sync : STD_LOGIC; ----------------------------------------------------------------------------- + SIGNAL HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL HK_sel_s : STD_LOGIC_VECTOR( 1 DOWNTO 0); SIGNAL rstn_LFR_TM : STD_LOGIC; @@ -153,11 +164,11 @@ BEGIN --APB Write OP IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN CASE apbi.paddr(7 DOWNTO 2) IS - WHEN ADDR_LFR_TM_CONTROL => + WHEN ADDR_LFR_MANAGMENT_CONTROL => r.ctrl <= apbi.pwdata(0); r.soft_reset <= apbi.pwdata(1); r.LFR_soft_reset <= apbi.pwdata(2); - WHEN ADDR_LFR_TM_TIME_LOAD => + WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); coarsetime_reg_updated <= '1'; WHEN OTHERS => @@ -175,18 +186,27 @@ BEGIN --APB READ OP IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN CASE apbi.paddr(7 DOWNTO 2) IS - WHEN ADDR_LFR_TM_CONTROL => + WHEN ADDR_LFR_MANAGMENT_CONTROL => Rdata(0) <= r.ctrl; Rdata(1) <= r.soft_reset; Rdata(2) <= r.LFR_soft_reset; Rdata(31 DOWNTO 3) <= (others => '0'); - WHEN ADDR_LFR_TM_TIME_LOAD => + WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); - WHEN ADDR_LFR_TM_TIME_COARSE => + WHEN ADDR_LFR_MANAGMENT_TIME_COARSE => Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); - WHEN ADDR_LFR_TM_TIME_FINE => + WHEN ADDR_LFR_MANAGMENT_TIME_FINE => Rdata(31 DOWNTO 16) <= (OTHERS => '0'); Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); + WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 => + Rdata(31 DOWNTO 16) <= (OTHERS => '0'); + Rdata(15 DOWNTO 0) <= r.HK_temp_0; + WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 => + Rdata(31 DOWNTO 16) <= (OTHERS => '0'); + Rdata(15 DOWNTO 0) <= r.HK_temp_1; + WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 => + Rdata(31 DOWNTO 16) <= (OTHERS => '0'); + Rdata(15 DOWNTO 0) <= r.HK_temp_2; WHEN OTHERS => Rdata(31 DOWNTO 0) <= (others => '0'); END CASE; @@ -326,4 +346,35 @@ BEGIN coarse_time => coarse_time_49, coarse_time_new => coarse_time_new_49); -END Behavioral; + ----------------------------------------------------------------------------- + -- HK + ----------------------------------------------------------------------------- + + PROCESS (clk25MHz, resetn) + BEGIN -- PROCESS + IF resetn = '0' THEN -- asynchronous reset (active low) + + r.HK_temp_0 <= (OTHERS => '0'); + r.HK_temp_1 <= (OTHERS => '0'); + r.HK_temp_2 <= (OTHERS => '0'); + + HK_sel_s <= "00"; + + ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge + + IF HK_val = '1' THEN + CASE HK_sel_s IS + WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01"; + WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10"; + WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00"; + WHEN OTHERS => NULL; + END CASE; + + END IF; + + END IF; + END PROCESS; + + HK_sel <= HK_sel_s; + +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lfr_time_management/coarse_time_counter.vhd b/lib/lpp/lfr_management/coarse_time_counter.vhd rename from lib/lpp/lfr_time_management/coarse_time_counter.vhd rename to lib/lpp/lfr_management/coarse_time_counter.vhd diff --git a/lib/lpp/lfr_time_management/fine_time_counter.vhd b/lib/lpp/lfr_management/fine_time_counter.vhd rename from lib/lpp/lfr_time_management/fine_time_counter.vhd rename to lib/lpp/lfr_management/fine_time_counter.vhd diff --git a/lib/lpp/lfr_time_management/lfr_time_management.vhd b/lib/lpp/lfr_management/lfr_time_management.vhd rename from lib/lpp/lfr_time_management/lfr_time_management.vhd rename to lib/lpp/lfr_management/lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_management/lfr_time_management.vhd @@ -21,7 +21,7 @@ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; LIBRARY lpp; -USE lpp.lpp_lfr_time_management.ALL; +USE lpp.lpp_lfr_management.ALL; ENTITY lfr_time_management IS GENERIC ( diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd b/lib/lpp/lfr_management/lpp_lfr_management.vhd rename from lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd rename to lib/lpp/lfr_management/lpp_lfr_management.vhd --- a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +++ b/lib/lpp/lfr_management/lpp_lfr_management.vhd @@ -24,29 +24,31 @@ USE grlib.amba.ALL; USE grlib.stdlib.ALL; USE grlib.devices.ALL; -PACKAGE lpp_lfr_time_management IS +PACKAGE lpp_lfr_management IS --*************************** --- APB_LFR_TIME_MANAGEMENT +-- APB_LFR_MANAGEMENT - COMPONENT apb_lfr_time_management IS - GENERIC( - pindex : INTEGER := 0; --! APB slave index - paddr : INTEGER := 0; --! ADDR field of the APB BAR - pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR - FIRST_DIVISION : INTEGER; - NB_SECOND_DESYNC : INTEGER); + COMPONENT apb_lfr_management + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + FIRST_DIVISION : INTEGER; + NB_SECOND_DESYNC : INTEGER); PORT ( - clk25MHz : IN STD_LOGIC; --! Clock - clk24_576MHz : IN STD_LOGIC; --! secondary clock - resetn : IN STD_LOGIC; --! Reset - grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received - apbi : IN apb_slv_in_type; --! APB slave input signals - apbo : OUT apb_slv_out_type; --! APB slave output signals - coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time - fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME - LFR_soft_rstn : OUT STD_LOGIC - ); + clk25MHz : IN STD_LOGIC; + clk24_576MHz : IN STD_LOGIC; + resetn : IN STD_LOGIC; + grspw_tick : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + HK_val : IN STD_LOGIC; + HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + LFR_soft_rstn : OUT STD_LOGIC); END COMPONENT; COMPONENT lfr_time_management @@ -99,5 +101,5 @@ PACKAGE lpp_lfr_time_management IS END COMPONENT; -END lpp_lfr_time_management; +END lpp_lfr_management; diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management_apbreg_pkg.vhd b/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd rename from lib/lpp/lfr_time_management/lpp_lfr_time_management_apbreg_pkg.vhd rename to lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd --- a/lib/lpp/lfr_time_management/lpp_lfr_time_management_apbreg_pkg.vhd +++ b/lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd @@ -2,11 +2,14 @@ LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -PACKAGE lpp_lfr_time_management_apbreg_pkg IS +PACKAGE lpp_lfr_management_apbreg_pkg IS - CONSTANT ADDR_LFR_TM_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000"; - CONSTANT ADDR_LFR_TM_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001"; - CONSTANT ADDR_LFR_TM_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010"; - CONSTANT ADDR_LFR_TM_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011"; + CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000"; + CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001"; + CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010"; + CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011"; + CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100"; + CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101"; + CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110"; -END lpp_lfr_time_management_apbreg_pkg; +END lpp_lfr_management_apbreg_pkg; diff --git a/lib/lpp/lfr_time_management/vhdlsyn.txt b/lib/lpp/lfr_management/vhdlsyn.txt rename from lib/lpp/lfr_time_management/vhdlsyn.txt rename to lib/lpp/lfr_management/vhdlsyn.txt --- a/lib/lpp/lfr_time_management/vhdlsyn.txt +++ b/lib/lpp/lfr_management/vhdlsyn.txt @@ -1,6 +1,6 @@ -lpp_lfr_time_management.vhd -lpp_lfr_time_management_apbreg_pkg.vhd -apb_lfr_time_management.vhd +lpp_lfr_management.vhd +lpp_lfr_management_apbreg_pkg.vhd +apb_lfr_management.vhd lfr_time_management.vhd fine_time_counter.vhd coarse_time_counter.vhd diff --git a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3_soc.vhd @@ -39,7 +39,6 @@ USE lpp.lpp_ad_conv.ALL; USE lpp.lpp_lfr_pkg.ALL; USE lpp.iir_filter.ALL; USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; USE lpp.lpp_leon3_soc_pkg.ALL; LIBRARY iap; USE iap.memctrl.all; diff --git a/lib/lpp/lpp_leon3_soc/leon3ft_soc.vhd b/lib/lpp/lpp_leon3_soc/leon3ft_soc.vhd --- a/lib/lpp/lpp_leon3_soc/leon3ft_soc.vhd +++ b/lib/lpp/lpp_leon3_soc/leon3ft_soc.vhd @@ -1,488 +1,487 @@ ------------------------------------------------------------------------------ --- LEON3 Demonstration design --- Copyright (C) 2004 Jiri Gaisler, Gaisler Research --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; -LIBRARY gaisler; -USE gaisler.memctrl.ALL; -USE gaisler.leon3.ALL; -USE gaisler.uart.ALL; -USE gaisler.misc.ALL; -USE gaisler.spacewire.ALL; -- PLE -LIBRARY esa; -USE esa.memoryctrl.ALL; -LIBRARY lpp; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_ad_conv.ALL; -USE lpp.lpp_lfr_pkg.ALL; -USE lpp.iir_filter.ALL; -USE lpp.general_purpose.ALL; -USE lpp.lpp_lfr_time_management.ALL; -USE lpp.lpp_leon3_soc_pkg.ALL; - -ENTITY leon3ft_soc IS - GENERIC ( - fabtech : INTEGER := apa3e; - memtech : INTEGER := apa3e; - padtech : INTEGER := inferred; - clktech : INTEGER := inferred; - disas : INTEGER := 0; -- Enable disassembly to console - dbguart : INTEGER := 0; -- Print UART on console - pclow : INTEGER := 2; - -- - clk_freq : INTEGER := 25000; --kHz - -- - NB_CPU : INTEGER := 1; - ENABLE_FPU : INTEGER := 1; - FPU_NETLIST : INTEGER := 1; - ENABLE_DSU : INTEGER := 1; - ENABLE_AHB_UART : INTEGER := 1; - ENABLE_APB_UART : INTEGER := 1; - ENABLE_IRQMP : INTEGER := 1; - ENABLE_GPT : INTEGER := 1; - -- - NB_AHB_MASTER : INTEGER := 11; - NB_AHB_SLAVE : INTEGER := 1; - NB_APB_SLAVE : INTEGER := 2 - ); - PORT ( - clk : IN STD_ULOGIC; - reset : IN STD_ULOGIC; - - errorn : OUT STD_ULOGIC; - - -- UART AHB --------------------------------------------------------------- - ahbrxd : IN STD_ULOGIC; -- DSU rx data - ahbtxd : OUT STD_ULOGIC; -- DSU tx data - - -- UART APB --------------------------------------------------------------- - urxd1 : IN STD_ULOGIC; -- UART1 rx data - utxd1 : OUT STD_ULOGIC; -- UART1 tx data - - -- RAM -------------------------------------------------------------------- - address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); - data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); - nSRAM_BE0 : OUT STD_LOGIC; - nSRAM_BE1 : OUT STD_LOGIC; - nSRAM_BE2 : OUT STD_LOGIC; - nSRAM_BE3 : OUT STD_LOGIC; - nSRAM_WE : OUT STD_LOGIC; - nSRAM_CE : OUT STD_LOGIC; - nSRAM_OE : OUT STD_LOGIC; - - -- APB -------------------------------------------------------------------- - apbi_ext : OUT apb_slv_in_type; - apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); - -- AHB_Slave -------------------------------------------------------------- - ahbi_s_ext : OUT ahb_slv_in_type; - ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); - -- AHB_Master ------------------------------------------------------------- - ahbi_m_ext : OUT AHB_Mst_In_Type; - ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) - - ); -END; - -ARCHITECTURE Behavioral OF leon3ft_soc IS - - ----------------------------------------------------------------------------- - -- CONFIG ------------------------------------------------------------------- - ----------------------------------------------------------------------------- - - -- Clock generator - CONSTANT CFG_CLKMUL : INTEGER := (1); - CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz - CONSTANT CFG_OCLKDIV : INTEGER := (1); - CONSTANT CFG_CLK_NOFB : INTEGER := 0; - -- LEON3 processor core - CONSTANT CFG_LEON3 : INTEGER := 1; - CONSTANT CFG_NCPU : INTEGER := NB_CPU; - CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC - CONSTANT CFG_V8 : INTEGER := 0; - CONSTANT CFG_MAC : INTEGER := 0; - CONSTANT CFG_SVT : INTEGER := 0; - CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; - CONSTANT CFG_LDDEL : INTEGER := (1); - CONSTANT CFG_NWP : INTEGER := (0); - CONSTANT CFG_PWD : INTEGER := 1*2; - CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST); - -- 1*(8 + 16 * 0) => grfpu-light - -- 1*(8 + 16 * 1) => netlist - -- 0*(8 + 16 * 0) => No FPU - -- 0*(8 + 16 * 1) => No FPU; - CONSTANT CFG_ICEN : INTEGER := 1; - CONSTANT CFG_ISETS : INTEGER := 1; - CONSTANT CFG_ISETSZ : INTEGER := 4; - CONSTANT CFG_ILINE : INTEGER := 4; - CONSTANT CFG_IREPL : INTEGER := 0; - CONSTANT CFG_ILOCK : INTEGER := 0; - CONSTANT CFG_ILRAMEN : INTEGER := 0; - CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; - CONSTANT CFG_ILRAMSZ : INTEGER := 1; - CONSTANT CFG_DCEN : INTEGER := 1; - CONSTANT CFG_DSETS : INTEGER := 1; - CONSTANT CFG_DSETSZ : INTEGER := 4; - CONSTANT CFG_DLINE : INTEGER := 4; - CONSTANT CFG_DREPL : INTEGER := 0; - CONSTANT CFG_DLOCK : INTEGER := 0; - CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; - CONSTANT CFG_DLRAMEN : INTEGER := 0; - CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; - CONSTANT CFG_DLRAMSZ : INTEGER := 1; - CONSTANT CFG_MMUEN : INTEGER := 0; - CONSTANT CFG_ITLBNUM : INTEGER := 2; - CONSTANT CFG_DTLBNUM : INTEGER := 2; - CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2; - CONSTANT CFG_TLB_REP : INTEGER := 1; - - CONSTANT CFG_DSU : INTEGER := ENABLE_DSU; - CONSTANT CFG_ITBSZ : INTEGER := 0; - CONSTANT CFG_ATBSZ : INTEGER := 0; - - -- AMBA settings - CONSTANT CFG_DEFMST : INTEGER := (0); - CONSTANT CFG_RROBIN : INTEGER := 1; - CONSTANT CFG_SPLIT : INTEGER := 0; - CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; - CONSTANT CFG_APBADDR : INTEGER := 16#800#; - - -- DSU UART - CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART; - - -- LEON2 memory controller - CONSTANT CFG_MCTRL_SDEN : INTEGER := 0; - - -- UART 1 - CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART; - CONSTANT CFG_UART1_FIFO : INTEGER := 1; - - -- LEON3 interrupt controller - CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP; - - -- Modular timer - CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT; - CONSTANT CFG_GPT_NTIM : INTEGER := (2); - CONSTANT CFG_GPT_SW : INTEGER := (8); - CONSTANT CFG_GPT_TW : INTEGER := (32); - CONSTANT CFG_GPT_IRQ : INTEGER := (8); - CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; - CONSTANT CFG_GPT_WDOGEN : INTEGER := 0; - CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#; - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- SIGNALs - ----------------------------------------------------------------------------- - CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; - -- CLK & RST -- - SIGNAL clk2x : STD_ULOGIC; - SIGNAL clkmn : STD_ULOGIC; - SIGNAL clkm : STD_ULOGIC; - SIGNAL rstn : STD_ULOGIC; - SIGNAL rstraw : STD_ULOGIC; - SIGNAL pciclk : STD_ULOGIC; - SIGNAL sdclkl : STD_ULOGIC; - SIGNAL cgi : clkgen_in_type; - SIGNAL cgo : clkgen_out_type; - --- AHB / APB - SIGNAL apbi : apb_slv_in_type; - SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); - SIGNAL ahbsi : ahb_slv_in_type; - SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); - SIGNAL ahbmi : ahb_mst_in_type; - SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); - --UART - SIGNAL ahbuarti : uart_in_type; - SIGNAL ahbuarto : uart_out_type; - SIGNAL apbuarti : uart_in_type; - SIGNAL apbuarto : uart_out_type; - --MEM CTRLR - SIGNAL memi : memory_in_type; - SIGNAL memo : memory_out_type; - SIGNAL wpo : wprot_out_type; - SIGNAL sdo : sdram_out_type; - --IRQ - SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); - SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); - --Timer - SIGNAL gpti : gptimer_in_type; - SIGNAL gpto : gptimer_out_type; - --DSU - SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); - SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); - SIGNAL dsui : dsu_in_type; - SIGNAL dsuo : dsu_out_type; - ----------------------------------------------------------------------------- - - SIGNAL nSRAM_CE_s : STD_LOGIC; -BEGIN - - ----------------------------------------------------------------------- ---- Reset and Clock generation ------------------------------------- ----------------------------------------------------------------------- - - cgi.pllctrl <= "00"; - cgi.pllrst <= rstraw; - - rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); - - clkgen0 : clkgen -- clock generator - GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, - CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) - PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); - ----------------------------------------------------------------------- ---- LEON3 processor / DSU / IRQ ------------------------------------ ----------------------------------------------------------------------- - - l3 : IF CFG_LEON3 = 1 GENERATE - cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE - u0 : leon3ft - GENERIC MAP ( - hindex => i, --: integer; - fabtech => fabtech, - memtech => memtech, - nwindows => CFG_NWIN, - dsu => CFG_DSU, - fpu => CFG_FPU, - v8 => CFG_V8, - cp => 0, - mac => CFG_MAC, - pclow => pclow, - notag => 0, - nwp => CFG_NWP, - icen => CFG_ICEN, - irepl => CFG_IREPL, - isets => CFG_ISETS, - ilinesize => CFG_ILINE, - isetsize => CFG_ISETSZ, - isetlock => CFG_ILOCK, - dcen => CFG_DCEN, - drepl => CFG_DREPL, - dsets => CFG_DSETS, - dlinesize => CFG_DLINE, - dsetsize => CFG_DSETSZ, - dsetlock => CFG_DLOCK, - dsnoop => CFG_DSNOOP, - ilram => CFG_ILRAMEN, - ilramsize => CFG_ILRAMSZ, - ilramstart => CFG_ILRAMADDR, - dlram => CFG_DLRAMEN, - dlramsize => CFG_DLRAMSZ, - dlramstart => CFG_DLRAMADDR, - mmuen => CFG_MMUEN, - itlbnum => CFG_ITLBNUM, - dtlbnum => CFG_DTLBNUM, - tlb_type => CFG_TLB_TYPE, - tlb_rep => CFG_TLB_REP, - lddel => CFG_LDDEL, - disas => disas, - tbuf => CFG_ITBSZ, - pwd => CFG_PWD, - svt => CFG_SVT, - rstaddr => CFG_RSTADDR, - smp => CFG_NCPU-1, - iuft => 2, --: integer range 0 to 4; - fpft => 1, --: integer range 0 to 4; - cmft => 1, --: integer range 0 to 1; - iuinj => 0, --: integer; - ceinj => 0, --: integer range 0 to 3; - cached => 0, --: integer; - netlist => 0, --: integer; - scantest => 0, --: integer; - mmupgsz => 0, --: integer range 0 to 5; - bp => 1) --: integer); - PORT MAP ( - clk => clkm, - rstn => rstn, - ahbi => ahbmi, - ahbo => ahbmo(i), - ahbsi => ahbsi, - ahbso => ahbso, - irqi => irqi(i), - irqo => irqo(i), - dbgi => dbgi(i), - dbgo => dbgo(i), - gclk => clkm - ); - - END GENERATE; - - - errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); - - dsugen : IF CFG_DSU = 1 GENERATE - dsu0 : dsu3 -- LEON3 Debug Support Unit - GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsui.break <= '0'; - END GENERATE; - END GENERATE; - - nodsu : IF CFG_DSU = 0 GENERATE - ahbso(2) <= ahbs_none; - dsuo.tstop <= '0'; - dsuo.active <= '0'; - END GENERATE; - - irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE - irqctrl0 : irqmp -- interrupt controller - GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); - END GENERATE; - irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE - x : FOR i IN 0 TO CFG_NCPU-1 GENERATE - irqi(i).irl <= "0000"; - END GENERATE; - apbo(2) <= apb_none; - END GENERATE; - ----------------------------------------------------------------------- ---- Memory controllers --------------------------------------------- ----------------------------------------------------------------------- - memctrlr : mctrl GENERIC MAP ( - hindex => 0, - pindex => 0, - paddr => 0, - srbanks => 1 - ) - PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); - - memi.brdyn <= '1'; - memi.bexcn <= '1'; - memi.writen <= '1'; - memi.wrn <= "1111"; - memi.bwidth <= "10"; - - bdr : FOR i IN 0 TO 3 GENERATE - data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) - PORT MAP ( - data(31-i*8 DOWNTO 24-i*8), - memo.data(31-i*8 DOWNTO 24-i*8), - memo.bdrive(i), - memi.data(31-i*8 DOWNTO 24-i*8)); - END GENERATE; - - addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) - PORT MAP (address, memo.address(21 DOWNTO 2)); - nSRAM_CE_s <= NOT(memo.ramsn(0)); - rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); - oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); - nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); - nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); - nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); - nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); - nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); - ----------------------------------------------------------------------- ---- AHB CONTROLLER ------------------------------------------------- ----------------------------------------------------------------------- - ahb0 : ahbctrl -- AHB arbiter/multiplexer - GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, - rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, - ioen => 0, nahbm => maxahbmsp, nahbs => 8) - PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); - ----------------------------------------------------------------------- ---- AHB UART ------------------------------------------------------- ----------------------------------------------------------------------- - dcomgen : IF CFG_AHB_UART = 1 GENERATE - dcom0 : ahbuart - GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) - PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); - dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); - dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); - END GENERATE; - nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; - ----------------------------------------------------------------------- ---- APB Bridge ----------------------------------------------------- ----------------------------------------------------------------------- - apb0 : apbctrl -- AHB/APB bridge - GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) - PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); - ----------------------------------------------------------------------- ---- GPT Timer ------------------------------------------------------ ----------------------------------------------------------------------- - gpt : IF CFG_GPT_ENABLE /= 0 GENERATE - timer0 : gptimer -- timer unit - GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, - sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, - nbits => CFG_GPT_TW) - PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); - gpti.dhalt <= dsuo.tstop; - gpti.extclk <= '0'; - END GENERATE; - notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; - - ----------------------------------------------------------------------- ---- APB UART ------------------------------------------------------- ----------------------------------------------------------------------- - ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE - uart1 : apbuart -- UART 1 - GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, - fifosize => CFG_UART1_FIFO) - PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); - apbuarti.rxd <= urxd1; - apbuarti.extclk <= '0'; - utxd1 <= apbuarto.txd; - apbuarti.ctsn <= '0'; - END GENERATE; - noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; - -------------------------------------------------------------------------------- --- AMBA BUS ------------------------------------------------------------------- -------------------------------------------------------------------------------- - - -- APB -------------------------------------------------------------------- - apbi_ext <= apbi; - all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE - max_16_apb : IF I + 5 < 16 GENERATE - apbo(I+5) <= apbo_ext(I+5); - END GENERATE max_16_apb; - END GENERATE all_apb; - -- AHB_Slave -------------------------------------------------------------- - ahbi_s_ext <= ahbsi; - all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE - max_16_ahbs : IF I + 3 < 16 GENERATE - ahbso(I+3) <= ahbo_s_ext(I+3); - END GENERATE max_16_ahbs; - END GENERATE all_ahbs; - -- AHB_Master ------------------------------------------------------------- - ahbi_m_ext <= ahbmi; - all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE - max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE - ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); - END GENERATE max_16_ahbm; - END GENERATE all_ahbm; - - - -END Behavioral; +----------------------------------------------------------------------------- +-- LEON3 Demonstration design +-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.leon3.ALL; +USE gaisler.uart.ALL; +USE gaisler.misc.ALL; +USE gaisler.spacewire.ALL; -- PLE +LIBRARY esa; +USE esa.memoryctrl.ALL; +LIBRARY lpp; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_ad_conv.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.iir_filter.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_leon3_soc_pkg.ALL; + +ENTITY leon3ft_soc IS + GENERIC ( + fabtech : INTEGER := apa3e; + memtech : INTEGER := apa3e; + padtech : INTEGER := inferred; + clktech : INTEGER := inferred; + disas : INTEGER := 0; -- Enable disassembly to console + dbguart : INTEGER := 0; -- Print UART on console + pclow : INTEGER := 2; + -- + clk_freq : INTEGER := 25000; --kHz + -- + NB_CPU : INTEGER := 1; + ENABLE_FPU : INTEGER := 1; + FPU_NETLIST : INTEGER := 1; + ENABLE_DSU : INTEGER := 1; + ENABLE_AHB_UART : INTEGER := 1; + ENABLE_APB_UART : INTEGER := 1; + ENABLE_IRQMP : INTEGER := 1; + ENABLE_GPT : INTEGER := 1; + -- + NB_AHB_MASTER : INTEGER := 11; + NB_AHB_SLAVE : INTEGER := 1; + NB_APB_SLAVE : INTEGER := 2 + ); + PORT ( + clk : IN STD_ULOGIC; + reset : IN STD_ULOGIC; + + errorn : OUT STD_ULOGIC; + + -- UART AHB --------------------------------------------------------------- + ahbrxd : IN STD_ULOGIC; -- DSU rx data + ahbtxd : OUT STD_ULOGIC; -- DSU tx data + + -- UART APB --------------------------------------------------------------- + urxd1 : IN STD_ULOGIC; -- UART1 rx data + utxd1 : OUT STD_ULOGIC; -- UART1 tx data + + -- RAM -------------------------------------------------------------------- + address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); + data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); + nSRAM_BE0 : OUT STD_LOGIC; + nSRAM_BE1 : OUT STD_LOGIC; + nSRAM_BE2 : OUT STD_LOGIC; + nSRAM_BE3 : OUT STD_LOGIC; + nSRAM_WE : OUT STD_LOGIC; + nSRAM_CE : OUT STD_LOGIC; + nSRAM_OE : OUT STD_LOGIC; + + -- APB -------------------------------------------------------------------- + apbi_ext : OUT apb_slv_in_type; + apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); + -- AHB_Slave -------------------------------------------------------------- + ahbi_s_ext : OUT ahb_slv_in_type; + ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); + -- AHB_Master ------------------------------------------------------------- + ahbi_m_ext : OUT AHB_Mst_In_Type; + ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) + + ); +END; + +ARCHITECTURE Behavioral OF leon3ft_soc IS + + ----------------------------------------------------------------------------- + -- CONFIG ------------------------------------------------------------------- + ----------------------------------------------------------------------------- + + -- Clock generator + CONSTANT CFG_CLKMUL : INTEGER := (1); + CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz + CONSTANT CFG_OCLKDIV : INTEGER := (1); + CONSTANT CFG_CLK_NOFB : INTEGER := 0; + -- LEON3 processor core + CONSTANT CFG_LEON3 : INTEGER := 1; + CONSTANT CFG_NCPU : INTEGER := NB_CPU; + CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC + CONSTANT CFG_V8 : INTEGER := 0; + CONSTANT CFG_MAC : INTEGER := 0; + CONSTANT CFG_SVT : INTEGER := 0; + CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; + CONSTANT CFG_LDDEL : INTEGER := (1); + CONSTANT CFG_NWP : INTEGER := (0); + CONSTANT CFG_PWD : INTEGER := 1*2; + CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST); + -- 1*(8 + 16 * 0) => grfpu-light + -- 1*(8 + 16 * 1) => netlist + -- 0*(8 + 16 * 0) => No FPU + -- 0*(8 + 16 * 1) => No FPU; + CONSTANT CFG_ICEN : INTEGER := 1; + CONSTANT CFG_ISETS : INTEGER := 1; + CONSTANT CFG_ISETSZ : INTEGER := 4; + CONSTANT CFG_ILINE : INTEGER := 4; + CONSTANT CFG_IREPL : INTEGER := 0; + CONSTANT CFG_ILOCK : INTEGER := 0; + CONSTANT CFG_ILRAMEN : INTEGER := 0; + CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; + CONSTANT CFG_ILRAMSZ : INTEGER := 1; + CONSTANT CFG_DCEN : INTEGER := 1; + CONSTANT CFG_DSETS : INTEGER := 1; + CONSTANT CFG_DSETSZ : INTEGER := 4; + CONSTANT CFG_DLINE : INTEGER := 4; + CONSTANT CFG_DREPL : INTEGER := 0; + CONSTANT CFG_DLOCK : INTEGER := 0; + CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; + CONSTANT CFG_DLRAMEN : INTEGER := 0; + CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; + CONSTANT CFG_DLRAMSZ : INTEGER := 1; + CONSTANT CFG_MMUEN : INTEGER := 0; + CONSTANT CFG_ITLBNUM : INTEGER := 2; + CONSTANT CFG_DTLBNUM : INTEGER := 2; + CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2; + CONSTANT CFG_TLB_REP : INTEGER := 1; + + CONSTANT CFG_DSU : INTEGER := ENABLE_DSU; + CONSTANT CFG_ITBSZ : INTEGER := 0; + CONSTANT CFG_ATBSZ : INTEGER := 0; + + -- AMBA settings + CONSTANT CFG_DEFMST : INTEGER := (0); + CONSTANT CFG_RROBIN : INTEGER := 1; + CONSTANT CFG_SPLIT : INTEGER := 0; + CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; + CONSTANT CFG_APBADDR : INTEGER := 16#800#; + + -- DSU UART + CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART; + + -- LEON2 memory controller + CONSTANT CFG_MCTRL_SDEN : INTEGER := 0; + + -- UART 1 + CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART; + CONSTANT CFG_UART1_FIFO : INTEGER := 1; + + -- LEON3 interrupt controller + CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP; + + -- Modular timer + CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT; + CONSTANT CFG_GPT_NTIM : INTEGER := (2); + CONSTANT CFG_GPT_SW : INTEGER := (8); + CONSTANT CFG_GPT_TW : INTEGER := (32); + CONSTANT CFG_GPT_IRQ : INTEGER := (8); + CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; + CONSTANT CFG_GPT_WDOGEN : INTEGER := 0; + CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- SIGNALs + ----------------------------------------------------------------------------- + CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; + -- CLK & RST -- + SIGNAL clk2x : STD_ULOGIC; + SIGNAL clkmn : STD_ULOGIC; + SIGNAL clkm : STD_ULOGIC; + SIGNAL rstn : STD_ULOGIC; + SIGNAL rstraw : STD_ULOGIC; + SIGNAL pciclk : STD_ULOGIC; + SIGNAL sdclkl : STD_ULOGIC; + SIGNAL cgi : clkgen_in_type; + SIGNAL cgo : clkgen_out_type; + --- AHB / APB + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + --UART + SIGNAL ahbuarti : uart_in_type; + SIGNAL ahbuarto : uart_out_type; + SIGNAL apbuarti : uart_in_type; + SIGNAL apbuarto : uart_out_type; + --MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + --IRQ + SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); + SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); + --Timer + SIGNAL gpti : gptimer_in_type; + SIGNAL gpto : gptimer_out_type; + --DSU + SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); + SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); + SIGNAL dsui : dsu_in_type; + SIGNAL dsuo : dsu_out_type; + ----------------------------------------------------------------------------- + + SIGNAL nSRAM_CE_s : STD_LOGIC; +BEGIN + + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + cgi.pllctrl <= "00"; + cgi.pllrst <= rstraw; + + rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); + + clkgen0 : clkgen -- clock generator + GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, + CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) + PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); + +---------------------------------------------------------------------- +--- LEON3 processor / DSU / IRQ ------------------------------------ +---------------------------------------------------------------------- + + l3 : IF CFG_LEON3 = 1 GENERATE + cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE + u0 : leon3ft + GENERIC MAP ( + hindex => i, --: integer; + fabtech => fabtech, + memtech => memtech, + nwindows => CFG_NWIN, + dsu => CFG_DSU, + fpu => CFG_FPU, + v8 => CFG_V8, + cp => 0, + mac => CFG_MAC, + pclow => pclow, + notag => 0, + nwp => CFG_NWP, + icen => CFG_ICEN, + irepl => CFG_IREPL, + isets => CFG_ISETS, + ilinesize => CFG_ILINE, + isetsize => CFG_ISETSZ, + isetlock => CFG_ILOCK, + dcen => CFG_DCEN, + drepl => CFG_DREPL, + dsets => CFG_DSETS, + dlinesize => CFG_DLINE, + dsetsize => CFG_DSETSZ, + dsetlock => CFG_DLOCK, + dsnoop => CFG_DSNOOP, + ilram => CFG_ILRAMEN, + ilramsize => CFG_ILRAMSZ, + ilramstart => CFG_ILRAMADDR, + dlram => CFG_DLRAMEN, + dlramsize => CFG_DLRAMSZ, + dlramstart => CFG_DLRAMADDR, + mmuen => CFG_MMUEN, + itlbnum => CFG_ITLBNUM, + dtlbnum => CFG_DTLBNUM, + tlb_type => CFG_TLB_TYPE, + tlb_rep => CFG_TLB_REP, + lddel => CFG_LDDEL, + disas => disas, + tbuf => CFG_ITBSZ, + pwd => CFG_PWD, + svt => CFG_SVT, + rstaddr => CFG_RSTADDR, + smp => CFG_NCPU-1, + iuft => 2, --: integer range 0 to 4; + fpft => 1, --: integer range 0 to 4; + cmft => 1, --: integer range 0 to 1; + iuinj => 0, --: integer; + ceinj => 0, --: integer range 0 to 3; + cached => 0, --: integer; + netlist => 0, --: integer; + scantest => 0, --: integer; + mmupgsz => 0, --: integer range 0 to 5; + bp => 1) --: integer); + PORT MAP ( + clk => clkm, + rstn => rstn, + ahbi => ahbmi, + ahbo => ahbmo(i), + ahbsi => ahbsi, + ahbso => ahbso, + irqi => irqi(i), + irqo => irqo(i), + dbgi => dbgi(i), + dbgo => dbgo(i), + gclk => clkm + ); + + END GENERATE; + + + errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); + + dsugen : IF CFG_DSU = 1 GENERATE + dsu0 : dsu3 -- LEON3 Debug Support Unit + GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui.break <= '0'; + END GENERATE; + END GENERATE; + + nodsu : IF CFG_DSU = 0 GENERATE + ahbso(2) <= ahbs_none; + dsuo.tstop <= '0'; + dsuo.active <= '0'; + END GENERATE; + + irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE + irqctrl0 : irqmp -- interrupt controller + GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); + END GENERATE; + irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE + x : FOR i IN 0 TO CFG_NCPU-1 GENERATE + irqi(i).irl <= "0000"; + END GENERATE; + apbo(2) <= apb_none; + END GENERATE; + +---------------------------------------------------------------------- +--- Memory controllers --------------------------------------------- +---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + nSRAM_CE_s <= NOT(memo.ramsn(0)); + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + +---------------------------------------------------------------------- +--- AHB CONTROLLER ------------------------------------------------- +---------------------------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, + ioen => 0, nahbm => maxahbmsp, nahbs => 8) + PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- AHB UART ------------------------------------------------------- +---------------------------------------------------------------------- + dcomgen : IF CFG_AHB_UART = 1 GENERATE + dcom0 : ahbuart + GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) + PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); + dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); + dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); + END GENERATE; + nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; + +---------------------------------------------------------------------- +--- APB Bridge ----------------------------------------------------- +---------------------------------------------------------------------- + apb0 : apbctrl -- AHB/APB bridge + GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) + PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); + +---------------------------------------------------------------------- +--- GPT Timer ------------------------------------------------------ +---------------------------------------------------------------------- + gpt : IF CFG_GPT_ENABLE /= 0 GENERATE + timer0 : gptimer -- timer unit + GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW) + PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; + gpti.extclk <= '0'; + END GENERATE; + notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; + + +---------------------------------------------------------------------- +--- APB UART ------------------------------------------------------- +---------------------------------------------------------------------- + ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE + uart1 : apbuart -- UART 1 + GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); + apbuarti.rxd <= urxd1; + apbuarti.extclk <= '0'; + utxd1 <= apbuarto.txd; + apbuarti.ctsn <= '0'; + END GENERATE; + noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; + +------------------------------------------------------------------------------- +-- AMBA BUS ------------------------------------------------------------------- +------------------------------------------------------------------------------- + + -- APB -------------------------------------------------------------------- + apbi_ext <= apbi; + all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE + max_16_apb : IF I + 5 < 16 GENERATE + apbo(I+5) <= apbo_ext(I+5); + END GENERATE max_16_apb; + END GENERATE all_apb; + -- AHB_Slave -------------------------------------------------------------- + ahbi_s_ext <= ahbsi; + all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE + max_16_ahbs : IF I + 3 < 16 GENERATE + ahbso(I+3) <= ahbo_s_ext(I+3); + END GENERATE max_16_ahbs; + END GENERATE all_ahbs; + -- AHB_Master ------------------------------------------------------------- + ahbi_m_ext <= ahbmi; + all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE + max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE + ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); + END GENERATE max_16_ahbm; + END GENERATE all_ahbm; + + + +END Behavioral; \ No newline at end of file