HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r513:cb7d6dc9cf10

(MINI-LFR) WFP_MS 0.1.49...

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designs/LFR-em-WFP_MS/LFR-em.vhd +8 -19

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
-            USE lpp.lpp_lfr_time_management.ALL;
+            USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1           : IN    STD_ULOGIC;  -- DSU rx data
                 TAG3           : OUT   STD_ULOGIC;  -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2           : IN    STD_ULOGIC;  -- UART1 rx data
                 TAG4           : OUT   STD_ULOGIC;  -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address        : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0      : OUT   STD_LOGIC;
                 nSRAM_BE1      : OUT   STD_LOGIC;
                 nSRAM_BE2      : OUT   STD_LOGIC;
                 nSRAM_BE3      : OUT   STD_LOGIC;
                 nSRAM_WE       : OUT   STD_LOGIC;
                 nSRAM_CE       : OUT   STD_LOGIC;
                 nSRAM_OE       : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din       : IN    STD_LOGIC;
                 spw1_sin       : IN    STD_LOGIC;
                 spw1_dout      : OUT   STD_LOGIC;
                 spw1_sout      : OUT   STD_LOGIC;
                 spw2_din       : IN    STD_LOGIC;
                 spw2_sin       : IN    STD_LOGIC;
                 spw2_dout      : OUT   STD_LOGIC;
                 spw2_sout      : OUT   STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT   STD_LOGIC;
                 ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT   STD_LOGIC;
                 ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
                 -- HK ---------------------------------------------------------------------
                 HK_smpclk      : OUT   STD_LOGIC;
                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8           : OUT   STD_LOGIC;
                 led            : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(8 DOWNTO 0);
               SIGNAL sample_s    : Samples(8 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL  ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   ahbtxd => TAG3,
                   urxd1  => TAG2,
                   utxd1  => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE_s,
                   nSRAM_OE  => nSRAM_OE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               nSRAM_CE <= nSRAM_CE_s(0);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
-              apb_lfr_time_management_1 : apb_lfr_time_management
+              apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
+                  HK_sample     => sample_s(8),
+                  HK_val        => sample_val,
+                  HK_sel        => HK_SEL,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"01012F")  -- aa.bb.cc version
+                  top_lfr_version        => X"010131")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   debug_vector    => OPEN,
                   debug_vector_ms => OPEN);     --,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 9,
                   ncycle_cnv_high => 13,
                   ncycle_cnv      => 25,
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,
                   sample_val => sample_val);
               ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
               TAG8 <= ADC_smpclk_s;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
-              lpp_lfr_hk_1: lpp_lfr_hk
-                GENERIC MAP (
-                  pindex => 7,
-                  paddr  => 7,
-                  pmask  => 16#fff#)
-                PORT MAP (
-                  clk        => clk_25,
-                  rstn       => rstn,
-                  apbi       => apbi_ext,
-                  apbo       => apbo_ext(7),
-                  sample_val => sample_val,
-                  sample     => sample_s(8),
-                  HK_SEL     => HK_SEL);
             END beh;

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +8 -21

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
-            USE lpp.lpp_lfr_time_management.ALL;
+            USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY MINI_LFR_top IS
               PORT (
                 clk_50 : IN  STD_LOGIC;
                 clk_49 : IN  STD_LOGIC;
                 reset  : IN  STD_LOGIC;
                 --BPs
                 BP0    : IN  STD_LOGIC;
                 BP1    : IN  STD_LOGIC;
                 --LEDs
                 LED0   : OUT STD_LOGIC;
                 LED1   : OUT STD_LOGIC;
                 LED2   : OUT STD_LOGIC;
                 --UARTs
                 TXD1   : IN  STD_LOGIC;
                 RXD1   : OUT STD_LOGIC;
                 nCTS1  : OUT STD_LOGIC;
                 nRTS1  : IN  STD_LOGIC;
                 TXD2  : IN  STD_LOGIC;
                 RXD2  : OUT STD_LOGIC;
                 nCTS2 : OUT STD_LOGIC;
                 nDTR2 : IN  STD_LOGIC;
                 nRTS2 : IN  STD_LOGIC;
                 nDCD2 : OUT STD_LOGIC;
                 --EXT CONNECTOR
                 IO0  : INOUT STD_LOGIC;
                 IO1  : INOUT STD_LOGIC;
                 IO2  : INOUT STD_LOGIC;
                 IO3  : INOUT STD_LOGIC;
                 IO4  : INOUT STD_LOGIC;
                 IO5  : INOUT STD_LOGIC;
                 IO6  : INOUT STD_LOGIC;
                 IO7  : INOUT STD_LOGIC;
                 IO8  : INOUT STD_LOGIC;
                 IO9  : INOUT STD_LOGIC;
                 IO10 : INOUT STD_LOGIC;
                 IO11 : INOUT STD_LOGIC;
                 --SPACE WIRE
                 SPW_EN       : OUT STD_LOGIC;       -- 0 => off
                 SPW_NOM_DIN  : IN  STD_LOGIC;       -- NOMINAL LINK
                 SPW_NOM_SIN  : IN  STD_LOGIC;
                 SPW_NOM_DOUT : OUT STD_LOGIC;
                 SPW_NOM_SOUT : OUT STD_LOGIC;
                 SPW_RED_DIN  : IN  STD_LOGIC;       -- REDUNDANT LINK
                 SPW_RED_SIN  : IN  STD_LOGIC;
                 SPW_RED_DOUT : OUT STD_LOGIC;
                 SPW_RED_SOUT : OUT STD_LOGIC;
                 -- MINI LFR ADC INPUTS
                 ADC_nCS      : OUT STD_LOGIC;
                 ADC_CLK      : OUT STD_LOGIC;
                 ADC_SDO      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 -- SRAM
                 SRAM_nWE : OUT   STD_LOGIC;
                 SRAM_CE  : OUT   STD_LOGIC;
                 SRAM_nOE : OUT   STD_LOGIC;
                 SRAM_nBE : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                 SRAM_A   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 SRAM_DQ  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END MINI_LFR_top;
             ARCHITECTURE beh OF MINI_LFR_top IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL errorn      : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
             --  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
             --  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
               -- UART APB ---------------------------------------------------------------
             --  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
             --  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
               --
               SIGNAL I00_s : STD_LOGIC;
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               --
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);  --  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);  --  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);  -- := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --  SIGNAL clkmn                : STD_ULOGIC;
             --  SIGNAL txclk                : STD_ULOGIC;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL bias_fail_sw_sig : STD_LOGIC;
               SIGNAL observation_reg      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL rstn_25    : STD_LOGIC;
               SIGNAL rstn_25_d1 : STD_LOGIC;
               SIGNAL rstn_25_d2 : STD_LOGIC;
               SIGNAL rstn_25_d3 : STD_LOGIC;
               SIGNAL rstn_50    : STD_LOGIC;
               SIGNAL rstn_50_d1 : STD_LOGIC;
               SIGNAL rstn_50_d2 : STD_LOGIC;
               SIGNAL rstn_50_d3 : STD_LOGIC;
               SIGNAL lfr_debug_vector    : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
               --
               SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               --
               SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL HK_SEL    : STD_LOGIC_VECTOR( 1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               --PROCESS(clk_50)
               --BEGIN
               --  IF clk_50'EVENT AND clk_50 = '1' THEN
               --    clk_50_s <= NOT clk_50_s;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_50_s)
               --BEGIN
               --  IF clk_50_s'EVENT AND clk_50_s = '1' THEN
               --    clk_25 <= NOT clk_25;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_49)
               --BEGIN
               --  IF clk_49'EVENT AND clk_49 = '1' THEN
               --    clk_24 <= NOT clk_24;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_25)
               --BEGIN
               --  IF clk_25'EVENT AND clk_25 = '1' THEN
               --    rstn_25 <= reset;
               --  END IF;
               --END PROCESS;
               PROCESS (clk_50, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_50_s   <= '0';
                   rstn_50    <= '0';
                   rstn_50_d1 <= '0';
                   rstn_50_d2 <= '0';
                   rstn_50_d3 <= '0';
                 ELSIF clk_50'EVENT AND clk_50 = '1' THEN  -- rising clock edge
                   clk_50_s   <= NOT clk_50_s;
                   rstn_50_d1 <= '1';
                   rstn_50_d2 <= rstn_50_d1;
                   rstn_50_d3 <= rstn_50_d2;
                   rstn_50    <= rstn_50_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_50_s, rstn_50)
               BEGIN  -- PROCESS
                 IF rstn_50 = '0' THEN               -- asynchronous reset (active low)
                   clk_25     <= '0';
                   rstn_25    <= '0';
                   rstn_25_d1 <= '0';
                   rstn_25_d2 <= '0';
                   rstn_25_d3 <= '0';
                 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN  -- rising clock edge
                   clk_25     <= NOT clk_25;
                   rstn_25_d1 <= '1';
                   rstn_25_d2 <= rstn_25_d1;
                   rstn_25_d3 <= rstn_25_d2;
                   rstn_25    <= rstn_25_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_24 <= '0';
                 ELSIF clk_49'EVENT AND clk_49 = '1' THEN  -- rising clock edge
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   LED0 <= '0';
                   LED1 <= '0';
                   LED2 <= '0';
                   --IO1  <= '0';
                   --IO2  <= '1';
                   --IO3  <= '0';
                   --IO4  <= '0';
                   --IO5  <= '0';
                   --IO6  <= '0';
                   --IO7  <= '0';
                   --IO8  <= '0';
                   --IO9  <= '0';
                   --IO10 <= '0';
                   --IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   LED0 <= '0';
                   LED1 <= '1';
                   LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                   --IO1  <= '1';
                   --IO2  <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
                   --IO3  <= ADC_SDO(0);
                   --IO4  <= ADC_SDO(1);
                   --IO5  <= ADC_SDO(2);
                   --IO6  <= ADC_SDO(3);
                   --IO7  <= ADC_SDO(4);
                   --IO8  <= ADC_SDO(5);
                   --IO9  <= ADC_SDO(6);
                   --IO10 <= ADC_SDO(7);
                   --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                 END IF;
               END PROCESS;
               PROCESS (clk_24, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s;
                 END IF;
               END PROCESS;
             --  IO0 <= I00_s;
               --UARTs
               nCTS1 <= '1';
               nCTS2 <= '1';
               nDCD2 <= '1';
               --EXT CONNECTOR
               --SPACE WIRE
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn_25,
                   errorn    => errorn,
                   ahbrxd    => TXD1,
                   ahbtxd    => RXD1,
                   urxd1     => TXD2,
                   utxd1     => RXD2,
                   address   => SRAM_A,
                   data      => SRAM_DQ,
                   nSRAM_BE0 => SRAM_nBE(0),
                   nSRAM_BE1 => SRAM_nBE(1),
                   nSRAM_BE2 => SRAM_nBE(2),
                   nSRAM_BE3 => SRAM_nBE(3),
                   nSRAM_WE  => SRAM_nWE,
                   nSRAM_CE  => SRAM_CE_s,
                   nSRAM_OE  => SRAM_nOE,
                   nSRAM_READY => '0',
                   SRAM_MBE    => OPEN,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               SRAM_CE <= SRAM_CE_s(0);
             -------------------------------------------------------------------------------
-            -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
+            -- APB_LFR_MANAGEMENT ---------------------------------------------------------
             -------------------------------------------------------------------------------
-              apb_lfr_time_management_1 : apb_lfr_time_management
+              apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn_25,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
+                  HK_sample     => sample_hk,
+                  HK_val        => sample_val,
+                  HK_sel        => HK_SEL,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DIN, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SIN, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DOUT, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SOUT, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_SIN, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_DIN, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_DOUT, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_SOUT, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               swni.rmapnodeaddr <= (OTHERS => '0');
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn_25;
               --LFR_rstn <= rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"00012E")  -- aa.bb.cc version
+                  top_lfr_version        => X"000131")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw_sig,
                   debug_vector    => lfr_debug_vector,
                   debug_vector_ms => lfr_debug_vector_ms
                   );
               observation_reg(11 DOWNTO 0)      <= lfr_debug_vector;
               observation_reg(31 DOWNTO 12)     <= (OTHERS => '0');
               observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
               observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
               IO0                               <= rstn_25;
               IO1                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT data_valid
               IO2                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT ready
               IO3                               <= lfr_debug_vector(0);  -- LFR APBREG error_buffer_full
               IO4                               <= lfr_debug_vector(1);  -- LFR APBREG reg_sp.status_error_buffer_full
               IO5                               <= lfr_debug_vector(8);  -- LFR APBREG  ready_matrix_f2
               IO6                               <= lfr_debug_vector(9);  -- LFR APBREG reg0_ready_matrix_f2
               IO7                               <= lfr_debug_vector(10);  -- LFR APBREG reg0_ready_matrix_f2
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
               END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,
                   SampleNbBits    => 14,
                   ncycle_cnv_high => 40,  -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
                   ncycle_cnv      => 249)           -- 49 152 000 / 98304 /2
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn_25,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
                   rstn       => rstn_25,
                   sck        => ADC_CLK_sig,
                   sdo        => ADC_SDO_sig,
                   -- SAMPLE
                   sample     => sample,
                   sample_val => sample_val);
               --IO10 <= ADC_SDO_sig(5);
               --IO9  <= ADC_SDO_sig(4);
               --IO8  <= ADC_SDO_sig(3);
               ADC_nCS     <= ADC_nCS_sig;
               ADC_CLK     <= ADC_CLK_sig;
               ADC_SDO_sig <= ADC_SDO;
-              lpp_lfr_hk_1: lpp_lfr_hk
-                GENERIC MAP (
-                  pindex => 7,
-                  paddr  => 7,
-                  pmask  => 16#fff#)
-                PORT MAP (
-                  clk        => clk_25,
-                  rstn       => rstn_25,
-                  apbi       => apbi_ext,
-                  apbo       => apbo_ext(7),
-                  sample_val => sample_val,
-                  sample     => sample_hk,
-                  HK_SEL     => HK_SEL);
               sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
                            "0010001000100010" WHEN HK_SEL = "10" ELSE
                            "0100010001000100" WHEN HK_SEL = "10" ELSE
                            (OTHERS => '0');
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------
             ----------------------------------------------------------------------
               grgpio0 : grgpio
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
               gpioi.sig_en <= (OTHERS => '0');
               gpioi.sig_in <= (OTHERS => '0');
               gpioi.din    <= (OTHERS => '0');
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
               --pio_pad_1 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
               --pio_pad_2 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
               --pio_pad_3 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
               --pio_pad_4 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
               --pio_pad_5 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
               --pio_pad_6 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
               --pio_pad_7 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   --    --IO0  <= '0';
                   --    IO1  <= '0';
                   --    IO2  <= '0';
                   --    IO3  <= '0';
                   --    IO4  <= '0';
                   --    IO5  <= '0';
                   --    IO6  <= '0';
                   --    IO7  <= '0';
                   IO8  <= '0';
                   IO9  <= '0';
                   IO10 <= '0';
                   IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   CASE gpioo.dout(2 DOWNTO 0) IS
                     WHEN "011" =>
                       --        --IO0  <= observation_reg(0 );
                       --        IO1  <= observation_reg(1 );
                       --        IO2  <= observation_reg(2 );
                       --        IO3  <= observation_reg(3 );
                       --        IO4  <= observation_reg(4 );
                       --        IO5  <= observation_reg(5 );
                       --        IO6  <= observation_reg(6 );
                       --        IO7  <= observation_reg(7 );
                       IO8  <= observation_reg(8);
                       IO9  <= observation_reg(9);
                       IO10 <= observation_reg(10);
                       IO11 <= observation_reg(11);
                     WHEN "001" =>
                       --        --IO0  <= observation_reg(0  + 12);
                       --        IO1  <= observation_reg(1  + 12);
                       --        IO2  <= observation_reg(2  + 12);
                       --        IO3  <= observation_reg(3  + 12);
                       --        IO4  <= observation_reg(4  + 12);
                       --        IO5  <= observation_reg(5  + 12);
                       --        IO6  <= observation_reg(6  + 12);
                       --        IO7  <= observation_reg(7  + 12);
                       IO8  <= observation_reg(8 + 12);
                       IO9  <= observation_reg(9 + 12);
                       IO10 <= observation_reg(10 + 12);
                       IO11 <= observation_reg(11 + 12);
                     WHEN "010" =>
                       --        --IO0  <= observation_reg(0  + 12 + 12);
                       --        IO1  <= observation_reg(1  + 12 + 12);
                       --        IO2  <= observation_reg(2  + 12 + 12);
                       --        IO3  <= observation_reg(3  + 12 + 12);
                       --        IO4  <= observation_reg(4  + 12 + 12);
                       --        IO5  <= observation_reg(5  + 12 + 12);
                       --        IO6  <= observation_reg(6  + 12 + 12);
                       --        IO7  <= observation_reg(7  + 12 + 12);
                       IO8  <= '0';
                       IO9  <= '0';
                       IO10 <= '0';
                       IO11 <= '0';
                     WHEN "000" =>
                       --        --IO0  <= observation_vector_0(0 );
                       --        IO1  <= observation_vector_0(1 );
                       --        IO2  <= observation_vector_0(2 );
                       --        IO3  <= observation_vector_0(3 );
                       --        IO4  <= observation_vector_0(4 );
                       --        IO5  <= observation_vector_0(5 );
                       --        IO6  <= observation_vector_0(6 );
                       --        IO7  <= observation_vector_0(7 );
                       IO8  <= observation_vector_0(8);
                       IO9  <= observation_vector_0(9);
                       IO10 <= observation_vector_0(10);
                       IO11 <= observation_vector_0(11);
                     WHEN "100" =>
                       --        --IO0  <= observation_vector_1(0 );
                       --        IO1  <= observation_vector_1(1 );
                       --        IO2  <= observation_vector_1(2 );
                       --        IO3  <= observation_vector_1(3 );
                       --        IO4  <= observation_vector_1(4 );
                       --        IO5  <= observation_vector_1(5 );
                       --        IO6  <= observation_vector_1(6 );
                       --        IO7  <= observation_vector_1(7 );
                       IO8  <= observation_vector_1(8);
                       IO9  <= observation_vector_1(9);
                       IO10 <= observation_vector_1(10);
                       IO11 <= observation_vector_1(11);
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
-                apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 7 AND I /= 11 AND I /= 15 GENERATE
+                apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
                   apbo_ext(I) <= apb_none;
                 END GENERATE apbo_ext_not_used;
               END GENERATE all_apbo_ext;
               all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
                 ahbo_s_ext(I) <= ahbs_none;
               END GENERATE all_ahbo_ext;
               all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
                 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
                   ahbo_m_ext(I) <= ahbm_none;
                 END GENERATE ahbo_m_ext_not_used;
               END GENERATE all_ahbo_m_ext;
             END beh;

lib/lpp/dirs.txt +1 -1

             ./amba_lcd_16x2_ctrlr
             ./general_purpose
             ./general_purpose/lpp_AMR
             ./general_purpose/lpp_balise
             ./general_purpose/lpp_delay
             ./lpp_amba
             ./dsp/chirp
             ./dsp/iir_filter
             ./dsp/cic
             ./dsp/lpp_downsampling
             ./dsp/lpp_fft_rtax
             ./lpp_memory
             ./dsp/lpp_fft
-            ./lfr_time_management
+            ./lfr_management
             ./lpp_ad_Conv
             ./lpp_bootloader
             ./lpp_cna
             ./lpp_spectral_matrix
             ./lpp_demux
             ./lpp_Header
             ./lpp_matrix
             ./lpp_uart
             ./lpp_usb
             ./lpp_dma
             ./lpp_waveform
             ./lpp_top_lfr
             ./lpp_Header
             ./lpp_leon3_soc
             ./lpp_debug_lfr
             ./lpp_sim/CY7C1061DV33
             ./lpp_sim

lib/lpp/lfr_management/apb_lfr_management.vhd ~~lib/lpp/lfr_time_management/apb_lfr_time_management.vhd~~ renamed +64 -13

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    11:17:05 07/02/2012
             -- Design Name:
             -- Module Name:    apb_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.apb_devices_list.ALL;
             USE lpp.general_purpose.ALL;
-            USE lpp.lpp_lfr_time_management.ALL;
+            USE lpp.lpp_lfr_management.ALL;
-            USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
+            USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
-            ENTITY apb_lfr_time_management IS
+            ENTITY apb_lfr_management IS
               GENERIC(
                 pindex         : INTEGER := 0;        --! APB slave index
                 paddr          : INTEGER := 0;        --! ADDR field of the APB BAR
                 pmask          : INTEGER := 16#fff#;   --! MASK field of the APB BAR
                 FIRST_DIVISION   : INTEGER := 374;
                 NB_SECOND_DESYNC : INTEGER := 60
                 );
               PORT (
                 clk25MHz     : IN STD_LOGIC;        --! Clock
                 clk24_576MHz : IN STD_LOGIC;        --! secondary clock
                 resetn       : IN STD_LOGIC;        --! Reset
                 grspw_tick : IN STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
                 apbi : IN  apb_slv_in_type;         --! APB slave input signals
                 apbo : OUT apb_slv_out_type;        --! APB slave output signals
+                ---------------------------------------------------------------------------
+                HK_sample : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
+                HK_val    : IN  STD_LOGIC;
+                HK_sel    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+                ---------------------------------------------------------------------------
                 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
                 fine_time   : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);   --! fine TIME
                 ---------------------------------------------------------------------------
                 LFR_soft_rstn : OUT STD_LOGIC
                 );
-            END apb_lfr_time_management;
+            END apb_lfr_management;
-            ARCHITECTURE Behavioral OF apb_lfr_time_management IS
+            ARCHITECTURE Behavioral OF apb_lfr_management IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
 => apb_iobar(paddr, pmask)
                 );
               TYPE apb_lfr_time_management_Reg IS RECORD
                 ctrl             : STD_LOGIC;
                 soft_reset       : STD_LOGIC;
                 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
                 coarse_time      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fine_time        : STD_LOGIC_VECTOR(15 DOWNTO 0);
                 LFR_soft_reset   : STD_LOGIC;
+                HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
+                HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
+                HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
               END RECORD;
               SIGNAL r                   : apb_lfr_time_management_Reg;
               SIGNAL Rdata               : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL force_tick          : STD_LOGIC;
               SIGNAL previous_force_tick : STD_LOGIC;
               SIGNAL soft_tick           : STD_LOGIC;
               SIGNAL coarsetime_reg_updated : STD_LOGIC;
               SIGNAL coarsetime_reg         : STD_LOGIC_VECTOR(30 DOWNTO 0);
               --SIGNAL coarse_time_new    : STD_LOGIC;
               SIGNAL coarse_time_new_49 : STD_LOGIC;
               SIGNAL coarse_time_49     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL coarse_time_s      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               --SIGNAL fine_time_new      : STD_LOGIC;
               --SIGNAL fine_time_new_temp : STD_LOGIC;
               SIGNAL fine_time_new_49   : STD_LOGIC;
               SIGNAL fine_time_49       : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fine_time_s        : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL tick               : STD_LOGIC;
               SIGNAL new_timecode       : STD_LOGIC;
               SIGNAL new_coarsetime     : STD_LOGIC;
               SIGNAL time_new_49 : STD_LOGIC;
               SIGNAL time_new    : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL force_reset          : STD_LOGIC;
               SIGNAL previous_force_reset : STD_LOGIC;
               SIGNAL soft_reset           : STD_LOGIC;
               SIGNAL soft_reset_sync      : STD_LOGIC;
               -----------------------------------------------------------------------------
+              SIGNAL  HK_temp_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
+              SIGNAL  HK_temp_1_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
+              SIGNAL  HK_temp_2_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
+              SIGNAL  HK_sel_s    : STD_LOGIC_VECTOR( 1 DOWNTO 0);
               SIGNAL rstn_LFR_TM : STD_LOGIC;
             BEGIN
               LFR_soft_rstn <= NOT r.LFR_soft_reset;
               PROCESS(resetn, clk25MHz)
               BEGIN
                 IF resetn = '0' THEN
                   Rdata               <= (OTHERS => '0');
                   r.coarse_time_load  <= (OTHERS => '0');
                   r.soft_reset              <= '0';
                   r.ctrl              <= '0';
                   r.LFR_soft_reset    <= '1';
                   force_tick          <= '0';
                   previous_force_tick <= '0';
                   soft_tick           <= '0';
                   coarsetime_reg_updated <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
                   coarsetime_reg_updated <= '0';
                   force_tick          <= r.ctrl;
                   previous_force_tick <= force_tick;
                   IF (previous_force_tick = '0') AND (force_tick = '1') THEN
                     soft_tick <= '1';
                   ELSE
                     soft_tick <= '0';
                   END IF;
                   force_reset          <= r.soft_reset;
                   previous_force_reset <= force_reset;
                   IF (previous_force_reset = '0') AND (force_reset = '1') THEN
                     soft_reset <= '1';
                   ELSE
                     soft_reset <= '0';
                   END IF;
             --APB Write OP
                   IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
                     CASE apbi.paddr(7 DOWNTO 2) IS
-                      WHEN ADDR_LFR_TM_CONTROL =>
+                      WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                         r.ctrl              <= apbi.pwdata(0);
                         r.soft_reset        <= apbi.pwdata(1);
                         r.LFR_soft_reset    <= apbi.pwdata(2);
-                      WHEN ADDR_LFR_TM_TIME_LOAD =>
+                      WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                         r.coarse_time_load     <= apbi.pwdata(30 DOWNTO 0);
                         coarsetime_reg_updated <= '1';
                       WHEN OTHERS =>
                         NULL;
                     END CASE;
                   ELSE
                     IF r.ctrl = '1' THEN
                       r.ctrl <= '0';
                     END if;
                     IF r.soft_reset = '1' THEN
                       r.soft_reset <= '0';
                     END if;
                   END IF;
             --APB READ OP
                   IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
                     CASE apbi.paddr(7 DOWNTO 2) IS
-                      WHEN ADDR_LFR_TM_CONTROL =>
+                      WHEN ADDR_LFR_MANAGMENT_CONTROL =>
                         Rdata(0)            <= r.ctrl;
                         Rdata(1)            <= r.soft_reset;
                         Rdata(2)            <= r.LFR_soft_reset;
                         Rdata(31 DOWNTO 3)  <= (others => '0');
-                      WHEN ADDR_LFR_TM_TIME_LOAD =>
+                      WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
                         Rdata(30 DOWNTO 0)  <= r.coarse_time_load(30 DOWNTO 0);
-                      WHEN ADDR_LFR_TM_TIME_COARSE =>
+                      WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
                         Rdata(31 DOWNTO 0)  <= r.coarse_time(31 DOWNTO 0);
-                      WHEN ADDR_LFR_TM_TIME_FINE =>
+                      WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.fine_time(15 DOWNTO 0);
+                      WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
+                        Rdata(31 DOWNTO 16) <= (OTHERS => '0');
+                        Rdata(15 DOWNTO 0)  <= r.HK_temp_0;
+                      WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
+                        Rdata(31 DOWNTO 16) <= (OTHERS => '0');
+                        Rdata(15 DOWNTO 0)  <= r.HK_temp_1;
+                      WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
+                        Rdata(31 DOWNTO 16) <= (OTHERS => '0');
+                        Rdata(15 DOWNTO 0)  <= r.HK_temp_2;
                       WHEN OTHERS =>
                         Rdata(31 DOWNTO 0)  <= (others => '0');
                     END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               apbo.pirq    <= (OTHERS => '0');
               apbo.prdata  <= Rdata;
               apbo.pconfig <= pconfig;
               apbo.pindex  <= pindex;
               -----------------------------------------------------------------------------
               -- IN
               coarse_time    <= r.coarse_time;
               fine_time      <= r.fine_time;
               coarsetime_reg <= r.coarse_time_load;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- OUT
               r.coarse_time  <= coarse_time_s;
               r.fine_time    <= fine_time_s;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               tick <= grspw_tick OR soft_tick;
               SYNC_VALID_BIT_1 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => tick,
                   sout    => new_timecode);
               SYNC_VALID_BIT_2 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => coarsetime_reg_updated,
                   sout    => new_coarsetime);
               SYNC_VALID_BIT_3 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => soft_reset,
                   sout    => soft_reset_sync);
               -----------------------------------------------------------------------------
               --SYNC_FF_1 : SYNC_FF
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk    => clk25MHz,
               --    rstn   => resetn,
               --    A      => fine_time_new_49,
               --    A_sync => fine_time_new_temp);
               --lpp_front_detection_1 : lpp_front_detection
               --  PORT MAP (
               --    clk  => clk25MHz,
               --    rstn => resetn,
               --    sin  => fine_time_new_temp,
               --    sout => fine_time_new);
               --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk24_576MHz,
               --    clk_out => clk25MHz,
               --    rstn    => resetn,
               --    sin     => coarse_time_new_49,
               --    sout    => coarse_time_new);
               time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
               SYNC_VALID_BIT_4 : SYNC_VALID_BIT
                GENERIC MAP (
                  NB_FF_OF_SYNC => 2)
                PORT MAP (
                  clk_in  => clk24_576MHz,
                  clk_out => clk25MHz,
                  rstn    => resetn,
                  sin     => time_new_49,
                  sout    => time_new);
               PROCESS (clk25MHz, resetn)
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)
                   fine_time_s   <= (OTHERS => '0');
                   coarse_time_s <= (OTHERS => '0');
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF time_new = '1' THEN
                     fine_time_s   <= fine_time_49;
                     coarse_time_s <= coarse_time_49;
                   END IF;
                 END IF;
               END PROCESS;
               rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
                              '0' WHEN soft_reset_sync = '1' ELSE
                              '1';
               -----------------------------------------------------------------------------
               -- LFR_TIME_MANAGMENT
               -----------------------------------------------------------------------------
               lfr_time_management_1 : lfr_time_management
                 GENERIC MAP (
                   FIRST_DIVISION   => FIRST_DIVISION,
                   NB_SECOND_DESYNC => NB_SECOND_DESYNC)
                 PORT MAP (
                   clk  => clk24_576MHz,
                   rstn => rstn_LFR_TM,
                   tick           => new_timecode,
                   new_coarsetime => new_coarsetime,
                   coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
                   fine_time       => fine_time_49,
                   fine_time_new   => fine_time_new_49,
                   coarse_time     => coarse_time_49,
                   coarse_time_new => coarse_time_new_49);
-            END Behavioral;
+              -----------------------------------------------------------------------------
+              -- HK
+              -----------------------------------------------------------------------------
+              PROCESS (clk25MHz, resetn)
+              BEGIN  -- PROCESS
+                IF resetn = '0' THEN                  -- asynchronous reset (active low)
+                  r.HK_temp_0 <= (OTHERS => '0');
+                  r.HK_temp_1 <= (OTHERS => '0');
+                  r.HK_temp_2 <= (OTHERS => '0');
+                  HK_sel_s <= "00";
+                ELSIF clk25MHz'event AND clk25MHz = '1' THEN  -- rising clock edge
+                  IF HK_val = '1' THEN
+                    CASE HK_sel_s IS
+                      WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01";
+                      WHEN "01" => r.HK_temp_1 <= HK_sample; HK_sel_s <= "10";
+                      WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00";
+                      WHEN OTHERS => NULL;
+                    END CASE;
+                  END IF;
+                END IF;
+              END PROCESS;
+              HK_sel <= HK_sel_s;
+            END Behavioral;
  No newline at end of file

lib/lpp/lfr_management/coarse_time_counter.vhd ~~lib/lpp/lfr_time_management/coarse_time_counter.vhd~~ renamed 0 0

NO CONTENT: file renamed from lib/lpp/lfr_time_management/coarse_time_counter.vhd to lib/lpp/lfr_management/coarse_time_counter.vhd

lib/lpp/lfr_management/fine_time_counter.vhd ~~lib/lpp/lfr_time_management/fine_time_counter.vhd~~ renamed 0 0

NO CONTENT: file renamed from lib/lpp/lfr_time_management/fine_time_counter.vhd to lib/lpp/lfr_management/fine_time_counter.vhd

lib/lpp/lfr_management/lfr_time_management.vhd ~~lib/lpp/lfr_time_management/lfr_time_management.vhd~~ renamed +1 -1

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    11:14:05 07/02/2012
             -- Design Name:
             -- Module Name:    lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY lpp;
-            USE lpp.lpp_lfr_time_management.ALL;
+            USE lpp.lpp_lfr_management.ALL;
             ENTITY lfr_time_management IS
               GENERIC (
                 FIRST_DIVISION   : INTEGER := 374;
                 NB_SECOND_DESYNC : INTEGER := 60);
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 tick           : IN STD_LOGIC;      -- transition signal information
                 new_coarsetime : IN STD_LOGIC;      -- transition signal information
                 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                 fine_time       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                 fine_time_new   : OUT STD_LOGIC;
                 coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 coarse_time_new : OUT STD_LOGIC
                 );
             END lfr_time_management;
             ARCHITECTURE Behavioral OF lfr_time_management IS
               SIGNAL FT_max : STD_LOGIC;
               SIGNAL FT_half : STD_LOGIC;
               SIGNAL FT_wait : STD_LOGIC;
               TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
               SIGNAL state : state_fsm_time_management;
               SIGNAL fsm_desync   : STD_LOGIC;
               SIGNAL fsm_transition : STD_LOGIC;
               SIGNAL set_TCU : STD_LOGIC;
               SIGNAL CT_add1 : STD_LOGIC;
               SIGNAL new_coarsetime_reg : STD_LOGIC;
             BEGIN
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   new_coarsetime_reg <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF new_coarsetime = '1' THEN
                     new_coarsetime_reg <= '1';
                   ELSIF tick = '1' THEN
                     new_coarsetime_reg <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FINE_TIME
               -----------------------------------------------------------------------------
               fine_time_counter_1: fine_time_counter
                 GENERIC MAP (
                   WAITING_TIME => X"0040",
                   FIRST_DIVISION => FIRST_DIVISION)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   tick           => tick,
                   fsm_transition => fsm_transition,  -- todo
                   FT_max         => FT_max,
                   FT_half        => FT_half,
                   FT_wait        => FT_wait,
                   fine_time      => fine_time,
                   fine_time_new  => fine_time_new);
               -----------------------------------------------------------------------------
               -- COARSE_TIME
               -----------------------------------------------------------------------------
               coarse_time_counter_1: coarse_time_counter
                 GENERIC MAP(
                   NB_SECOND_DESYNC => NB_SECOND_DESYNC )
                 PORT MAP (
                   clk           => clk,
                   rstn          => rstn,
                   tick          => tick,
                   set_TCU       => set_TCU,         -- todo
                   new_TCU       => new_coarsetime_reg,
                   set_TCU_value => coarsetime_reg,  -- todo
                   CT_add1       => CT_add1,         -- todo
                   fsm_desync    => fsm_desync,      -- todo
                   FT_max        => FT_max,
                   coarse_time   => coarse_time,
                   coarse_time_new   => coarse_time_new);
               -----------------------------------------------------------------------------
               -- FSM
               -----------------------------------------------------------------------------
               fsm_desync     <= '1' WHEN state = DESYNC     ELSE '0';
               fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   state <= DESYNC;
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   --CT_add1 <= '0';
                   set_TCU <= '0';
                   CASE state IS
                     WHEN DESYNC =>
                       IF tick = '1' THEN
                         state <= SYNC;
                         set_TCU <= new_coarsetime_reg;
                         --IF new_coarsetime = '0' AND FT_half = '1' THEN
                         --  CT_add1 <= '1';
                         --END IF;
                       --ELSIF FT_max = '1' THEN
                       --  CT_add1 <= '1';
                       END IF;
                     WHEN TRANSITION =>
                       IF tick = '1' THEN
                         state         <= SYNC;
                         set_TCU       <= new_coarsetime_reg;
                         --IF new_coarsetime = '0' THEN
                         --  CT_add1 <= '1';
                         --END IF;
                       ELSIF FT_wait = '1' THEN
                         --CT_add1 <= '1';
                         state         <= DESYNC;
                       END IF;
                     WHEN SYNC =>
                       IF tick = '1' THEN
                         set_TCU       <= new_coarsetime_reg;
                         --IF new_coarsetime = '0' THEN
                         --  CT_add1 <= '1';
                         --END IF;
                       ELSIF FT_max = '1' THEN
                         state         <= TRANSITION;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               CT_add1 <= '1' WHEN state = SYNC   AND tick = '1' AND new_coarsetime_reg = '0' ELSE
                          '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
                          '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
                          '1' WHEN state = TRANSITION AND  tick = '1' AND new_coarsetime_reg = '0' ELSE
                          '1' WHEN state = TRANSITION AND  tick = '0' AND FT_wait = '1' ELSE
                          '0';
             END Behavioral;

lib/lpp/lfr_management/lpp_lfr_management.vhd ~~lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd~~ renamed +22 -20

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    13:04:01 07/02/2012
             -- Design Name:
             -- Module Name:    lpp_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
-            PACKAGE lpp_lfr_time_management IS
+            PACKAGE lpp_lfr_management IS
             --***************************
-            -- APB_LFR_TIME_MANAGEMENT
+            -- APB_LFR_MANAGEMENT
-              COMPONENT apb_lfr_time_management IS
+              COMPONENT apb_lfr_management
-                GENERIC(
+                GENERIC (
-                  pindex            : INTEGER := 0;            --! APB slave index
+                  pindex           : INTEGER;
-                  paddr             : INTEGER := 0;            --! ADDR field of the APB BAR
+                  paddr            : INTEGER;
-                  pmask             : INTEGER := 16#fff#;       --! MASK field of the APB BAR
+                  pmask            : INTEGER;
-                  FIRST_DIVISION    : INTEGER;
+                  FIRST_DIVISION   : INTEGER;
-                  NB_SECOND_DESYNC  : INTEGER);
+                  NB_SECOND_DESYNC : INTEGER);
                 PORT (
-                  clk25MHz     : IN  STD_LOGIC;     --! Clock
+                  clk25MHz      : IN  STD_LOGIC;
-                  clk24_576MHz : IN  STD_LOGIC;     --! secondary clock
+                  clk24_576MHz  : IN  STD_LOGIC;
-                  resetn       : IN  STD_LOGIC;     --! Reset
+                  resetn        : IN  STD_LOGIC;
-                  grspw_tick   : IN  STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
+                  grspw_tick    : IN  STD_LOGIC;
-                  apbi         : IN  apb_slv_in_type;   --! APB slave input signals
+                  apbi          : IN  apb_slv_in_type;
-                  apbo         : OUT apb_slv_out_type;  --! APB slave output signals
+                  apbo          : OUT apb_slv_out_type;
-                  coarse_time  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
+                  HK_sample     : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
-                  fine_time    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);   --! fine TIME
+                  HK_val        : IN  STD_LOGIC;
-                  LFR_soft_rstn : OUT STD_LOGIC
+                  HK_sel        : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-                  );
+                  coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  fine_time     : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+                  LFR_soft_rstn : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lfr_time_management
                 GENERIC (
                   FIRST_DIVISION   : INTEGER;
                   NB_SECOND_DESYNC : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   tick            : IN  STD_LOGIC;
                   new_coarsetime  : IN  STD_LOGIC;
                   coarsetime_reg  : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   fine_time       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fine_time_new   : OUT STD_LOGIC;
                   coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   coarse_time_new : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT coarse_time_counter
                 GENERIC (
                   NB_SECOND_DESYNC : INTEGER );
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   tick            : IN  STD_LOGIC;
                   set_TCU         : IN  STD_LOGIC;
                   new_TCU         : IN  STD_LOGIC;
                   set_TCU_value   : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   CT_add1         : IN  STD_LOGIC;
                   fsm_desync      : IN  STD_LOGIC;
                   FT_max          : IN  STD_LOGIC;
                   coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   coarse_time_new : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fine_time_counter
                 GENERIC (
                   WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
                   FIRST_DIVISION : INTEGER );
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   tick           : IN  STD_LOGIC;
                   fsm_transition : IN  STD_LOGIC;
                   FT_max         : OUT STD_LOGIC;
                   FT_half        : OUT STD_LOGIC;
                   FT_wait        : OUT STD_LOGIC;
                   fine_time      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fine_time_new  : OUT STD_LOGIC);
               END COMPONENT;
-            END lpp_lfr_time_management;
+            END lpp_lfr_management;

lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd ~~lib/lpp/lfr_time_management/lpp_lfr_time_management_apbreg_pkg.vhd~~ renamed +9 -6

@@ -1,12 +1,15
1	LIBRARY ieee;	1	LIBRARY ieee;
2	USE ieee.std_logic_1164.ALL;	2	USE ieee.std_logic_1164.ALL;
3	USE ieee.numeric_std.ALL;	3	USE ieee.numeric_std.ALL;
4		4
5	PACKAGE lpp_lfr_~~time_~~management_apbreg_pkg IS	5	PACKAGE lpp_lfr_management_apbreg_pkg IS
6		6
7	CONSTANT ADDR_LFR_TM_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";	7	CONSTANT ADDR_LFR_MANAGMENT_CONTROL : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000000";
8	CONSTANT ADDR_LFR_TM_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";	8	CONSTANT ADDR_LFR_MANAGMENT_TIME_LOAD : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000001";
9	CONSTANT ADDR_LFR_TM_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";	9	CONSTANT ADDR_LFR_MANAGMENT_TIME_COARSE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000010";
10	CONSTANT ADDR_LFR_TM_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";	10	CONSTANT ADDR_LFR_MANAGMENT_TIME_FINE : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000011";
		11	CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_0 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000100";
		12	CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_1 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000101";
		13	CONSTANT ADDR_LFR_MANAGMENT_HK_TEMP_2 : STD_LOGIC_VECTOR(7 DOWNTO 2) := "000110";
11		14
12	END lpp_lfr_~~time_~~management_apbreg_pkg;	15	END lpp_lfr_management_apbreg_pkg;

lib/lpp/lfr_management/vhdlsyn.txt ~~lib/lpp/lfr_time_management/vhdlsyn.txt~~ renamed +3 -3

-            lpp_lfr_time_management.vhd
+            lpp_lfr_management.vhd
-            lpp_lfr_time_management_apbreg_pkg.vhd
+            lpp_lfr_management_apbreg_pkg.vhd
-            apb_lfr_time_management.vhd
+            apb_lfr_management.vhd
             lfr_time_management.vhd
             fine_time_counter.vhd
             coarse_time_counter.vhd

lib/lpp/lpp_leon3_soc/leon3_soc.vhd 0 -1

             -----------------------------------------------------------------------------
             --  LEON3 Demonstration design
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;              -- PLE
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
-            USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             LIBRARY iap;
             USE iap.memctrl.all;
             ENTITY leon3_soc IS
               GENERIC (
                 fabtech : INTEGER := apa3e;
                 memtech : INTEGER := apa3e;
                 padtech : INTEGER := inferred;
                 clktech : INTEGER := inferred;
                 disas   : INTEGER := 0;     -- Enable disassembly to console
                 dbguart : INTEGER := 0;     -- Print UART on console
                 pclow   : INTEGER := 2;
                 --
                 clk_freq : INTEGER := 25000;       --kHz
                 --
                 NB_CPU      : INTEGER := 1;
                 ENABLE_FPU  : INTEGER := 1;
                 FPU_NETLIST : INTEGER := 1;
                 ENABLE_DSU : INTEGER := 1;
                 ENABLE_AHB_UART : INTEGER := 1;
                 ENABLE_APB_UART : INTEGER := 1;
                 ENABLE_IRQMP : INTEGER := 1;
                 ENABLE_GPT : INTEGER := 1;
                 --
                 NB_AHB_MASTER : INTEGER := 1;
                 NB_AHB_SLAVE  : INTEGER := 1;
                 NB_APB_SLAVE  : INTEGER := 1;
                 --
                 ADDRESS_SIZE      : INTEGER := 20;
                 USES_IAP_MEMCTRLR : INTEGER := 0
                 );
               PORT (
                 clk    : IN STD_ULOGIC;
                 reset  : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address     : OUT   STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
                 data        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0   : OUT   STD_LOGIC;
                 nSRAM_BE1   : OUT   STD_LOGIC;
                 nSRAM_BE2   : OUT   STD_LOGIC;
                 nSRAM_BE3   : OUT   STD_LOGIC;
                 nSRAM_WE    : OUT   STD_LOGIC;
                 nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 downto 0);
                 nSRAM_OE    : OUT   STD_LOGIC;
                 nSRAM_READY : IN    STD_LOGIC;
                 SRAM_MBE    : INOUT STD_LOGIC;
                 -- APB --------------------------------------------------------------------
                 apbi_ext    : OUT apb_slv_in_type;
                 apbo_ext    : IN  soc_apb_slv_out_vector(NB_APB_SLAVE-1+5  DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
                 ahbi_s_ext  : OUT ahb_slv_in_type;
                 ahbo_s_ext  : IN  soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3  DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
                 ahbi_m_ext  : OUT AHB_Mst_In_Type;
                 ahbo_m_ext  : IN  soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
                 );
             END;
             ARCHITECTURE Behavioral OF leon3_soc IS
               -----------------------------------------------------------------------------
               -- CONFIG -------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- Clock generator
               constant CFG_CLKMUL : integer := (1);
               constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
               constant CFG_OCLKDIV : integer := (1);
               constant CFG_CLK_NOFB : integer := 0;
               -- LEON3 processor core
               constant CFG_LEON3 : integer := 1;
               constant CFG_NCPU  : integer := NB_CPU;
               constant CFG_NWIN  : integer := (8); -- to be compatible with BCC and RCC
               constant CFG_V8    : integer := 0;
               constant CFG_MAC   : integer := 0;
               constant CFG_SVT    : integer := 0;
               constant CFG_RSTADDR : integer := 16#00000#;
               constant CFG_LDDEL : integer := (1);
               constant CFG_NWP : integer := (0);
               constant CFG_PWD : integer := 1*2;
               constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
               -- 1*(8 + 16 * 0) => grfpu-light
               -- 1*(8 + 16 * 1) => netlist
               -- 0*(8 + 16 * 0) => No FPU
               -- 0*(8 + 16 * 1) => No FPU;
               constant CFG_ICEN : integer := 1;
               constant CFG_ISETS : integer := 1;
               constant CFG_ISETSZ : integer := 4;
               constant CFG_ILINE : integer := 4;
               constant CFG_IREPL : integer := 0;
               constant CFG_ILOCK : integer := 0;
               constant CFG_ILRAMEN : integer := 0;
               constant CFG_ILRAMADDR: integer := 16#8E#;
               constant CFG_ILRAMSZ : integer := 1;
               constant CFG_DCEN : integer := 1;
               constant CFG_DSETS : integer := 1;
               constant CFG_DSETSZ : integer := 4;
               constant CFG_DLINE : integer := 4;
               constant CFG_DREPL : integer := 0;
               constant CFG_DLOCK : integer := 0;
               constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
               constant CFG_DLRAMEN : integer := 0;
               constant CFG_DLRAMADDR: integer := 16#8F#;
               constant CFG_DLRAMSZ : integer := 1;
               constant CFG_MMUEN : integer := 0;
               constant CFG_ITLBNUM : integer := 2;
               constant CFG_DTLBNUM : integer := 2;
               constant CFG_TLB_TYPE : integer := 1 + 0*2;
               constant CFG_TLB_REP : integer := 1;
               constant CFG_DSU : integer := ENABLE_DSU;
               constant CFG_ITBSZ : integer := 0;
               constant CFG_ATBSZ : integer := 0;
               -- AMBA settings
               constant CFG_DEFMST : integer := (0);
               constant CFG_RROBIN : integer := 1;
               constant CFG_SPLIT : integer := 0;
               constant CFG_AHBIO : integer := 16#FFF#;
               constant CFG_APBADDR : integer := 16#800#;
               -- DSU UART
               constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
               -- LEON2 memory controller
               constant CFG_MCTRL_SDEN : integer := 0;
               -- UART 1
               constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
               constant CFG_UART1_FIFO : integer := 1;
               -- LEON3 interrupt controller
               constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
               -- Modular timer
               constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
               constant CFG_GPT_NTIM : integer := (2);
               constant CFG_GPT_SW : integer := (8);
               constant CFG_GPT_TW : integer := (32);
               constant CFG_GPT_IRQ : integer := (8);
               constant CFG_GPT_SEPIRQ : integer := 1;
               constant CFG_GPT_WDOGEN : integer := 0;
               constant CFG_GPT_WDOG : integer := 16#0#;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SIGNALs
               -----------------------------------------------------------------------------
               CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
               -- CLK & RST --
               SIGNAL clk2x      : STD_ULOGIC;
               SIGNAL clkmn       : STD_ULOGIC;
               SIGNAL clkm       : STD_ULOGIC;
               SIGNAL rstn       : STD_ULOGIC;
               SIGNAL rstraw     : STD_ULOGIC;
               SIGNAL pciclk     : STD_ULOGIC;
               SIGNAL sdclkl     : STD_ULOGIC;
               SIGNAL cgi        : clkgen_in_type;
               SIGNAL cgo        : clkgen_out_type;
               --- AHB / APB
               SIGNAL apbi       : apb_slv_in_type;
               SIGNAL apbo       : apb_slv_out_vector := (OTHERS => apb_none);
               SIGNAL ahbsi      : ahb_slv_in_type;
               SIGNAL ahbso      : ahb_slv_out_vector := (OTHERS => ahbs_none);
               SIGNAL ahbmi      : ahb_mst_in_type;
               SIGNAL ahbmo      : ahb_mst_out_vector := (OTHERS => ahbm_none);
               --UART
               SIGNAL ahbuarti   : uart_in_type;
               SIGNAL ahbuarto   : uart_out_type;
               SIGNAL apbuarti   : uart_in_type;
               SIGNAL apbuarto   : uart_out_type;
               --MEM CTRLR
               SIGNAL memi       : memory_in_type;
               SIGNAL memo       : memory_out_type;
               SIGNAL wpo        : wprot_out_type;
               SIGNAL sdo        : sdram_out_type;
               SIGNAl mbe        : std_logic;        -- enable memory programming
               SIGNAL mbe_drive  : std_logic;       -- drive the MBE memory signal
               SIGNAL nSRAM_CE_s  : STD_LOGIC_VECTOR(1 downto 0);
               SIGNAL nSRAM_OE_s    : STD_LOGIC;
               --IRQ
               SIGNAL irqi       : irq_in_vector(0 TO CFG_NCPU-1);
               SIGNAL irqo       : irq_out_vector(0 TO CFG_NCPU-1);
               --Timer
               SIGNAL gpti       : gptimer_in_type;
               SIGNAL gpto       : gptimer_out_type;
               --DSU
               SIGNAL dbgi       : l3_debug_in_vector(0 TO CFG_NCPU-1);
               SIGNAL dbgo       : l3_debug_out_vector(0 TO CFG_NCPU-1);
               SIGNAL dsui       : dsu_in_type;
               SIGNAL dsuo       : dsu_out_type;
               -----------------------------------------------------------------------------
             BEGIN
             ----------------------------------------------------------------------
             ---  Reset and Clock generation  -------------------------------------
             ----------------------------------------------------------------------
               cgi.pllctrl <= "00";
               cgi.pllrst  <= rstraw;
               rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
               clkgen0 : clkgen                      -- clock generator
                 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
                              CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
                 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
             ----------------------------------------------------------------------
             ---  LEON3 processor / DSU / IRQ  ------------------------------------
             ----------------------------------------------------------------------
               l3 : IF CFG_LEON3 = 1 GENERATE
                 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   u0 : leon3s                       -- LEON3 processor
                     GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
 , CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
                                  CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
                                  CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
                                  CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
                                  CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
                     PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
                               irqi(i), irqo(i), dbgi(i), dbgo(i));
                 END GENERATE;
                 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
                 dsugen : IF CFG_DSU = 1 GENERATE
                   dsu0 : dsu3                       -- LEON3 Debug Support Unit
                     GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
                                  ncpu   => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
                     PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
                   dsui.enable <= '1';
                   dsui.break  <= '0';
                 END GENERATE;
               END GENERATE;
               nodsu : IF CFG_DSU = 0 GENERATE
                 ahbso(2) <= ahbs_none;
                 dsuo.tstop <= '0';
                 dsuo.active <= '0';
               END GENERATE;
               irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
                 irqctrl0 : irqmp                    -- interrupt controller
                   GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
                   PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
               END GENERATE;
               irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
                 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   irqi(i).irl <= "0000";
                 END GENERATE;
                 apbo(2) <= apb_none;
               END GENERATE;
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
             ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
               memctrlr : mctrl GENERIC MAP (
                 hindex  => 0,
                 pindex  => 0,
                 paddr   => 0,
                 srbanks => 1
                 )
                 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
                memi.bexcn  <= '1';
                memi.brdyn  <= '1';
               nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0));
               nSRAM_OE_s <= memo.ramoen(0);
             END GENERATE;
             IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
               memctrlr : srctrle_0ws
               GENERIC MAP(
                 hindex  => 0,
                 pindex  => 0,
                 paddr   => 0,
                 srbanks => 2,
                 banksz  => 8, --512k * 32
                 rmw     => 1,
                 --Aeroflex memory generics:
                 mprog   => 1,   -- program memory by default values after reset
                 mpsrate => 12,  -- default scrub rate period
                 mpb2s   => 4,   -- default busy to scrub delay
                 mpapb   => 1,   -- instantiate apb register
                 mchipcnt => 2,
                 mpenall => 1    -- when 0 program only E1 chip, else program all dies
               )
               PORT MAP (
                 rst     => rstn,
                 clk     => clkm,
                 ahbsi   => ahbsi,
                 ahbso   => ahbso(0),
                 apbi    => apbi,
                 apbo    => apbo(0),
                 sri     => memi,
                 sro     => memo,
                 --Aeroflex memory signals:
                 ucerr   => open,        -- uncorrectable error signal
                 mbe     => mbe,        -- enable memory programming
                 mbe_drive => mbe_drive      -- drive the MBE memory signal
               );
               memi.brdyn  <= nSRAM_READY;
               mbe_pad : iopad
               GENERIC MAP(tech => padtech)
               PORT MAP(pad => SRAM_MBE,
                        i   => mbe,
                        en  => mbe_drive,
                        o   => memi.bexcn );
               nSRAM_CE_s <= (memo.ramsn(1 downto 0));
               nSRAM_OE_s <= memo.oen;
             END GENERATE;
               memi.writen <= '1';
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
               bdr : FOR i IN 0 TO 3 GENERATE
                 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
                     memo.data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
                     memi.data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
               addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
                 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
               rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
               oen_pad  : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
               nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
               nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
               nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
               nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
               nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
                              rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
                              ioen    => 0, nahbm => maxahbmsp, nahbs => 8)
                 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : IF CFG_AHB_UART = 1 GENERATE
                 dcom0 : ahbuart
                   GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
                   PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
                 dsurx_pad : inpad GENERIC MAP (tech  => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
                 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
               END GENERATE;
               nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl                        -- AHB/APB bridge
                 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
                 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
             ----------------------------------------------------------------------
             ---  GPT Timer  ------------------------------------------------------
             ----------------------------------------------------------------------
               gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
                 timer0 : gptimer                    -- timer unit
                   GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
                                sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
                                nbits  => CFG_GPT_TW)
                   PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
                 gpti.dhalt  <= dsuo.tstop;
                 gpti.extclk <= '0';
               END GENERATE;
               notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
                 uart1 : apbuart                     -- UART 1
                   GENERIC MAP (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
                                fifosize => CFG_UART1_FIFO)
                   PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd    <= urxd1;
                 apbuarti.extclk <= '0';
                 utxd1           <= apbuarto.txd;
                 apbuarti.ctsn   <= '0';
               END GENERATE;
               noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
             -------------------------------------------------------------------------------
             -- AMBA BUS -------------------------------------------------------------------
             -------------------------------------------------------------------------------
               -- APB --------------------------------------------------------------------
               apbi_ext   <= apbi;
               all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
                 max_16_apb: IF I + 5 < 16 GENERATE
                   apbo(I+5)<= apbo_ext(I+5);
                 END GENERATE max_16_apb;
               END GENERATE all_apb;
               -- AHB_Slave --------------------------------------------------------------
               ahbi_s_ext <= ahbsi;
               all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
                 max_16_ahbs: IF I + 3 < 16 GENERATE
                   ahbso(I+3) <= ahbo_s_ext(I+3);
                 END GENERATE max_16_ahbs;
               END GENERATE all_ahbs;
               -- AHB_Master -------------------------------------------------------------
               ahbi_m_ext <= ahbmi;
               all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
                 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
                   ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
                 END GENERATE max_16_ahbm;
               END GENERATE all_ahbm;
             END Behavioral;

lib/lpp/lpp_leon3_soc/leon3ft_soc.vhd +487 -488

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	@@ -1,488 +1,487
	1	-----------------------------------------------------------------------------	1	-----------------------------------------------------------------------------
	2	-- LEON3 Demonstration design	2	-- LEON3 Demonstration design
	3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research	3	-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
	4	--	4	--
	5	-- This program is free software; you can redistribute it and/or modify	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 2 of the License, or	7	-- the Free Software Foundation; either version 2 of the License, or
	8	-- (at your option) any later version.	8	-- (at your option) any later version.
	9	--	9	--
	10	-- This program is distributed in the hope that it will be useful,	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.	13	-- GNU General Public License for more details.
	14	--	14	--
	15	-- You should have received a copy of the GNU General Public License	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	------------------------------------------------------------------------------	18	------------------------------------------------------------------------------
	19		19
	20		20
	21	LIBRARY ieee;	21	LIBRARY ieee;
	22	USE ieee.std_logic_1164.ALL;	22	USE ieee.std_logic_1164.ALL;
	23	LIBRARY grlib;	23	LIBRARY grlib;
	24	USE grlib.amba.ALL;	24	USE grlib.amba.ALL;
	25	USE grlib.stdlib.ALL;	25	USE grlib.stdlib.ALL;
	26	LIBRARY techmap;	26	LIBRARY techmap;
	27	USE techmap.gencomp.ALL;	27	USE techmap.gencomp.ALL;
	28	LIBRARY gaisler;	28	LIBRARY gaisler;
	29	USE gaisler.memctrl.ALL;	29	USE gaisler.memctrl.ALL;
	30	USE gaisler.leon3.ALL;	30	USE gaisler.leon3.ALL;
	31	USE gaisler.uart.ALL;	31	USE gaisler.uart.ALL;
	32	USE gaisler.misc.ALL;	32	USE gaisler.misc.ALL;
	33	USE gaisler.spacewire.ALL; -- PLE	33	USE gaisler.spacewire.ALL; -- PLE
	34	LIBRARY esa;	34	LIBRARY esa;
	35	USE esa.memoryctrl.ALL;	35	USE esa.memoryctrl.ALL;
	36	LIBRARY lpp;	36	LIBRARY lpp;
	37	USE lpp.lpp_memory.ALL;	37	USE lpp.lpp_memory.ALL;
	38	USE lpp.lpp_ad_conv.ALL;	38	USE lpp.lpp_ad_conv.ALL;
	39	USE lpp.lpp_lfr_pkg.ALL;	39	USE lpp.lpp_lfr_pkg.ALL;
	40	USE lpp.iir_filter.ALL;	40	USE lpp.iir_filter.ALL;
	41	USE lpp.general_purpose.ALL;	41	USE lpp.general_purpose.ALL;
	42	USE lpp.lpp_l~~fr_time_management~~.ALL;	42	USE lpp.lpp_leon3_soc_pkg.ALL;
	43	USE lpp.lpp_leon3_soc_pkg.ALL;	43
	44		44	ENTITY leon3ft_soc IS
	45	ENTITY leon3ft_soc IS	45	GENERIC (
	46	GENERIC (	46	fabtech : INTEGER := apa3e;
	47	~~fab~~tech : INTEGER := apa3e;	47	memtech : INTEGER := apa3e;
	48	~~mem~~tech : INTEGER := ~~apa3e~~;	48	padtech : INTEGER := inferred;
	49	~~pad~~tech : INTEGER := inferred;	49	clktech : INTEGER := inferred;
	50	clktech : INTEGER := inferred;	50	disas : INTEGER := 0; -- Enable disassembly to console
	51	d~~isas~~ : INTEGER := 0; -- ~~Enable disassembly to~~ console	51	dbguart : INTEGER := 0; -- Print UART on console
	52	dbguart : INTEGER := 0; -- Print UART on console	52	pclow : INTEGER := 2;
	53	pclow : INTEGER := 2;	53	--
	54	--	54	clk_freq : INTEGER := 25000; --kHz
	55	clk_freq : INTEGER := 25000; --kHz	55	--
	56	--	56	NB_CPU : INTEGER := 1;
	57	~~NB_CPU~~ : INTEGER := 1;	57	ENABLE_FPU : INTEGER := 1;
	58	~~ENABLE_FPU~~ : INTEGER := 1;	58	FPU_NETLIST : INTEGER := 1;
	59	~~FPU_NETLIST~~ : INTEGER := 1;	59	ENABLE_DSU : INTEGER := 1;
	60	ENABLE_~~DSU~~ : INTEGER := 1;	60	ENABLE_AHB_UART : INTEGER := 1;
	61	ENABLE_AHB_UART : INTEGER := 1;	61	ENABLE_APB_UART : INTEGER := 1;
	62	ENABLE_~~APB_UART~~ : INTEGER := 1;	62	ENABLE_IRQMP : INTEGER := 1;
	63	ENABLE_~~IRQMP~~ : INTEGER := 1;	63	ENABLE_GPT : INTEGER := 1;
	64	ENABLE_GPT : INTEGER := 1;	64	--
	65	--	65	NB_AHB_MASTER : INTEGER := 11;
	66	NB_AHB_~~MASTER~~ : INTEGER := 11;	66	NB_AHB_SLAVE : INTEGER := 1;
	67	NB_AHB_SLAVE : INTEGER := 1;	67	NB_APB_SLAVE : INTEGER := 2
	68	NB_APB_SLAVE : INTEGER := 2	68	);
	69	);	69	PORT (
	70	PORT (	70	clk : IN STD_ULOGIC;
	71	~~clk~~ : IN STD_ULOGIC;	71	reset : IN STD_ULOGIC;
	72	reset : IN STD_ULOGIC;	72
	73		73	errorn : OUT STD_ULOGIC;
	74	errorn : OUT STD_ULOGIC;	74
	75		75	-- UART AHB ---------------------------------------------------------------
	76	-- UART AHB ---------------------------------------------------------------	76	ahbrxd : IN STD_ULOGIC; -- DSU rx data
	77	ahbrxd : IN STD_ULOGIC; -- DSU rx data	77	ahbtxd : OUT STD_ULOGIC; -- DSU tx data
	78	ahbtxd : OUT STD_ULOGIC; -- DSU tx data	78
	79		79	-- UART APB ---------------------------------------------------------------
	80	-- UART APB ---------------------------------------------------------------	80	urxd1 : IN STD_ULOGIC; -- UART1 rx data
	81	urxd1 : IN STD_ULOGIC; -- UART1 rx data	81	utxd1 : OUT STD_ULOGIC; -- UART1 tx data
	82	utxd1 : OUT STD_ULOGIC; -- UART1 tx data	82
	83		83	-- RAM --------------------------------------------------------------------
	84	-- RAM --------------------------------------------------------------------	84	address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
	85	~~address~~ : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);	85	data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
	86	data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);	86	nSRAM_BE0 : OUT STD_LOGIC;
	87	nSRAM_BE0 : OUT STD_LOGIC;	87	nSRAM_BE1 : OUT STD_LOGIC;
	88	nSRAM_BE1 : OUT STD_LOGIC;	88	nSRAM_BE2 : OUT STD_LOGIC;
	89	nSRAM_BE2 : OUT STD_LOGIC;	89	nSRAM_BE3 : OUT STD_LOGIC;
	90	nSRAM_~~BE3~~ : OUT STD_LOGIC;	90	nSRAM_WE : OUT STD_LOGIC;
	91	nSRAM_WE : OUT STD_LOGIC;	91	nSRAM_CE : OUT STD_LOGIC;
	92	nSRAM_CE : OUT STD_LOGIC;	92	nSRAM_OE : OUT STD_LOGIC;
	93	nSRAM_OE : OUT STD_LOGIC;	93
	94		94	-- APB --------------------------------------------------------------------
	95	-- APB --------------------------------------------------------------------	95	apbi_ext : OUT apb_slv_in_type;
	96	apbi_ext : OUT apb_slv_in_type;	96	apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
	97	apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);	97	-- AHB_Slave --------------------------------------------------------------
	98	-- AHB_Slave --------------------------------------------------------------	98	ahbi_s_ext : OUT ahb_slv_in_type;
	99	ahbi_s_ext : OUT ahb_slv_in_type;	99	ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
	100	ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);	100	-- AHB_Master -------------------------------------------------------------
	101	-- AHB_Master -------------------------------------------------------------	101	ahbi_m_ext : OUT AHB_Mst_In_Type;
	102	ahbi_m_ext : OUT AHB_Mst_In_Type;	102	ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
	103	ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)	103
	104		104	);
	105	);	105	END;
	106	END;	106
	107		107	ARCHITECTURE Behavioral OF leon3ft_soc IS
	108	ARCHITECTURE Behavioral OF leon3ft_soc IS	108
	109		109	-----------------------------------------------------------------------------
	110	--~~--------~~-------------------------------------------------------------------	110	-- CONFIG -------------------------------------------------------------------
	111	-- ~~CONFIG~~ -------------------------------------------------------------------	111	-----------------------------------------------------------------------------
	112	-----------------------------------------------------------------------------	112
	113		113	-- Clock generator
	114	-- Clock generator	114	CONSTANT CFG_CLKMUL : INTEGER := (1);
	115	CONSTANT CFG_CLK~~MUL~~ : INTEGER := (1);	115	CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
	116	CONSTANT CFG_CLKDIV : INTEGER := (1); ~~-- divide 50MHz by 2 to get 25MHz~~	116	CONSTANT CFG_OCLKDIV : INTEGER := (1);
	117	CONSTANT CFG_~~OCLKDIV~~ : INTEGER := (1);	117	CONSTANT CFG_CLK_NOFB : INTEGER := 0;
	118	CONSTANT CFG_CLK_NOFB : INTEGER := 0;	118	-- LEON3 processor core
	119	-- LEON3 processor core	119	CONSTANT CFG_LEON3 : INTEGER := 1;
	120	CONSTANT CFG_~~LEON3~~ : INTEGER := 1;	120	CONSTANT CFG_NCPU : INTEGER := NB_CPU;
	121	CONSTANT CFG_NCPU : INTEGER := NB_CPU;	121	CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
	122	CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC	122	CONSTANT CFG_V8 : INTEGER := 0;
	123	CONSTANT CFG_V8 : INTEGER := 0;	123	CONSTANT CFG_MAC : INTEGER := 0;
	124	CONSTANT CFG_~~MAC~~ : INTEGER := 0;	124	CONSTANT CFG_SVT : INTEGER := 0;
	125	CONSTANT CFG_~~SVT~~ : INTEGER := 0;	125	CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
	126	CONSTANT CFG_~~RSTADDR~~ : INTEGER := ~~16#00000#~~;	126	CONSTANT CFG_LDDEL : INTEGER := (1);
	127	CONSTANT CFG_~~LDDEL~~ : INTEGER := (1);	127	CONSTANT CFG_NWP : INTEGER := (0);
	128	CONSTANT CFG_NWP : INTEGER := (0);	128	CONSTANT CFG_PWD : INTEGER := 1*2;
	129	CONSTANT CFG_~~PWD~~ : INTEGER := 1*2;	129	CONSTANT CFG_FPU : INTEGER := ENABLE_FPU (8 + 16 FPU_NETLIST);
	130	CONSTANT CFG_FPU : INTEGER := ENABLE_FPU (8 + 16 FPU_NETLIST);	130	-- 1(8 + 16 0) => grfpu-light
	131	-- 1(8 + 16 ~~0) => grfpu-ligh~~t	131	-- 1(8 + 16 1) => netlist
	132	-- 1(8 + 16 ~~1) => netlist~~	132	-- 0(8 + 16 0) => No FPU
	133	-- 0(8 + 16 0) => No FPU	133	-- 0(8 + 16 1) => No FPU;
	134	-- 0(8 + 16 1) => No FPU;	134	CONSTANT CFG_ICEN : INTEGER := 1;
	135	CONSTANT CFG_I~~CEN~~ : INTEGER := 1;	135	CONSTANT CFG_ISETS : INTEGER := 1;
	136	CONSTANT CFG_ISETS : INTEGER := 1;	136	CONSTANT CFG_ISETSZ : INTEGER := 4;
	137	CONSTANT CFG_I~~SETSZ~~ : INTEGER := 4;	137	CONSTANT CFG_ILINE : INTEGER := 4;
	138	CONSTANT CFG_I~~LINE~~ : INTEGER := 4;	138	CONSTANT CFG_IREPL : INTEGER := 0;
	139	CONSTANT CFG_I~~REP~~L : INTEGER := 0;	139	CONSTANT CFG_ILOCK : INTEGER := 0;
	140	CONSTANT CFG_IL~~OCK~~ : INTEGER := 0;	140	CONSTANT CFG_ILRAMEN : INTEGER := 0;
	141	CONSTANT CFG_ILRAMEN : INTEGER := 0;	141	CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
	142	CONSTANT CFG_ILRAM~~ADDR~~ : INTEGER := 1~~6#8E#~~;	142	CONSTANT CFG_ILRAMSZ : INTEGER := 1;
	143	CONSTANT CFG_~~ILRAMSZ~~ : INTEGER := 1;	143	CONSTANT CFG_DCEN : INTEGER := 1;
	144	CONSTANT CFG_D~~CEN~~ : INTEGER := 1;	144	CONSTANT CFG_DSETS : INTEGER := 1;
	145	CONSTANT CFG_DSETS : INTEGER := 1;	145	CONSTANT CFG_DSETSZ : INTEGER := 4;
	146	CONSTANT CFG_D~~SETSZ~~ : INTEGER := 4;	146	CONSTANT CFG_DLINE : INTEGER := 4;
	147	CONSTANT CFG_D~~LINE~~ : INTEGER := 4;	147	CONSTANT CFG_DREPL : INTEGER := 0;
	148	CONSTANT CFG_D~~REP~~L : INTEGER := 0;	148	CONSTANT CFG_DLOCK : INTEGER := 0;
	149	CONSTANT CFG_D~~LOCK~~ : INTEGER := 0;	149	CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
	150	CONSTANT CFG_D~~SNOOP~~ : INTEGER := 0 + 0 + 4*0;	150	CONSTANT CFG_DLRAMEN : INTEGER := 0;
	151	CONSTANT CFG_DLRAMEN : INTEGER := 0;	151	CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
	152	CONSTANT CFG_DLRAM~~ADDR~~ : INTEGER := 1~~6#8F#~~;	152	CONSTANT CFG_DLRAMSZ : INTEGER := 1;
	153	CONSTANT CFG_~~DLRAMSZ~~ : INTEGER := 1;	153	CONSTANT CFG_MMUEN : INTEGER := 0;
	154	CONSTANT CFG_~~MMUEN~~ : INTEGER := 0;	154	CONSTANT CFG_ITLBNUM : INTEGER := 2;
	155	CONSTANT CFG_ITLBNUM : INTEGER := 2;	155	CONSTANT CFG_DTLBNUM : INTEGER := 2;
	156	CONSTANT CFG_~~DTLBNUM~~ : INTEGER := 2;	156	CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
	157	CONSTANT CFG_TLB_~~TYPE~~ : INTEGER := 1 + 0*2;	157	CONSTANT CFG_TLB_REP : INTEGER := 1;
	158	CONSTANT CFG_TLB_REP : INTEGER := 1;	158
	159		159	CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
	160	CONSTANT CFG_~~DSU~~ : INTEGER := ~~ENABLE_DSU~~;	160	CONSTANT CFG_ITBSZ : INTEGER := 0;
	161	CONSTANT CFG_ITBSZ : INTEGER := 0;	161	CONSTANT CFG_ATBSZ : INTEGER := 0;
	162	CONSTANT CFG_ATBSZ : INTEGER := 0;	162
	163		163	-- AMBA settings
	164	-- AMBA settings	164	CONSTANT CFG_DEFMST : INTEGER := (0);
	165	CONSTANT CFG_~~DEFMST~~ : INTEGER := (0);	165	CONSTANT CFG_RROBIN : INTEGER := 1;
	166	CONSTANT CFG_~~RROBIN~~ : INTEGER := 1;	166	CONSTANT CFG_SPLIT : INTEGER := 0;
	167	CONSTANT CFG_~~SPLIT~~ : INTEGER := 0;	167	CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
	168	CONSTANT CFG_A~~HBIO~~ : INTEGER := 16#~~FFF~~#;	168	CONSTANT CFG_APBADDR : INTEGER := 16#800#;
	169	CONSTANT CFG_APBADDR : INTEGER := 16#800#;	169
	170		170	-- DSU UART
	171	-- DSU UART	171	CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
	172	CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;	172
	173		173	-- LEON2 memory controller
	174	-- LEON2 memory controller	174	CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
	175	CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;	175
	176		176	-- UART 1
	177	-- UART 1	177	CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
	178	CONSTANT CFG_UART1_~~ENABLE~~ : INTEGER := ~~ENABLE_APB_UART~~;	178	CONSTANT CFG_UART1_FIFO : INTEGER := 1;
	179	CONSTANT CFG_UART1_FIFO : INTEGER := 1;	179
	180		180	-- LEON3 interrupt controller
	181	-- LEON3 interrupt controller	181	CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
	182	CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;	182
	183		183	-- Modular timer
	184	-- Modular timer	184	CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
	185	CONSTANT CFG_GPT_~~ENABLE~~ : INTEGER := ~~ENABLE_GPT~~;	185	CONSTANT CFG_GPT_NTIM : INTEGER := (2);
	186	CONSTANT CFG_GPT_~~NTIM~~ : INTEGER := (2);	186	CONSTANT CFG_GPT_SW : INTEGER := (8);
	187	CONSTANT CFG_GPT_SW : INTEGER := (8);	187	CONSTANT CFG_GPT_TW : INTEGER := (32);
	188	CONSTANT CFG_GPT_TW : INTEGER := (32);	188	CONSTANT CFG_GPT_IRQ : INTEGER := (8);
	189	CONSTANT CFG_GPT_IRQ : INTEGER := (8);	189	CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
	190	CONSTANT CFG_GPT_~~SEPIRQ~~ : INTEGER := 1;	190	CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
	191	CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;	191	CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
	192	CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;	192	-----------------------------------------------------------------------------
	193	-----------------------------------------------------------------------------	193
	194		194	-----------------------------------------------------------------------------
	195	-----------------------------------------------------------------------------	195	-- SIGNALs
	196	-- SIGNALs	196	-----------------------------------------------------------------------------
	197	-----------------------------------------------------------------------------	197	CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
	198	CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;	198	-- CLK & RST --
	199	-- CLK & RST --	199	SIGNAL clk2x : STD_ULOGIC;
	200	SIGNAL clk2x : STD_ULOGIC;	200	SIGNAL clkmn : STD_ULOGIC;
	201	SIGNAL clkmn : STD_ULOGIC;	201	SIGNAL clkm : STD_ULOGIC;
	202	SIGNAL ~~clkm~~ : STD_ULOGIC;	202	SIGNAL rstn : STD_ULOGIC;
	203	SIGNAL rstn : STD_ULOGIC;	203	SIGNAL rstraw : STD_ULOGIC;
	204	SIGNAL ~~rstraw~~ : STD_ULOGIC;	204	SIGNAL pciclk : STD_ULOGIC;
	205	SIGNAL ~~pciclk~~ : STD_ULOGIC;	205	SIGNAL sdclkl : STD_ULOGIC;
	206	SIGNAL sdclkl : STD_ULOGIC;	206	SIGNAL cgi : clkgen_in_type;
	207	SIGNAL cgi : clkgen_in_type;	207	SIGNAL cgo : clkgen_out_type;
	208	SIGNAL cgo : clkgen_out_type;	208	--- AHB / APB
	209	--- AHB / APB	209	SIGNAL apbi : apb_slv_in_type;
	210	SIGNAL apbi : apb_slv_~~in_type~~;	210	SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
	211	SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);	211	SIGNAL ahbsi : ahb_slv_in_type;
	212	SIGNAL ahbsi : ahb_slv_~~in_type~~;	212	SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
	213	SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);	213	SIGNAL ahbmi : ahb_mst_in_type;
	214	SIGNAL ahbmi : ahb_mst_~~in_type~~;	214	SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
	215	SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);	215	--UART
	216	--UART	216	SIGNAL ahbuarti : uart_in_type;
	217	SIGNAL ahbuarti : uart_in_type;	217	SIGNAL ahbuarto : uart_out_type;
	218	SIGNAL a~~hbuarto~~ : uart_~~out~~_type;	218	SIGNAL apbuarti : uart_in_type;
	219	SIGNAL apbuarti : uart_in_type;	219	SIGNAL apbuarto : uart_out_type;
	220	SIGNAL apbuarto : uart_out_type;	220	--MEM CTRLR
	221	--MEM CTRLR	221	SIGNAL memi : memory_in_type;
	222	SIGNAL memi : memory_in_type;	222	SIGNAL memo : memory_out_type;
	223	SIGNAL ~~memo~~ : ~~memory~~_out_type;	223	SIGNAL wpo : wprot_out_type;
	224	SIGNAL wpo : ~~wprot~~_out_type;	224	SIGNAL sdo : sdram_out_type;
	225	SIGNAL sdo : sdram_out_type;	225	--IRQ
	226	--IRQ	226	SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
	227	SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);	227	SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
	228	SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);	228	--Timer
	229	--Timer	229	SIGNAL gpti : gptimer_in_type;
	230	SIGNAL gpti : gptimer_in_type;	230	SIGNAL gpto : gptimer_out_type;
	231	SIGNAL gpto : gptimer_out_type;	231	--DSU
	232	--DSU	232	SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
	233	SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);	233	SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
	234	SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);	234	SIGNAL dsui : dsu_in_type;
	235	SIGNAL dsui : dsu_in_type;	235	SIGNAL dsuo : dsu_out_type;
	236	SIGNAL dsuo : dsu_out_type;	236	-----------------------------------------------------------------------------
	237	-----------------------------------------------------------------------------	237
	238		238	SIGNAL nSRAM_CE_s : STD_LOGIC;
	239	SIGNAL nSRAM_CE_s : STD_LOGIC;	239	BEGIN
	240	BEGIN	240
	241		241
	242		242	----------------------------------------------------------------------
	243	----------------------------------------------------------------------	243	--- Reset and Clock generation -------------------------------------
	244	--- Reset and Clock generation -------------------------------------	244	----------------------------------------------------------------------
	245	----------------------------------------------------------------------	245
	246		246	cgi.pllctrl <= "00";
	247	cgi.pll~~ctrl~~ <= ~~"00"~~;	247	cgi.pllrst <= rstraw;
	248	cgi.pllrst <= rstraw;	248
	249		249	rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
	250	rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);	250
	251		251	clkgen0 : clkgen -- clock generator
	252	clkgen0 : clkgen -- clock generator	252	GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
	253	GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,	253	CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
	254	CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)	254	PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
	255	PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);	255
	256		256	----------------------------------------------------------------------
	257	----------------------------------------------------------------------	257	--- LEON3 processor / DSU / IRQ ------------------------------------
	258	--- LEON3 processor / DSU / IRQ ------------------------------------	258	----------------------------------------------------------------------
	259	----------------------------------------------------------------------	259
	260		260	l3 : IF CFG_LEON3 = 1 GENERATE
	261	l3 : IF CFG_LEON3 = 1 GENERATE	261	cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
	262	cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE	262	u0 : leon3ft
	263	u0 : leon3ft	263	GENERIC MAP (
	264	GENERIC MAP (	264	hindex => i, --: integer;
	265	hindex => i, --: integer;	265	fabtech => fabtech,
	266	~~fab~~tech => ~~fab~~tech,	266	memtech => memtech,
	267	memtech => memtech,	267	nwindows => CFG_NWIN,
	268	~~nwin~~dows => CFG_~~NWIN~~,	268	dsu => CFG_DSU,
	269	dsu => CFG_DSU,	269	fpu => CFG_FPU,
	270	~~fpu~~ => CFG_~~FPU~~,	270	v8 => CFG_V8,
	271	v8 => ~~CFG_V8~~,	271	cp => 0,
	272	cp => 0,	272	mac => CFG_MAC,
	273	~~mac~~ => ~~CFG_MAC~~,	273	pclow => pclow,
	274	~~pclow~~ => ~~pclow~~,	274	notag => 0,
	275	n~~otag~~ => 0,	275	nwp => CFG_NWP,
	276	nwp => CFG_NWP,	276	icen => CFG_ICEN,
	277	i~~cen~~ => CFG_I~~CEN~~,	277	irepl => CFG_IREPL,
	278	i~~repl~~ => CFG_I~~REPL~~,	278	isets => CFG_ISETS,
	279	i~~sets~~ => CFG_I~~SETS~~,	279	ilinesize => CFG_ILINE,
	280	i~~linesize~~ => CFG_I~~LINE~~,	280	isetsize => CFG_ISETSZ,
	281	iset~~size~~ => CFG_I~~SETSZ~~,	281	isetlock => CFG_ILOCK,
	282	~~isetlock~~ => CFG_~~ILOCK~~,	282	dcen => CFG_DCEN,
	283	d~~cen~~ => CFG_D~~CEN~~,	283	drepl => CFG_DREPL,
	284	d~~repl~~ => CFG_D~~REPL~~,	284	dsets => CFG_DSETS,
	285	d~~sets~~ => CFG_D~~SETS~~,	285	dlinesize => CFG_DLINE,
	286	d~~linesize~~ => CFG_D~~LINE~~,	286	dsetsize => CFG_DSETSZ,
	287	dset~~size~~ => CFG_D~~SETSZ~~,	287	dsetlock => CFG_DLOCK,
	288	ds~~etlock~~ => CFG_D~~LOCK~~,	288	dsnoop => CFG_DSNOOP,
	289	~~dsnoop~~ => CFG_~~DSNOOP~~,	289	ilram => CFG_ILRAMEN,
	290	ilram => CFG_ILRAMEN,	290	ilramsize => CFG_ILRAMSZ,
	291	ilrams~~ize~~ => CFG_ILRAMSZ,	291	ilramstart => CFG_ILRAMADDR,
	292	~~ilramstart~~ => CFG_~~ILRAMADDR~~,	292	dlram => CFG_DLRAMEN,
	293	dlram => CFG_DLRAMEN,	293	dlramsize => CFG_DLRAMSZ,
	294	dlrams~~ize~~ => CFG_DLRAMSZ,	294	dlramstart => CFG_DLRAMADDR,
	295	dlramstart => CFG_DLRAMADDR,	295	mmuen => CFG_MMUEN,
	296	~~mmuen~~ => CFG_~~MMUEN~~,	296	itlbnum => CFG_ITLBNUM,
	297	itlbnum => CFG_ITLBNUM,	297	dtlbnum => CFG_DTLBNUM,
	298	~~dtlbnum~~ => CFG_~~DTLBNUM~~,	298	tlb_type => CFG_TLB_TYPE,
	299	tlb_~~type~~ => CFG_TLB_~~TYPE~~,	299	tlb_rep => CFG_TLB_REP,
	300	~~tlb_rep~~ => CFG_~~TLB_REP~~,	300	lddel => CFG_LDDEL,
	301	~~lddel~~ => ~~CFG_LDDEL~~,	301	disas => disas,
	302	~~disas~~ => ~~disas~~,	302	tbuf => CFG_ITBSZ,
	303	~~tbuf~~ => CFG_~~ITBSZ~~,	303	pwd => CFG_PWD,
	304	~~pwd~~ => CFG_~~PWD~~,	304	svt => CFG_SVT,
	305	~~svt~~ => CFG_SVT,	305	rstaddr => CFG_RSTADDR,
	306	~~rstaddr~~ => CFG_~~RSTADDR~~,	306	smp => CFG_NCPU-1,
	307	smp => CFG_NCPU-1,	307	iuft => 2, --: integer range 0 to 4;
	308	iuft => 2, --: integer range 0 to 4;	308	fpft => 1, --: integer range 0 to 4;
	309	fpft => 1, --: integer range 0 to 4;	309	cmft => 1, --: integer range 0 to 1;
	310	~~cmft~~ => 1, --: integer ~~range 0 to 1~~;	310	iuinj => 0, --: integer;
	311	iuinj => 0, --: integer;	311	ceinj => 0, --: integer range 0 to 3;
	312	c~~einj~~ => 0, --: integer ~~range 0 to 3~~;	312	cached => 0, --: integer;
	313	~~cached~~ => 0, --: integer;	313	netlist => 0, --: integer;
	314	~~netlist~~ => 0, --: integer;	314	scantest => 0, --: integer;
	315	~~scantest~~ => 0, --: integer;	315	mmupgsz => 0, --: integer range 0 to 5;
	316	~~mmupgsz~~ => 0, --: integer ~~range 0 to 5;~~	316	bp => 1) --: integer);
	317	bp => 1) --: integer);	317	PORT MAP (
	318	PORT MAP (	318	clk => clkm,
	319	~~clk~~ => ~~clkm~~,	319	rstn => rstn,
	320	~~rstn~~ => ~~rstn~~,	320	ahbi => ahbmi,
	321	ahbi => ahbmi,	321	ahbo => ahbmo(i),
	322	ahbo => ahbmo(i),	322	ahbsi => ahbsi,
	323	ahbsi => ahbsi,	323	ahbso => ahbso,
	324	ahbso => ahbso,	324	irqi => irqi(i),
	325	irqi => irqi(i),	325	irqo => irqo(i),
	326	i~~rqo~~ => i~~rqo~~(i),	326	dbgi => dbgi(i),
	327	dbgi => dbgi(i),	327	dbgo => dbgo(i),
	328	~~dbgo~~ => ~~dbgo~~(i),	328	gclk => clkm
	329	~~gclk~~ => ~~clkm~~	329	);
	330	);	330
	331		331	END GENERATE;
	332	END GENERATE;	332
	333		333
	334		334	errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
	335	errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);	335
	336		336	dsugen : IF CFG_DSU = 1 GENERATE
	337	dsugen : IF CFG_DSU = 1 GENERATE	337	dsu0 : dsu3 -- LEON3 Debug Support Unit
	338	dsu0 : dsu3 -- LEON3 Debug Support Unit	338	GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
	339	GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,	339	ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
	340	ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)	340	PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
	341	PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);	341	dsui.enable <= '1';
	342	dsui.~~enable~~ <= '1';	342	dsui.break <= '0';
	343	dsui.break <= '0';	343	END GENERATE;
	344	END GENERATE;	344	END GENERATE;
	345	END GENERATE;	345
	346		346	nodsu : IF CFG_DSU = 0 GENERATE
	347	nodsu : IF CFG_DSU = 0 GENERATE	347	ahbso(2) <= ahbs_none;
	348	ahbso(2) <= ahbs_none;	348	dsuo.tstop <= '0';
	349	dsuo.~~tstop~~ <= '0';	349	dsuo.active <= '0';
	350	dsuo.active <= '0';	350	END GENERATE;
	351	END GENERATE;	351
	352		352	irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
	353	irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE	353	irqctrl0 : irqmp -- interrupt controller
	354	irqctrl0 : irqmp -- interrupt controller	354	GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
	355	GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)	355	PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
	356	PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);	356	END GENERATE;
	357	END GENERATE;	357	irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
	358	irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE	358	x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
	359	x : FOR i IN 0 TO CFG_NCPU-1 GENERATE	359	irqi(i).irl <= "0000";
	360	irqi(i).irl <= "0000";	360	END GENERATE;
	361	END GENERATE;	361	apbo(2) <= apb_none;
	362	apbo(2) <= apb_none;	362	END GENERATE;
	363	END GENERATE;	363
	364		364	----------------------------------------------------------------------
	365	---~~----------------------~~---------------------------------------------	365	--- Memory controllers ---------------------------------------------
	366	--- ~~Memory controllers~~ ---------------------------------------------	366	----------------------------------------------------------------------
	367	----------------------------------------------------------------------	367	memctrlr : mctrl GENERIC MAP (
	368	memctrlr : mctrl GENERIC MAP (	368	hindex => 0,
	369	hindex => 0,	369	pindex => 0,
	370	p~~index~~ => 0,	370	paddr => 0,
	371	paddr => 0,	371	srbanks => 1
	372	srbanks => 1	372	)
	373	)	373	PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
	374	PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);	374
	375		375	memi.brdyn <= '1';
	376	memi.b~~rdy~~n <= '1';	376	memi.bexcn <= '1';
	377	memi.~~bexcn~~ <= '1';	377	memi.writen <= '1';
	378	memi.wr~~ite~~n <= ~~'1'~~;	378	memi.wrn <= "1111";
	379	memi.~~wrn~~ <= "1~~111~~";	379	memi.bwidth <= "10";
	380	memi.bwidth <= "10";	380
	381		381	bdr : FOR i IN 0 TO 3 GENERATE
	382	bdr : FOR i IN 0 TO 3 GENERATE	382	data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
	383	data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)	383	PORT MAP (
	384	PORT MAP (	384	data(31-i8 DOWNTO 24-i8),
	385	data(31-i8 DOWNTO 24-i8),	385	memo.data(31-i8 DOWNTO 24-i8),
	386	memo.data(31-i8 DOWNTO 24-i8),	386	memo.bdrive(i),
	387	memo.bdrive(i),	387	memi.data(31-i8 DOWNTO 24-i8));
	388	memi.data(31-i8 DOWNTO 24-i8));	388	END GENERATE;
	389	END GENERATE;	389
	390		390	addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
	391	addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)	391	PORT MAP (address, memo.address(21 DOWNTO 2));
	392	PORT MAP (address, memo.address(21 DOWNTO 2));	392	nSRAM_CE_s <= NOT(memo.ramsn(0));
	393	nSRAM_CE_s <= NOT(memo.ramsn(0));	393	rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
	394	~~rams_pad~~ : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, ~~nSRAM_CE_s~~);	394	oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
	395	oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.~~ramoen~~(0));	395	nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
	396	nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.~~writen~~);	396	nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
	397	nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));	397	nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
	398	nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));	398	nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
	399	nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));	399	nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
	400	nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));	400
	401		401	----------------------------------------------------------------------
	402	---~~------------------~~-------------------------------------------------	402	--- AHB CONTROLLER -------------------------------------------------
	403	--- ~~AHB CONTROLLER~~ -------------------------------------------------	403	----------------------------------------------------------------------
	404	----------------------------------------------------------------------	404	ahb0 : ahbctrl -- AHB arbiter/multiplexer
	405	ahb0 : ahbctrl -- AHB arbiter/multiplexer	405	GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
	406	GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,	406	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
	407	rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,	407	ioen => 0, nahbm => maxahbmsp, nahbs => 8)
	408	ioen => 0, nahbm => maxahbmsp, nahbs => 8)	408	PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
	409	PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);	409
	410		410	----------------------------------------------------------------------
	411	---~~------------~~-------------------------------------------------------	411	--- AHB UART -------------------------------------------------------
	412	--- ~~AHB UART~~ -------------------------------------------------------	412	----------------------------------------------------------------------
	413	----------------------------------------------------------------------	413	dcomgen : IF CFG_AHB_UART = 1 GENERATE
	414	dcomgen : IF CFG_AHB_UART = 1 GENERATE	414	dcom0 : ahbuart
	415	dcom0 : ahbuart	415	GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
	416	GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)	416	PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
	417	PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));	417	dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
	418	dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);	418	dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
	419	dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);	419	END GENERATE;
	420	END GENERATE;	420	nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
	421	nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;	421
	422		422	----------------------------------------------------------------------
	423	---~~--------------~~-----------------------------------------------------	423	--- APB Bridge -----------------------------------------------------
	424	--- ~~APB Bridge~~ -----------------------------------------------------	424	----------------------------------------------------------------------
	425	----------------------------------------------------------------------	425	apb0 : apbctrl -- AHB/APB bridge
	426	apb0 : apbctrl -- AHB/APB bridge	426	GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
	427	GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)	427	PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
	428	PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);	428
	429		429	----------------------------------------------------------------------
	430	---~~-------------~~------------------------------------------------------	430	--- GPT Timer ------------------------------------------------------
	431	--- ~~GPT Timer~~ ------------------------------------------------------	431	----------------------------------------------------------------------
	432	----------------------------------------------------------------------	432	gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
	433	gpt : IF CFG_GPT_ENABLE /= 0 GENERATE	433	timer0 : gptimer -- timer unit
	434	timer0 : gptimer -- timer unit	434	GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
	435	GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,	435	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
	436	sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,	436	nbits => CFG_GPT_TW)
	437	nbits => CFG_GPT_TW)	437	PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
	438	PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);	438	gpti.dhalt <= dsuo.tstop;
	439	gpti.dhalt <= dsuo.tstop;	439	gpti.extclk <= '0';
	440	gpti.extclk <= '0';	440	END GENERATE;
	441	END GENERATE;	441	notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
	442	notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;	442
	443		443
	444		444	----------------------------------------------------------------------
	445	---~~------------~~-------------------------------------------------------	445	--- APB UART -------------------------------------------------------
	446	--- ~~APB UART~~ -------------------------------------------------------	446	----------------------------------------------------------------------
	447	----------------------------------------------------------------------	447	ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
	448	ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE	448	uart1 : apbuart -- UART 1
	449	uart1 : apbuart -- UART 1	449	GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
	450	GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,	450	fifosize => CFG_UART1_FIFO)
	451	fifosize => CFG_UART1_FIFO)	451	PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
	452	PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);	452	apbuarti.rxd <= urxd1;
	453	apbuarti.~~rxd~~ <= ~~urxd1~~;	453	apbuarti.extclk <= '0';
	454	apbuarti.extclk <= '0';	454	utxd1 <= apbuarto.txd;
	455	utxd1 <= apbuarto.txd;	455	apbuarti.ctsn <= '0';
	456	apbuarti.ctsn <= '0';	456	END GENERATE;
	457	END GENERATE;	457	noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
	458	noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;	458
	459		459	-------------------------------------------------------------------------------
	460	--~~----------~~-------------------------------------------------------------------	460	-- AMBA BUS -------------------------------------------------------------------
	461	-- ~~AMBA BUS~~ -------------------------------------------------------------------	461	-------------------------------------------------------------------------------
	462	-------------------------------------------------------------------------------	462
	463		463	-- APB --------------------------------------------------------------------
	464	-- APB --------------------------------------------------------------------	464	apbi_ext <= apbi;
	465	apbi_ext <= apbi;	465	all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
	466	~~all~~_apb : FOR I IN 0 TO ~~NB_APB_SLAVE~~-1 GENERATE	466	max_16_apb : IF I + 5 < 16 GENERATE
	467	max_16_apb : IF I + 5 < 16 GENERATE	467	apbo(I+5) <= apbo_ext(I+5);
	468	apbo(I+5) <= apbo_ext(I+5);	468	END GENERATE max_16_apb;
	469	END GENERATE ~~max_16~~_apb;	469	END GENERATE all_apb;
	470	END GENERATE all_apb;	470	-- AHB_Slave --------------------------------------------------------------
	471	-- AHB_Slave --------------------------------------------------------------	471	ahbi_s_ext <= ahbsi;
	472	ahbi_s_ext <= ahbsi;	472	all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
	473	~~all~~_ahbs : FOR I IN 0 TO ~~NB_AHB_SLAVE~~-1 GENERATE	473	max_16_ahbs : IF I + 3 < 16 GENERATE
	474	max_16_ahbs : IF I + 3 < 16 GENERATE	474	ahbso(I+3) <= ahbo_s_ext(I+3);
	475	ahbso(I+3) <= ahbo_s_ext(I+3);	475	END GENERATE max_16_ahbs;
	476	END GENERATE ~~max_16~~_ahbs;	476	END GENERATE all_ahbs;
	477	END GENERATE all_ahbs;	477	-- AHB_Master -------------------------------------------------------------
	478	-- AHB_Master -------------------------------------------------------------	478	ahbi_m_ext <= ahbmi;
	479	ahbi_m_ext <= ahbmi;	479	all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
	480	~~all~~_ahbm : FOR I IN 0 TO ~~NB_AHB_MASTER~~-1 GENERATE	480	max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
	481	max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE	481	ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
	482	ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);	482	END GENERATE max_16_ahbm;
	483	END GENERATE ~~max_16~~_ahbm;	483	END GENERATE all_ahbm;
	484	END GENERATE all_ahbm;	484
	485		485
	486		486
	487		487	END Behavioral; No newline at end of file
	488	END Behavioral;

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