HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r237:c95f017c99af

update CAL 2/2 + driver C

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r237:c95f017c99af martin

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lib/lpp/lpp_cna/APB_CNA.vhd +2 0

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                        Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.apb_devices_list.all;
             use lpp.lpp_cna.all;
             --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
             entity APB_CNA is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 clk     : in  std_logic;           --! Horloge du composant
                 rst     : in  std_logic;           --! Reset general du composant
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type;    --! Registre de gestion des sorties du bus
+                Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
                 SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
                 SCLK    : out std_logic;           --! Horloge systeme du convertisseur
                 DATA    : out std_logic            --! Donn�e num�rique s�rialis�
                 );
             end APB_CNA;
             --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
             --! et les sorties seront cabl�es vers le convertisseur.
             architecture ar_APB_CNA of APB_CNA is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             signal enable   : std_logic;
             signal flag_sd : std_logic;
             type CNA_ctrlr_Reg is record
                  CNA_Cfg  : std_logic_vector(1 downto 0);
                  CNA_Data : std_logic_vector(15 downto 0);
             end record;
             signal Rec : CNA_ctrlr_Reg;
             signal Rdata     : std_logic_vector(31 downto 0);
             begin
             enable <= Rec.CNA_Cfg(0);
             Rec.CNA_Cfg(1) <= flag_sd;
                 CONVERTER : CNA_TabloC
                     port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
                 process(rst,clk)
                 begin
                     if(rst='0')then
                         Rec.CNA_Data <=  (others => '0');
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                     Rec.CNA_Cfg(0) <= apbi.pwdata(0);
                                 when "000001" =>
                                     Rec.CNA_Data <= apbi.pwdata(15 downto 0);
                                 when others =>
                                     null;
                             end case;
                         end if;
                 --APB READ OP
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                     Rdata(31 downto 2) <= X"ABCDEF5" & "00";
                                     Rdata(1 downto 0) <= Rec.CNA_Cfg;
                                 when "000001" =>
                                     Rdata(31 downto 16) <= X"FD18";
                                     Rdata(15 downto 0) <= Rec.CNA_Data;
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
+            Cal_EN <= enable;
             end ar_APB_CNA;

lib/lpp/lpp_cna/CNA_TabloC.vhd +3 -18

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             use work.Convertisseur_config.all;
             --! Programme du Convertisseur Num�rique/Analogique
             entity CNA_TabloC is
               port(
-                clock       : in std_logic;                        --! Horloge du composant
+                clk         : in std_logic;                        --! Horloge du composant
                 rst         : in std_logic;                        --! Reset general du composant
                 enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant
                 Data_C      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
                 SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
                 SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
                 flag_sd     : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e
                 Data        : out std_logic                        --! Donn�e num�rique s�rialis�
                 );
             end CNA_TabloC;
             --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
             --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
             architecture ar_CNA_TabloC of CNA_TabloC is
-            --component CLKINT
-            --port( A : in    std_logic := 'U';
-            --      Y : out   std_logic);
-            --end component;
-            --signal clk      : std_logic;
-            --signal raz          : std_logic;
             signal s_SCLK      : std_logic;
             signal OKAI_send    : std_logic;
             begin
-            --CLKINT_0 : CLKINT
-            --    port map(A => clock, Y => clk);
-            --CLKINT_1 : CLKINT
-            --    port map(A => rst, Y => raz);
             SystemCLK : entity work.Systeme_Clock
                 generic map (nb_serial)
-                port map (clock,rst,s_SCLK);
+                port map (clk,rst,s_SCLK);
             Signal_sync : entity work.Gene_SYNC
                 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
             Serial : entity work.serialize
-                port map (clock,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
+                port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
             SCLK        <= s_SCLK;
             end ar_CNA_TabloC;

lib/lpp/lpp_cna/lpp_cna.vhd +2 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Martin Morlot
             --                     Mail : martin.morlot@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use std.textio.all;
             library lpp;
             use lpp.lpp_amba.all;
             --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
             package lpp_cna is
             component APB_CNA is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
+                Cal_EN  : out std_logic;
                 SYNC    : out std_logic;
                 SCLK    : out std_logic;
                 DATA    : out std_logic
                 );
             end component;
             component CNA_TabloC is
                 port(
-                    clock       : in std_logic;
+                    clk       : in std_logic;
                     rst         : in std_logic;
                     enable      : in std_logic;
                     Data_C      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
                     flag_sd     : out std_logic;
                     Data        : out std_logic
                     );
             end component;
             component Systeme_Clock is
                 generic(N :integer := 695);
                 port(
                     clk, raz   : in std_logic ;
                     clock      : out std_logic);
             end component;
             component Gene_SYNC is
                 port(
                     clk,raz     : in std_logic;
                     send     : in std_logic;
                     Sysclk      : in std_logic;
                     OKAI_send   : out std_logic;
                     SYNC        : out std_logic);
             end component;
             component Serialize is
             port(
                 clk,raz : in std_logic;
                 sclk    : in std_logic;
                 vectin  : in std_logic_vector(15 downto 0);
                 send    : in std_logic;
                 sended  : out std_logic;
                 Data    : out std_logic);
             end component;
             end;

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