@@ -44,6 +44,7 entity APB_CNA is | |||
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44 | 44 | rst : in std_logic; --! Reset general du composant |
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45 | 45 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
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46 | 46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
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47 | Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL | |
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47 | 48 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
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48 | 49 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
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49 | 50 | DATA : out std_logic --! Donn�e num�rique s�rialis� |
@@ -120,4 +121,5 Rec.CNA_Cfg(1) <= flag_sd; | |||
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120 | 121 | end process; |
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121 | 122 | |
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122 | 123 | apbo.prdata <= Rdata when apbi.penable = '1'; |
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124 | Cal_EN <= enable; | |
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123 | 125 | end ar_APB_CNA; |
@@ -28,7 +28,7 use work.Convertisseur_config.all; | |||
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28 | 28 | |
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29 | 29 | entity CNA_TabloC is |
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30 | 30 | port( |
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31 |
cl |
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31 | clk : in std_logic; --! Horloge du composant | |
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32 | 32 | rst : in std_logic; --! Reset general du composant |
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33 | 33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant |
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34 | 34 | Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits |
@@ -44,29 +44,14 end CNA_TabloC; | |||
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44 | 44 | |
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45 | 45 | architecture ar_CNA_TabloC of CNA_TabloC is |
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46 | 46 | |
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47 | --component CLKINT | |
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48 | --port( A : in std_logic := 'U'; | |
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49 | -- Y : out std_logic); | |
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50 | --end component; | |
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51 | ||
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52 | --signal clk : std_logic; | |
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53 | ||
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54 | --signal raz : std_logic; | |
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55 | 47 | signal s_SCLK : std_logic; |
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56 | 48 | signal OKAI_send : std_logic; |
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57 | 49 | |
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58 | 50 | begin |
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59 | 51 | |
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60 | --CLKINT_0 : CLKINT | |
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61 | -- port map(A => clock, Y => clk); | |
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62 | ||
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63 | --CLKINT_1 : CLKINT | |
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64 | -- port map(A => rst, Y => raz); | |
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65 | ||
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66 | ||
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67 | 52 | SystemCLK : entity work.Systeme_Clock |
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68 | 53 | generic map (nb_serial) |
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69 |
port map (cl |
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54 | port map (clk,rst,s_SCLK); | |
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70 | 55 | |
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71 | 56 | |
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72 | 57 | Signal_sync : entity work.Gene_SYNC |
@@ -74,7 +59,7 Signal_sync : entity work.Gene_SYNC | |||
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74 | 59 | |
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75 | 60 | |
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76 | 61 | Serial : entity work.serialize |
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77 |
port map (cl |
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62 | port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
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78 | 63 | |
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79 | 64 | |
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80 | 65 | SCLK <= s_SCLK; |
@@ -43,6 +43,7 component APB_CNA is | |||
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43 | 43 | rst : in std_logic; |
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44 | 44 | apbi : in apb_slv_in_type; |
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45 | 45 | apbo : out apb_slv_out_type; |
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46 | Cal_EN : out std_logic; | |
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46 | 47 | SYNC : out std_logic; |
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47 | 48 | SCLK : out std_logic; |
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48 | 49 | DATA : out std_logic |
@@ -52,7 +53,7 end component; | |||
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52 | 53 | |
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53 | 54 | component CNA_TabloC is |
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54 | 55 | port( |
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55 |
cl |
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56 | clk : in std_logic; | |
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56 | 57 | rst : in std_logic; |
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57 | 58 | enable : in std_logic; |
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58 | 59 | Data_C : in std_logic_vector(15 downto 0); |
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