@@ -1,123 +1,125 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------ |
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19 | 19 | -- Author : Martin Morlot |
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20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------ |
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22 | 22 | library ieee; |
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23 | 23 | use ieee.std_logic_1164.all; |
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24 | 24 | library grlib; |
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25 | 25 | use grlib.amba.all; |
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26 | 26 | use grlib.stdlib.all; |
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27 | 27 | use grlib.devices.all; |
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28 | 28 | library lpp; |
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29 | 29 | use lpp.lpp_amba.all; |
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30 | 30 | use lpp.apb_devices_list.all; |
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31 | 31 | use lpp.lpp_cna.all; |
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32 | 32 | |
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33 | 33 | --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba |
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34 | 34 | |
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35 | 35 | entity APB_CNA is |
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36 | 36 | generic ( |
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37 | 37 | pindex : integer := 0; |
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38 | 38 | paddr : integer := 0; |
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39 | 39 | pmask : integer := 16#fff#; |
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40 | 40 | pirq : integer := 0; |
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41 | 41 | abits : integer := 8); |
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42 | 42 | port ( |
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43 | 43 | clk : in std_logic; --! Horloge du composant |
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44 | 44 | rst : in std_logic; --! Reset general du composant |
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45 | 45 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
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46 | 46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
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47 | Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL | |
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47 | 48 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
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48 | 49 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
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49 | 50 | DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ |
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50 | 51 | ); |
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51 | 52 | end APB_CNA; |
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52 | 53 | |
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53 | 54 | --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus |
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54 | 55 | --! et les sorties seront cablοΏ½es vers le convertisseur. |
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55 | 56 | |
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56 | 57 | architecture ar_APB_CNA of APB_CNA is |
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57 | 58 | |
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58 | 59 | constant REVISION : integer := 1; |
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59 | 60 | |
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60 | 61 | constant pconfig : apb_config_type := ( |
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61 | 62 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
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62 | 63 | 1 => apb_iobar(paddr, pmask)); |
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63 | 64 | |
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64 | 65 | signal enable : std_logic; |
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65 | 66 | signal flag_sd : std_logic; |
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66 | 67 | |
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67 | 68 | type CNA_ctrlr_Reg is record |
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68 | 69 | CNA_Cfg : std_logic_vector(1 downto 0); |
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69 | 70 | CNA_Data : std_logic_vector(15 downto 0); |
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70 | 71 | end record; |
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71 | 72 | |
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72 | 73 | signal Rec : CNA_ctrlr_Reg; |
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73 | 74 | signal Rdata : std_logic_vector(31 downto 0); |
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74 | 75 | |
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75 | 76 | begin |
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76 | 77 | |
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77 | 78 | enable <= Rec.CNA_Cfg(0); |
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78 | 79 | Rec.CNA_Cfg(1) <= flag_sd; |
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79 | 80 | |
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80 | 81 | CONVERTER : CNA_TabloC |
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81 | 82 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); |
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82 | 83 | |
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83 | 84 | |
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84 | 85 | process(rst,clk) |
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85 | 86 | begin |
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86 | 87 | if(rst='0')then |
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87 | 88 | Rec.CNA_Data <= (others => '0'); |
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88 | 89 | |
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89 | 90 | elsif(clk'event and clk='1')then |
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90 | 91 | |
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91 | 92 | |
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92 | 93 | --APB Write OP |
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93 | 94 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
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94 | 95 | case apbi.paddr(abits-1 downto 2) is |
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95 | 96 | when "000000" => |
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96 | 97 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); |
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97 | 98 | when "000001" => |
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98 | 99 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
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99 | 100 | when others => |
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100 | 101 | null; |
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101 | 102 | end case; |
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102 | 103 | end if; |
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103 | 104 | |
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104 | 105 | --APB READ OP |
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105 | 106 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
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106 | 107 | case apbi.paddr(abits-1 downto 2) is |
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107 | 108 | when "000000" => |
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108 | 109 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; |
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109 | 110 | Rdata(1 downto 0) <= Rec.CNA_Cfg; |
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110 | 111 | when "000001" => |
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111 | 112 | Rdata(31 downto 16) <= X"FD18"; |
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112 | 113 | Rdata(15 downto 0) <= Rec.CNA_Data; |
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113 | 114 | when others => |
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114 | 115 | Rdata <= (others => '0'); |
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115 | 116 | end case; |
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116 | 117 | end if; |
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117 | 118 | |
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118 | 119 | end if; |
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119 | 120 | apbo.pconfig <= pconfig; |
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120 | 121 | end process; |
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121 | 122 | |
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122 | 123 | apbo.prdata <= Rdata when apbi.penable = '1'; |
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124 | Cal_EN <= enable; | |
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123 | 125 | end ar_APB_CNA; |
@@ -1,82 +1,67 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------ |
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22 | 22 | library IEEE; |
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23 | 23 | use IEEE.std_logic_1164.all; |
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24 | 24 | use IEEE.numeric_std.all; |
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25 | 25 | use work.Convertisseur_config.all; |
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26 | 26 | |
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27 | 27 | --! Programme du Convertisseur NumοΏ½rique/Analogique |
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28 | 28 | |
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29 | 29 | entity CNA_TabloC is |
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30 | 30 | port( |
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31 |
cl |
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31 | clk : in std_logic; --! Horloge du composant | |
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32 | 32 | rst : in std_logic; --! Reset general du composant |
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33 | 33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant |
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34 | 34 | Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits |
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35 | 35 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
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36 | 36 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
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37 | 37 | flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e |
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38 | 38 | Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ |
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39 | 39 | ); |
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40 | 40 | end CNA_TabloC; |
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41 | 41 | |
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42 | 42 | --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits, |
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43 | 43 | --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur. |
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44 | 44 | |
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45 | 45 | architecture ar_CNA_TabloC of CNA_TabloC is |
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46 | 46 | |
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47 | --component CLKINT | |
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48 | --port( A : in std_logic := 'U'; | |
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49 | -- Y : out std_logic); | |
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50 | --end component; | |
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51 | ||
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52 | --signal clk : std_logic; | |
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53 | ||
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54 | --signal raz : std_logic; | |
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55 | 47 | signal s_SCLK : std_logic; |
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56 | 48 | signal OKAI_send : std_logic; |
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57 | 49 | |
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58 | 50 | begin |
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59 | 51 | |
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60 | --CLKINT_0 : CLKINT | |
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61 | -- port map(A => clock, Y => clk); | |
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62 | ||
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63 | --CLKINT_1 : CLKINT | |
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64 | -- port map(A => rst, Y => raz); | |
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65 | ||
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66 | ||
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67 | 52 | SystemCLK : entity work.Systeme_Clock |
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68 | 53 | generic map (nb_serial) |
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69 |
port map (cl |
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54 | port map (clk,rst,s_SCLK); | |
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70 | 55 | |
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71 | 56 | |
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72 | 57 | Signal_sync : entity work.Gene_SYNC |
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73 | 58 | port map (s_SCLK,rst,enable,OKAI_send,SYNC); |
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74 | 59 | |
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75 | 60 | |
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76 | 61 | Serial : entity work.serialize |
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77 |
port map (cl |
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62 | port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
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78 | 63 | |
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79 | 64 | |
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80 | 65 | SCLK <= s_SCLK; |
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81 | 66 | |
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82 | 67 | end ar_CNA_TabloC; No newline at end of file |
@@ -1,95 +1,96 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Martin Morlot |
|
20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | library ieee; |
|
23 | 23 | use ieee.std_logic_1164.all; |
|
24 | 24 | library grlib; |
|
25 | 25 | use grlib.amba.all; |
|
26 | 26 | use std.textio.all; |
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27 | 27 | library lpp; |
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28 | 28 | use lpp.lpp_amba.all; |
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29 | 29 | |
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30 | 30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
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31 | 31 | |
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32 | 32 | package lpp_cna is |
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33 | 33 | |
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34 | 34 | component APB_CNA is |
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35 | 35 | generic ( |
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36 | 36 | pindex : integer := 0; |
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37 | 37 | paddr : integer := 0; |
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38 | 38 | pmask : integer := 16#fff#; |
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39 | 39 | pirq : integer := 0; |
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40 | 40 | abits : integer := 8); |
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41 | 41 | port ( |
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42 | 42 | clk : in std_logic; |
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43 | 43 | rst : in std_logic; |
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44 | 44 | apbi : in apb_slv_in_type; |
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45 | 45 | apbo : out apb_slv_out_type; |
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46 | Cal_EN : out std_logic; | |
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46 | 47 | SYNC : out std_logic; |
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47 | 48 | SCLK : out std_logic; |
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48 | 49 | DATA : out std_logic |
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49 | 50 | ); |
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50 | 51 | end component; |
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51 | 52 | |
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52 | 53 | |
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53 | 54 | component CNA_TabloC is |
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54 | 55 | port( |
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55 |
cl |
|
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56 | clk : in std_logic; | |
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56 | 57 | rst : in std_logic; |
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57 | 58 | enable : in std_logic; |
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58 | 59 | Data_C : in std_logic_vector(15 downto 0); |
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59 | 60 | SYNC : out std_logic; |
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60 | 61 | SCLK : out std_logic; |
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61 | 62 | flag_sd : out std_logic; |
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62 | 63 | Data : out std_logic |
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63 | 64 | ); |
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64 | 65 | end component; |
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65 | 66 | |
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66 | 67 | |
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67 | 68 | component Systeme_Clock is |
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68 | 69 | generic(N :integer := 695); |
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69 | 70 | port( |
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70 | 71 | clk, raz : in std_logic ; |
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71 | 72 | clock : out std_logic); |
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72 | 73 | end component; |
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73 | 74 | |
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74 | 75 | |
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75 | 76 | component Gene_SYNC is |
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76 | 77 | port( |
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77 | 78 | clk,raz : in std_logic; |
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78 | 79 | send : in std_logic; |
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79 | 80 | Sysclk : in std_logic; |
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80 | 81 | OKAI_send : out std_logic; |
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81 | 82 | SYNC : out std_logic); |
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82 | 83 | end component; |
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83 | 84 | |
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84 | 85 | |
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85 | 86 | component Serialize is |
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86 | 87 | port( |
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87 | 88 | clk,raz : in std_logic; |
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88 | 89 | sclk : in std_logic; |
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89 | 90 | vectin : in std_logic_vector(15 downto 0); |
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90 | 91 | send : in std_logic; |
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91 | 92 | sended : out std_logic; |
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92 | 93 | Data : out std_logic); |
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93 | 94 | end component; |
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94 | 95 | |
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95 | 96 | end; |
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