@@ -44,6 +44,7 entity APB_CNA is | |||||
44 | rst : in std_logic; --! Reset general du composant |
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44 | rst : in std_logic; --! Reset general du composant | |
45 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus |
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45 | apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus | |
46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
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46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus | |
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47 | Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL | |||
47 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
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48 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | |
48 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
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49 | SCLK : out std_logic; --! Horloge systeme du convertisseur | |
49 | DATA : out std_logic --! Donn�e num�rique s�rialis� |
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50 | DATA : out std_logic --! Donn�e num�rique s�rialis� | |
@@ -120,4 +121,5 Rec.CNA_Cfg(1) <= flag_sd; | |||||
120 | end process; |
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121 | end process; | |
121 |
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122 | |||
122 | apbo.prdata <= Rdata when apbi.penable = '1'; |
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123 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
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124 | Cal_EN <= enable; | |||
123 | end ar_APB_CNA; |
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125 | end ar_APB_CNA; |
@@ -28,7 +28,7 use work.Convertisseur_config.all; | |||||
28 |
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28 | |||
29 | entity CNA_TabloC is |
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29 | entity CNA_TabloC is | |
30 | port( |
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30 | port( | |
31 |
cl |
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31 | clk : in std_logic; --! Horloge du composant | |
32 | rst : in std_logic; --! Reset general du composant |
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32 | rst : in std_logic; --! Reset general du composant | |
33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant |
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33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant | |
34 | Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits |
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34 | Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits | |
@@ -44,29 +44,14 end CNA_TabloC; | |||||
44 |
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44 | |||
45 | architecture ar_CNA_TabloC of CNA_TabloC is |
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45 | architecture ar_CNA_TabloC of CNA_TabloC is | |
46 |
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46 | |||
47 | --component CLKINT |
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48 | --port( A : in std_logic := 'U'; |
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49 | -- Y : out std_logic); |
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50 | --end component; |
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51 |
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52 | --signal clk : std_logic; |
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53 |
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54 | --signal raz : std_logic; |
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55 | signal s_SCLK : std_logic; |
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47 | signal s_SCLK : std_logic; | |
56 | signal OKAI_send : std_logic; |
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48 | signal OKAI_send : std_logic; | |
57 |
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49 | |||
58 | begin |
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50 | begin | |
59 |
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51 | |||
60 | --CLKINT_0 : CLKINT |
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61 | -- port map(A => clock, Y => clk); |
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62 |
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63 | --CLKINT_1 : CLKINT |
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64 | -- port map(A => rst, Y => raz); |
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65 |
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66 |
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67 | SystemCLK : entity work.Systeme_Clock |
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52 | SystemCLK : entity work.Systeme_Clock | |
68 | generic map (nb_serial) |
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53 | generic map (nb_serial) | |
69 |
port map (cl |
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54 | port map (clk,rst,s_SCLK); | |
70 |
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55 | |||
71 |
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56 | |||
72 | Signal_sync : entity work.Gene_SYNC |
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57 | Signal_sync : entity work.Gene_SYNC | |
@@ -74,7 +59,7 Signal_sync : entity work.Gene_SYNC | |||||
74 |
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59 | |||
75 |
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60 | |||
76 | Serial : entity work.serialize |
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61 | Serial : entity work.serialize | |
77 |
port map (cl |
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62 | port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
78 |
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63 | |||
79 |
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64 | |||
80 | SCLK <= s_SCLK; |
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65 | SCLK <= s_SCLK; |
@@ -43,6 +43,7 component APB_CNA is | |||||
43 | rst : in std_logic; |
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43 | rst : in std_logic; | |
44 | apbi : in apb_slv_in_type; |
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44 | apbi : in apb_slv_in_type; | |
45 | apbo : out apb_slv_out_type; |
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45 | apbo : out apb_slv_out_type; | |
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46 | Cal_EN : out std_logic; | |||
46 | SYNC : out std_logic; |
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47 | SYNC : out std_logic; | |
47 | SCLK : out std_logic; |
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48 | SCLK : out std_logic; | |
48 | DATA : out std_logic |
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49 | DATA : out std_logic | |
@@ -52,7 +53,7 end component; | |||||
52 |
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53 | |||
53 | component CNA_TabloC is |
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54 | component CNA_TabloC is | |
54 | port( |
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55 | port( | |
55 |
cl |
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56 | clk : in std_logic; | |
56 | rst : in std_logic; |
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57 | rst : in std_logic; | |
57 | enable : in std_logic; |
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58 | enable : in std_logic; | |
58 | Data_C : in std_logic_vector(15 downto 0); |
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59 | Data_C : in std_logic_vector(15 downto 0); |
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