@@ -1,123 +1,125 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use grlib.stdlib.all; |
|
26 | use grlib.stdlib.all; | |
27 | use grlib.devices.all; |
|
27 | use grlib.devices.all; | |
28 | library lpp; |
|
28 | library lpp; | |
29 | use lpp.lpp_amba.all; |
|
29 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
30 | use lpp.apb_devices_list.all; | |
31 | use lpp.lpp_cna.all; |
|
31 | use lpp.lpp_cna.all; | |
32 |
|
32 | |||
33 | --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba |
|
33 | --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba | |
34 |
|
34 | |||
35 | entity APB_CNA is |
|
35 | entity APB_CNA is | |
36 | generic ( |
|
36 | generic ( | |
37 | pindex : integer := 0; |
|
37 | pindex : integer := 0; | |
38 | paddr : integer := 0; |
|
38 | paddr : integer := 0; | |
39 | pmask : integer := 16#fff#; |
|
39 | pmask : integer := 16#fff#; | |
40 | pirq : integer := 0; |
|
40 | pirq : integer := 0; | |
41 | abits : integer := 8); |
|
41 | abits : integer := 8); | |
42 | port ( |
|
42 | port ( | |
43 | clk : in std_logic; --! Horloge du composant |
|
43 | clk : in std_logic; --! Horloge du composant | |
44 | rst : in std_logic; --! Reset general du composant |
|
44 | rst : in std_logic; --! Reset general du composant | |
45 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
|
45 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus | |
46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
|
46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus | |
|
47 | Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL | |||
47 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
|
48 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | |
48 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
|
49 | SCLK : out std_logic; --! Horloge systeme du convertisseur | |
49 | DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ |
|
50 | DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ | |
50 | ); |
|
51 | ); | |
51 | end APB_CNA; |
|
52 | end APB_CNA; | |
52 |
|
53 | |||
53 | --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus |
|
54 | --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus | |
54 | --! et les sorties seront cablοΏ½es vers le convertisseur. |
|
55 | --! et les sorties seront cablοΏ½es vers le convertisseur. | |
55 |
|
56 | |||
56 | architecture ar_APB_CNA of APB_CNA is |
|
57 | architecture ar_APB_CNA of APB_CNA is | |
57 |
|
58 | |||
58 | constant REVISION : integer := 1; |
|
59 | constant REVISION : integer := 1; | |
59 |
|
60 | |||
60 | constant pconfig : apb_config_type := ( |
|
61 | constant pconfig : apb_config_type := ( | |
61 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
|
62 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), | |
62 | 1 => apb_iobar(paddr, pmask)); |
|
63 | 1 => apb_iobar(paddr, pmask)); | |
63 |
|
64 | |||
64 | signal enable : std_logic; |
|
65 | signal enable : std_logic; | |
65 | signal flag_sd : std_logic; |
|
66 | signal flag_sd : std_logic; | |
66 |
|
67 | |||
67 | type CNA_ctrlr_Reg is record |
|
68 | type CNA_ctrlr_Reg is record | |
68 | CNA_Cfg : std_logic_vector(1 downto 0); |
|
69 | CNA_Cfg : std_logic_vector(1 downto 0); | |
69 | CNA_Data : std_logic_vector(15 downto 0); |
|
70 | CNA_Data : std_logic_vector(15 downto 0); | |
70 | end record; |
|
71 | end record; | |
71 |
|
72 | |||
72 | signal Rec : CNA_ctrlr_Reg; |
|
73 | signal Rec : CNA_ctrlr_Reg; | |
73 | signal Rdata : std_logic_vector(31 downto 0); |
|
74 | signal Rdata : std_logic_vector(31 downto 0); | |
74 |
|
75 | |||
75 | begin |
|
76 | begin | |
76 |
|
77 | |||
77 | enable <= Rec.CNA_Cfg(0); |
|
78 | enable <= Rec.CNA_Cfg(0); | |
78 | Rec.CNA_Cfg(1) <= flag_sd; |
|
79 | Rec.CNA_Cfg(1) <= flag_sd; | |
79 |
|
80 | |||
80 | CONVERTER : CNA_TabloC |
|
81 | CONVERTER : CNA_TabloC | |
81 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); |
|
82 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); | |
82 |
|
83 | |||
83 |
|
84 | |||
84 | process(rst,clk) |
|
85 | process(rst,clk) | |
85 | begin |
|
86 | begin | |
86 | if(rst='0')then |
|
87 | if(rst='0')then | |
87 | Rec.CNA_Data <= (others => '0'); |
|
88 | Rec.CNA_Data <= (others => '0'); | |
88 |
|
89 | |||
89 | elsif(clk'event and clk='1')then |
|
90 | elsif(clk'event and clk='1')then | |
90 |
|
91 | |||
91 |
|
92 | |||
92 | --APB Write OP |
|
93 | --APB Write OP | |
93 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
94 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
94 | case apbi.paddr(abits-1 downto 2) is |
|
95 | case apbi.paddr(abits-1 downto 2) is | |
95 | when "000000" => |
|
96 | when "000000" => | |
96 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); |
|
97 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); | |
97 | when "000001" => |
|
98 | when "000001" => | |
98 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
|
99 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); | |
99 | when others => |
|
100 | when others => | |
100 | null; |
|
101 | null; | |
101 | end case; |
|
102 | end case; | |
102 | end if; |
|
103 | end if; | |
103 |
|
104 | |||
104 | --APB READ OP |
|
105 | --APB READ OP | |
105 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
106 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
106 | case apbi.paddr(abits-1 downto 2) is |
|
107 | case apbi.paddr(abits-1 downto 2) is | |
107 | when "000000" => |
|
108 | when "000000" => | |
108 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; |
|
109 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; | |
109 | Rdata(1 downto 0) <= Rec.CNA_Cfg; |
|
110 | Rdata(1 downto 0) <= Rec.CNA_Cfg; | |
110 | when "000001" => |
|
111 | when "000001" => | |
111 | Rdata(31 downto 16) <= X"FD18"; |
|
112 | Rdata(31 downto 16) <= X"FD18"; | |
112 | Rdata(15 downto 0) <= Rec.CNA_Data; |
|
113 | Rdata(15 downto 0) <= Rec.CNA_Data; | |
113 | when others => |
|
114 | when others => | |
114 | Rdata <= (others => '0'); |
|
115 | Rdata <= (others => '0'); | |
115 | end case; |
|
116 | end case; | |
116 | end if; |
|
117 | end if; | |
117 |
|
118 | |||
118 | end if; |
|
119 | end if; | |
119 | apbo.pconfig <= pconfig; |
|
120 | apbo.pconfig <= pconfig; | |
120 | end process; |
|
121 | end process; | |
121 |
|
122 | |||
122 | apbo.prdata <= Rdata when apbi.penable = '1'; |
|
123 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
|
124 | Cal_EN <= enable; | |||
123 | end ar_APB_CNA; |
|
125 | end ar_APB_CNA; |
@@ -1,82 +1,67 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.std_logic_1164.all; |
|
23 | use IEEE.std_logic_1164.all; | |
24 | use IEEE.numeric_std.all; |
|
24 | use IEEE.numeric_std.all; | |
25 | use work.Convertisseur_config.all; |
|
25 | use work.Convertisseur_config.all; | |
26 |
|
26 | |||
27 | --! Programme du Convertisseur NumοΏ½rique/Analogique |
|
27 | --! Programme du Convertisseur NumοΏ½rique/Analogique | |
28 |
|
28 | |||
29 | entity CNA_TabloC is |
|
29 | entity CNA_TabloC is | |
30 | port( |
|
30 | port( | |
31 |
cl |
|
31 | clk : in std_logic; --! Horloge du composant | |
32 | rst : in std_logic; --! Reset general du composant |
|
32 | rst : in std_logic; --! Reset general du composant | |
33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant |
|
33 | enable : in std_logic; --! Autorise ou non l'utilisation du composant | |
34 | Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits |
|
34 | Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits | |
35 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
|
35 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur | |
36 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
|
36 | SCLK : out std_logic; --! Horloge systeme du convertisseur | |
37 | flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e |
|
37 | flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e | |
38 | Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ |
|
38 | Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ | |
39 | ); |
|
39 | ); | |
40 | end CNA_TabloC; |
|
40 | end CNA_TabloC; | |
41 |
|
41 | |||
42 | --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits, |
|
42 | --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits, | |
43 | --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur. |
|
43 | --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur. | |
44 |
|
44 | |||
45 | architecture ar_CNA_TabloC of CNA_TabloC is |
|
45 | architecture ar_CNA_TabloC of CNA_TabloC is | |
46 |
|
46 | |||
47 | --component CLKINT |
|
|||
48 | --port( A : in std_logic := 'U'; |
|
|||
49 | -- Y : out std_logic); |
|
|||
50 | --end component; |
|
|||
51 |
|
||||
52 | --signal clk : std_logic; |
|
|||
53 |
|
||||
54 | --signal raz : std_logic; |
|
|||
55 | signal s_SCLK : std_logic; |
|
47 | signal s_SCLK : std_logic; | |
56 | signal OKAI_send : std_logic; |
|
48 | signal OKAI_send : std_logic; | |
57 |
|
49 | |||
58 | begin |
|
50 | begin | |
59 |
|
51 | |||
60 | --CLKINT_0 : CLKINT |
|
|||
61 | -- port map(A => clock, Y => clk); |
|
|||
62 |
|
||||
63 | --CLKINT_1 : CLKINT |
|
|||
64 | -- port map(A => rst, Y => raz); |
|
|||
65 |
|
||||
66 |
|
||||
67 | SystemCLK : entity work.Systeme_Clock |
|
52 | SystemCLK : entity work.Systeme_Clock | |
68 | generic map (nb_serial) |
|
53 | generic map (nb_serial) | |
69 |
port map (cl |
|
54 | port map (clk,rst,s_SCLK); | |
70 |
|
55 | |||
71 |
|
56 | |||
72 | Signal_sync : entity work.Gene_SYNC |
|
57 | Signal_sync : entity work.Gene_SYNC | |
73 | port map (s_SCLK,rst,enable,OKAI_send,SYNC); |
|
58 | port map (s_SCLK,rst,enable,OKAI_send,SYNC); | |
74 |
|
59 | |||
75 |
|
60 | |||
76 | Serial : entity work.serialize |
|
61 | Serial : entity work.serialize | |
77 |
port map (cl |
|
62 | port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); | |
78 |
|
63 | |||
79 |
|
64 | |||
80 | SCLK <= s_SCLK; |
|
65 | SCLK <= s_SCLK; | |
81 |
|
66 | |||
82 | end ar_CNA_TabloC; No newline at end of file |
|
67 | end ar_CNA_TabloC; |
@@ -1,95 +1,96 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use std.textio.all; |
|
26 | use std.textio.all; | |
27 | library lpp; |
|
27 | library lpp; | |
28 | use lpp.lpp_amba.all; |
|
28 | use lpp.lpp_amba.all; | |
29 |
|
29 | |||
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on |
|
30 | --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on | |
31 |
|
31 | |||
32 | package lpp_cna is |
|
32 | package lpp_cna is | |
33 |
|
33 | |||
34 | component APB_CNA is |
|
34 | component APB_CNA is | |
35 | generic ( |
|
35 | generic ( | |
36 | pindex : integer := 0; |
|
36 | pindex : integer := 0; | |
37 | paddr : integer := 0; |
|
37 | paddr : integer := 0; | |
38 | pmask : integer := 16#fff#; |
|
38 | pmask : integer := 16#fff#; | |
39 | pirq : integer := 0; |
|
39 | pirq : integer := 0; | |
40 | abits : integer := 8); |
|
40 | abits : integer := 8); | |
41 | port ( |
|
41 | port ( | |
42 | clk : in std_logic; |
|
42 | clk : in std_logic; | |
43 | rst : in std_logic; |
|
43 | rst : in std_logic; | |
44 | apbi : in apb_slv_in_type; |
|
44 | apbi : in apb_slv_in_type; | |
45 | apbo : out apb_slv_out_type; |
|
45 | apbo : out apb_slv_out_type; | |
|
46 | Cal_EN : out std_logic; | |||
46 | SYNC : out std_logic; |
|
47 | SYNC : out std_logic; | |
47 | SCLK : out std_logic; |
|
48 | SCLK : out std_logic; | |
48 | DATA : out std_logic |
|
49 | DATA : out std_logic | |
49 | ); |
|
50 | ); | |
50 | end component; |
|
51 | end component; | |
51 |
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52 | |||
52 |
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53 | |||
53 | component CNA_TabloC is |
|
54 | component CNA_TabloC is | |
54 | port( |
|
55 | port( | |
55 |
cl |
|
56 | clk : in std_logic; | |
56 | rst : in std_logic; |
|
57 | rst : in std_logic; | |
57 | enable : in std_logic; |
|
58 | enable : in std_logic; | |
58 | Data_C : in std_logic_vector(15 downto 0); |
|
59 | Data_C : in std_logic_vector(15 downto 0); | |
59 | SYNC : out std_logic; |
|
60 | SYNC : out std_logic; | |
60 | SCLK : out std_logic; |
|
61 | SCLK : out std_logic; | |
61 | flag_sd : out std_logic; |
|
62 | flag_sd : out std_logic; | |
62 | Data : out std_logic |
|
63 | Data : out std_logic | |
63 | ); |
|
64 | ); | |
64 | end component; |
|
65 | end component; | |
65 |
|
66 | |||
66 |
|
67 | |||
67 | component Systeme_Clock is |
|
68 | component Systeme_Clock is | |
68 | generic(N :integer := 695); |
|
69 | generic(N :integer := 695); | |
69 | port( |
|
70 | port( | |
70 | clk, raz : in std_logic ; |
|
71 | clk, raz : in std_logic ; | |
71 | clock : out std_logic); |
|
72 | clock : out std_logic); | |
72 | end component; |
|
73 | end component; | |
73 |
|
74 | |||
74 |
|
75 | |||
75 | component Gene_SYNC is |
|
76 | component Gene_SYNC is | |
76 | port( |
|
77 | port( | |
77 | clk,raz : in std_logic; |
|
78 | clk,raz : in std_logic; | |
78 | send : in std_logic; |
|
79 | send : in std_logic; | |
79 | Sysclk : in std_logic; |
|
80 | Sysclk : in std_logic; | |
80 | OKAI_send : out std_logic; |
|
81 | OKAI_send : out std_logic; | |
81 | SYNC : out std_logic); |
|
82 | SYNC : out std_logic); | |
82 | end component; |
|
83 | end component; | |
83 |
|
84 | |||
84 |
|
85 | |||
85 | component Serialize is |
|
86 | component Serialize is | |
86 | port( |
|
87 | port( | |
87 | clk,raz : in std_logic; |
|
88 | clk,raz : in std_logic; | |
88 | sclk : in std_logic; |
|
89 | sclk : in std_logic; | |
89 | vectin : in std_logic_vector(15 downto 0); |
|
90 | vectin : in std_logic_vector(15 downto 0); | |
90 | send : in std_logic; |
|
91 | send : in std_logic; | |
91 | sended : out std_logic; |
|
92 | sended : out std_logic; | |
92 | Data : out std_logic); |
|
93 | Data : out std_logic); | |
93 | end component; |
|
94 | end component; | |
94 |
|
95 | |||
95 | end; |
|
96 | end; |
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