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(MINI-LFR) 0.1.44...
pellion -
r502:c71ce0e554fc (MINI-LFR) WFP_MS-0-1-46 (LFR-EM) WFP_MS_1-1-47 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- HK ---------------------------------------------------------------------
85 -- HK ---------------------------------------------------------------------
86 HK_smpclk : OUT STD_LOGIC;
86 HK_smpclk : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
89 ---------------------------------------------------------------------------
89 ---------------------------------------------------------------------------
90 TAG8 : OUT STD_LOGIC;
90 TAG8 : OUT STD_LOGIC;
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
92 );
92 );
93
93
94 END LFR_em;
94 END LFR_em;
95
95
96
96
97 ARCHITECTURE beh OF LFR_em IS
97 ARCHITECTURE beh OF LFR_em IS
98 SIGNAL clk_50_s : STD_LOGIC := '0';
98 SIGNAL clk_50_s : STD_LOGIC := '0';
99 SIGNAL clk_25 : STD_LOGIC := '0';
99 SIGNAL clk_25 : STD_LOGIC := '0';
100 SIGNAL clk_24 : STD_LOGIC := '0';
100 SIGNAL clk_24 : STD_LOGIC := '0';
101 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
104
104
105 -- CONSTANTS
105 -- CONSTANTS
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
110
110
111 SIGNAL apbi_ext : apb_slv_in_type;
111 SIGNAL apbi_ext : apb_slv_in_type;
112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
117
117
118 -- Spacewire signals
118 -- Spacewire signals
119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 SIGNAL spw_rxtxclk : STD_ULOGIC;
122 SIGNAL spw_rxtxclk : STD_ULOGIC;
123 SIGNAL spw_rxclkn : STD_ULOGIC;
123 SIGNAL spw_rxclkn : STD_ULOGIC;
124 SIGNAL spw_clk : STD_LOGIC;
124 SIGNAL spw_clk : STD_LOGIC;
125 SIGNAL swni : grspw_in_type;
125 SIGNAL swni : grspw_in_type;
126 SIGNAL swno : grspw_out_type;
126 SIGNAL swno : grspw_out_type;
127
127
128 --GPIO
128 --GPIO
129 SIGNAL gpioi : gpio_in_type;
129 SIGNAL gpioi : gpio_in_type;
130 SIGNAL gpioo : gpio_out_type;
130 SIGNAL gpioo : gpio_out_type;
131
131
132 -- AD Converter ADS7886
132 -- AD Converter ADS7886
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
135 SIGNAL sample_val : STD_LOGIC;
135 SIGNAL sample_val : STD_LOGIC;
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140
140
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142 SIGNAL rstn : STD_LOGIC;
142 SIGNAL rstn : STD_LOGIC;
143
143
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
146
146
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
150
150
151 BEGIN -- beh
151 BEGIN -- beh
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 -- CLK
154 -- CLK
155 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
157
157
158 PROCESS(clk100MHz)
158 PROCESS(clk100MHz)
159 BEGIN
159 BEGIN
160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
161 clk_50_s <= NOT clk_50_s;
161 clk_50_s <= NOT clk_50_s;
162 END IF;
162 END IF;
163 END PROCESS;
163 END PROCESS;
164
164
165 PROCESS(clk_50_s)
165 PROCESS(clk_50_s)
166 BEGIN
166 BEGIN
167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
168 clk_25 <= NOT clk_25;
168 clk_25 <= NOT clk_25;
169 END IF;
169 END IF;
170 END PROCESS;
170 END PROCESS;
171
171
172 PROCESS(clk49_152MHz)
172 PROCESS(clk49_152MHz)
173 BEGIN
173 BEGIN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 clk_24 <= NOT clk_24;
175 clk_24 <= NOT clk_24;
176 END IF;
176 END IF;
177 END PROCESS;
177 END PROCESS;
178
178
179 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180
180
181 PROCESS (clk_25, rstn)
181 PROCESS (clk_25, rstn)
182 BEGIN -- PROCESS
182 BEGIN -- PROCESS
183 IF rstn = '0' THEN -- asynchronous reset (active low)
183 IF rstn = '0' THEN -- asynchronous reset (active low)
184 led(0) <= '0';
184 led(0) <= '0';
185 led(1) <= '0';
185 led(1) <= '0';
186 led(2) <= '0';
186 led(2) <= '0';
187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
188 led(0) <= '0';
188 led(0) <= '0';
189 led(1) <= '1';
189 led(1) <= '1';
190 led(2) <= '1';
190 led(2) <= '1';
191 END IF;
191 END IF;
192 END PROCESS;
192 END PROCESS;
193
193
194 --
194 --
195 leon3_soc_1 : leon3_soc
195 leon3_soc_1 : leon3_soc
196 GENERIC MAP (
196 GENERIC MAP (
197 fabtech => apa3e,
197 fabtech => apa3e,
198 memtech => apa3e,
198 memtech => apa3e,
199 padtech => inferred,
199 padtech => inferred,
200 clktech => inferred,
200 clktech => inferred,
201 disas => 0,
201 disas => 0,
202 dbguart => 0,
202 dbguart => 0,
203 pclow => 2,
203 pclow => 2,
204 clk_freq => 25000,
204 clk_freq => 25000,
205 NB_CPU => 1,
205 NB_CPU => 1,
206 ENABLE_FPU => 1,
206 ENABLE_FPU => 1,
207 FPU_NETLIST => 0,
207 FPU_NETLIST => 0,
208 ENABLE_DSU => 1,
208 ENABLE_DSU => 1,
209 ENABLE_AHB_UART => 1,
209 ENABLE_AHB_UART => 1,
210 ENABLE_APB_UART => 1,
210 ENABLE_APB_UART => 1,
211 ENABLE_IRQMP => 1,
211 ENABLE_IRQMP => 1,
212 ENABLE_GPT => 1,
212 ENABLE_GPT => 1,
213 NB_AHB_MASTER => NB_AHB_MASTER,
213 NB_AHB_MASTER => NB_AHB_MASTER,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
215 NB_APB_SLAVE => NB_APB_SLAVE,
215 NB_APB_SLAVE => NB_APB_SLAVE,
216 ADDRESS_SIZE => 20,
216 ADDRESS_SIZE => 20,
217 USES_IAP_MEMCTRLR => 0)
217 USES_IAP_MEMCTRLR => 0)
218 PORT MAP (
218 PORT MAP (
219 clk => clk_25,
219 clk => clk_25,
220 reset => rstn,
220 reset => rstn,
221 errorn => OPEN,
221 errorn => OPEN,
222
222
223 ahbrxd => TAG1,
223 ahbrxd => TAG1,
224 ahbtxd => TAG3,
224 ahbtxd => TAG3,
225 urxd1 => TAG2,
225 urxd1 => TAG2,
226 utxd1 => TAG4,
226 utxd1 => TAG4,
227
227
228 address => address,
228 address => address,
229 data => data,
229 data => data,
230 nSRAM_BE0 => nSRAM_BE0,
230 nSRAM_BE0 => nSRAM_BE0,
231 nSRAM_BE1 => nSRAM_BE1,
231 nSRAM_BE1 => nSRAM_BE1,
232 nSRAM_BE2 => nSRAM_BE2,
232 nSRAM_BE2 => nSRAM_BE2,
233 nSRAM_BE3 => nSRAM_BE3,
233 nSRAM_BE3 => nSRAM_BE3,
234 nSRAM_WE => nSRAM_WE,
234 nSRAM_WE => nSRAM_WE,
235 nSRAM_CE => nSRAM_CE_s,
235 nSRAM_CE => nSRAM_CE_s,
236 nSRAM_OE => nSRAM_OE,
236 nSRAM_OE => nSRAM_OE,
237 nSRAM_READY => '0',
237 nSRAM_READY => '0',
238 SRAM_MBE => OPEN,
238 SRAM_MBE => OPEN,
239
239
240 apbi_ext => apbi_ext,
240 apbi_ext => apbi_ext,
241 apbo_ext => apbo_ext,
241 apbo_ext => apbo_ext,
242 ahbi_s_ext => ahbi_s_ext,
242 ahbi_s_ext => ahbi_s_ext,
243 ahbo_s_ext => ahbo_s_ext,
243 ahbo_s_ext => ahbo_s_ext,
244 ahbi_m_ext => ahbi_m_ext,
244 ahbi_m_ext => ahbi_m_ext,
245 ahbo_m_ext => ahbo_m_ext);
245 ahbo_m_ext => ahbo_m_ext);
246
246
247
247
248 nSRAM_CE <= nSRAM_CE_s(0);
248 nSRAM_CE <= nSRAM_CE_s(0);
249
249
250 -------------------------------------------------------------------------------
250 -------------------------------------------------------------------------------
251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
252 -------------------------------------------------------------------------------
252 -------------------------------------------------------------------------------
253 apb_lfr_time_management_1 : apb_lfr_time_management
253 apb_lfr_time_management_1 : apb_lfr_time_management
254 GENERIC MAP (
254 GENERIC MAP (
255 pindex => 6,
255 pindex => 6,
256 paddr => 6,
256 paddr => 6,
257 pmask => 16#fff#,
257 pmask => 16#fff#,
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
260 PORT MAP (
260 PORT MAP (
261 clk25MHz => clk_25,
261 clk25MHz => clk_25,
262 clk24_576MHz => clk_24, -- 49.152MHz/2
262 clk24_576MHz => clk_24, -- 49.152MHz/2
263 resetn => rstn,
263 resetn => rstn,
264 grspw_tick => swno.tickout,
264 grspw_tick => swno.tickout,
265 apbi => apbi_ext,
265 apbi => apbi_ext,
266 apbo => apbo_ext(6),
266 apbo => apbo_ext(6),
267 coarse_time => coarse_time,
267 coarse_time => coarse_time,
268 fine_time => fine_time,
268 fine_time => fine_time,
269 LFR_soft_rstn => LFR_soft_rstn
269 LFR_soft_rstn => LFR_soft_rstn
270 );
270 );
271
271
272 -----------------------------------------------------------------------
272 -----------------------------------------------------------------------
273 --- SpaceWire --------------------------------------------------------
273 --- SpaceWire --------------------------------------------------------
274 -----------------------------------------------------------------------
274 -----------------------------------------------------------------------
275
275
276 -- SPW_EN <= '1';
276 -- SPW_EN <= '1';
277
277
278 spw_clk <= clk_50_s;
278 spw_clk <= clk_50_s;
279 spw_rxtxclk <= spw_clk;
279 spw_rxtxclk <= spw_clk;
280 spw_rxclkn <= NOT spw_rxtxclk;
280 spw_rxclkn <= NOT spw_rxtxclk;
281
281
282 -- PADS for SPW1
282 -- PADS for SPW1
283 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
283 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
284 PORT MAP (spw1_din, dtmp(0));
284 PORT MAP (spw1_din, dtmp(0));
285 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
285 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
286 PORT MAP (spw1_sin, stmp(0));
286 PORT MAP (spw1_sin, stmp(0));
287 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
287 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
288 PORT MAP (spw1_dout, swno.d(0));
288 PORT MAP (spw1_dout, swno.d(0));
289 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
289 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
290 PORT MAP (spw1_sout, swno.s(0));
290 PORT MAP (spw1_sout, swno.s(0));
291 -- PADS FOR SPW2
291 -- PADS FOR SPW2
292 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
292 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
293 PORT MAP (spw2_din, dtmp(1));
293 PORT MAP (spw2_din, dtmp(1));
294 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
294 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
295 PORT MAP (spw2_sin, stmp(1));
295 PORT MAP (spw2_sin, stmp(1));
296 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
296 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
297 PORT MAP (spw2_dout, swno.d(1));
297 PORT MAP (spw2_dout, swno.d(1));
298 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
298 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
299 PORT MAP (spw2_sout, swno.s(1));
299 PORT MAP (spw2_sout, swno.s(1));
300
300
301 -- GRSPW PHY
301 -- GRSPW PHY
302 --spw1_input: if CFG_SPW_GRSPW = 1 generate
302 --spw1_input: if CFG_SPW_GRSPW = 1 generate
303 spw_inputloop : FOR j IN 0 TO 1 GENERATE
303 spw_inputloop : FOR j IN 0 TO 1 GENERATE
304 spw_phy0 : grspw_phy
304 spw_phy0 : grspw_phy
305 GENERIC MAP(
305 GENERIC MAP(
306 tech => apa3e,
306 tech => apa3e,
307 rxclkbuftype => 1,
307 rxclkbuftype => 1,
308 scantest => 0)
308 scantest => 0)
309 PORT MAP(
309 PORT MAP(
310 rxrst => swno.rxrst,
310 rxrst => swno.rxrst,
311 di => dtmp(j),
311 di => dtmp(j),
312 si => stmp(j),
312 si => stmp(j),
313 rxclko => spw_rxclk(j),
313 rxclko => spw_rxclk(j),
314 do => swni.d(j),
314 do => swni.d(j),
315 ndo => swni.nd(j*5+4 DOWNTO j*5),
315 ndo => swni.nd(j*5+4 DOWNTO j*5),
316 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
316 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
317 END GENERATE spw_inputloop;
317 END GENERATE spw_inputloop;
318
318
319 -- SPW core
319 -- SPW core
320 sw0 : grspwm GENERIC MAP(
320 sw0 : grspwm GENERIC MAP(
321 tech => apa3e,
321 tech => apa3e,
322 hindex => 1,
322 hindex => 1,
323 pindex => 5,
323 pindex => 5,
324 paddr => 5,
324 paddr => 5,
325 pirq => 11,
325 pirq => 11,
326 sysfreq => 25000, -- CPU_FREQ
326 sysfreq => 25000, -- CPU_FREQ
327 rmap => 1,
327 rmap => 1,
328 rmapcrc => 1,
328 rmapcrc => 1,
329 fifosize1 => 16,
329 fifosize1 => 16,
330 fifosize2 => 16,
330 fifosize2 => 16,
331 rxclkbuftype => 1,
331 rxclkbuftype => 1,
332 rxunaligned => 0,
332 rxunaligned => 0,
333 rmapbufs => 4,
333 rmapbufs => 4,
334 ft => 0,
334 ft => 0,
335 netlist => 0,
335 netlist => 0,
336 ports => 2,
336 ports => 2,
337 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
337 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
338 memtech => apa3e,
338 memtech => apa3e,
339 destkey => 2,
339 destkey => 2,
340 spwcore => 1
340 spwcore => 1
341 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
341 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
342 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
342 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
343 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
343 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
344 )
344 )
345 PORT MAP(rstn, clk_25, spw_rxclk(0),
345 PORT MAP(rstn, clk_25, spw_rxclk(0),
346 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
346 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
347 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
347 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
348 swni, swno);
348 swni, swno);
349
349
350 swni.tickin <= '0';
350 swni.tickin <= '0';
351 swni.rmapen <= '1';
351 swni.rmapen <= '1';
352 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
352 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
353 swni.tickinraw <= '0';
353 swni.tickinraw <= '0';
354 swni.timein <= (OTHERS => '0');
354 swni.timein <= (OTHERS => '0');
355 swni.dcrstval <= (OTHERS => '0');
355 swni.dcrstval <= (OTHERS => '0');
356 swni.timerrstval <= (OTHERS => '0');
356 swni.timerrstval <= (OTHERS => '0');
357
357
358 -------------------------------------------------------------------------------
358 -------------------------------------------------------------------------------
359 -- LFR ------------------------------------------------------------------------
359 -- LFR ------------------------------------------------------------------------
360 -------------------------------------------------------------------------------
360 -------------------------------------------------------------------------------
361 LFR_rstn <= LFR_soft_rstn AND rstn;
361 LFR_rstn <= LFR_soft_rstn AND rstn;
362
362
363 lpp_lfr_1 : lpp_lfr
363 lpp_lfr_1 : lpp_lfr
364 GENERIC MAP (
364 GENERIC MAP (
365 Mem_use => use_RAM,
365 Mem_use => use_RAM,
366 nb_data_by_buffer_size => 32,
366 nb_data_by_buffer_size => 32,
367 --nb_word_by_buffer_size => 30,
367 --nb_word_by_buffer_size => 30,
368 nb_snapshot_param_size => 32,
368 nb_snapshot_param_size => 32,
369 delta_vector_size => 32,
369 delta_vector_size => 32,
370 delta_vector_size_f0_2 => 7, -- log2(96)
370 delta_vector_size_f0_2 => 7, -- log2(96)
371 pindex => 15,
371 pindex => 15,
372 paddr => 15,
372 paddr => 15,
373 pmask => 16#fff#,
373 pmask => 16#fff#,
374 pirq_ms => 6,
374 pirq_ms => 6,
375 pirq_wfp => 14,
375 pirq_wfp => 14,
376 hindex => 2,
376 hindex => 2,
377 top_lfr_version => X"01012D") -- aa.bb.cc version
377 top_lfr_version => X"01012F") -- aa.bb.cc version
378 -- AA : BOARD NUMBER
378 -- AA : BOARD NUMBER
379 -- 0 => MINI_LFR
379 -- 0 => MINI_LFR
380 -- 1 => EM
380 -- 1 => EM
381 PORT MAP (
381 PORT MAP (
382 clk => clk_25,
382 clk => clk_25,
383 rstn => LFR_rstn,
383 rstn => LFR_rstn,
384 sample_B => sample_s(2 DOWNTO 0),
384 sample_B => sample_s(2 DOWNTO 0),
385 sample_E => sample_s(7 DOWNTO 3),
385 sample_E => sample_s(7 DOWNTO 3),
386 sample_val => sample_val,
386 sample_val => sample_val,
387 apbi => apbi_ext,
387 apbi => apbi_ext,
388 apbo => apbo_ext(15),
388 apbo => apbo_ext(15),
389 ahbi => ahbi_m_ext,
389 ahbi => ahbi_m_ext,
390 ahbo => ahbo_m_ext(2),
390 ahbo => ahbo_m_ext(2),
391 coarse_time => coarse_time,
391 coarse_time => coarse_time,
392 fine_time => fine_time,
392 fine_time => fine_time,
393 data_shaping_BW => bias_fail_sw,
393 data_shaping_BW => bias_fail_sw,
394 debug_vector => OPEN,
394 debug_vector => OPEN,
395 debug_vector_ms => OPEN); --,
395 debug_vector_ms => OPEN); --,
396 --observation_vector_0 => OPEN,
396 --observation_vector_0 => OPEN,
397 --observation_vector_1 => OPEN,
397 --observation_vector_1 => OPEN,
398 --observation_reg => observation_reg);
398 --observation_reg => observation_reg);
399
399
400
400
401 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
401 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
402 sample_s(I) <= sample(I) & '0' & '0';
402 sample_s(I) <= sample(I) & '0' & '0';
403 END GENERATE all_sample;
403 END GENERATE all_sample;
404 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
404 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
405
405
406 -----------------------------------------------------------------------------
406 -----------------------------------------------------------------------------
407 --
407 --
408 -----------------------------------------------------------------------------
408 -----------------------------------------------------------------------------
409 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
409 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
410 GENERIC MAP (
410 GENERIC MAP (
411 ChanelCount => 9,
411 ChanelCount => 9,
412 ncycle_cnv_high => 13,
412 ncycle_cnv_high => 13,
413 ncycle_cnv => 25,
413 ncycle_cnv => 25,
414 FILTER_ENABLED => 16#FF#)
414 FILTER_ENABLED => 16#FF#)
415 PORT MAP (
415 PORT MAP (
416 cnv_clk => clk_24,
416 cnv_clk => clk_24,
417 cnv_rstn => rstn,
417 cnv_rstn => rstn,
418 cnv => ADC_smpclk_s,
418 cnv => ADC_smpclk_s,
419 clk => clk_25,
419 clk => clk_25,
420 rstn => rstn,
420 rstn => rstn,
421 ADC_data => ADC_data,
421 ADC_data => ADC_data,
422 ADC_nOE => ADC_OEB_bar_CH_s,
422 ADC_nOE => ADC_OEB_bar_CH_s,
423 sample => sample,
423 sample => sample,
424 sample_val => sample_val);
424 sample_val => sample_val);
425
425
426 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
426 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
427
427
428 ADC_smpclk <= ADC_smpclk_s;
428 ADC_smpclk <= ADC_smpclk_s;
429 HK_smpclk <= ADC_smpclk_s;
429 HK_smpclk <= ADC_smpclk_s;
430
430
431 TAG8 <= ADC_smpclk_s;
431 TAG8 <= ADC_smpclk_s;
432
432
433 -----------------------------------------------------------------------------
433 -----------------------------------------------------------------------------
434 -- HK
434 -- HK
435 -----------------------------------------------------------------------------
435 -----------------------------------------------------------------------------
436 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
436 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
437
437
438 lpp_lfr_hk_1: lpp_lfr_hk
438 lpp_lfr_hk_1: lpp_lfr_hk
439 GENERIC MAP (
439 GENERIC MAP (
440 pindex => 7,
440 pindex => 7,
441 paddr => 7,
441 paddr => 7,
442 pmask => 16#fff#)
442 pmask => 16#fff#)
443 PORT MAP (
443 PORT MAP (
444 clk => clk_25,
444 clk => clk_25,
445 rstn => rstn,
445 rstn => rstn,
446
446
447 apbi => apbi_ext,
447 apbi => apbi_ext,
448 apbo => apbo_ext(7),
448 apbo => apbo_ext(7),
449
449
450 sample_val => sample_val,
450 sample_val => sample_val,
451 sample => sample_s(8),
451 sample => sample_s(8),
452 HK_SEL => HK_SEL);
452 HK_SEL => HK_SEL);
453
453
454 END beh;
454 END beh;
Show file before | Show file after | Hide comments
@@ -1,720 +1,746
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 --
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
199 --
200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
198
202
199 BEGIN -- beh
203 BEGIN -- beh
200
204
201 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
202 -- CLK
206 -- CLK
203 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
204
208
205 --PROCESS(clk_50)
209 --PROCESS(clk_50)
206 --BEGIN
210 --BEGIN
207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
208 -- clk_50_s <= NOT clk_50_s;
212 -- clk_50_s <= NOT clk_50_s;
209 -- END IF;
213 -- END IF;
210 --END PROCESS;
214 --END PROCESS;
211
215
212 --PROCESS(clk_50_s)
216 --PROCESS(clk_50_s)
213 --BEGIN
217 --BEGIN
214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
215 -- clk_25 <= NOT clk_25;
219 -- clk_25 <= NOT clk_25;
216 -- END IF;
220 -- END IF;
217 --END PROCESS;
221 --END PROCESS;
218
222
219 --PROCESS(clk_49)
223 --PROCESS(clk_49)
220 --BEGIN
224 --BEGIN
221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
222 -- clk_24 <= NOT clk_24;
226 -- clk_24 <= NOT clk_24;
223 -- END IF;
227 -- END IF;
224 --END PROCESS;
228 --END PROCESS;
225
229
226 --PROCESS(clk_25)
230 --PROCESS(clk_25)
227 --BEGIN
231 --BEGIN
228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
229 -- rstn_25 <= reset;
233 -- rstn_25 <= reset;
230 -- END IF;
234 -- END IF;
231 --END PROCESS;
235 --END PROCESS;
232
236
233 PROCESS (clk_50, reset)
237 PROCESS (clk_50, reset)
234 BEGIN -- PROCESS
238 BEGIN -- PROCESS
235 IF reset = '0' THEN -- asynchronous reset (active low)
239 IF reset = '0' THEN -- asynchronous reset (active low)
236 clk_50_s <= '0';
240 clk_50_s <= '0';
237 rstn_50 <= '0';
241 rstn_50 <= '0';
238 rstn_50_d1 <= '0';
242 rstn_50_d1 <= '0';
239 rstn_50_d2 <= '0';
243 rstn_50_d2 <= '0';
240 rstn_50_d3 <= '0';
244 rstn_50_d3 <= '0';
241
245
242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
243 clk_50_s <= NOT clk_50_s;
247 clk_50_s <= NOT clk_50_s;
244 rstn_50_d1 <= '1';
248 rstn_50_d1 <= '1';
245 rstn_50_d2 <= rstn_50_d1;
249 rstn_50_d2 <= rstn_50_d1;
246 rstn_50_d3 <= rstn_50_d2;
250 rstn_50_d3 <= rstn_50_d2;
247 rstn_50 <= rstn_50_d3;
251 rstn_50 <= rstn_50_d3;
248 END IF;
252 END IF;
249 END PROCESS;
253 END PROCESS;
250
254
251 PROCESS (clk_50_s, rstn_50)
255 PROCESS (clk_50_s, rstn_50)
252 BEGIN -- PROCESS
256 BEGIN -- PROCESS
253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
254 clk_25 <= '0';
258 clk_25 <= '0';
255 rstn_25 <= '0';
259 rstn_25 <= '0';
256 rstn_25_d1 <= '0';
260 rstn_25_d1 <= '0';
257 rstn_25_d2 <= '0';
261 rstn_25_d2 <= '0';
258 rstn_25_d3 <= '0';
262 rstn_25_d3 <= '0';
259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
260 clk_25 <= NOT clk_25;
264 clk_25 <= NOT clk_25;
261 rstn_25_d1 <= '1';
265 rstn_25_d1 <= '1';
262 rstn_25_d2 <= rstn_25_d1;
266 rstn_25_d2 <= rstn_25_d1;
263 rstn_25_d3 <= rstn_25_d2;
267 rstn_25_d3 <= rstn_25_d2;
264 rstn_25 <= rstn_25_d3;
268 rstn_25 <= rstn_25_d3;
265 END IF;
269 END IF;
266 END PROCESS;
270 END PROCESS;
267
271
268 PROCESS (clk_49, reset)
272 PROCESS (clk_49, reset)
269 BEGIN -- PROCESS
273 BEGIN -- PROCESS
270 IF reset = '0' THEN -- asynchronous reset (active low)
274 IF reset = '0' THEN -- asynchronous reset (active low)
271 clk_24 <= '0';
275 clk_24 <= '0';
272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
273 clk_24 <= NOT clk_24;
277 clk_24 <= NOT clk_24;
274 END IF;
278 END IF;
275 END PROCESS;
279 END PROCESS;
276
280
277 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
278
282
279 PROCESS (clk_25, rstn_25)
283 PROCESS (clk_25, rstn_25)
280 BEGIN -- PROCESS
284 BEGIN -- PROCESS
281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
282 LED0 <= '0';
286 LED0 <= '0';
283 LED1 <= '0';
287 LED1 <= '0';
284 LED2 <= '0';
288 LED2 <= '0';
285 --IO1 <= '0';
289 --IO1 <= '0';
286 --IO2 <= '1';
290 --IO2 <= '1';
287 --IO3 <= '0';
291 --IO3 <= '0';
288 --IO4 <= '0';
292 --IO4 <= '0';
289 --IO5 <= '0';
293 --IO5 <= '0';
290 --IO6 <= '0';
294 --IO6 <= '0';
291 --IO7 <= '0';
295 --IO7 <= '0';
292 --IO8 <= '0';
296 --IO8 <= '0';
293 --IO9 <= '0';
297 --IO9 <= '0';
294 --IO10 <= '0';
298 --IO10 <= '0';
295 --IO11 <= '0';
299 --IO11 <= '0';
296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
297 LED0 <= '0';
301 LED0 <= '0';
298 LED1 <= '1';
302 LED1 <= '1';
299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
300 --IO1 <= '1';
304 --IO1 <= '1';
301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
302 --IO3 <= ADC_SDO(0);
306 --IO3 <= ADC_SDO(0);
303 --IO4 <= ADC_SDO(1);
307 --IO4 <= ADC_SDO(1);
304 --IO5 <= ADC_SDO(2);
308 --IO5 <= ADC_SDO(2);
305 --IO6 <= ADC_SDO(3);
309 --IO6 <= ADC_SDO(3);
306 --IO7 <= ADC_SDO(4);
310 --IO7 <= ADC_SDO(4);
307 --IO8 <= ADC_SDO(5);
311 --IO8 <= ADC_SDO(5);
308 --IO9 <= ADC_SDO(6);
312 --IO9 <= ADC_SDO(6);
309 --IO10 <= ADC_SDO(7);
313 --IO10 <= ADC_SDO(7);
310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
311 END IF;
315 END IF;
312 END PROCESS;
316 END PROCESS;
313
317
314 PROCESS (clk_24, rstn_25)
318 PROCESS (clk_24, rstn_25)
315 BEGIN -- PROCESS
319 BEGIN -- PROCESS
316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
317 I00_s <= '0';
321 I00_s <= '0';
318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
319 I00_s <= NOT I00_s;
323 I00_s <= NOT I00_s;
320 END IF;
324 END IF;
321 END PROCESS;
325 END PROCESS;
322 -- IO0 <= I00_s;
326 -- IO0 <= I00_s;
323
327
324 --UARTs
328 --UARTs
325 nCTS1 <= '1';
329 nCTS1 <= '1';
326 nCTS2 <= '1';
330 nCTS2 <= '1';
327 nDCD2 <= '1';
331 nDCD2 <= '1';
328
332
329 --EXT CONNECTOR
333 --EXT CONNECTOR
330
334
331 --SPACE WIRE
335 --SPACE WIRE
332
336
333 leon3_soc_1 : leon3_soc
337 leon3_soc_1 : leon3_soc
334 GENERIC MAP (
338 GENERIC MAP (
335 fabtech => apa3e,
339 fabtech => apa3e,
336 memtech => apa3e,
340 memtech => apa3e,
337 padtech => inferred,
341 padtech => inferred,
338 clktech => inferred,
342 clktech => inferred,
339 disas => 0,
343 disas => 0,
340 dbguart => 0,
344 dbguart => 0,
341 pclow => 2,
345 pclow => 2,
342 clk_freq => 25000,
346 clk_freq => 25000,
343 NB_CPU => 1,
347 NB_CPU => 1,
344 ENABLE_FPU => 1,
348 ENABLE_FPU => 1,
345 FPU_NETLIST => 0,
349 FPU_NETLIST => 0,
346 ENABLE_DSU => 1,
350 ENABLE_DSU => 1,
347 ENABLE_AHB_UART => 1,
351 ENABLE_AHB_UART => 1,
348 ENABLE_APB_UART => 1,
352 ENABLE_APB_UART => 1,
349 ENABLE_IRQMP => 1,
353 ENABLE_IRQMP => 1,
350 ENABLE_GPT => 1,
354 ENABLE_GPT => 1,
351 NB_AHB_MASTER => NB_AHB_MASTER,
355 NB_AHB_MASTER => NB_AHB_MASTER,
352 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 NB_AHB_SLAVE => NB_AHB_SLAVE,
353 NB_APB_SLAVE => NB_APB_SLAVE,
357 NB_APB_SLAVE => NB_APB_SLAVE,
354 ADDRESS_SIZE => 20,
358 ADDRESS_SIZE => 20,
355 USES_IAP_MEMCTRLR => 0)
359 USES_IAP_MEMCTRLR => 0)
356 PORT MAP (
360 PORT MAP (
357 clk => clk_25,
361 clk => clk_25,
358 reset => rstn_25,
362 reset => rstn_25,
359 errorn => errorn,
363 errorn => errorn,
360 ahbrxd => TXD1,
364 ahbrxd => TXD1,
361 ahbtxd => RXD1,
365 ahbtxd => RXD1,
362 urxd1 => TXD2,
366 urxd1 => TXD2,
363 utxd1 => RXD2,
367 utxd1 => RXD2,
364 address => SRAM_A,
368 address => SRAM_A,
365 data => SRAM_DQ,
369 data => SRAM_DQ,
366 nSRAM_BE0 => SRAM_nBE(0),
370 nSRAM_BE0 => SRAM_nBE(0),
367 nSRAM_BE1 => SRAM_nBE(1),
371 nSRAM_BE1 => SRAM_nBE(1),
368 nSRAM_BE2 => SRAM_nBE(2),
372 nSRAM_BE2 => SRAM_nBE(2),
369 nSRAM_BE3 => SRAM_nBE(3),
373 nSRAM_BE3 => SRAM_nBE(3),
370 nSRAM_WE => SRAM_nWE,
374 nSRAM_WE => SRAM_nWE,
371 nSRAM_CE => SRAM_CE_s,
375 nSRAM_CE => SRAM_CE_s,
372 nSRAM_OE => SRAM_nOE,
376 nSRAM_OE => SRAM_nOE,
373 nSRAM_READY => '0',
377 nSRAM_READY => '0',
374 SRAM_MBE => OPEN,
378 SRAM_MBE => OPEN,
375 apbi_ext => apbi_ext,
379 apbi_ext => apbi_ext,
376 apbo_ext => apbo_ext,
380 apbo_ext => apbo_ext,
377 ahbi_s_ext => ahbi_s_ext,
381 ahbi_s_ext => ahbi_s_ext,
378 ahbo_s_ext => ahbo_s_ext,
382 ahbo_s_ext => ahbo_s_ext,
379 ahbi_m_ext => ahbi_m_ext,
383 ahbi_m_ext => ahbi_m_ext,
380 ahbo_m_ext => ahbo_m_ext);
384 ahbo_m_ext => ahbo_m_ext);
381
385
382 SRAM_CE <= SRAM_CE_s(0);
386 SRAM_CE <= SRAM_CE_s(0);
383 -------------------------------------------------------------------------------
387 -------------------------------------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
388 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
385 -------------------------------------------------------------------------------
389 -------------------------------------------------------------------------------
386 apb_lfr_time_management_1 : apb_lfr_time_management
390 apb_lfr_time_management_1 : apb_lfr_time_management
387 GENERIC MAP (
391 GENERIC MAP (
388 pindex => 6,
392 pindex => 6,
389 paddr => 6,
393 paddr => 6,
390 pmask => 16#fff#,
394 pmask => 16#fff#,
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
393 PORT MAP (
397 PORT MAP (
394 clk25MHz => clk_25,
398 clk25MHz => clk_25,
395 clk24_576MHz => clk_24, -- 49.152MHz/2
399 clk24_576MHz => clk_24, -- 49.152MHz/2
396 resetn => rstn_25,
400 resetn => rstn_25,
397 grspw_tick => swno.tickout,
401 grspw_tick => swno.tickout,
398 apbi => apbi_ext,
402 apbi => apbi_ext,
399 apbo => apbo_ext(6),
403 apbo => apbo_ext(6),
400 coarse_time => coarse_time,
404 coarse_time => coarse_time,
401 fine_time => fine_time,
405 fine_time => fine_time,
402 LFR_soft_rstn => LFR_soft_rstn
406 LFR_soft_rstn => LFR_soft_rstn
403 );
407 );
404
408
405 -----------------------------------------------------------------------
409 -----------------------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
410 --- SpaceWire --------------------------------------------------------
407 -----------------------------------------------------------------------
411 -----------------------------------------------------------------------
408
412
409 SPW_EN <= '1';
413 SPW_EN <= '1';
410
414
411 spw_clk <= clk_50_s;
415 spw_clk <= clk_50_s;
412 spw_rxtxclk <= spw_clk;
416 spw_rxtxclk <= spw_clk;
413 spw_rxclkn <= NOT spw_rxtxclk;
417 spw_rxclkn <= NOT spw_rxtxclk;
414
418
415 -- PADS for SPW1
419 -- PADS for SPW1
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
420 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
421 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
422 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_SIN, stmp(0));
423 PORT MAP (SPW_NOM_SIN, stmp(0));
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
424 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
425 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
426 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
427 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 -- PADS FOR SPW2
428 -- PADS FOR SPW2
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
429 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 PORT MAP (SPW_RED_SIN, dtmp(1));
430 PORT MAP (SPW_RED_SIN, dtmp(1));
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
431 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 PORT MAP (SPW_RED_DIN, stmp(1));
432 PORT MAP (SPW_RED_DIN, stmp(1));
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
433 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
434 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
435 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
436 PORT MAP (SPW_RED_SOUT, swno.s(1));
433
437
434 -- GRSPW PHY
438 -- GRSPW PHY
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
439 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
440 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 spw_phy0 : grspw_phy
441 spw_phy0 : grspw_phy
438 GENERIC MAP(
442 GENERIC MAP(
439 tech => apa3e,
443 tech => apa3e,
440 rxclkbuftype => 1,
444 rxclkbuftype => 1,
441 scantest => 0)
445 scantest => 0)
442 PORT MAP(
446 PORT MAP(
443 rxrst => swno.rxrst,
447 rxrst => swno.rxrst,
444 di => dtmp(j),
448 di => dtmp(j),
445 si => stmp(j),
449 si => stmp(j),
446 rxclko => spw_rxclk(j),
450 rxclko => spw_rxclk(j),
447 do => swni.d(j),
451 do => swni.d(j),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
452 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
453 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 END GENERATE spw_inputloop;
454 END GENERATE spw_inputloop;
451
455
452 swni.rmapnodeaddr <= (OTHERS => '0');
456 swni.rmapnodeaddr <= (OTHERS => '0');
453
457
454 -- SPW core
458 -- SPW core
455 sw0 : grspwm GENERIC MAP(
459 sw0 : grspwm GENERIC MAP(
456 tech => apa3e,
460 tech => apa3e,
457 hindex => 1,
461 hindex => 1,
458 pindex => 5,
462 pindex => 5,
459 paddr => 5,
463 paddr => 5,
460 pirq => 11,
464 pirq => 11,
461 sysfreq => 25000, -- CPU_FREQ
465 sysfreq => 25000, -- CPU_FREQ
462 rmap => 1,
466 rmap => 1,
463 rmapcrc => 1,
467 rmapcrc => 1,
464 fifosize1 => 16,
468 fifosize1 => 16,
465 fifosize2 => 16,
469 fifosize2 => 16,
466 rxclkbuftype => 1,
470 rxclkbuftype => 1,
467 rxunaligned => 0,
471 rxunaligned => 0,
468 rmapbufs => 4,
472 rmapbufs => 4,
469 ft => 0,
473 ft => 0,
470 netlist => 0,
474 netlist => 0,
471 ports => 2,
475 ports => 2,
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
476 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 memtech => apa3e,
477 memtech => apa3e,
474 destkey => 2,
478 destkey => 2,
475 spwcore => 1
479 spwcore => 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
480 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
481 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
482 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 )
483 )
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
484 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
485 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
486 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 swni, swno);
487 swni, swno);
484
488
485 swni.tickin <= '0';
489 swni.tickin <= '0';
486 swni.rmapen <= '1';
490 swni.rmapen <= '1';
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
491 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 swni.tickinraw <= '0';
492 swni.tickinraw <= '0';
489 swni.timein <= (OTHERS => '0');
493 swni.timein <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
494 swni.dcrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
495 swni.timerrstval <= (OTHERS => '0');
492
496
493 -------------------------------------------------------------------------------
497 -------------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
498 -- LFR ------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
499 -------------------------------------------------------------------------------
496
500
497
501
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
502 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 --LFR_rstn <= rstn_25;
503 --LFR_rstn <= rstn_25;
500
504
501 lpp_lfr_1 : lpp_lfr
505 lpp_lfr_1 : lpp_lfr
502 GENERIC MAP (
506 GENERIC MAP (
503 Mem_use => use_RAM,
507 Mem_use => use_RAM,
504 nb_data_by_buffer_size => 32,
508 nb_data_by_buffer_size => 32,
505 nb_snapshot_param_size => 32,
509 nb_snapshot_param_size => 32,
506 delta_vector_size => 32,
510 delta_vector_size => 32,
507 delta_vector_size_f0_2 => 7, -- log2(96)
511 delta_vector_size_f0_2 => 7, -- log2(96)
508 pindex => 15,
512 pindex => 15,
509 paddr => 15,
513 paddr => 15,
510 pmask => 16#fff#,
514 pmask => 16#fff#,
511 pirq_ms => 6,
515 pirq_ms => 6,
512 pirq_wfp => 14,
516 pirq_wfp => 14,
513 hindex => 2,
517 hindex => 2,
514 top_lfr_version => X"00012C") -- aa.bb.cc version
518 top_lfr_version => X"00012E") -- aa.bb.cc version
515 PORT MAP (
519 PORT MAP (
516 clk => clk_25,
520 clk => clk_25,
517 rstn => LFR_rstn,
521 rstn => LFR_rstn,
518 sample_B => sample_s(2 DOWNTO 0),
522 sample_B => sample_s(2 DOWNTO 0),
519 sample_E => sample_s(7 DOWNTO 3),
523 sample_E => sample_s(7 DOWNTO 3),
520 sample_val => sample_val,
524 sample_val => sample_val,
521 apbi => apbi_ext,
525 apbi => apbi_ext,
522 apbo => apbo_ext(15),
526 apbo => apbo_ext(15),
523 ahbi => ahbi_m_ext,
527 ahbi => ahbi_m_ext,
524 ahbo => ahbo_m_ext(2),
528 ahbo => ahbo_m_ext(2),
525 coarse_time => coarse_time,
529 coarse_time => coarse_time,
526 fine_time => fine_time,
530 fine_time => fine_time,
527 data_shaping_BW => bias_fail_sw_sig,
531 data_shaping_BW => bias_fail_sw_sig,
528 debug_vector => lfr_debug_vector,
532 debug_vector => lfr_debug_vector,
529 debug_vector_ms => lfr_debug_vector_ms
533 debug_vector_ms => lfr_debug_vector_ms
530 );
534 );
531
535
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
536 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
537 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
538 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
539 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 IO0 <= rstn_25;
540 IO0 <= rstn_25;
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
541 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
542 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
543 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
544 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
545 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
546 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
547 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544
548
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
549 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
550 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 END GENERATE all_sample;
551 END GENERATE all_sample;
548
552
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
553 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 GENERIC MAP(
554 GENERIC MAP(
551 ChannelCount => 8,
555 ChannelCount => 8,
552 SampleNbBits => 14,
556 SampleNbBits => 14,
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
557 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
558 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 PORT MAP (
559 PORT MAP (
556 -- CONV
560 -- CONV
557 cnv_clk => clk_24,
561 cnv_clk => clk_24,
558 cnv_rstn => rstn_25,
562 cnv_rstn => rstn_25,
559 cnv => ADC_nCS_sig,
563 cnv => ADC_nCS_sig,
560 -- DATA
564 -- DATA
561 clk => clk_25,
565 clk => clk_25,
562 rstn => rstn_25,
566 rstn => rstn_25,
563 sck => ADC_CLK_sig,
567 sck => ADC_CLK_sig,
564 sdo => ADC_SDO_sig,
568 sdo => ADC_SDO_sig,
565 -- SAMPLE
569 -- SAMPLE
566 sample => sample,
570 sample => sample,
567 sample_val => sample_val);
571 sample_val => sample_val);
568
572
569 --IO10 <= ADC_SDO_sig(5);
573 --IO10 <= ADC_SDO_sig(5);
570 --IO9 <= ADC_SDO_sig(4);
574 --IO9 <= ADC_SDO_sig(4);
571 --IO8 <= ADC_SDO_sig(3);
575 --IO8 <= ADC_SDO_sig(3);
572
576
573 ADC_nCS <= ADC_nCS_sig;
577 ADC_nCS <= ADC_nCS_sig;
574 ADC_CLK <= ADC_CLK_sig;
578 ADC_CLK <= ADC_CLK_sig;
575 ADC_SDO_sig <= ADC_SDO;
579 ADC_SDO_sig <= ADC_SDO;
576
580
581 lpp_lfr_hk_1: lpp_lfr_hk
582 GENERIC MAP (
583 pindex => 7,
584 paddr => 7,
585 pmask => 16#fff#)
586 PORT MAP (
587 clk => clk_25,
588 rstn => rstn_25,
589
590 apbi => apbi_ext,
591 apbo => apbo_ext(7),
592
593 sample_val => sample_val,
594 sample => sample_hk,
595 HK_SEL => HK_SEL);
596
597 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
598 "0010001000100010" WHEN HK_SEL = "10" ELSE
599 "0100010001000100" WHEN HK_SEL = "10" ELSE
600 (OTHERS => '0');
601
602
577 ----------------------------------------------------------------------
603 ----------------------------------------------------------------------
578 --- GPIO -----------------------------------------------------------
604 --- GPIO -----------------------------------------------------------
579 ----------------------------------------------------------------------
605 ----------------------------------------------------------------------
580
606
581 grgpio0 : grgpio
607 grgpio0 : grgpio
582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
608 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
609 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
584
610
585 gpioi.sig_en <= (OTHERS => '0');
611 gpioi.sig_en <= (OTHERS => '0');
586 gpioi.sig_in <= (OTHERS => '0');
612 gpioi.sig_in <= (OTHERS => '0');
587 gpioi.din <= (OTHERS => '0');
613 gpioi.din <= (OTHERS => '0');
588 --pio_pad_0 : iopad
614 --pio_pad_0 : iopad
589 -- GENERIC MAP (tech => CFG_PADTECH)
615 -- GENERIC MAP (tech => CFG_PADTECH)
590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
616 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
591 --pio_pad_1 : iopad
617 --pio_pad_1 : iopad
592 -- GENERIC MAP (tech => CFG_PADTECH)
618 -- GENERIC MAP (tech => CFG_PADTECH)
593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
619 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
594 --pio_pad_2 : iopad
620 --pio_pad_2 : iopad
595 -- GENERIC MAP (tech => CFG_PADTECH)
621 -- GENERIC MAP (tech => CFG_PADTECH)
596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
622 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
597 --pio_pad_3 : iopad
623 --pio_pad_3 : iopad
598 -- GENERIC MAP (tech => CFG_PADTECH)
624 -- GENERIC MAP (tech => CFG_PADTECH)
599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
625 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
600 --pio_pad_4 : iopad
626 --pio_pad_4 : iopad
601 -- GENERIC MAP (tech => CFG_PADTECH)
627 -- GENERIC MAP (tech => CFG_PADTECH)
602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
628 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
603 --pio_pad_5 : iopad
629 --pio_pad_5 : iopad
604 -- GENERIC MAP (tech => CFG_PADTECH)
630 -- GENERIC MAP (tech => CFG_PADTECH)
605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
631 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
606 --pio_pad_6 : iopad
632 --pio_pad_6 : iopad
607 -- GENERIC MAP (tech => CFG_PADTECH)
633 -- GENERIC MAP (tech => CFG_PADTECH)
608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
634 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
609 --pio_pad_7 : iopad
635 --pio_pad_7 : iopad
610 -- GENERIC MAP (tech => CFG_PADTECH)
636 -- GENERIC MAP (tech => CFG_PADTECH)
611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
637 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
612
638
613 PROCESS (clk_25, rstn_25)
639 PROCESS (clk_25, rstn_25)
614 BEGIN -- PROCESS
640 BEGIN -- PROCESS
615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
641 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
616 -- --IO0 <= '0';
642 -- --IO0 <= '0';
617 -- IO1 <= '0';
643 -- IO1 <= '0';
618 -- IO2 <= '0';
644 -- IO2 <= '0';
619 -- IO3 <= '0';
645 -- IO3 <= '0';
620 -- IO4 <= '0';
646 -- IO4 <= '0';
621 -- IO5 <= '0';
647 -- IO5 <= '0';
622 -- IO6 <= '0';
648 -- IO6 <= '0';
623 -- IO7 <= '0';
649 -- IO7 <= '0';
624 IO8 <= '0';
650 IO8 <= '0';
625 IO9 <= '0';
651 IO9 <= '0';
626 IO10 <= '0';
652 IO10 <= '0';
627 IO11 <= '0';
653 IO11 <= '0';
628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
654 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
629 CASE gpioo.dout(2 DOWNTO 0) IS
655 CASE gpioo.dout(2 DOWNTO 0) IS
630 WHEN "011" =>
656 WHEN "011" =>
631 -- --IO0 <= observation_reg(0 );
657 -- --IO0 <= observation_reg(0 );
632 -- IO1 <= observation_reg(1 );
658 -- IO1 <= observation_reg(1 );
633 -- IO2 <= observation_reg(2 );
659 -- IO2 <= observation_reg(2 );
634 -- IO3 <= observation_reg(3 );
660 -- IO3 <= observation_reg(3 );
635 -- IO4 <= observation_reg(4 );
661 -- IO4 <= observation_reg(4 );
636 -- IO5 <= observation_reg(5 );
662 -- IO5 <= observation_reg(5 );
637 -- IO6 <= observation_reg(6 );
663 -- IO6 <= observation_reg(6 );
638 -- IO7 <= observation_reg(7 );
664 -- IO7 <= observation_reg(7 );
639 IO8 <= observation_reg(8);
665 IO8 <= observation_reg(8);
640 IO9 <= observation_reg(9);
666 IO9 <= observation_reg(9);
641 IO10 <= observation_reg(10);
667 IO10 <= observation_reg(10);
642 IO11 <= observation_reg(11);
668 IO11 <= observation_reg(11);
643 WHEN "001" =>
669 WHEN "001" =>
644 -- --IO0 <= observation_reg(0 + 12);
670 -- --IO0 <= observation_reg(0 + 12);
645 -- IO1 <= observation_reg(1 + 12);
671 -- IO1 <= observation_reg(1 + 12);
646 -- IO2 <= observation_reg(2 + 12);
672 -- IO2 <= observation_reg(2 + 12);
647 -- IO3 <= observation_reg(3 + 12);
673 -- IO3 <= observation_reg(3 + 12);
648 -- IO4 <= observation_reg(4 + 12);
674 -- IO4 <= observation_reg(4 + 12);
649 -- IO5 <= observation_reg(5 + 12);
675 -- IO5 <= observation_reg(5 + 12);
650 -- IO6 <= observation_reg(6 + 12);
676 -- IO6 <= observation_reg(6 + 12);
651 -- IO7 <= observation_reg(7 + 12);
677 -- IO7 <= observation_reg(7 + 12);
652 IO8 <= observation_reg(8 + 12);
678 IO8 <= observation_reg(8 + 12);
653 IO9 <= observation_reg(9 + 12);
679 IO9 <= observation_reg(9 + 12);
654 IO10 <= observation_reg(10 + 12);
680 IO10 <= observation_reg(10 + 12);
655 IO11 <= observation_reg(11 + 12);
681 IO11 <= observation_reg(11 + 12);
656 WHEN "010" =>
682 WHEN "010" =>
657 -- --IO0 <= observation_reg(0 + 12 + 12);
683 -- --IO0 <= observation_reg(0 + 12 + 12);
658 -- IO1 <= observation_reg(1 + 12 + 12);
684 -- IO1 <= observation_reg(1 + 12 + 12);
659 -- IO2 <= observation_reg(2 + 12 + 12);
685 -- IO2 <= observation_reg(2 + 12 + 12);
660 -- IO3 <= observation_reg(3 + 12 + 12);
686 -- IO3 <= observation_reg(3 + 12 + 12);
661 -- IO4 <= observation_reg(4 + 12 + 12);
687 -- IO4 <= observation_reg(4 + 12 + 12);
662 -- IO5 <= observation_reg(5 + 12 + 12);
688 -- IO5 <= observation_reg(5 + 12 + 12);
663 -- IO6 <= observation_reg(6 + 12 + 12);
689 -- IO6 <= observation_reg(6 + 12 + 12);
664 -- IO7 <= observation_reg(7 + 12 + 12);
690 -- IO7 <= observation_reg(7 + 12 + 12);
665 IO8 <= '0';
691 IO8 <= '0';
666 IO9 <= '0';
692 IO9 <= '0';
667 IO10 <= '0';
693 IO10 <= '0';
668 IO11 <= '0';
694 IO11 <= '0';
669 WHEN "000" =>
695 WHEN "000" =>
670 -- --IO0 <= observation_vector_0(0 );
696 -- --IO0 <= observation_vector_0(0 );
671 -- IO1 <= observation_vector_0(1 );
697 -- IO1 <= observation_vector_0(1 );
672 -- IO2 <= observation_vector_0(2 );
698 -- IO2 <= observation_vector_0(2 );
673 -- IO3 <= observation_vector_0(3 );
699 -- IO3 <= observation_vector_0(3 );
674 -- IO4 <= observation_vector_0(4 );
700 -- IO4 <= observation_vector_0(4 );
675 -- IO5 <= observation_vector_0(5 );
701 -- IO5 <= observation_vector_0(5 );
676 -- IO6 <= observation_vector_0(6 );
702 -- IO6 <= observation_vector_0(6 );
677 -- IO7 <= observation_vector_0(7 );
703 -- IO7 <= observation_vector_0(7 );
678 IO8 <= observation_vector_0(8);
704 IO8 <= observation_vector_0(8);
679 IO9 <= observation_vector_0(9);
705 IO9 <= observation_vector_0(9);
680 IO10 <= observation_vector_0(10);
706 IO10 <= observation_vector_0(10);
681 IO11 <= observation_vector_0(11);
707 IO11 <= observation_vector_0(11);
682 WHEN "100" =>
708 WHEN "100" =>
683 -- --IO0 <= observation_vector_1(0 );
709 -- --IO0 <= observation_vector_1(0 );
684 -- IO1 <= observation_vector_1(1 );
710 -- IO1 <= observation_vector_1(1 );
685 -- IO2 <= observation_vector_1(2 );
711 -- IO2 <= observation_vector_1(2 );
686 -- IO3 <= observation_vector_1(3 );
712 -- IO3 <= observation_vector_1(3 );
687 -- IO4 <= observation_vector_1(4 );
713 -- IO4 <= observation_vector_1(4 );
688 -- IO5 <= observation_vector_1(5 );
714 -- IO5 <= observation_vector_1(5 );
689 -- IO6 <= observation_vector_1(6 );
715 -- IO6 <= observation_vector_1(6 );
690 -- IO7 <= observation_vector_1(7 );
716 -- IO7 <= observation_vector_1(7 );
691 IO8 <= observation_vector_1(8);
717 IO8 <= observation_vector_1(8);
692 IO9 <= observation_vector_1(9);
718 IO9 <= observation_vector_1(9);
693 IO10 <= observation_vector_1(10);
719 IO10 <= observation_vector_1(10);
694 IO11 <= observation_vector_1(11);
720 IO11 <= observation_vector_1(11);
695 WHEN OTHERS => NULL;
721 WHEN OTHERS => NULL;
696 END CASE;
722 END CASE;
697
723
698 END IF;
724 END IF;
699 END PROCESS;
725 END PROCESS;
700 -----------------------------------------------------------------------------
726 -----------------------------------------------------------------------------
701 --
727 --
702 -----------------------------------------------------------------------------
728 -----------------------------------------------------------------------------
703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
729 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
730 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 7 AND I /= 11 AND I /= 15 GENERATE
705 apbo_ext(I) <= apb_none;
731 apbo_ext(I) <= apb_none;
706 END GENERATE apbo_ext_not_used;
732 END GENERATE apbo_ext_not_used;
707 END GENERATE all_apbo_ext;
733 END GENERATE all_apbo_ext;
708
734
709
735
710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
736 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
711 ahbo_s_ext(I) <= ahbs_none;
737 ahbo_s_ext(I) <= ahbs_none;
712 END GENERATE all_ahbo_ext;
738 END GENERATE all_ahbo_ext;
713
739
714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
740 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
741 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
716 ahbo_m_ext(I) <= ahbm_none;
742 ahbo_m_ext(I) <= ahbm_none;
717 END GENERATE ahbo_m_ext_not_used;
743 END GENERATE ahbo_m_ext_not_used;
718 END GENERATE all_ahbo_m_ext;
744 END GENERATE all_ahbo_m_ext;
719
745
720 END beh;
746 END beh;
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