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LFR EQM2
pellion -
r620:c6d218df80ba simu_with_Leon3
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@@ -48,7 +48,7 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
48 SIGNAL SMP_CLK_RisingEdge_1 : STD_LOGIC := '0';
48 SIGNAL SMP_CLK_RisingEdge_1 : STD_LOGIC := '0';
49 SIGNAL SMP_CLK_RisingEdge_2 : STD_LOGIC := '0';
49 SIGNAL SMP_CLK_RisingEdge_2 : STD_LOGIC := '0';
50
50
51 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
51 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth DOWNTO 0) := (OTHERS => '0');
52 SIGNAL shiftcnt : INTEGER := 0;
52 SIGNAL shiftcnt : INTEGER := 0;
53 SIGNAL shifting : STD_LOGIC := '0';
53 SIGNAL shifting : STD_LOGIC := '0';
54
54
@@ -64,7 +64,9 BEGIN
64 END GENERATE;
64 END GENERATE;
65
65
66 LSB : IF MSBFIRST = 0 GENERATE
66 LSB : IF MSBFIRST = 0 GENERATE
67 DATA_s(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
67 all_bits: FOR I IN 0 TO datawidth-1 GENERATE
68 DATA_s(datawidth-1 - I) <= DATA(I);
69 END GENERATE all_bits;
68 END GENERATE;
70 END GENERATE;
69
71
70 -----------------------------------------------------------------------------
72 -----------------------------------------------------------------------------
@@ -89,7 +91,7 BEGIN
89 --
91 --
90 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
91 SCLK <= SCLK_s;
93 SCLK <= SCLK_s;
92 DOUT <= SHIFTREG(datawidth-1);
94 DOUT <= SHIFTREG(datawidth);
93
95
94 PROCESS (clk, rstn)
96 PROCESS (clk, rstn)
95 BEGIN -- PROCESS
97 BEGIN -- PROCESS
@@ -123,9 +125,9 BEGIN
123
125
124 IF shifting = '1' THEN
126 IF shifting = '1' THEN
125 shiftcnt <= shiftcnt + 1;
127 shiftcnt <= shiftcnt + 1;
126 SHIFTREG(datawidth-1 DOWNTO 1) <= SHIFTREG (datawidth-2 DOWNTO 0);
128 SHIFTREG(datawidth DOWNTO 1) <= SHIFTREG (datawidth-1 DOWNTO 0);
127 ELSE
129 ELSE
128 SHIFTREG <= DATA_s;
130 SHIFTREG(datawidth-1 DOWNTO 0) <= DATA_s;
129 shiftcnt <= 0;
131 shiftcnt <= 0;
130 END IF;
132 END IF;
131
133
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@@ -165,7 +165,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
165 TYPE lpp_SpectralMatrix_regs IS RECORD
165 TYPE lpp_SpectralMatrix_regs IS RECORD
166 config_active_interruption_onNewMatrix : STD_LOGIC;
166 config_active_interruption_onNewMatrix : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
168 -- config_ms_run : STD_LOGIC;
168 config_ms_run : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
@@ -310,12 +310,12 BEGIN -- beh
310 data_shaping_R2 <= reg_wp.data_shaping_R2;
310 data_shaping_R2 <= reg_wp.data_shaping_R2;
311
311
312 delta_snapshot <= reg_wp.delta_snapshot;
312 delta_snapshot <= reg_wp.delta_snapshot;
313 delta_f0 <= reg_wp.delta_f0;
313 delta_f0 <= reg_wp.delta_f0; --<= X"0001280A";
314 delta_f0_2 <= reg_wp.delta_f0_2;
314 delta_f0_2 <= reg_wp.delta_f0_2; --<= "0110000";
315 delta_f1 <= reg_wp.delta_f1;
315 delta_f1 <= reg_wp.delta_f1; --<= X"0001283F";
316 delta_f2 <= reg_wp.delta_f2;
316 delta_f2 <= reg_wp.delta_f2; --<= X"000127FF";
317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;--<= X"00000A7F";
318 nb_snapshot_param <= reg_wp.nb_snapshot_param;
318 nb_snapshot_param <= reg_wp.nb_snapshot_param;--<= X"00000A80";
319
319
320 enable_f0 <= reg_wp.enable_f0;
320 enable_f0 <= reg_wp.enable_f0;
321 enable_f1 <= reg_wp.enable_f1;
321 enable_f1 <= reg_wp.enable_f1;
@@ -335,10 +335,10 BEGIN -- beh
335
335
336 start_date <= reg_wp.start_date;
336 start_date <= reg_wp.start_date;
337
337
338 length_matrix_f0 <= reg_sp.length_matrix;
338 length_matrix_f0 <= "00" & X"0000C8";--reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
339 length_matrix_f1 <= "00" & X"0000C8";--reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
340 length_matrix_f2 <= "00" & X"0000C8";--reg_sp.length_matrix;
341 wfp_length_buffer <= reg_wp.length_buffer;
341 wfp_length_buffer <= "00" & X"0001F8"; --<= reg_wp.length_buffer;
342
342
343
343
344
344
@@ -358,22 +358,23 BEGIN -- beh
358 END PROCESS;
358 END PROCESS;
359
359
360
360
361 reg_sp.length_matrix <= "00" & X"0000C8";
361 -- reg_sp.length_matrix <= "00" & X"0000C8";
362 reg_sp.config_active_interruption_onError <= '0';
362 -- reg_sp.config_active_interruption_onError <= '0';
363 reg_wp.delta_f0 <= X"0001280A";
363 --reg_wp.delta_f0 <= X"0001280A";
364 reg_wp.delta_f0_2 <= "0110000";
364 --reg_wp.delta_f0_2 <= "0110000";
365 reg_wp.delta_f1 <= X"0001283F";
365 --reg_wp.delta_f1 <= X"0001283F";
366 reg_wp.delta_f2 <= X"000127FF";
366 --reg_wp.delta_f2 <= X"000127FF";
367 reg_wp.nb_data_by_buffer <= X"00000A7F";
367 --reg_wp.nb_data_by_buffer <= X"00000A7F";
368 reg_wp.nb_snapshot_param <= X"00000A80";
368 --reg_wp.nb_snapshot_param <= X"00000A80";
369 reg_wp.length_buffer <= "00" & X"0001F8"; --25 .. 0
369 --reg_wp.length_buffer <= "00" & X"0001F8"; --25 .. 0
370
370
371 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
371 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
372 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
372 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
373 BEGIN -- PROCESS lpp_dma_top
373 BEGIN -- PROCESS lpp_dma_top
374 IF HRESETn = '0' THEN -- asynchronous reset (active low)
374 IF HRESETn = '0' THEN -- asynchronous reset (active low)
375 reg_sp.config_active_interruption_onNewMatrix <= '0';
375 reg_sp.config_active_interruption_onNewMatrix <= '0';
376 -- reg_sp.config_ms_run <= '0';
376 reg_sp.config_active_interruption_onError <= '0';
377 reg_sp.config_ms_run <= '0';
377 reg_sp.status_ready_matrix_f0_0 <= '0';
378 reg_sp.status_ready_matrix_f0_0 <= '0';
378 reg_sp.status_ready_matrix_f1_0 <= '0';
379 reg_sp.status_ready_matrix_f1_0 <= '0';
379 reg_sp.status_ready_matrix_f2_0 <= '0';
380 reg_sp.status_ready_matrix_f2_0 <= '0';
@@ -391,7 +392,7 BEGIN -- beh
391 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
392 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
392 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
393 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
393
394
394 -- reg_sp.length_matrix <= (OTHERS => '0');
395 reg_sp.length_matrix <= (OTHERS => '0');
395
396
396 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
397 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
397 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
398 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
@@ -429,16 +430,16 BEGIN -- beh
429 reg_wp.status_new_err <= (OTHERS => '0');
430 reg_wp.status_new_err <= (OTHERS => '0');
430 reg_wp.error_buffer_full <= (OTHERS => '0');
431 reg_wp.error_buffer_full <= (OTHERS => '0');
431 reg_wp.delta_snapshot <= (OTHERS => '0');
432 reg_wp.delta_snapshot <= (OTHERS => '0');
432 --reg_wp.delta_f0 <= (OTHERS => '0');
433 reg_wp.delta_f0 <= (OTHERS => '0');
433 --reg_wp.delta_f0_2 <= (OTHERS => '0');
434 reg_wp.delta_f0_2 <= (OTHERS => '0');
434 --reg_wp.delta_f1 <= (OTHERS => '0');
435 reg_wp.delta_f1 <= (OTHERS => '0');
435 --reg_wp.delta_f2 <= (OTHERS => '0');
436 reg_wp.delta_f2 <= (OTHERS => '0');
436 --reg_wp.nb_data_by_buffer <= (OTHERS => '0');
437 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
437 --reg_wp.nb_snapshot_param <= (OTHERS => '0');
438 reg_wp.nb_snapshot_param <= (OTHERS => '0');
438 reg_wp.start_date <= (OTHERS => '1');
439 reg_wp.start_date <= (OTHERS => '1');
439
440
440 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
441 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
441 --reg_wp.length_buffer <= (OTHERS => '0');
442 reg_wp.length_buffer <= (OTHERS => '0');
442
443
443 pirq_temp <= (OTHERS => '0');
444 pirq_temp <= (OTHERS => '0');
444
445
@@ -482,8 +483,8 BEGIN -- beh
482
483
483 WHEN ADDR_LFR_SM_CONFIG =>
484 WHEN ADDR_LFR_SM_CONFIG =>
484 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
485 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
485 -- prdata(1) <= reg_sp.config_active_interruption_onError;
486 prdata(1) <= reg_sp.config_active_interruption_onError;
486 -- prdata(2) <= reg_sp.config_ms_run;
487 prdata(2) <= reg_sp.config_ms_run;
487
488
488 WHEN ADDR_LFR_SM_STATUS =>
489 WHEN ADDR_LFR_SM_STATUS =>
489 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
490 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
@@ -516,7 +517,7 BEGIN -- beh
516 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
517 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
517 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
518 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
518 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
519 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
519 -- WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
520 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
520 ---------------------------------------------------------------------
521 ---------------------------------------------------------------------
521 WHEN ADDR_LFR_WP_DATASHAPING =>
522 WHEN ADDR_LFR_WP_DATASHAPING =>
522 prdata(0) <= reg_wp.data_shaping_BW;
523 prdata(0) <= reg_wp.data_shaping_BW;
@@ -549,12 +550,12 BEGIN -- beh
549 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
550 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
550
551
551 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
552 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
552 -- WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
553 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
553 -- WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
554 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
554 -- WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
555 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
555 -- WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
556 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
556 -- WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
557 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
557 -- WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
558 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
558 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
559 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
559
560
560 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
561 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
@@ -577,7 +578,7 BEGIN -- beh
577 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
578 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
578 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
579 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
579
580
580 -- WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
581 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
581
582
582 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
583 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
583 prdata(31 DOWNTO 16) <= (OTHERS => '0');
584 prdata(31 DOWNTO 16) <= (OTHERS => '0');
@@ -596,8 +597,8 BEGIN -- beh
596 --
597 --
597 WHEN ADDR_LFR_SM_CONFIG =>
598 WHEN ADDR_LFR_SM_CONFIG =>
598 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
599 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
599 -- reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
600 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
600 -- reg_sp.config_ms_run <= apbi.pwdata(2);
601 reg_sp.config_ms_run <= apbi.pwdata(2);
601
602
602 WHEN ADDR_LFR_SM_STATUS =>
603 WHEN ADDR_LFR_SM_STATUS =>
603 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
604 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
@@ -617,7 +618,7 BEGIN -- beh
617 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
618 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
618 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
619 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
619
620
620 -- WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
621 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
621 ---------------------------------------------------------------------
622 ---------------------------------------------------------------------
622 WHEN ADDR_LFR_WP_DATASHAPING =>
623 WHEN ADDR_LFR_WP_DATASHAPING =>
623 reg_wp.data_shaping_BW <= apbi.pwdata(0);
624 reg_wp.data_shaping_BW <= apbi.pwdata(0);
@@ -651,16 +652,16 BEGIN -- beh
651 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I);
652 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I);
652 END LOOP all_reg_wp_status_bit;
653 END LOOP all_reg_wp_status_bit;
653
654
654 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
655 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
655 --WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
656 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
656 --WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
657 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
657 --WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
658 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
658 --WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
659 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
659 --WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
660 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
660 --WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
661 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
661 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
662 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
662
663
663 --WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
664 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
664
665
665 WHEN OTHERS => NULL;
666 WHEN OTHERS => NULL;
666 END CASE;
667 END CASE;
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