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Added AdvancedTrigger IP....
Alexis Jeandet -
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
42 set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
43 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
44 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
45 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
47 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
48 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
49 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
61 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
62 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
63 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
65 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
66 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
67 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
71 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
72 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
73 address[7] SRAM_A[8] SRAM_A[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
75 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
76 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
77 address[7] SRAM_A[8] SRAM_A[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
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1 PACKAGE=\"\"
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 DESIGNER_PACKAGE=FBGA
12 DESIGNER_PINS=324
13
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
16 MGCPART=$(PART)
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
19
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1 # Actel Physical design constraints file
2 # Generated file
3
4 # Version: 9.1 SP3 9.1.3.4
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
6 # Date generated: Tue Oct 18 08:21:45 2011
7
8
9 #
10 # IO banks setting
11 #
12
13
14 #
15 # I/O constraints
16 #
17
18 set_io clk100MHz \
19 -pinname F7 \
20 -fixed yes \
21 -DIRECTION Inout
22
23 set_io clk49_152MHz \
24 -pinname F8 \
25 -fixed yes \
26 -DIRECTION Inout
27
28 set_io reset \
29 -pinname J12 \
30 -fixed yes \
31 -DIRECTION Inout
32 #====================================================================
33 # BPs
34 #====================================================================
35 set_io BP0 \
36 -pinname F16 \
37 -fixed yes \
38 -DIRECTION Inout
39
40 set_io BP1 \
41 -pinname F13 \
42 -fixed yes \
43 -DIRECTION Inout
44
45 #====================================================================
46 # LEDs
47 #====================================================================
48
49 set_io LED0 \
50 -pinname R13 \
51 -fixed yes \
52 -DIRECTION Inout
53
54 set_io LED1 \
55 -pinname P13 \
56 -fixed yes \
57 -DIRECTION Inout
58
59 set_io LED2 \
60 -pinname N11 \
61 -fixed yes \
62 -DIRECTION Inout
63
64 #====================================================================
65 # TRIGGERs
66 #====================================================================
67
68 set_io DISCO1_TRIG1 \
69 -pinname J15 \
70 -fixed yes \
71 -DIRECTION Inout
72
73 set_io DISCO2_TRIG1 \
74 -pinname H15 \
75 -fixed yes \
76 -DIRECTION Inout
77
78 set_io DISCO3_TRIG1 \
79 -pinname D14 \
80 -fixed yes \
81 -DIRECTION Inout
82
83 set_io DISCO4_TRIG1 \
84 -pinname A8 \
85 -fixed yes \
86 -DIRECTION Inout
87
88 #====================================================================
89 # UARTS
90 #====================================================================
91
92 set_io TXD1 \
93 -pinname N12 \
94 -fixed yes \
95 -DIRECTION Inout
96
97 set_io RXD1 \
98 -pinname N10 \
99 -fixed yes \
100 -DIRECTION Inout
101
102 set_io nCTS1 \
103 -pinname L13 \
104 -fixed yes \
105 -DIRECTION Inout
106
107 set_io nRTS1 \
108 -pinname M9 \
109 -fixed yes \
110 -DIRECTION Inout
111
112
113 set_io TXD2 \
114 -pinname G6 \
115 -fixed yes \
116 -DIRECTION Inout
117
118 set_io RXD2 \
119 -pinname F6 \
120 -fixed yes \
121 -DIRECTION Inout
122
123
124
125 #====================================================================
126 # SPACE WIRE
127 #====================================================================
128
129 set_io SPW_EN \
130 -pinname U9 \
131 -fixed yes \
132 -DIRECTION Inout
133
134 #================================
135 # NOMINAL LINK
136 #================================
137
138 set_io SPW_NOM_DIN \
139 -pinname T9 \
140 -fixed yes \
141 -DIRECTION Inout
142
143 set_io SPW_NOM_SIN \
144 -pinname T8 \
145 -fixed yes \
146 -DIRECTION Inout
147
148 set_io SPW_NOM_DOUT \
149 -pinname U7 \
150 -fixed yes \
151 -DIRECTION Inout
152
153 set_io SPW_NOM_SOUT \
154 -pinname U1 \
155 -fixed yes \
156 -DIRECTION Inout
157
158 #================================
159 # REDUNDANT LINK
160 #================================
161
162 set_io SPW_RED_DIN \
163 -pinname R10 \
164 -fixed yes \
165 -DIRECTION Inout
166
167 set_io SPW_RED_SIN \
168 -pinname T10 \
169 -fixed yes \
170 -DIRECTION Inout
171
172 set_io SPW_RED_DOUT \
173 -pinname V2 \
174 -fixed yes \
175 -DIRECTION Inout
176
177 set_io SPW_RED_SOUT \
178 -pinname T11 \
179 -fixed yes \
180 -DIRECTION Inout
181
182
183 #====================================================================
184 # SRAM
185 #====================================================================
186
187 #================================
188 # SRAM CTRL
189 #================================
190
191 set_io SRAM_nWE \
192 -pinname D4 \
193 -fixed yes \
194 -DIRECTION Inout
195
196 set_io SRAM_CE \
197 -pinname J6 \
198 -fixed yes \
199 -DIRECTION Inout
200
201 set_io SRAM_nOE \
202 -pinname J1 \
203 -fixed yes \
204 -DIRECTION Inout
205
206 set_io SRAM_nBE\[0\] \
207 -pinname N2 \
208 -fixed yes \
209 -DIRECTION Inout
210
211 set_io SRAM_nBE\[1\] \
212 -pinname K5 \
213 -fixed yes \
214 -DIRECTION Inout
215
216 set_io SRAM_nBE\[2\] \
217 -pinname G2 \
218 -fixed yes \
219 -DIRECTION Inout
220
221 set_io SRAM_nBE\[3\] \
222 -pinname J2 \
223 -fixed yes \
224 -DIRECTION Inout
225
226
227 #================================
228 # SRAM ADDRESS
229 #================================
230
231 set_io SRAM_A\[0\] \
232 -pinname A3 \
233 -fixed yes \
234 -DIRECTION Inout
235
236 set_io SRAM_A\[1\] \
237 -pinname A2 \
238 -fixed yes \
239 -DIRECTION Inout
240
241 set_io SRAM_A\[2\] \
242 -pinname B1 \
243 -fixed yes \
244 -DIRECTION Inout
245
246 set_io SRAM_A\[3\] \
247 -pinname C1 \
248 -fixed yes \
249 -DIRECTION Inout
250
251 set_io SRAM_A\[4\] \
252 -pinname D1 \
253 -fixed yes \
254 -DIRECTION Inout
255
256 set_io SRAM_A\[5\] \
257 -pinname B6 \
258 -fixed yes \
259 -DIRECTION Inout
260
261 set_io SRAM_A\[6\] \
262 -pinname F1 \
263 -fixed yes \
264 -DIRECTION Inout
265
266 set_io SRAM_A\[7\] \
267 -pinname C6 \
268 -fixed yes \
269 -DIRECTION Inout
270
271 set_io SRAM_A\[8\] \
272 -pinname H1 \
273 -fixed yes \
274 -DIRECTION Inout
275
276 set_io SRAM_A\[9\] \
277 -pinname A5 \
278 -fixed yes \
279 -DIRECTION Inout
280
281 set_io SRAM_A\[10\] \
282 -pinname D5 \
283 -fixed yes \
284 -DIRECTION Inout
285
286 set_io SRAM_A\[11\] \
287 -pinname K1 \
288 -fixed yes \
289 -DIRECTION Inout
290
291 set_io SRAM_A\[12\] \
292 -pinname A4 \
293 -fixed yes \
294 -DIRECTION Inout
295
296 set_io SRAM_A\[13\] \
297 -pinname E10 \
298 -fixed yes \
299 -DIRECTION Inout
300
301 set_io SRAM_A\[14\] \
302 -pinname C4 \
303 -fixed yes \
304 -DIRECTION Inout
305
306 set_io SRAM_A\[15\] \
307 -pinname G4 \
308 -fixed yes \
309 -DIRECTION Inout
310
311 set_io SRAM_A\[16\] \
312 -pinname K7 \
313 -fixed yes \
314 -DIRECTION Inout
315
316 set_io SRAM_A\[17\] \
317 -pinname F4 \
318 -fixed yes \
319 -DIRECTION Inout
320
321 set_io SRAM_A\[18\] \
322 -pinname K2 \
323 -fixed yes \
324 -DIRECTION Inout
325
326 set_io SRAM_A\[19\] \
327 -pinname E4 \
328 -fixed yes \
329 -DIRECTION Inout
330
331
332 #================================
333 # SRAM DATA
334 #================================
335
336 set_io SRAM_DQ\[0\] \
337 -pinname M3 \
338 -fixed yes \
339 -DIRECTION Inout
340
341 set_io SRAM_DQ\[1\] \
342 -pinname N8 \
343 -fixed yes \
344 -DIRECTION Inout
345
346 set_io SRAM_DQ\[2\] \
347 -pinname M2 \
348 -fixed yes \
349 -DIRECTION Inout
350
351 set_io SRAM_DQ\[3\] \
352 -pinname N9 \
353 -fixed yes \
354 -DIRECTION Inout
355
356 set_io SRAM_DQ\[4\] \
357 -pinname R11 \
358 -fixed yes \
359 -DIRECTION Inout
360
361 set_io SRAM_DQ\[5\] \
362 -pinname K12 \
363 -fixed yes \
364 -DIRECTION Inout
365
366 set_io SRAM_DQ\[6\] \
367 -pinname J4 \
368 -fixed yes \
369 -DIRECTION Inout
370
371 set_io SRAM_DQ\[7\] \
372 -pinname N3 \
373 -fixed yes \
374 -DIRECTION Inout
375
376 set_io SRAM_DQ\[8\] \
377 -pinname M6 \
378 -fixed yes \
379 -DIRECTION Inout
380
381 set_io SRAM_DQ\[9\] \
382 -pinname L3 \
383 -fixed yes \
384 -DIRECTION Inout
385
386 set_io SRAM_DQ\[10\] \
387 -pinname L6 \
388 -fixed yes \
389 -DIRECTION Inout
390
391 set_io SRAM_DQ\[11\] \
392 -pinname K4 \
393 -fixed yes \
394 -DIRECTION Inout
395
396 set_io SRAM_DQ\[12\] \
397 -pinname L4 \
398 -fixed yes \
399 -DIRECTION Inout
400
401 set_io SRAM_DQ\[13\] \
402 -pinname N7 \
403 -fixed yes \
404 -DIRECTION Inout
405
406 set_io SRAM_DQ\[14\] \
407 -pinname M7 \
408 -fixed yes \
409 -DIRECTION Inout
410
411 set_io SRAM_DQ\[15\] \
412 -pinname K6 \
413 -fixed yes \
414 -DIRECTION Inout
415
416 set_io SRAM_DQ\[16\] \
417 -pinname E1 \
418 -fixed yes \
419 -DIRECTION Inout
420
421 set_io SRAM_DQ\[17\] \
422 -pinname J7 \
423 -fixed yes \
424 -DIRECTION Inout
425
426 set_io SRAM_DQ\[18\] \
427 -pinname H4 \
428 -fixed yes \
429 -DIRECTION Inout
430
431 set_io SRAM_DQ\[19\] \
432 -pinname F10 \
433 -fixed yes \
434 -DIRECTION Inout
435
436 set_io SRAM_DQ\[20\] \
437 -pinname B3 \
438 -fixed yes \
439 -DIRECTION Inout
440
441 set_io SRAM_DQ\[21\] \
442 -pinname F3 \
443 -fixed yes \
444 -DIRECTION Inout
445
446 set_io SRAM_DQ\[22\] \
447 -pinname C3 \
448 -fixed yes \
449 -DIRECTION Inout
450
451 set_io SRAM_DQ\[23\] \
452 -pinname G3 \
453 -fixed yes \
454 -DIRECTION Inout
455
456 set_io SRAM_DQ\[24\] \
457 -pinname R6 \
458 -fixed yes \
459 -DIRECTION Inout
460
461 set_io SRAM_DQ\[25\] \
462 -pinname P4 \
463 -fixed yes \
464 -DIRECTION Inout
465
466 set_io SRAM_DQ\[26\] \
467 -pinname R4 \
468 -fixed yes \
469 -DIRECTION Inout
470
471 set_io SRAM_DQ\[27\] \
472 -pinname M4 \
473 -fixed yes \
474 -DIRECTION Inout
475
476 set_io SRAM_DQ\[28\] \
477 -pinname F9 \
478 -fixed yes \
479 -DIRECTION Inout
480
481 set_io SRAM_DQ\[29\] \
482 -pinname B2 \
483 -fixed yes \
484 -DIRECTION Inout
485
486 set_io SRAM_DQ\[30\] \
487 -pinname H3 \
488 -fixed yes \
489 -DIRECTION Inout
490
491 set_io SRAM_DQ\[31\] \
492 -pinname C2 \
493 -fixed yes \
494 -DIRECTION Inout
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 use lpp.lpp_amba.all;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 ENTITY DISCOSPACE_top IS
50
51 PORT (
52 clk100MHz : IN STD_LOGIC;
53 clk49_152MHz : IN STD_LOGIC;
54 reset : IN STD_LOGIC;
55 --BPs
56 BP0 : IN STD_LOGIC;
57 BP1 : IN STD_LOGIC;
58 --LEDs
59 LED0 : OUT STD_LOGIC;
60 LED1 : OUT STD_LOGIC;
61 LED2 : OUT STD_LOGIC;
62 --UARTs
63 TXD1 : IN STD_LOGIC;
64 RXD1 : OUT STD_LOGIC;
65 nCTS1 : OUT STD_LOGIC;
66 nRTS1 : IN STD_LOGIC;
67
68 TXD2 : IN STD_LOGIC;
69 RXD2 : OUT STD_LOGIC;
70 nCTS2 : OUT STD_LOGIC;
71 nDTR2 : IN STD_LOGIC;
72 nRTS2 : IN STD_LOGIC;
73 nDCD2 : OUT STD_LOGIC;
74
75 --EXT CONNECTOR
76 DISCO1_TRIG1 : OUT STD_LOGIC;
77 DISCO2_TRIG1 : OUT STD_LOGIC;
78 DISCO3_TRIG1 : OUT STD_LOGIC;
79 DISCO4_TRIG1 : OUT STD_LOGIC;
80
81 -- MINI LFR ADC INPUTS
82 ADC_nCS : OUT STD_LOGIC;
83 ADC_CLK : OUT STD_LOGIC;
84 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
85 --SPACE WIRE
86 SPW_EN : OUT STD_LOGIC; -- 0 => off
87 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
88 SPW_NOM_SIN : IN STD_LOGIC;
89 SPW_NOM_DOUT : OUT STD_LOGIC;
90 SPW_NOM_SOUT : OUT STD_LOGIC;
91 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
92 SPW_RED_SIN : IN STD_LOGIC;
93 SPW_RED_DOUT : OUT STD_LOGIC;
94 SPW_RED_SOUT : OUT STD_LOGIC;
95
96 -- SRAM
97 SRAM_nWE : OUT STD_LOGIC;
98 SRAM_CE : OUT STD_LOGIC;
99 SRAM_nOE : OUT STD_LOGIC;
100 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
102 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103 );
104
105 END DISCOSPACE_top;
106
107
108 ARCHITECTURE beh OF DISCOSPACE_top IS
109
110 --==========================================================================
111 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
112 -- when enabled, chip enable polarity should be reversed and bank size also
113 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
114 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
115 --==========================================================================
116 CONSTANT USE_IAP_MEMCTRL : integer := 1;
117 --==========================================================================
118
119 SIGNAL clk_50_s : STD_LOGIC := '0';
120 SIGNAL clk_25 : STD_LOGIC := '0';
121 SIGNAL clk_24 : STD_LOGIC := '0';
122 -----------------------------------------------------------------------------
123 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
125 --
126 SIGNAL errorn : STD_LOGIC;
127 --
128 SIGNAL I00_s : STD_LOGIC;
129
130 -- CONSTANTS
131 CONSTANT CFG_PADTECH : INTEGER := inferred;
132 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
143
144 -- Spacewire signals
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
153
154
155 -- AdvancedTrigger
156 SIGNAL Trigger : STD_LOGIC;
157
158 -- AD Converter ADS7886
159 SIGNAL sample : Samples14v(7 DOWNTO 0);
160 SIGNAL sample_s : Samples(7 DOWNTO 0);
161 SIGNAL sample_val : STD_LOGIC;
162 SIGNAL ADC_nCS_sig : STD_LOGIC;
163 SIGNAL ADC_CLK_sig : STD_LOGIC;
164 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
165
166 SIGNAL bias_fail_sw_sig : STD_LOGIC;
167
168
169 -----------------------------------------------------------------------------
170
171 SIGNAL LFR_soft_rstn : STD_LOGIC;
172 SIGNAL LFR_rstn : STD_LOGIC;
173
174
175 SIGNAL rstn_25 : STD_LOGIC;
176 SIGNAL rstn_25_d1 : STD_LOGIC;
177 SIGNAL rstn_25_d2 : STD_LOGIC;
178 SIGNAL rstn_25_d3 : STD_LOGIC;
179
180 SIGNAL rstn_24 : STD_LOGIC;
181 SIGNAL rstn_24_d1 : STD_LOGIC;
182 SIGNAL rstn_24_d2 : STD_LOGIC;
183 SIGNAL rstn_24_d3 : STD_LOGIC;
184
185 SIGNAL rstn_50 : STD_LOGIC;
186 SIGNAL rstn_50_d1 : STD_LOGIC;
187 SIGNAL rstn_50_d2 : STD_LOGIC;
188 SIGNAL rstn_50_d3 : STD_LOGIC;
189 --
190 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
191
192 --
193 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
194 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
195
196 SIGNAL nSRAM_READY : STD_LOGIC;
197
198 BEGIN -- beh
199
200 -----------------------------------------------------------------------------
201 PROCESS (clk100MHz, reset)
202 BEGIN -- PROCESS
203 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
204 clk_50_s <= NOT clk_50_s;
205 END IF;
206 END PROCESS;
207 -----------------------------------------------------------------------------
208
209 PROCESS (clk_50_s, reset)
210 BEGIN -- PROCESS
211 IF reset = '0' THEN -- asynchronous reset (active low)
212 clk_25 <= '0';
213 rstn_25 <= '0';
214 rstn_25_d1 <= '0';
215 rstn_25_d2 <= '0';
216 rstn_25_d3 <= '0';
217 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
218 clk_25 <= NOT clk_25;
219 rstn_25_d1 <= '1';
220 rstn_25_d2 <= rstn_25_d1;
221 rstn_25_d3 <= rstn_25_d2;
222 rstn_25 <= rstn_25_d3;
223 END IF;
224 END PROCESS;
225
226 PROCESS (clk49_152MHz, reset)
227 BEGIN -- PROCESS
228 IF reset = '0' THEN -- asynchronous reset (active low)
229 clk_24 <= '0';
230 rstn_24_d1 <= '0';
231 rstn_24_d2 <= '0';
232 rstn_24_d3 <= '0';
233 rstn_24 <= '0';
234 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
235 clk_24 <= NOT clk_24;
236 rstn_24_d1 <= '1';
237 rstn_24_d2 <= rstn_24_d1;
238 rstn_24_d3 <= rstn_24_d2;
239 rstn_24 <= rstn_24_d3;
240 END IF;
241 END PROCESS;
242
243 -----------------------------------------------------------------------------
244
245 PROCESS (clk_25, rstn_25)
246 BEGIN -- PROCESS
247 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
248 LED0 <= '0';
249 LED1 <= '0';
250 LED2 <= '0';
251 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
252 LED0 <= '0';
253 LED1 <= '1';
254 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
255 END IF;
256 END PROCESS;
257
258 PROCESS (clk49_152MHz, rstn_24)
259 BEGIN -- PROCESS
260 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
261 I00_s <= '0';
262 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
263 I00_s <= NOT I00_s;
264 END IF;
265 END PROCESS;
266
267 --UARTs
268 nCTS1 <= '1';
269 nCTS2 <= '1';
270 nDCD2 <= '1';
271 -- No AHB UART
272 RXD1 <= TXD1;
273
274 --
275
276 leon3_soc_1 : leon3_soc
277 GENERIC MAP (
278 fabtech => apa3e,
279 memtech => apa3e,
280 padtech => inferred,
281 clktech => inferred,
282 disas => 0,
283 dbguart => 0,
284 pclow => 2,
285 clk_freq => 25000,
286 IS_RADHARD => 0,
287 NB_CPU => 1,
288 ENABLE_FPU => 1,
289 FPU_NETLIST => 0,
290 ENABLE_DSU => 1,
291 ENABLE_AHB_UART => 0,
292 ENABLE_APB_UART => 1,
293 ENABLE_IRQMP => 1,
294 ENABLE_GPT => 1,
295 NB_AHB_MASTER => NB_AHB_MASTER,
296 NB_AHB_SLAVE => NB_AHB_SLAVE,
297 NB_APB_SLAVE => NB_APB_SLAVE,
298 ADDRESS_SIZE => 20,
299 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
300 BYPASS_EDAC_MEMCTRLR => '0',
301 SRBANKSZ => 9)
302 PORT MAP (
303 clk => clk_25,
304 reset => rstn_25,
305 errorn => errorn,
306 ahbrxd => OPEN,--TXD1,
307 ahbtxd => OPEN,--RXD1,
308 urxd1 => TXD2,
309 utxd1 => RXD2,
310 address => SRAM_A,
311 data => SRAM_DQ,
312 nSRAM_BE0 => SRAM_nBE(0),
313 nSRAM_BE1 => SRAM_nBE(1),
314 nSRAM_BE2 => SRAM_nBE(2),
315 nSRAM_BE3 => SRAM_nBE(3),
316 nSRAM_WE => SRAM_nWE,
317 nSRAM_CE => SRAM_CE_s,
318 nSRAM_OE => SRAM_nOE,
319 nSRAM_READY => nSRAM_READY,
320 SRAM_MBE => OPEN,
321 apbi_ext => apbi_ext,
322 apbo_ext => apbo_ext,
323 ahbi_s_ext => ahbi_s_ext,
324 ahbo_s_ext => ahbo_s_ext,
325 ahbi_m_ext => ahbi_m_ext,
326 ahbo_m_ext => ahbo_m_ext);
327
328 PROCESS (clk_25, rstn_25)
329 BEGIN -- PROCESS
330 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
331 nSRAM_READY <= '1';
332 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
333 nSRAM_READY <= '1';
334 END IF;
335 END PROCESS;
336
337
338
339 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
340 SRAM_CE <= not SRAM_CE_s(0);
341 END GENERATE;
342
343 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
344 SRAM_CE <= SRAM_CE_s(0);
345 END GENERATE;
346 -------------------------------------------------------------------------------
347 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
348 -------------------------------------------------------------------------------
349 apb_lfr_management_1 : apb_lfr_management
350 GENERIC MAP (
351 tech => apa3e,
352 pindex => 6,
353 paddr => 6,
354 pmask => 16#fff#,
355 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
356 PORT MAP (
357 clk25MHz => clk_25,
358 resetn_25MHz => rstn_25,
359 grspw_tick => swno.tickout,
360 apbi => apbi_ext,
361 apbo => apbo_ext(6),
362 HK_sample => sample_hk,
363 HK_val => sample_val,
364 HK_sel => HK_SEL,
365 DAC_SDO => OPEN,
366 DAC_SCK => OPEN,
367 DAC_SYNC => OPEN,
368 DAC_CAL_EN => OPEN,
369 coarse_time => coarse_time,
370 fine_time => fine_time,
371 LFR_soft_rstn => LFR_soft_rstn
372 );
373
374 -----------------------------------------------------------------------
375 --- SpaceWire --------------------------------------------------------
376 -----------------------------------------------------------------------
377
378 SPW_EN <= '1';
379
380 spw_clk <= clk_50_s;
381 spw_rxtxclk <= spw_clk;
382 spw_rxclkn <= NOT spw_rxtxclk;
383
384 -- PADS for SPW1
385 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
386 PORT MAP (SPW_NOM_DIN, dtmp(0));
387 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
388 PORT MAP (SPW_NOM_SIN, stmp(0));
389 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
390 PORT MAP (SPW_NOM_DOUT, swno.d(0));
391 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
392 PORT MAP (SPW_NOM_SOUT, swno.s(0));
393 -- PADS FOR SPW2
394 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
395 PORT MAP (SPW_RED_SIN, dtmp(1));
396 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
397 PORT MAP (SPW_RED_DIN, stmp(1));
398 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
399 PORT MAP (SPW_RED_DOUT, swno.d(1));
400 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
401 PORT MAP (SPW_RED_SOUT, swno.s(1));
402
403 -- GRSPW PHY
404 spw_inputloop : FOR j IN 0 TO 1 GENERATE
405 spw_phy0 : grspw_phy
406 GENERIC MAP(
407 tech => apa3e,
408 rxclkbuftype => 1,
409 scantest => 0)
410 PORT MAP(
411 rxrst => swno.rxrst,
412 di => dtmp(j),
413 si => stmp(j),
414 rxclko => spw_rxclk(j),
415 do => swni.d(j),
416 ndo => swni.nd(j*5+4 DOWNTO j*5),
417 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
418 END GENERATE spw_inputloop;
419
420 swni.rmapnodeaddr <= (OTHERS => '0');
421
422 -- SPW core
423 sw0 : grspwm GENERIC MAP(
424 tech => apa3e,
425 hindex => 1,
426 pindex => 5,
427 paddr => 5,
428 pirq => 11,
429 sysfreq => 25000, -- CPU_FREQ
430 rmap => 1,
431 rmapcrc => 1,
432 fifosize1 => 16,
433 fifosize2 => 16,
434 rxclkbuftype => 1,
435 rxunaligned => 0,
436 rmapbufs => 4,
437 ft => 0,
438 netlist => 0,
439 ports => 2,
440 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
441 memtech => apa3e,
442 destkey => 2,
443 spwcore => 1
444 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
445 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
446 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
447 )
448 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
449 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
450 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
451 swni, swno);
452
453 swni.tickin <= '0';
454 swni.rmapen <= '1';
455 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
456 swni.tickinraw <= '0';
457 swni.timein <= (OTHERS => '0');
458 swni.dcrstval <= (OTHERS => '0');
459 swni.timerrstval <= (OTHERS => '0');
460
461 -------------------------------------------------------------------------------
462 -- LFR ------------------------------------------------------------------------
463 -------------------------------------------------------------------------------
464
465
466 LFR_rstn <= LFR_soft_rstn AND rstn_25;
467
468 lpp_lfr_1 : lpp_lfr
469 GENERIC MAP (
470 Mem_use => use_RAM,
471 nb_data_by_buffer_size => 32,
472 nb_snapshot_param_size => 32,
473 delta_vector_size => 32,
474 delta_vector_size_f0_2 => 7, -- log2(96)
475 pindex => 15,
476 paddr => 15,
477 pmask => 16#fff#,
478 pirq_ms => 6,
479 pirq_wfp => 14,
480 hindex => 2,
481 top_lfr_version => X"000159") -- aa.bb.cc version
482 PORT MAP (
483 clk => clk_25,
484 rstn => LFR_rstn,
485 sample_B => sample_s(2 DOWNTO 0),
486 sample_E => sample_s(7 DOWNTO 3),
487 sample_val => sample_val,
488 apbi => apbi_ext,
489 apbo => apbo_ext(15),
490 ahbi => ahbi_m_ext,
491 ahbo => ahbo_m_ext(2),
492 coarse_time => coarse_time,
493 fine_time => fine_time,
494 data_shaping_BW => bias_fail_sw_sig,
495 debug_vector => open,
496 debug_vector_ms => open
497 );
498
499 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
500 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
501 END GENERATE all_sample;
502
503 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
504 GENERIC MAP(
505 ChannelCount => 8,
506 SampleNbBits => 14,
507 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
508 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
509 PORT MAP (
510 -- CONV
511 cnv_clk => clk_24,
512 cnv_rstn => rstn_24,
513 cnv => ADC_nCS_sig,
514 -- DATA
515 clk => clk_25,
516 rstn => rstn_25,
517 sck => ADC_CLK_sig,
518 sdo => ADC_SDO_sig,
519 -- SAMPLE
520 sample => sample,
521 sample_val => sample_val);
522
523 ADC_nCS <= ADC_nCS_sig;
524 ADC_CLK <= ADC_CLK_sig;
525 ADC_SDO_sig <= ADC_SDO;
526
527 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
528 "0010001000100010" WHEN HK_SEL = "01" ELSE
529 "0100010001000100" WHEN HK_SEL = "10" ELSE
530 (OTHERS => '0');
531
532
533
534 ----------------------------------------------------------------------
535 --- APB_ADVANCED_TRIGGER -----------------------------------------------------------
536 ----------------------------------------------------------------------
537 advtrig0: APB_ADVANCED_TRIGGER
538 generic map(
539 pindex => 12,
540 paddr => 12)
541 port map(
542 rstn => rstn_25,
543 clk => clk_25,
544 apbi => apbi_ext,
545 apbo => apbo_ext(12),
546
547 SPW_Tickout => swno.tickout,
548 CoarseTime => coarse_time,
549 FineTime => fine_time,
550
551 Trigger => Trigger
552 );
553
554
555 DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
556 PORT MAP (DISCO1_TRIG1, Trigger);
557 DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
558 PORT MAP (DISCO2_TRIG1, Trigger);
559 DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
560 PORT MAP (DISCO3_TRIG1, Trigger);
561 DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
562 PORT MAP (DISCO4_TRIG1, Trigger);
563
564 -----------------------------------------------------------------------------
565 --
566 -----------------------------------------------------------------------------
567 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
568 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 12 AND I /= 15 GENERATE
569 apbo_ext(I) <= apb_none;
570 END GENERATE apbo_ext_not_used;
571 END GENERATE all_apbo_ext;
572
573
574 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
575 ahbo_s_ext(I) <= ahbs_none;
576 END GENERATE all_ahbo_ext;
577
578 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
579 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
580 ahbo_m_ext(I) <= ahbm_none;
581 END GENERATE ahbo_m_ext_not_used;
582 END GENERATE all_ahbo_m_ext;
583
584 END beh; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 use lpp.lpp_amba.all;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 ENTITY DISCOSPACE_top IS
50
51 PORT (
52 clk100MHz : IN STD_LOGIC;
53 clk49_152MHz : IN STD_LOGIC;
54 reset : IN STD_LOGIC;
55 --BPs
56 BP0 : IN STD_LOGIC;
57 BP1 : IN STD_LOGIC;
58 --LEDs
59 LED0 : OUT STD_LOGIC;
60 LED1 : OUT STD_LOGIC;
61 LED2 : OUT STD_LOGIC;
62 --UARTs
63 TXD1 : IN STD_LOGIC;
64 RXD1 : OUT STD_LOGIC;
65 nCTS1 : OUT STD_LOGIC;
66 nRTS1 : IN STD_LOGIC;
67
68 TXD2 : IN STD_LOGIC;
69 RXD2 : OUT STD_LOGIC;
70 nCTS2 : OUT STD_LOGIC;
71 nDTR2 : IN STD_LOGIC;
72 nRTS2 : IN STD_LOGIC;
73 nDCD2 : OUT STD_LOGIC;
74
75 --EXT CONNECTOR
76 DISCO1_TRIG1 : OUT STD_LOGIC;
77 DISCO2_TRIG1 : OUT STD_LOGIC;
78 DISCO3_TRIG1 : OUT STD_LOGIC;
79 DISCO4_TRIG1 : OUT STD_LOGIC;
80
81 -- MINI LFR ADC INPUTS
82 ADC_nCS : OUT STD_LOGIC;
83 ADC_CLK : OUT STD_LOGIC;
84 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
85 --SPACE WIRE
86 SPW_EN : OUT STD_LOGIC; -- 0 => off
87 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
88 SPW_NOM_SIN : IN STD_LOGIC;
89 SPW_NOM_DOUT : OUT STD_LOGIC;
90 SPW_NOM_SOUT : OUT STD_LOGIC;
91 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
92 SPW_RED_SIN : IN STD_LOGIC;
93 SPW_RED_DOUT : OUT STD_LOGIC;
94 SPW_RED_SOUT : OUT STD_LOGIC;
95
96 -- SRAM
97 SRAM_nWE : OUT STD_LOGIC;
98 SRAM_CE : OUT STD_LOGIC;
99 SRAM_nOE : OUT STD_LOGIC;
100 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
102 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103 );
104
105 END DISCOSPACE_top;
106
107
108 ARCHITECTURE beh OF DISCOSPACE_top IS
109
110 --==========================================================================
111 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
112 -- when enabled, chip enable polarity should be reversed and bank size also
113 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
114 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
115 --==========================================================================
116 CONSTANT USE_IAP_MEMCTRL : integer := 1;
117 --==========================================================================
118
119 SIGNAL clk_50_s : STD_LOGIC := '0';
120 SIGNAL clk_25 : STD_LOGIC := '0';
121 SIGNAL clk_24 : STD_LOGIC := '0';
122 -----------------------------------------------------------------------------
123 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
125 --
126 SIGNAL errorn : STD_LOGIC;
127 --
128 SIGNAL I00_s : STD_LOGIC;
129
130 -- CONSTANTS
131 CONSTANT CFG_PADTECH : INTEGER := inferred;
132 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
143
144 -- Spacewire signals
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
153
154
155 -- AdvancedTrigger
156 SIGNAL Trigger : STD_LOGIC;
157
158 -- AD Converter ADS7886
159 SIGNAL sample : Samples14v(7 DOWNTO 0);
160 SIGNAL sample_s : Samples(7 DOWNTO 0);
161 SIGNAL sample_val : STD_LOGIC;
162 SIGNAL ADC_nCS_sig : STD_LOGIC;
163 SIGNAL ADC_CLK_sig : STD_LOGIC;
164 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
165
166 SIGNAL bias_fail_sw_sig : STD_LOGIC;
167
168
169 -----------------------------------------------------------------------------
170
171 SIGNAL LFR_soft_rstn : STD_LOGIC;
172 SIGNAL LFR_rstn : STD_LOGIC;
173
174
175 SIGNAL rstn_25 : STD_LOGIC;
176 SIGNAL rstn_25_d1 : STD_LOGIC;
177 SIGNAL rstn_25_d2 : STD_LOGIC;
178 SIGNAL rstn_25_d3 : STD_LOGIC;
179
180 SIGNAL rstn_24 : STD_LOGIC;
181 SIGNAL rstn_24_d1 : STD_LOGIC;
182 SIGNAL rstn_24_d2 : STD_LOGIC;
183 SIGNAL rstn_24_d3 : STD_LOGIC;
184
185 SIGNAL rstn_50 : STD_LOGIC;
186 SIGNAL rstn_50_d1 : STD_LOGIC;
187 SIGNAL rstn_50_d2 : STD_LOGIC;
188 SIGNAL rstn_50_d3 : STD_LOGIC;
189 --
190 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
191
192 --
193 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
194 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
195
196 SIGNAL nSRAM_READY : STD_LOGIC;
197
198 BEGIN -- beh
199
200 -----------------------------------------------------------------------------
201 PROCESS (clk100MHz, reset)
202 BEGIN -- PROCESS
203 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
204 clk_50_s <= NOT clk_50_s;
205 END IF;
206 END PROCESS;
207 -----------------------------------------------------------------------------
208
209 PROCESS (clk_50_s, reset)
210 BEGIN -- PROCESS
211 IF reset = '0' THEN -- asynchronous reset (active low)
212 clk_25 <= '0';
213 rstn_25 <= '0';
214 rstn_25_d1 <= '0';
215 rstn_25_d2 <= '0';
216 rstn_25_d3 <= '0';
217 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
218 clk_25 <= NOT clk_25;
219 rstn_25_d1 <= '1';
220 rstn_25_d2 <= rstn_25_d1;
221 rstn_25_d3 <= rstn_25_d2;
222 rstn_25 <= rstn_25_d3;
223 END IF;
224 END PROCESS;
225
226 PROCESS (clk49_152MHz, reset)
227 BEGIN -- PROCESS
228 IF reset = '0' THEN -- asynchronous reset (active low)
229 clk_24 <= '0';
230 rstn_24_d1 <= '0';
231 rstn_24_d2 <= '0';
232 rstn_24_d3 <= '0';
233 rstn_24 <= '0';
234 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
235 clk_24 <= NOT clk_24;
236 rstn_24_d1 <= '1';
237 rstn_24_d2 <= rstn_24_d1;
238 rstn_24_d3 <= rstn_24_d2;
239 rstn_24 <= rstn_24_d3;
240 END IF;
241 END PROCESS;
242
243 -----------------------------------------------------------------------------
244
245 PROCESS (clk_25, rstn_25)
246 BEGIN -- PROCESS
247 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
248 LED0 <= '0';
249 LED1 <= '0';
250 LED2 <= '0';
251 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
252 LED0 <= '0';
253 LED1 <= '1';
254 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
255 END IF;
256 END PROCESS;
257
258 PROCESS (clk49_152MHz, rstn_24)
259 BEGIN -- PROCESS
260 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
261 I00_s <= '0';
262 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
263 I00_s <= NOT I00_s;
264 END IF;
265 END PROCESS;
266
267 --UARTs
268 nCTS1 <= '1';
269 nCTS2 <= '1';
270 nDCD2 <= '1';
271 -- No AHB UART
272 RXD1 <= TXD1;
273
274 --
275
276 leon3_soc_1 : leon3_soc
277 GENERIC MAP (
278 fabtech => apa3e,
279 memtech => apa3e,
280 padtech => inferred,
281 clktech => inferred,
282 disas => 0,
283 dbguart => 0,
284 pclow => 2,
285 clk_freq => 25000,
286 IS_RADHARD => 0,
287 NB_CPU => 1,
288 ENABLE_FPU => 1,
289 FPU_NETLIST => 0,
290 ENABLE_DSU => 1,
291 ENABLE_AHB_UART => 0,
292 ENABLE_APB_UART => 1,
293 ENABLE_IRQMP => 1,
294 ENABLE_GPT => 1,
295 NB_AHB_MASTER => NB_AHB_MASTER,
296 NB_AHB_SLAVE => NB_AHB_SLAVE,
297 NB_APB_SLAVE => NB_APB_SLAVE,
298 ADDRESS_SIZE => 20,
299 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
300 BYPASS_EDAC_MEMCTRLR => '0',
301 SRBANKSZ => 9)
302 PORT MAP (
303 clk => clk_25,
304 reset => rstn_25,
305 errorn => errorn,
306 ahbrxd => OPEN,--TXD1,
307 ahbtxd => OPEN,--RXD1,
308 urxd1 => TXD2,
309 utxd1 => RXD2,
310 address => SRAM_A,
311 data => SRAM_DQ,
312 nSRAM_BE0 => SRAM_nBE(0),
313 nSRAM_BE1 => SRAM_nBE(1),
314 nSRAM_BE2 => SRAM_nBE(2),
315 nSRAM_BE3 => SRAM_nBE(3),
316 nSRAM_WE => SRAM_nWE,
317 nSRAM_CE => SRAM_CE_s,
318 nSRAM_OE => SRAM_nOE,
319 nSRAM_READY => nSRAM_READY,
320 SRAM_MBE => OPEN,
321 apbi_ext => apbi_ext,
322 apbo_ext => apbo_ext,
323 ahbi_s_ext => ahbi_s_ext,
324 ahbo_s_ext => ahbo_s_ext,
325 ahbi_m_ext => ahbi_m_ext,
326 ahbo_m_ext => ahbo_m_ext);
327
328 PROCESS (clk_25, rstn_25)
329 BEGIN -- PROCESS
330 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
331 nSRAM_READY <= '1';
332 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
333 nSRAM_READY <= '1';
334 END IF;
335 END PROCESS;
336
337
338
339 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
340 SRAM_CE <= not SRAM_CE_s(0);
341 END GENERATE;
342
343 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
344 SRAM_CE <= SRAM_CE_s(0);
345 END GENERATE;
346 -------------------------------------------------------------------------------
347 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
348 -------------------------------------------------------------------------------
349 apb_lfr_management_1 : apb_lfr_management
350 GENERIC MAP (
351 tech => apa3e,
352 pindex => 6,
353 paddr => 6,
354 pmask => 16#fff#,
355 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
356 PORT MAP (
357 clk25MHz => clk_25,
358 resetn_25MHz => rstn_25,
359 grspw_tick => swno.tickout,
360 apbi => apbi_ext,
361 apbo => apbo_ext(6),
362 HK_sample => sample_hk,
363 HK_val => sample_val,
364 HK_sel => HK_SEL,
365 DAC_SDO => OPEN,
366 DAC_SCK => OPEN,
367 DAC_SYNC => OPEN,
368 DAC_CAL_EN => OPEN,
369 coarse_time => coarse_time,
370 fine_time => fine_time,
371 LFR_soft_rstn => LFR_soft_rstn
372 );
373
374 -----------------------------------------------------------------------
375 --- SpaceWire --------------------------------------------------------
376 -----------------------------------------------------------------------
377
378 SPW_EN <= '1';
379
380 spw_clk <= clk_50_s;
381 spw_rxtxclk <= spw_clk;
382 spw_rxclkn <= NOT spw_rxtxclk;
383
384 -- PADS for SPW1
385 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
386 PORT MAP (SPW_NOM_DIN, dtmp(0));
387 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
388 PORT MAP (SPW_NOM_SIN, stmp(0));
389 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
390 PORT MAP (SPW_NOM_DOUT, swno.d(0));
391 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
392 PORT MAP (SPW_NOM_SOUT, swno.s(0));
393 -- PADS FOR SPW2
394 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
395 PORT MAP (SPW_RED_SIN, dtmp(1));
396 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
397 PORT MAP (SPW_RED_DIN, stmp(1));
398 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
399 PORT MAP (SPW_RED_DOUT, swno.d(1));
400 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
401 PORT MAP (SPW_RED_SOUT, swno.s(1));
402
403 -- GRSPW PHY
404 spw_inputloop : FOR j IN 0 TO 1 GENERATE
405 spw_phy0 : grspw_phy
406 GENERIC MAP(
407 tech => apa3e,
408 rxclkbuftype => 1,
409 scantest => 0)
410 PORT MAP(
411 rxrst => swno.rxrst,
412 di => dtmp(j),
413 si => stmp(j),
414 rxclko => spw_rxclk(j),
415 do => swni.d(j),
416 ndo => swni.nd(j*5+4 DOWNTO j*5),
417 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
418 END GENERATE spw_inputloop;
419
420 swni.rmapnodeaddr <= (OTHERS => '0');
421
422 -- SPW core
423 sw0 : grspwm GENERIC MAP(
424 tech => apa3e,
425 hindex => 1,
426 pindex => 5,
427 paddr => 5,
428 pirq => 11,
429 sysfreq => 25000, -- CPU_FREQ
430 rmap => 1,
431 rmapcrc => 1,
432 fifosize1 => 16,
433 fifosize2 => 16,
434 rxclkbuftype => 1,
435 rxunaligned => 0,
436 rmapbufs => 4,
437 ft => 0,
438 netlist => 0,
439 ports => 2,
440 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
441 memtech => apa3e,
442 destkey => 2,
443 spwcore => 1
444 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
445 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
446 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
447 )
448 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
449 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
450 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
451 swni, swno);
452
453 swni.tickin <= '0';
454 swni.rmapen <= '1';
455 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
456 swni.tickinraw <= '0';
457 swni.timein <= (OTHERS => '0');
458 swni.dcrstval <= (OTHERS => '0');
459 swni.timerrstval <= (OTHERS => '0');
460
461 -------------------------------------------------------------------------------
462 -- LFR ------------------------------------------------------------------------
463 -------------------------------------------------------------------------------
464
465
466 LFR_rstn <= LFR_soft_rstn AND rstn_25;
467
468 lpp_lfr_1 : lpp_lfr
469 GENERIC MAP (
470 Mem_use => use_RAM,
471 nb_data_by_buffer_size => 32,
472 nb_snapshot_param_size => 32,
473 delta_vector_size => 32,
474 delta_vector_size_f0_2 => 7, -- log2(96)
475 pindex => 15,
476 paddr => 15,
477 pmask => 16#fff#,
478 pirq_ms => 6,
479 pirq_wfp => 14,
480 hindex => 2,
481 top_lfr_version => X"000159") -- aa.bb.cc version
482 PORT MAP (
483 clk => clk_25,
484 rstn => LFR_rstn,
485 sample_B => sample_s(2 DOWNTO 0),
486 sample_E => sample_s(7 DOWNTO 3),
487 sample_val => sample_val,
488 apbi => apbi_ext,
489 apbo => apbo_ext(15),
490 ahbi => ahbi_m_ext,
491 ahbo => ahbo_m_ext(2),
492 coarse_time => coarse_time,
493 fine_time => fine_time,
494 data_shaping_BW => bias_fail_sw_sig,
495 debug_vector => open,
496 debug_vector_ms => open
497 );
498
499 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
500 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
501 END GENERATE all_sample;
502
503 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
504 GENERIC MAP(
505 ChannelCount => 8,
506 SampleNbBits => 14,
507 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
508 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
509 PORT MAP (
510 -- CONV
511 cnv_clk => clk_24,
512 cnv_rstn => rstn_24,
513 cnv => ADC_nCS_sig,
514 -- DATA
515 clk => clk_25,
516 rstn => rstn_25,
517 sck => ADC_CLK_sig,
518 sdo => ADC_SDO_sig,
519 -- SAMPLE
520 sample => sample,
521 sample_val => sample_val);
522
523 ADC_nCS <= ADC_nCS_sig;
524 ADC_CLK <= ADC_CLK_sig;
525 ADC_SDO_sig <= ADC_SDO;
526
527 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
528 "0010001000100010" WHEN HK_SEL = "01" ELSE
529 "0100010001000100" WHEN HK_SEL = "10" ELSE
530 (OTHERS => '0');
531
532
533
534 ----------------------------------------------------------------------
535 --- APB_ADVANCED_TRIGGER -----------------------------------------------------------
536 ----------------------------------------------------------------------
537 advtrig0: APB_ADVANCED_TRIGGER
538 generic map(
539 pindex => 12,
540 paddr => 12)
541 port map(
542 rstn => rstn_25,
543 clk => clk_25,
544 apbi => apbi_ext,
545 apbo => apbo_ext(12),
546
547 SPW_Tickout => swno.tickout,
548 CoarseTime => coarse_time,
549 FineTime => fine_time,
550
551 Trigger => Trigger
552 );
553
554
555 DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
556 PORT MAP (DISCO1_TRIG1, Trigger);
557 DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
558 PORT MAP (DISCO2_TRIG1, Trigger);
559 DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
560 PORT MAP (DISCO3_TRIG1, Trigger);
561 DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
562 PORT MAP (DISCO4_TRIG1, Trigger);
563
564 -----------------------------------------------------------------------------
565 --
566 -----------------------------------------------------------------------------
567 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
568 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 12 AND I /= 15 GENERATE
569 apbo_ext(I) <= apb_none;
570 END GENERATE apbo_ext_not_used;
571 END GENERATE all_apbo_ext;
572
573
574 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
575 ahbo_s_ext(I) <= ahbs_none;
576 END GENERATE all_ahbo_ext;
577
578 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
579 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
580 ahbo_m_ext(I) <= ahbm_none;
581 END GENERATE ahbo_m_ext_not_used;
582 END GENERATE all_ahbo_m_ext;
583
584 END beh;
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1 KEY LIBERO "9.1"
2 KEY CAPTURE "9.1.5.1"
3 KEY DEFAULT_IMPORT_LOC "C:\opt\VHDLIB\tests\Validation_LFR_Filters"
4 KEY DEFAULT_OPEN_LOC ""
5 KEY ProjectID "2f64e589-285c-45b2-b6c4-709f59f83db9"
6 KEY HDLTechnology "VHDL"
7 KEY VendorTechnology_Family "ProASIC3E"
8 KEY VendorTechnology_Die "IT14X14M4"
9 KEY VendorTechnology_Package "fg324"
10 KEY ProjectLocation "C:\opt\VHDLIB\designs\TIMEGEN"
11 KEY SimulationType "VHDL"
12 KEY Vendor "Actel"
13 KEY ActiveRoot "DISCOSPACE_top::work"
14 LIST REVISIONS
15 VALUE="Impl1",NUM=1
16 VALUE="Impl2",NUM=2
17 CURREV=2
18 ENDLIST
19 LIST LIBRARIES
20 grlib
21 synplify
22 techmap
23 spw
24 eth
25 opencores
26 gaisler
27 esa
28 fmf
29 spansion
30 gsi
31 iap
32 lpp
33 cypress
34 ENDLIST
35 LIST LIBRARY_grlib
36 ALIAS=grlib
37 COMPILE_OPTION=COMPILE
38 ENDLIST
39 LIST LIBRARY_synplify
40 ALIAS=synplify
41 COMPILE_OPTION=COMPILE
42 ENDLIST
43 LIST LIBRARY_techmap
44 ALIAS=techmap
45 COMPILE_OPTION=COMPILE
46 ENDLIST
47 LIST LIBRARY_spw
48 ALIAS=spw
49 COMPILE_OPTION=COMPILE
50 ENDLIST
51 LIST LIBRARY_eth
52 ALIAS=eth
53 COMPILE_OPTION=COMPILE
54 ENDLIST
55 LIST LIBRARY_opencores
56 ALIAS=opencores
57 COMPILE_OPTION=COMPILE
58 ENDLIST
59 LIST LIBRARY_gaisler
60 ALIAS=gaisler
61 COMPILE_OPTION=COMPILE
62 ENDLIST
63 LIST LIBRARY_esa
64 ALIAS=esa
65 COMPILE_OPTION=COMPILE
66 ENDLIST
67 LIST LIBRARY_fmf
68 ALIAS=fmf
69 COMPILE_OPTION=COMPILE
70 ENDLIST
71 LIST LIBRARY_spansion
72 ALIAS=spansion
73 COMPILE_OPTION=COMPILE
74 ENDLIST
75 LIST LIBRARY_gsi
76 ALIAS=gsi
77 COMPILE_OPTION=COMPILE
78 ENDLIST
79 LIST LIBRARY_iap
80 ALIAS=iap
81 COMPILE_OPTION=COMPILE
82 ENDLIST
83 LIST LIBRARY_lpp
84 ALIAS=lpp
85 COMPILE_OPTION=COMPILE
86 ENDLIST
87 LIST LIBRARY_cypress
88 ALIAS=cypress
89 COMPILE_OPTION=COMPILE
90 ENDLIST
91 LIST FileManager
92 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
93 STATE="utd"
94 TIME="1472547172"
95 SIZE="3091"
96 LIBRARY="lpp"
97 ENDFILE
98 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
99 STATE="utd"
100 TIME="1472547172"
101 SIZE="1890"
102 LIBRARY="lpp"
103 ENDFILE
104 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
105 STATE="utd"
106 TIME="1472547172"
107 SIZE="4795"
108 LIBRARY="lpp"
109 ENDFILE
110 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
111 STATE="utd"
112 TIME="1472547172"
113 SIZE="3112"
114 LIBRARY="lpp"
115 ENDFILE
116 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
117 STATE="utd"
118 TIME="1472547172"
119 SIZE="3141"
120 LIBRARY="lpp"
121 ENDFILE
122 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
123 STATE="utd"
124 TIME="1472547172"
125 SIZE="2735"
126 LIBRARY="lpp"
127 ENDFILE
128 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
129 STATE="utd"
130 TIME="1472547172"
131 SIZE="15484"
132 LIBRARY="lpp"
133 ENDFILE
134 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
135 STATE="utd"
136 TIME="1472547172"
137 SIZE="2919"
138 LIBRARY="lpp"
139 ENDFILE
140 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
141 STATE="utd"
142 TIME="1472547172"
143 SIZE="3324"
144 LIBRARY="lpp"
145 ENDFILE
146 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
147 STATE="utd"
148 TIME="1472547172"
149 SIZE="10820"
150 LIBRARY="lpp"
151 ENDFILE
152 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
153 STATE="utd"
154 TIME="1472547172"
155 SIZE="10988"
156 LIBRARY="lpp"
157 ENDFILE
158 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
159 STATE="utd"
160 TIME="1472547172"
161 SIZE="15918"
162 LIBRARY="lpp"
163 ENDFILE
164 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
165 STATE="utd"
166 TIME="1472547172"
167 SIZE="6861"
168 LIBRARY="lpp"
169 ENDFILE
170 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
171 STATE="utd"
172 TIME="1472547172"
173 SIZE="7426"
174 LIBRARY="lpp"
175 ENDFILE
176 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
177 STATE="utd"
178 TIME="1478688463"
179 SIZE="9785"
180 LIBRARY="lpp"
181 ENDFILE
182 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
183 STATE="utd"
184 TIME="1478082550"
185 SIZE="11300"
186 LIBRARY="lpp"
187 ENDFILE
188 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
189 STATE="utd"
190 TIME="1478196483"
191 SIZE="7913"
192 LIBRARY="lpp"
193 ENDFILE
194 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
195 STATE="utd"
196 TIME="1478082253"
197 SIZE="17692"
198 LIBRARY="lpp"
199 ENDFILE
200 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
201 STATE="utd"
202 TIME="1472547172"
203 SIZE="6368"
204 LIBRARY="lpp"
205 ENDFILE
206 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
207 STATE="utd"
208 TIME="1478688463"
209 SIZE="11622"
210 LIBRARY="lpp"
211 ENDFILE
212 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
213 STATE="utd"
214 TIME="1472547172"
215 SIZE="2383"
216 LIBRARY="lpp"
217 ENDFILE
218 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
219 STATE="utd"
220 TIME="1478688463"
221 SIZE="3777"
222 LIBRARY="lpp"
223 ENDFILE
224 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
225 STATE="utd"
226 TIME="1478196483"
227 SIZE="5046"
228 LIBRARY="lpp"
229 ENDFILE
230 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
231 STATE="utd"
232 TIME="1472547172"
233 SIZE="2773"
234 LIBRARY="lpp"
235 ENDFILE
236 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
237 STATE="utd"
238 TIME="1472547172"
239 SIZE="141871"
240 LIBRARY="lpp"
241 ENDFILE
242 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
243 STATE="utd"
244 TIME="1472547172"
245 SIZE="4034"
246 LIBRARY="lpp"
247 ENDFILE
248 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
249 STATE="utd"
250 TIME="1472547172"
251 SIZE="12457"
252 LIBRARY="lpp"
253 ENDFILE
254 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
255 STATE="utd"
256 TIME="1472547172"
257 SIZE="3995"
258 LIBRARY="lpp"
259 ENDFILE
260 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
261 STATE="utd"
262 TIME="1472547172"
263 SIZE="3947"
264 LIBRARY="lpp"
265 ENDFILE
266 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
267 STATE="utd"
268 TIME="1472547172"
269 SIZE="25884"
270 LIBRARY="lpp"
271 ENDFILE
272 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
273 STATE="utd"
274 TIME="1472547172"
275 SIZE="32249"
276 LIBRARY="lpp"
277 ENDFILE
278 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
279 STATE="utd"
280 TIME="1472547172"
281 SIZE="5049"
282 LIBRARY="lpp"
283 ENDFILE
284 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
285 STATE="utd"
286 TIME="1472547172"
287 SIZE="3730"
288 LIBRARY="lpp"
289 ENDFILE
290 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
291 STATE="utd"
292 TIME="1472547172"
293 SIZE="9069"
294 LIBRARY="lpp"
295 ENDFILE
296 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
297 STATE="utd"
298 TIME="1472547172"
299 SIZE="3997"
300 LIBRARY="lpp"
301 ENDFILE
302 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
303 STATE="utd"
304 TIME="1472547172"
305 SIZE="12080"
306 LIBRARY="lpp"
307 ENDFILE
308 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
309 STATE="utd"
310 TIME="1472547172"
311 SIZE="3794"
312 LIBRARY="lpp"
313 ENDFILE
314 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
315 STATE="utd"
316 TIME="1472547172"
317 SIZE="4946"
318 LIBRARY="lpp"
319 ENDFILE
320 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
321 STATE="utd"
322 TIME="1472547172"
323 SIZE="3069"
324 LIBRARY="lpp"
325 ENDFILE
326 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
327 STATE="utd"
328 TIME="1472547172"
329 SIZE="2981"
330 LIBRARY="lpp"
331 ENDFILE
332 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
333 STATE="utd"
334 TIME="1472547172"
335 SIZE="2284"
336 LIBRARY="lpp"
337 ENDFILE
338 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
339 STATE="utd"
340 TIME="1472547172"
341 SIZE="1930"
342 LIBRARY="lpp"
343 ENDFILE
344 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
345 STATE="utd"
346 TIME="1472547172"
347 SIZE="2952"
348 LIBRARY="lpp"
349 ENDFILE
350 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
351 STATE="utd"
352 TIME="1472547172"
353 SIZE="1958"
354 LIBRARY="lpp"
355 ENDFILE
356 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
357 STATE="utd"
358 TIME="1472547172"
359 SIZE="685"
360 LIBRARY="lpp"
361 ENDFILE
362 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
363 STATE="utd"
364 TIME="1472547172"
365 SIZE="2306"
366 LIBRARY="lpp"
367 ENDFILE
368 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
369 STATE="utd"
370 TIME="1472547172"
371 SIZE="2319"
372 LIBRARY="lpp"
373 ENDFILE
374 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
375 STATE="utd"
376 TIME="1472547172"
377 SIZE="1537"
378 LIBRARY="lpp"
379 ENDFILE
380 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
381 STATE="utd"
382 TIME="1479489159"
383 SIZE="13529"
384 LIBRARY="lpp"
385 ENDFILE
386 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
387 STATE="utd"
388 TIME="1472547172"
389 SIZE="2014"
390 LIBRARY="lpp"
391 ENDFILE
392 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
393 STATE="utd"
394 TIME="1472547172"
395 SIZE="1985"
396 LIBRARY="lpp"
397 ENDFILE
398 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
399 STATE="utd"
400 TIME="1472547172"
401 SIZE="9428"
402 LIBRARY="lpp"
403 ENDFILE
404 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
405 STATE="utd"
406 TIME="1472547172"
407 SIZE="2314"
408 LIBRARY="lpp"
409 ENDFILE
410 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
411 STATE="utd"
412 TIME="1472547172"
413 SIZE="1941"
414 LIBRARY="lpp"
415 ENDFILE
416 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
417 STATE="utd"
418 TIME="1472547172"
419 SIZE="1667"
420 LIBRARY="lpp"
421 ENDFILE
422 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
423 STATE="utd"
424 TIME="1472547172"
425 SIZE="1731"
426 LIBRARY="lpp"
427 ENDFILE
428 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
429 STATE="utd"
430 TIME="1472547172"
431 SIZE="2185"
432 LIBRARY="lpp"
433 ENDFILE
434 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
435 STATE="utd"
436 TIME="1472547172"
437 SIZE="1692"
438 LIBRARY="lpp"
439 ENDFILE
440 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
441 STATE="utd"
442 TIME="1472547172"
443 SIZE="3295"
444 LIBRARY="lpp"
445 ENDFILE
446 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
447 STATE="utd"
448 TIME="1472547172"
449 SIZE="2482"
450 LIBRARY="lpp"
451 ENDFILE
452 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
453 STATE="utd"
454 TIME="1472547172"
455 SIZE="1812"
456 LIBRARY="lpp"
457 ENDFILE
458 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
459 STATE="utd"
460 TIME="1472547172"
461 SIZE="3487"
462 LIBRARY="lpp"
463 ENDFILE
464 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
465 STATE="utd"
466 TIME="1472547172"
467 SIZE="2198"
468 LIBRARY="lpp"
469 ENDFILE
470 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
471 STATE="utd"
472 TIME="1472547172"
473 SIZE="2089"
474 LIBRARY="lpp"
475 ENDFILE
476 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
477 STATE="utd"
478 TIME="1472547172"
479 SIZE="2273"
480 LIBRARY="lpp"
481 ENDFILE
482 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
483 STATE="utd"
484 TIME="1479495398"
485 SIZE="3634"
486 LIBRARY="lpp"
487 ENDFILE
488 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
489 STATE="utd"
490 TIME="1472547172"
491 SIZE="2848"
492 LIBRARY="lpp"
493 ENDFILE
494 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
495 STATE="utd"
496 TIME="1472547172"
497 SIZE="17466"
498 LIBRARY="lpp"
499 ENDFILE
500 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
501 STATE="utd"
502 TIME="1472547172"
503 SIZE="4205"
504 LIBRARY="lpp"
505 ENDFILE
506 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
507 STATE="utd"
508 TIME="1472547172"
509 SIZE="2933"
510 LIBRARY="lpp"
511 ENDFILE
512 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
513 STATE="utd"
514 TIME="1472547172"
515 SIZE="2238"
516 LIBRARY="lpp"
517 ENDFILE
518 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
519 STATE="utd"
520 TIME="1472547172"
521 SIZE="5325"
522 LIBRARY="lpp"
523 ENDFILE
524 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
525 STATE="utd"
526 TIME="1472547172"
527 SIZE="4786"
528 LIBRARY="lpp"
529 ENDFILE
530 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
531 STATE="utd"
532 TIME="1472547172"
533 SIZE="1264"
534 LIBRARY="lpp"
535 ENDFILE
536 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
537 STATE="utd"
538 TIME="1472547172"
539 SIZE="4316"
540 LIBRARY="lpp"
541 ENDFILE
542 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
543 STATE="utd"
544 TIME="1472547172"
545 SIZE="12321"
546 LIBRARY="lpp"
547 ENDFILE
548 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
549 STATE="utd"
550 TIME="1472547172"
551 SIZE="4539"
552 LIBRARY="lpp"
553 ENDFILE
554 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
555 STATE="utd"
556 TIME="1472547172"
557 SIZE="4454"
558 LIBRARY="lpp"
559 ENDFILE
560 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
561 STATE="utd"
562 TIME="1472547172"
563 SIZE="2479"
564 LIBRARY="lpp"
565 ENDFILE
566 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
567 STATE="utd"
568 TIME="1472547172"
569 SIZE="4091"
570 LIBRARY="lpp"
571 ENDFILE
572 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
573 STATE="utd"
574 TIME="1472547172"
575 SIZE="2677"
576 LIBRARY="lpp"
577 ENDFILE
578 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
579 STATE="utd"
580 TIME="1472547172"
581 SIZE="7740"
582 LIBRARY="lpp"
583 ENDFILE
584 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
585 STATE="utd"
586 TIME="1479920608"
587 SIZE="5053"
588 LIBRARY="lpp"
589 ENDFILE
590 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
591 STATE="utd"
592 TIME="1479911446"
593 SIZE="2143"
594 LIBRARY="lpp"
595 ENDFILE
596 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
597 STATE="utd"
598 TIME="1479913560"
599 SIZE="2634"
600 LIBRARY="lpp"
601 ENDFILE
602 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
603 STATE="utd"
604 TIME="1472547172"
605 SIZE="6288"
606 LIBRARY="lpp"
607 ENDFILE
608 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
609 STATE="utd"
610 TIME="1472547172"
611 SIZE="3856"
612 LIBRARY="lpp"
613 ENDFILE
614 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
615 STATE="utd"
616 TIME="1472547172"
617 SIZE="4819"
618 LIBRARY="lpp"
619 ENDFILE
620 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
621 STATE="utd"
622 TIME="1472547172"
623 SIZE="9925"
624 LIBRARY="lpp"
625 ENDFILE
626 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
627 STATE="utd"
628 TIME="1472547172"
629 SIZE="5162"
630 LIBRARY="lpp"
631 ENDFILE
632 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
633 STATE="utd"
634 TIME="1472547172"
635 SIZE="2965"
636 LIBRARY="lpp"
637 ENDFILE
638 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
639 STATE="utd"
640 TIME="1472547172"
641 SIZE="4811"
642 LIBRARY="lpp"
643 ENDFILE
644 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
645 STATE="utd"
646 TIME="1472547172"
647 SIZE="6901"
648 LIBRARY="lpp"
649 ENDFILE
650 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
651 STATE="utd"
652 TIME="1472547172"
653 SIZE="2457"
654 LIBRARY="lpp"
655 ENDFILE
656 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
657 STATE="utd"
658 TIME="1472547172"
659 SIZE="4636"
660 LIBRARY="lpp"
661 ENDFILE
662 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
663 STATE="utd"
664 TIME="1472547172"
665 SIZE="2302"
666 LIBRARY="lpp"
667 ENDFILE
668 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
669 STATE="utd"
670 TIME="1472547172"
671 SIZE="8553"
672 LIBRARY="lpp"
673 ENDFILE
674 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
675 STATE="utd"
676 TIME="1472547172"
677 SIZE="2966"
678 LIBRARY="lpp"
679 ENDFILE
680 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
681 STATE="utd"
682 TIME="1472547172"
683 SIZE="2465"
684 LIBRARY="lpp"
685 ENDFILE
686 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
687 STATE="utd"
688 TIME="1472547172"
689 SIZE="4291"
690 LIBRARY="lpp"
691 ENDFILE
692 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
693 STATE="utd"
694 TIME="1472547172"
695 SIZE="5071"
696 LIBRARY="lpp"
697 ENDFILE
698 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
699 STATE="utd"
700 TIME="1472547172"
701 SIZE="8480"
702 LIBRARY="lpp"
703 ENDFILE
704 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
705 STATE="utd"
706 TIME="1472547172"
707 SIZE="14356"
708 LIBRARY="lpp"
709 ENDFILE
710 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
711 STATE="utd"
712 TIME="1472547172"
713 SIZE="12064"
714 LIBRARY="lpp"
715 ENDFILE
716 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
717 STATE="utd"
718 TIME="1472547172"
719 SIZE="9280"
720 LIBRARY="lpp"
721 ENDFILE
722 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
723 STATE="utd"
724 TIME="1472547172"
725 SIZE="6032"
726 LIBRARY="lpp"
727 ENDFILE
728 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
729 STATE="utd"
730 TIME="1472547172"
731 SIZE="4061"
732 LIBRARY="lpp"
733 ENDFILE
734 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
735 STATE="utd"
736 TIME="1472547172"
737 SIZE="6996"
738 LIBRARY="lpp"
739 ENDFILE
740 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
741 STATE="utd"
742 TIME="1472547172"
743 SIZE="3724"
744 LIBRARY="lpp"
745 ENDFILE
746 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
747 STATE="utd"
748 TIME="1472547172"
749 SIZE="4664"
750 LIBRARY="lpp"
751 ENDFILE
752 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
753 STATE="utd"
754 TIME="1472547172"
755 SIZE="2306"
756 LIBRARY="lpp"
757 ENDFILE
758 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
759 STATE="utd"
760 TIME="1479827535"
761 SIZE="26034"
762 LIBRARY="lpp"
763 ENDFILE
764 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
765 STATE="utd"
766 TIME="1479827376"
767 SIZE="6066"
768 LIBRARY="lpp"
769 ENDFILE
770 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
771 STATE="utd"
772 TIME="1472547172"
773 SIZE="8186"
774 LIBRARY="lpp"
775 ENDFILE
776 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
777 STATE="utd"
778 TIME="1472547172"
779 SIZE="2863"
780 LIBRARY="lpp"
781 ENDFILE
782 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
783 STATE="utd"
784 TIME="1472547172"
785 SIZE="3738"
786 LIBRARY="lpp"
787 ENDFILE
788 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
789 STATE="utd"
790 TIME="1472547172"
791 SIZE="3703"
792 LIBRARY="lpp"
793 ENDFILE
794 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
795 STATE="utd"
796 TIME="1472547172"
797 SIZE="8911"
798 LIBRARY="lpp"
799 ENDFILE
800 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
801 STATE="utd"
802 TIME="1472547172"
803 SIZE="3302"
804 LIBRARY="lpp"
805 ENDFILE
806 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
807 STATE="utd"
808 TIME="1472547172"
809 SIZE="2979"
810 LIBRARY="lpp"
811 ENDFILE
812 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
813 STATE="utd"
814 TIME="1472547172"
815 SIZE="3145"
816 LIBRARY="lpp"
817 ENDFILE
818 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
819 STATE="utd"
820 TIME="1472547172"
821 SIZE="2907"
822 LIBRARY="lpp"
823 ENDFILE
824 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
825 STATE="utd"
826 TIME="1472547172"
827 SIZE="7397"
828 LIBRARY="lpp"
829 ENDFILE
830 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
831 STATE="utd"
832 TIME="1472547172"
833 SIZE="3225"
834 LIBRARY="lpp"
835 ENDFILE
836 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
837 STATE="utd"
838 TIME="1472547172"
839 SIZE="4323"
840 LIBRARY="lpp"
841 ENDFILE
842 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
843 STATE="utd"
844 TIME="1472547172"
845 SIZE="6735"
846 LIBRARY="lpp"
847 ENDFILE
848 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
849 STATE="utd"
850 TIME="1472547172"
851 SIZE="5354"
852 LIBRARY="lpp"
853 ENDFILE
854 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
855 STATE="utd"
856 TIME="1472547172"
857 SIZE="6258"
858 LIBRARY="lpp"
859 ENDFILE
860 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
861 STATE="utd"
862 TIME="1472547172"
863 SIZE="6154"
864 LIBRARY="lpp"
865 ENDFILE
866 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
867 STATE="utd"
868 TIME="1472547172"
869 SIZE="11043"
870 LIBRARY="lpp"
871 ENDFILE
872 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
873 STATE="utd"
874 TIME="1472547172"
875 SIZE="23856"
876 LIBRARY="lpp"
877 ENDFILE
878 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
879 STATE="utd"
880 TIME="1478688463"
881 SIZE="5730"
882 LIBRARY="lpp"
883 ENDFILE
884 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
885 STATE="utd"
886 TIME="1478688463"
887 SIZE="1605"
888 LIBRARY="lpp"
889 ENDFILE
890 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
891 STATE="utd"
892 TIME="1478688463"
893 SIZE="1200"
894 LIBRARY="lpp"
895 ENDFILE
896 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
897 STATE="utd"
898 TIME="1472547172"
899 SIZE="8177"
900 LIBRARY="lpp"
901 ENDFILE
902 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
903 STATE="utd"
904 TIME="1472547172"
905 SIZE="6072"
906 LIBRARY="lpp"
907 ENDFILE
908 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
909 STATE="utd"
910 TIME="1472547172"
911 SIZE="2638"
912 LIBRARY="lpp"
913 ENDFILE
914 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
915 STATE="utd"
916 TIME="1472547172"
917 SIZE="2925"
918 LIBRARY="lpp"
919 ENDFILE
920 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
921 STATE="utd"
922 TIME="1472547172"
923 SIZE="782"
924 LIBRARY="lpp"
925 ENDFILE
926 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
927 STATE="utd"
928 TIME="1478084024"
929 SIZE="21340"
930 LIBRARY="lpp"
931 ENDFILE
932 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
933 STATE="utd"
934 TIME="1472547172"
935 SIZE="42632"
936 LIBRARY="lpp"
937 ENDFILE
938 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
939 STATE="utd"
940 TIME="1472547172"
941 SIZE="3522"
942 LIBRARY="lpp"
943 ENDFILE
944 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
945 STATE="utd"
946 TIME="1472547172"
947 SIZE="5903"
948 LIBRARY="lpp"
949 ENDFILE
950 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
951 STATE="utd"
952 TIME="1478688463"
953 SIZE="25901"
954 LIBRARY="lpp"
955 ENDFILE
956 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
957 STATE="utd"
958 TIME="1472547172"
959 SIZE="4867"
960 LIBRARY="lpp"
961 ENDFILE
962 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
963 STATE="utd"
964 TIME="1472547172"
965 SIZE="49854"
966 LIBRARY="lpp"
967 ENDFILE
968 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
969 STATE="utd"
970 TIME="1472547172"
971 SIZE="3237"
972 LIBRARY="lpp"
973 ENDFILE
974 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
975 STATE="utd"
976 TIME="1472547172"
977 SIZE="7349"
978 LIBRARY="lpp"
979 ENDFILE
980 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
981 STATE="utd"
982 TIME="1472547172"
983 SIZE="3003"
984 LIBRARY="lpp"
985 ENDFILE
986 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
987 STATE="utd"
988 TIME="1478084031"
989 SIZE="18462"
990 LIBRARY="lpp"
991 ENDFILE
992 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
993 STATE="utd"
994 TIME="1472547172"
995 SIZE="9063"
996 LIBRARY="lpp"
997 ENDFILE
998 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
999 STATE="utd"
1000 TIME="1472547172"
1001 SIZE="20050"
1002 LIBRARY="lpp"
1003 ENDFILE
1004 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
1005 STATE="utd"
1006 TIME="1472547172"
1007 SIZE="988"
1008 LIBRARY="lpp"
1009 ENDFILE
1010 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
1011 STATE="utd"
1012 TIME="1472547172"
1013 SIZE="3170"
1014 LIBRARY="lpp"
1015 ENDFILE
1016 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
1017 STATE="utd"
1018 TIME="1472547172"
1019 SIZE="4440"
1020 LIBRARY="lpp"
1021 ENDFILE
1022 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
1023 STATE="utd"
1024 TIME="1472547172"
1025 SIZE="9316"
1026 LIBRARY="lpp"
1027 ENDFILE
1028 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
1029 STATE="utd"
1030 TIME="1472547172"
1031 SIZE="3230"
1032 LIBRARY="lpp"
1033 ENDFILE
1034 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
1035 STATE="utd"
1036 TIME="1472547172"
1037 SIZE="6124"
1038 LIBRARY="lpp"
1039 ENDFILE
1040 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
1041 STATE="utd"
1042 TIME="1472547172"
1043 SIZE="7653"
1044 LIBRARY="lpp"
1045 ENDFILE
1046 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
1047 STATE="utd"
1048 TIME="1472547172"
1049 SIZE="4033"
1050 LIBRARY="lpp"
1051 ENDFILE
1052 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
1053 STATE="utd"
1054 TIME="1472547172"
1055 SIZE="5609"
1056 LIBRARY="lpp"
1057 ENDFILE
1058 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
1059 STATE="utd"
1060 TIME="1472547172"
1061 SIZE="5006"
1062 LIBRARY="lpp"
1063 ENDFILE
1064 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
1065 STATE="utd"
1066 TIME="1472547172"
1067 SIZE="10418"
1068 LIBRARY="lpp"
1069 ENDFILE
1070 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
1071 STATE="utd"
1072 TIME="1472547172"
1073 SIZE="17107"
1074 LIBRARY="lpp"
1075 ENDFILE
1076 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
1077 STATE="utd"
1078 TIME="1472547172"
1079 SIZE="2491"
1080 LIBRARY="lpp"
1081 ENDFILE
1082 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
1083 STATE="utd"
1084 TIME="1472547172"
1085 SIZE="9119"
1086 LIBRARY="lpp"
1087 ENDFILE
1088 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
1089 STATE="utd"
1090 TIME="1472547186"
1091 SIZE="1327"
1092 LIBRARY="iap"
1093 ENDFILE
1094 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
1095 STATE="utd"
1096 TIME="1472547186"
1097 SIZE="615"
1098 LIBRARY="iap"
1099 ENDFILE
1100 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
1101 STATE="utd"
1102 TIME="1472547186"
1103 SIZE="3594"
1104 LIBRARY="iap"
1105 ENDFILE
1106 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
1107 STATE="utd"
1108 TIME="1472547186"
1109 SIZE="29411"
1110 LIBRARY="iap"
1111 ENDFILE
1112 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
1113 STATE="utd"
1114 TIME="1472547186"
1115 SIZE="26803"
1116 LIBRARY="iap"
1117 ENDFILE
1118 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
1119 STATE="utd"
1120 TIME="1465836263"
1121 SIZE="6333"
1122 LIBRARY="cypress"
1123 ENDFILE
1124 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
1125 STATE="utd"
1126 TIME="1465836263"
1127 SIZE="16818"
1128 LIBRARY="cypress"
1129 ENDFILE
1130 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
1131 STATE="utd"
1132 TIME="1465836263"
1133 SIZE="27113"
1134 LIBRARY="cypress"
1135 ENDFILE
1136 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
1137 STATE="utd"
1138 TIME="1465836263"
1139 SIZE="2115"
1140 LIBRARY="cypress"
1141 ENDFILE
1142 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
1143 STATE="utd"
1144 TIME="1465836264"
1145 SIZE="37496"
1146 LIBRARY="esa"
1147 ENDFILE
1148 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
1149 STATE="utd"
1150 TIME="1465836264"
1151 SIZE="2151"
1152 LIBRARY="esa"
1153 ENDFILE
1154 VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
1155 STATE="utd"
1156 TIME="1465836264"
1157 SIZE="19987"
1158 LIBRARY="eth"
1159 ENDFILE
1160 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
1161 STATE="utd"
1162 TIME="1465836264"
1163 SIZE="5579"
1164 LIBRARY="eth"
1165 ENDFILE
1166 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
1167 STATE="utd"
1168 TIME="1465836264"
1169 SIZE="5777"
1170 LIBRARY="eth"
1171 ENDFILE
1172 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
1173 STATE="utd"
1174 TIME="1465836264"
1175 SIZE="4225"
1176 LIBRARY="eth"
1177 ENDFILE
1178 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
1179 STATE="utd"
1180 TIME="1465836264"
1181 SIZE="1405"
1182 LIBRARY="eth"
1183 ENDFILE
1184 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
1185 STATE="utd"
1186 TIME="1465836264"
1187 SIZE="85494"
1188 LIBRARY="eth"
1189 ENDFILE
1190 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
1191 STATE="utd"
1192 TIME="1465836264"
1193 SIZE="138716"
1194 LIBRARY="eth"
1195 ENDFILE
1196 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
1197 STATE="utd"
1198 TIME="1465836264"
1199 SIZE="17322"
1200 LIBRARY="eth"
1201 ENDFILE
1202 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
1203 STATE="utd"
1204 TIME="1465836264"
1205 SIZE="12935"
1206 LIBRARY="eth"
1207 ENDFILE
1208 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
1209 STATE="utd"
1210 TIME="1465836264"
1211 SIZE="14338"
1212 LIBRARY="eth"
1213 ENDFILE
1214 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
1215 STATE="utd"
1216 TIME="1465836264"
1217 SIZE="23913"
1218 LIBRARY="eth"
1219 ENDFILE
1220 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
1221 STATE="utd"
1222 TIME="1465836264"
1223 SIZE="11414"
1224 LIBRARY="eth"
1225 ENDFILE
1226 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
1227 STATE="utd"
1228 TIME="1465836264"
1229 SIZE="17410"
1230 LIBRARY="eth"
1231 ENDFILE
1232 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
1233 STATE="utd"
1234 TIME="1465836264"
1235 SIZE="13418"
1236 LIBRARY="eth"
1237 ENDFILE
1238 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
1239 STATE="utd"
1240 TIME="1465836264"
1241 SIZE="13621"
1242 LIBRARY="eth"
1243 ENDFILE
1244 VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
1245 STATE="utd"
1246 TIME="1465836264"
1247 SIZE="32667"
1248 LIBRARY="fmf"
1249 ENDFILE
1250 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
1251 STATE="utd"
1252 TIME="1465836264"
1253 SIZE="5422"
1254 LIBRARY="fmf"
1255 ENDFILE
1256 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
1257 STATE="utd"
1258 TIME="1465836264"
1259 SIZE="52702"
1260 LIBRARY="fmf"
1261 ENDFILE
1262 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
1263 STATE="utd"
1264 TIME="1465836264"
1265 SIZE="53367"
1266 LIBRARY="fmf"
1267 ENDFILE
1268 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
1269 STATE="utd"
1270 TIME="1465836264"
1271 SIZE="40830"
1272 LIBRARY="fmf"
1273 ENDFILE
1274 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
1275 STATE="utd"
1276 TIME="1465836264"
1277 SIZE="6125"
1278 LIBRARY="fmf"
1279 ENDFILE
1280 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
1281 STATE="utd"
1282 TIME="1465836265"
1283 SIZE="14039"
1284 LIBRARY="gaisler"
1285 ENDFILE
1286 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
1287 STATE="utd"
1288 TIME="1465836265"
1289 SIZE="37327"
1290 LIBRARY="gaisler"
1291 ENDFILE
1292 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
1293 STATE="utd"
1294 TIME="1465836265"
1295 SIZE="4322"
1296 LIBRARY="gaisler"
1297 ENDFILE
1298 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
1299 STATE="utd"
1300 TIME="1465836265"
1301 SIZE="6723"
1302 LIBRARY="gaisler"
1303 ENDFILE
1304 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
1305 STATE="utd"
1306 TIME="1465836265"
1307 SIZE="14935"
1308 LIBRARY="gaisler"
1309 ENDFILE
1310 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
1311 STATE="utd"
1312 TIME="1465836265"
1313 SIZE="6491"
1314 LIBRARY="gaisler"
1315 ENDFILE
1316 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
1317 STATE="utd"
1318 TIME="1465836265"
1319 SIZE="930"
1320 LIBRARY="gaisler"
1321 ENDFILE
1322 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
1323 STATE="utd"
1324 TIME="1465836265"
1325 SIZE="5932"
1326 LIBRARY="gaisler"
1327 ENDFILE
1328 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
1329 STATE="utd"
1330 TIME="1465836265"
1331 SIZE="7365"
1332 LIBRARY="gaisler"
1333 ENDFILE
1334 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
1335 STATE="utd"
1336 TIME="1465836265"
1337 SIZE="5263"
1338 LIBRARY="gaisler"
1339 ENDFILE
1340 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
1341 STATE="utd"
1342 TIME="1465836265"
1343 SIZE="22146"
1344 LIBRARY="gaisler"
1345 ENDFILE
1346 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
1347 STATE="utd"
1348 TIME="1465836265"
1349 SIZE="6307"
1350 LIBRARY="gaisler"
1351 ENDFILE
1352 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
1353 STATE="utd"
1354 TIME="1465836265"
1355 SIZE="82838"
1356 LIBRARY="gaisler"
1357 ENDFILE
1358 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
1359 STATE="utd"
1360 TIME="1465836265"
1361 SIZE="2110"
1362 LIBRARY="gaisler"
1363 ENDFILE
1364 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
1365 STATE="utd"
1366 TIME="1465836265"
1367 SIZE="5053"
1368 LIBRARY="gaisler"
1369 ENDFILE
1370 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
1371 STATE="utd"
1372 TIME="1465836265"
1373 SIZE="5455"
1374 LIBRARY="gaisler"
1375 ENDFILE
1376 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
1377 STATE="utd"
1378 TIME="1465836266"
1379 SIZE="4509"
1380 LIBRARY="gaisler"
1381 ENDFILE
1382 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
1383 STATE="utd"
1384 TIME="1465836266"
1385 SIZE="15710"
1386 LIBRARY="gaisler"
1387 ENDFILE
1388 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
1389 STATE="utd"
1390 TIME="1465836266"
1391 SIZE="3233"
1392 LIBRARY="gaisler"
1393 ENDFILE
1394 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
1395 STATE="utd"
1396 TIME="1465836266"
1397 SIZE="4215"
1398 LIBRARY="gaisler"
1399 ENDFILE
1400 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
1401 STATE="utd"
1402 TIME="1465836266"
1403 SIZE="4246"
1404 LIBRARY="gaisler"
1405 ENDFILE
1406 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
1407 STATE="utd"
1408 TIME="1465836266"
1409 SIZE="4671"
1410 LIBRARY="gaisler"
1411 ENDFILE
1412 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
1413 STATE="utd"
1414 TIME="1465836266"
1415 SIZE="13232"
1416 LIBRARY="gaisler"
1417 ENDFILE
1418 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
1419 STATE="utd"
1420 TIME="1465836266"
1421 SIZE="6029"
1422 LIBRARY="gaisler"
1423 ENDFILE
1424 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
1425 STATE="utd"
1426 TIME="1465836266"
1427 SIZE="13018"
1428 LIBRARY="gaisler"
1429 ENDFILE
1430 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
1431 STATE="utd"
1432 TIME="1465836266"
1433 SIZE="13513"
1434 LIBRARY="gaisler"
1435 ENDFILE
1436 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
1437 STATE="utd"
1438 TIME="1465836266"
1439 SIZE="13648"
1440 LIBRARY="gaisler"
1441 ENDFILE
1442 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
1443 STATE="utd"
1444 TIME="1465836266"
1445 SIZE="27223"
1446 LIBRARY="gaisler"
1447 ENDFILE
1448 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
1449 STATE="utd"
1450 TIME="1465836266"
1451 SIZE="106245"
1452 LIBRARY="gaisler"
1453 ENDFILE
1454 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\synpe_grlfpc.vhd,hdl"
1455 STATE="utd"
1456 TIME="1465836266"
1457 SIZE="105334"
1458 LIBRARY="gaisler"
1459 ENDFILE
1460 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
1461 STATE="utd"
1462 TIME="1465836266"
1463 SIZE="216796"
1464 LIBRARY="gaisler"
1465 ENDFILE
1466 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\synpe_grlfpu.vhd,hdl"
1467 STATE="utd"
1468 TIME="1465836266"
1469 SIZE="215376"
1470 LIBRARY="gaisler"
1471 ENDFILE
1472 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
1473 STATE="utd"
1474 TIME="1465836267"
1475 SIZE="25247"
1476 LIBRARY="gaisler"
1477 ENDFILE
1478 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
1479 STATE="utd"
1480 TIME="1465836267"
1481 SIZE="4714"
1482 LIBRARY="gaisler"
1483 ENDFILE
1484 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
1485 STATE="utd"
1486 TIME="1465836267"
1487 SIZE="10957"
1488 LIBRARY="gaisler"
1489 ENDFILE
1490 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
1491 STATE="utd"
1492 TIME="1465836267"
1493 SIZE="4678"
1494 LIBRARY="gaisler"
1495 ENDFILE
1496 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
1497 STATE="utd"
1498 TIME="1465836267"
1499 SIZE="5844"
1500 LIBRARY="gaisler"
1501 ENDFILE
1502 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
1503 STATE="utd"
1504 TIME="1465836267"
1505 SIZE="2839"
1506 LIBRARY="gaisler"
1507 ENDFILE
1508 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
1509 STATE="utd"
1510 TIME="1465836267"
1511 SIZE="4606"
1512 LIBRARY="gaisler"
1513 ENDFILE
1514 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
1515 STATE="utd"
1516 TIME="1465836267"
1517 SIZE="2259"
1518 LIBRARY="gaisler"
1519 ENDFILE
1520 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
1521 STATE="utd"
1522 TIME="1465836267"
1523 SIZE="2593"
1524 LIBRARY="gaisler"
1525 ENDFILE
1526 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
1527 STATE="utd"
1528 TIME="1465836267"
1529 SIZE="6832"
1530 LIBRARY="gaisler"
1531 ENDFILE
1532 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
1533 STATE="utd"
1534 TIME="1465836267"
1535 SIZE="7460"
1536 LIBRARY="gaisler"
1537 ENDFILE
1538 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
1539 STATE="utd"
1540 TIME="1465836267"
1541 SIZE="9005"
1542 LIBRARY="gaisler"
1543 ENDFILE
1544 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
1545 STATE="utd"
1546 TIME="1465836267"
1547 SIZE="30211"
1548 LIBRARY="gaisler"
1549 ENDFILE
1550 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
1551 STATE="utd"
1552 TIME="1465836267"
1553 SIZE="2335"
1554 LIBRARY="gaisler"
1555 ENDFILE
1556 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
1557 STATE="utd"
1558 TIME="1465836267"
1559 SIZE="2598"
1560 LIBRARY="gaisler"
1561 ENDFILE
1562 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
1563 STATE="utd"
1564 TIME="1465836267"
1565 SIZE="681304"
1566 LIBRARY="gaisler"
1567 ENDFILE
1568 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\synpe_leon3v3.vhd,hdl"
1569 STATE="utd"
1570 TIME="1465836267"
1571 SIZE="677660"
1572 LIBRARY="gaisler"
1573 ENDFILE
1574 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
1575 STATE="utd"
1576 TIME="1465836267"
1577 SIZE="10473"
1578 LIBRARY="gaisler"
1579 ENDFILE
1580 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
1581 STATE="utd"
1582 TIME="1465836267"
1583 SIZE="36926"
1584 LIBRARY="gaisler"
1585 ENDFILE
1586 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
1587 STATE="utd"
1588 TIME="1465836268"
1589 SIZE="59984"
1590 LIBRARY="gaisler"
1591 ENDFILE
1592 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
1593 STATE="utd"
1594 TIME="1465836268"
1595 SIZE="27397"
1596 LIBRARY="gaisler"
1597 ENDFILE
1598 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
1599 STATE="utd"
1600 TIME="1465836268"
1601 SIZE="39968"
1602 LIBRARY="gaisler"
1603 ENDFILE
1604 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
1605 STATE="utd"
1606 TIME="1465836268"
1607 SIZE="21278"
1608 LIBRARY="gaisler"
1609 ENDFILE
1610 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
1611 STATE="utd"
1612 TIME="1465836268"
1613 SIZE="5246"
1614 LIBRARY="gaisler"
1615 ENDFILE
1616 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
1617 STATE="utd"
1618 TIME="1465836268"
1619 SIZE="31725"
1620 LIBRARY="gaisler"
1621 ENDFILE
1622 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
1623 STATE="utd"
1624 TIME="1465836268"
1625 SIZE="35358"
1626 LIBRARY="gaisler"
1627 ENDFILE
1628 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
1629 STATE="utd"
1630 TIME="1465836268"
1631 SIZE="20458"
1632 LIBRARY="gaisler"
1633 ENDFILE
1634 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
1635 STATE="utd"
1636 TIME="1465836268"
1637 SIZE="29852"
1638 LIBRARY="gaisler"
1639 ENDFILE
1640 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
1641 STATE="utd"
1642 TIME="1465836268"
1643 SIZE="29845"
1644 LIBRARY="gaisler"
1645 ENDFILE
1646 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
1647 STATE="utd"
1648 TIME="1465836268"
1649 SIZE="25626"
1650 LIBRARY="gaisler"
1651 ENDFILE
1652 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
1653 STATE="utd"
1654 TIME="1465836268"
1655 SIZE="15978"
1656 LIBRARY="gaisler"
1657 ENDFILE
1658 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
1659 STATE="utd"
1660 TIME="1465836268"
1661 SIZE="18077"
1662 LIBRARY="gaisler"
1663 ENDFILE
1664 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
1665 STATE="utd"
1666 TIME="1465836268"
1667 SIZE="144276"
1668 LIBRARY="gaisler"
1669 ENDFILE
1670 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
1671 STATE="utd"
1672 TIME="1465836268"
1673 SIZE="5511"
1674 LIBRARY="gaisler"
1675 ENDFILE
1676 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
1677 STATE="utd"
1678 TIME="1465836268"
1679 SIZE="4822"
1680 LIBRARY="gaisler"
1681 ENDFILE
1682 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
1683 STATE="utd"
1684 TIME="1465836268"
1685 SIZE="11940"
1686 LIBRARY="gaisler"
1687 ENDFILE
1688 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
1689 STATE="utd"
1690 TIME="1465836268"
1691 SIZE="8846"
1692 LIBRARY="gaisler"
1693 ENDFILE
1694 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
1695 STATE="utd"
1696 TIME="1465836268"
1697 SIZE="3865"
1698 LIBRARY="gaisler"
1699 ENDFILE
1700 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
1701 STATE="utd"
1702 TIME="1465836268"
1703 SIZE="1813"
1704 LIBRARY="gaisler"
1705 ENDFILE
1706 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
1707 STATE="utd"
1708 TIME="1465836268"
1709 SIZE="2188"
1710 LIBRARY="gaisler"
1711 ENDFILE
1712 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
1713 STATE="utd"
1714 TIME="1465836268"
1715 SIZE="19357"
1716 LIBRARY="gaisler"
1717 ENDFILE
1718 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
1719 STATE="utd"
1720 TIME="1465836268"
1721 SIZE="4570"
1722 LIBRARY="gaisler"
1723 ENDFILE
1724 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
1725 STATE="utd"
1726 TIME="1465836268"
1727 SIZE="13338"
1728 LIBRARY="gaisler"
1729 ENDFILE
1730 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
1731 STATE="utd"
1732 TIME="1465836268"
1733 SIZE="11680"
1734 LIBRARY="gaisler"
1735 ENDFILE
1736 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
1737 STATE="utd"
1738 TIME="1465836268"
1739 SIZE="121182"
1740 LIBRARY="gaisler"
1741 ENDFILE
1742 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
1743 STATE="utd"
1744 TIME="1465836268"
1745 SIZE="1147"
1746 LIBRARY="gaisler"
1747 ENDFILE
1748 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
1749 STATE="utd"
1750 TIME="1465836268"
1751 SIZE="14451"
1752 LIBRARY="gaisler"
1753 ENDFILE
1754 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
1755 STATE="utd"
1756 TIME="1465836268"
1757 SIZE="17226"
1758 LIBRARY="gaisler"
1759 ENDFILE
1760 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
1761 STATE="utd"
1762 TIME="1465836268"
1763 SIZE="17880"
1764 LIBRARY="gaisler"
1765 ENDFILE
1766 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
1767 STATE="utd"
1768 TIME="1465836268"
1769 SIZE="13844"
1770 LIBRARY="gaisler"
1771 ENDFILE
1772 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
1773 STATE="utd"
1774 TIME="1465836269"
1775 SIZE="38705"
1776 LIBRARY="gaisler"
1777 ENDFILE
1778 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
1779 STATE="utd"
1780 TIME="1465836269"
1781 SIZE="9094"
1782 LIBRARY="gaisler"
1783 ENDFILE
1784 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
1785 STATE="utd"
1786 TIME="1465836269"
1787 SIZE="9997"
1788 LIBRARY="gaisler"
1789 ENDFILE
1790 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
1791 STATE="utd"
1792 TIME="1465836269"
1793 SIZE="90518"
1794 LIBRARY="gaisler"
1795 ENDFILE
1796 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
1797 STATE="utd"
1798 TIME="1465836269"
1799 SIZE="11337"
1800 LIBRARY="gaisler"
1801 ENDFILE
1802 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
1803 STATE="utd"
1804 TIME="1465836269"
1805 SIZE="3181"
1806 LIBRARY="gaisler"
1807 ENDFILE
1808 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
1809 STATE="utd"
1810 TIME="1465836269"
1811 SIZE="4223"
1812 LIBRARY="gaisler"
1813 ENDFILE
1814 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
1815 STATE="utd"
1816 TIME="1465836269"
1817 SIZE="15198"
1818 LIBRARY="gaisler"
1819 ENDFILE
1820 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
1821 STATE="utd"
1822 TIME="1465836269"
1823 SIZE="16727"
1824 LIBRARY="gaisler"
1825 ENDFILE
1826 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
1827 STATE="utd"
1828 TIME="1465836269"
1829 SIZE="2528"
1830 LIBRARY="gaisler"
1831 ENDFILE
1832 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
1833 STATE="utd"
1834 TIME="1465836269"
1835 SIZE="4295"
1836 LIBRARY="gaisler"
1837 ENDFILE
1838 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
1839 STATE="utd"
1840 TIME="1465836269"
1841 SIZE="16786"
1842 LIBRARY="gaisler"
1843 ENDFILE
1844 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
1845 STATE="utd"
1846 TIME="1465836269"
1847 SIZE="35455"
1848 LIBRARY="gaisler"
1849 ENDFILE
1850 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
1851 STATE="utd"
1852 TIME="1465836269"
1853 SIZE="46512"
1854 LIBRARY="gaisler"
1855 ENDFILE
1856 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
1857 STATE="utd"
1858 TIME="1465836269"
1859 SIZE="3108"
1860 LIBRARY="gaisler"
1861 ENDFILE
1862 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
1863 STATE="utd"
1864 TIME="1465836269"
1865 SIZE="27694"
1866 LIBRARY="gaisler"
1867 ENDFILE
1868 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
1869 STATE="utd"
1870 TIME="1465836269"
1871 SIZE="10472"
1872 LIBRARY="gaisler"
1873 ENDFILE
1874 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
1875 STATE="utd"
1876 TIME="1465836269"
1877 SIZE="144797"
1878 LIBRARY="gaisler"
1879 ENDFILE
1880 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
1881 STATE="utd"
1882 TIME="1465836269"
1883 SIZE="2906"
1884 LIBRARY="gaisler"
1885 ENDFILE
1886 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
1887 STATE="utd"
1888 TIME="1465836269"
1889 SIZE="15433"
1890 LIBRARY="gaisler"
1891 ENDFILE
1892 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
1893 STATE="utd"
1894 TIME="1465836270"
1895 SIZE="4220"
1896 LIBRARY="gaisler"
1897 ENDFILE
1898 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
1899 STATE="utd"
1900 TIME="1465836270"
1901 SIZE="22444"
1902 LIBRARY="gaisler"
1903 ENDFILE
1904 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
1905 STATE="utd"
1906 TIME="1465836270"
1907 SIZE="30992"
1908 LIBRARY="gaisler"
1909 ENDFILE
1910 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
1911 STATE="utd"
1912 TIME="1465836270"
1913 SIZE="20300"
1914 LIBRARY="gaisler"
1915 ENDFILE
1916 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
1917 STATE="utd"
1918 TIME="1465836270"
1919 SIZE="1995"
1920 LIBRARY="gaisler"
1921 ENDFILE
1922 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
1923 STATE="utd"
1924 TIME="1465836270"
1925 SIZE="24680"
1926 LIBRARY="gaisler"
1927 ENDFILE
1928 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
1929 STATE="utd"
1930 TIME="1465836270"
1931 SIZE="31994"
1932 LIBRARY="gaisler"
1933 ENDFILE
1934 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
1935 STATE="utd"
1936 TIME="1465836270"
1937 SIZE="18393"
1938 LIBRARY="gaisler"
1939 ENDFILE
1940 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
1941 STATE="utd"
1942 TIME="1465836270"
1943 SIZE="30700"
1944 LIBRARY="gaisler"
1945 ENDFILE
1946 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
1947 STATE="utd"
1948 TIME="1465836270"
1949 SIZE="5396"
1950 LIBRARY="gaisler"
1951 ENDFILE
1952 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
1953 STATE="utd"
1954 TIME="1465836271"
1955 SIZE="3368"
1956 LIBRARY="gaisler"
1957 ENDFILE
1958 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
1959 STATE="utd"
1960 TIME="1465836271"
1961 SIZE="1309"
1962 LIBRARY="gaisler"
1963 ENDFILE
1964 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
1965 STATE="utd"
1966 TIME="1465836271"
1967 SIZE="4974"
1968 LIBRARY="gaisler"
1969 ENDFILE
1970 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
1971 STATE="utd"
1972 TIME="1465836271"
1973 SIZE="1836"
1974 LIBRARY="gaisler"
1975 ENDFILE
1976 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
1977 STATE="utd"
1978 TIME="1465836271"
1979 SIZE="5275"
1980 LIBRARY="gaisler"
1981 ENDFILE
1982 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
1983 STATE="utd"
1984 TIME="1465836271"
1985 SIZE="10727"
1986 LIBRARY="gaisler"
1987 ENDFILE
1988 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
1989 STATE="utd"
1990 TIME="1465836271"
1991 SIZE="15236"
1992 LIBRARY="gaisler"
1993 ENDFILE
1994 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
1995 STATE="utd"
1996 TIME="1465836271"
1997 SIZE="18294"
1998 LIBRARY="gaisler"
1999 ENDFILE
2000 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
2001 STATE="utd"
2002 TIME="1465836271"
2003 SIZE="10323"
2004 LIBRARY="gaisler"
2005 ENDFILE
2006 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
2007 STATE="utd"
2008 TIME="1465836271"
2009 SIZE="5060"
2010 LIBRARY="gaisler"
2011 ENDFILE
2012 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
2013 STATE="utd"
2014 TIME="1465836271"
2015 SIZE="6480"
2016 LIBRARY="gaisler"
2017 ENDFILE
2018 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
2019 STATE="utd"
2020 TIME="1465836271"
2021 SIZE="5154"
2022 LIBRARY="gaisler"
2023 ENDFILE
2024 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
2025 STATE="utd"
2026 TIME="1465836271"
2027 SIZE="30720"
2028 LIBRARY="gaisler"
2029 ENDFILE
2030 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
2031 STATE="utd"
2032 TIME="1465836271"
2033 SIZE="10955"
2034 LIBRARY="gaisler"
2035 ENDFILE
2036 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
2037 STATE="utd"
2038 TIME="1465836271"
2039 SIZE="20811"
2040 LIBRARY="gaisler"
2041 ENDFILE
2042 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
2043 STATE="utd"
2044 TIME="1465836271"
2045 SIZE="22308"
2046 LIBRARY="gaisler"
2047 ENDFILE
2048 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
2049 STATE="utd"
2050 TIME="1465836271"
2051 SIZE="7793"
2052 LIBRARY="gaisler"
2053 ENDFILE
2054 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
2055 STATE="utd"
2056 TIME="1465836271"
2057 SIZE="5042"
2058 LIBRARY="gaisler"
2059 ENDFILE
2060 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
2061 STATE="utd"
2062 TIME="1465836271"
2063 SIZE="2785"
2064 LIBRARY="gaisler"
2065 ENDFILE
2066 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
2067 STATE="utd"
2068 TIME="1465836271"
2069 SIZE="21585"
2070 LIBRARY="gaisler"
2071 ENDFILE
2072 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
2073 STATE="utd"
2074 TIME="1465836271"
2075 SIZE="9145"
2076 LIBRARY="gaisler"
2077 ENDFILE
2078 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
2079 STATE="utd"
2080 TIME="1465836271"
2081 SIZE="10027"
2082 LIBRARY="gaisler"
2083 ENDFILE
2084 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
2085 STATE="utd"
2086 TIME="1465836271"
2087 SIZE="2137"
2088 LIBRARY="gaisler"
2089 ENDFILE
2090 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
2091 STATE="utd"
2092 TIME="1465836271"
2093 SIZE="20732"
2094 LIBRARY="gaisler"
2095 ENDFILE
2096 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
2097 STATE="utd"
2098 TIME="1465836271"
2099 SIZE="5191"
2100 LIBRARY="gaisler"
2101 ENDFILE
2102 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
2103 STATE="utd"
2104 TIME="1465836271"
2105 SIZE="11383"
2106 LIBRARY="gaisler"
2107 ENDFILE
2108 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
2109 STATE="utd"
2110 TIME="1465836271"
2111 SIZE="4887"
2112 LIBRARY="gaisler"
2113 ENDFILE
2114 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
2115 STATE="utd"
2116 TIME="1465836271"
2117 SIZE="2166"
2118 LIBRARY="gaisler"
2119 ENDFILE
2120 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
2121 STATE="utd"
2122 TIME="1465836272"
2123 SIZE="42215"
2124 LIBRARY="grlib"
2125 ENDFILE
2126 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
2127 STATE="utd"
2128 TIME="1465836272"
2129 SIZE="28693"
2130 LIBRARY="grlib"
2131 ENDFILE
2132 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
2133 STATE="utd"
2134 TIME="1465836272"
2135 SIZE="5313"
2136 LIBRARY="grlib"
2137 ENDFILE
2138 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
2139 STATE="utd"
2140 TIME="1478196656"
2141 SIZE="49258"
2142 LIBRARY="grlib"
2143 ENDFILE
2144 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
2145 STATE="utd"
2146 TIME="1465836272"
2147 SIZE="2696"
2148 LIBRARY="grlib"
2149 ENDFILE
2150 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
2151 STATE="utd"
2152 TIME="1465836272"
2153 SIZE="73534"
2154 LIBRARY="grlib"
2155 ENDFILE
2156 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
2157 STATE="utd"
2158 TIME="1465836272"
2159 SIZE="11478"
2160 LIBRARY="grlib"
2161 ENDFILE
2162 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
2163 STATE="utd"
2164 TIME="1465836272"
2165 SIZE="6919"
2166 LIBRARY="grlib"
2167 ENDFILE
2168 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
2169 STATE="utd"
2170 TIME="1465836272"
2171 SIZE="1377"
2172 LIBRARY="grlib"
2173 ENDFILE
2174 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
2175 STATE="utd"
2176 TIME="1465836272"
2177 SIZE="45046"
2178 LIBRARY="grlib"
2179 ENDFILE
2180 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
2181 STATE="utd"
2182 TIME="1465836272"
2183 SIZE="25048"
2184 LIBRARY="grlib"
2185 ENDFILE
2186 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
2187 STATE="utd"
2188 TIME="1465836272"
2189 SIZE="5530"
2190 LIBRARY="grlib"
2191 ENDFILE
2192 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
2193 STATE="utd"
2194 TIME="1465836272"
2195 SIZE="68490"
2196 LIBRARY="grlib"
2197 ENDFILE
2198 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
2199 STATE="utd"
2200 TIME="1465836272"
2201 SIZE="4984"
2202 LIBRARY="grlib"
2203 ENDFILE
2204 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
2205 STATE="utd"
2206 TIME="1465836272"
2207 SIZE="32765"
2208 LIBRARY="grlib"
2209 ENDFILE
2210 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
2211 STATE="utd"
2212 TIME="1465836272"
2213 SIZE="21107"
2214 LIBRARY="grlib"
2215 ENDFILE
2216 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
2217 STATE="utd"
2218 TIME="1465836272"
2219 SIZE="508332"
2220 LIBRARY="grlib"
2221 ENDFILE
2222 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
2223 STATE="utd"
2224 TIME="1465836272"
2225 SIZE="54977"
2226 LIBRARY="grlib"
2227 ENDFILE
2228 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
2229 STATE="utd"
2230 TIME="1465836272"
2231 SIZE="57885"
2232 LIBRARY="grlib"
2233 ENDFILE
2234 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
2235 STATE="utd"
2236 TIME="1465836273"
2237 SIZE="22816"
2238 LIBRARY="grlib"
2239 ENDFILE
2240 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
2241 STATE="utd"
2242 TIME="1465836273"
2243 SIZE="20072"
2244 LIBRARY="grlib"
2245 ENDFILE
2246 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
2247 STATE="utd"
2248 TIME="1465836273"
2249 SIZE="190884"
2250 LIBRARY="grlib"
2251 ENDFILE
2252 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\synpe_ftlib.vhd,hdl"
2253 STATE="utd"
2254 TIME="1465836273"
2255 SIZE="189562"
2256 LIBRARY="grlib"
2257 ENDFILE
2258 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
2259 STATE="utd"
2260 TIME="1465836273"
2261 SIZE="707143"
2262 LIBRARY="grlib"
2263 ENDFILE
2264 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
2265 STATE="utd"
2266 TIME="1465836273"
2267 SIZE="1677"
2268 LIBRARY="grlib"
2269 ENDFILE
2270 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
2271 STATE="utd"
2272 TIME="1465836273"
2273 SIZE="3842"
2274 LIBRARY="grlib"
2275 ENDFILE
2276 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
2277 STATE="utd"
2278 TIME="1465836273"
2279 SIZE="9925"
2280 LIBRARY="grlib"
2281 ENDFILE
2282 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
2283 STATE="utd"
2284 TIME="1465836273"
2285 SIZE="27816"
2286 LIBRARY="grlib"
2287 ENDFILE
2288 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
2289 STATE="utd"
2290 TIME="1465836273"
2291 SIZE="2337"
2292 LIBRARY="grlib"
2293 ENDFILE
2294 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
2295 STATE="utd"
2296 TIME="1465836273"
2297 SIZE="1864"
2298 LIBRARY="grlib"
2299 ENDFILE
2300 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
2301 STATE="utd"
2302 TIME="1465836273"
2303 SIZE="8705"
2304 LIBRARY="grlib"
2305 ENDFILE
2306 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
2307 STATE="utd"
2308 TIME="1465836273"
2309 SIZE="19877"
2310 LIBRARY="grlib"
2311 ENDFILE
2312 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
2313 STATE="utd"
2314 TIME="1465836273"
2315 SIZE="32050"
2316 LIBRARY="grlib"
2317 ENDFILE
2318 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
2319 STATE="utd"
2320 TIME="1465836273"
2321 SIZE="280"
2322 LIBRARY="grlib"
2323 ENDFILE
2324 VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
2325 STATE="utd"
2326 TIME="1465836273"
2327 SIZE="1823"
2328 LIBRARY="grlib"
2329 ENDFILE
2330 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
2331 STATE="utd"
2332 TIME="1465836273"
2333 SIZE="21018"
2334 LIBRARY="gsi"
2335 ENDFILE
2336 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
2337 STATE="utd"
2338 TIME="1465836273"
2339 SIZE="101033"
2340 LIBRARY="gsi"
2341 ENDFILE
2342 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
2343 STATE="utd"
2344 TIME="1465836273"
2345 SIZE="7166"
2346 LIBRARY="gsi"
2347 ENDFILE
2348 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
2349 STATE="utd"
2350 TIME="1465836274"
2351 SIZE="3314"
2352 LIBRARY="opencores"
2353 ENDFILE
2354 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
2355 STATE="utd"
2356 TIME="1465836274"
2357 SIZE="355786"
2358 LIBRARY="opencores"
2359 ENDFILE
2360 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
2361 STATE="utd"
2362 TIME="1465836274"
2363 SIZE="162783"
2364 LIBRARY="opencores"
2365 ENDFILE
2366 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
2367 STATE="utd"
2368 TIME="1465836274"
2369 SIZE="372520"
2370 LIBRARY="opencores"
2371 ENDFILE
2372 VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
2373 STATE="utd"
2374 TIME="1465836274"
2375 SIZE="31632"
2376 LIBRARY="spw"
2377 ENDFILE
2378 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
2379 STATE="utd"
2380 TIME="1465836275"
2381 SIZE="675060"
2382 LIBRARY="spw"
2383 ENDFILE
2384 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\synpe_core.vhd,hdl"
2385 STATE="utd"
2386 TIME="1465836275"
2387 SIZE="671446"
2388 LIBRARY="spw"
2389 ENDFILE
2390 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
2391 STATE="utd"
2392 TIME="1465836275"
2393 SIZE="13746"
2394 LIBRARY="spw"
2395 ENDFILE
2396 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
2397 STATE="utd"
2398 TIME="1465836275"
2399 SIZE="7350"
2400 LIBRARY="spw"
2401 ENDFILE
2402 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
2403 STATE="utd"
2404 TIME="1465836275"
2405 SIZE="10828"
2406 LIBRARY="spw"
2407 ENDFILE
2408 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
2409 STATE="utd"
2410 TIME="1465836275"
2411 SIZE="22767"
2412 LIBRARY="synplify"
2413 ENDFILE
2414 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
2415 STATE="utd"
2416 TIME="1465836275"
2417 SIZE="9658"
2418 LIBRARY="synplify"
2419 ENDFILE
2420 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
2421 STATE="utd"
2422 TIME="1465836279"
2423 SIZE="87370"
2424 LIBRARY="techmap"
2425 ENDFILE
2426 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
2427 STATE="utd"
2428 TIME="1465836279"
2429 SIZE="68821"
2430 LIBRARY="techmap"
2431 ENDFILE
2432 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
2433 STATE="utd"
2434 TIME="1465836279"
2435 SIZE="8877"
2436 LIBRARY="techmap"
2437 ENDFILE
2438 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
2439 STATE="utd"
2440 TIME="1465836279"
2441 SIZE="2125"
2442 LIBRARY="techmap"
2443 ENDFILE
2444 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
2445 STATE="utd"
2446 TIME="1465836279"
2447 SIZE="16342"
2448 LIBRARY="techmap"
2449 ENDFILE
2450 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
2451 STATE="utd"
2452 TIME="1465836279"
2453 SIZE="9890"
2454 LIBRARY="techmap"
2455 ENDFILE
2456 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
2457 STATE="utd"
2458 TIME="1465836279"
2459 SIZE="9771"
2460 LIBRARY="techmap"
2461 ENDFILE
2462 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
2463 STATE="utd"
2464 TIME="1465836279"
2465 SIZE="3786"
2466 LIBRARY="techmap"
2467 ENDFILE
2468 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
2469 STATE="utd"
2470 TIME="1465836279"
2471 SIZE="6060"
2472 LIBRARY="techmap"
2473 ENDFILE
2474 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
2475 STATE="utd"
2476 TIME="1465836279"
2477 SIZE="8747"
2478 LIBRARY="techmap"
2479 ENDFILE
2480 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
2481 STATE="utd"
2482 TIME="1465836279"
2483 SIZE="20766"
2484 LIBRARY="techmap"
2485 ENDFILE
2486 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
2487 STATE="utd"
2488 TIME="1465836279"
2489 SIZE="47583"
2490 LIBRARY="techmap"
2491 ENDFILE
2492 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
2493 STATE="utd"
2494 TIME="1465836279"
2495 SIZE="49928"
2496 LIBRARY="techmap"
2497 ENDFILE
2498 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
2499 STATE="utd"
2500 TIME="1465836279"
2501 SIZE="2628"
2502 LIBRARY="techmap"
2503 ENDFILE
2504 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
2505 STATE="utd"
2506 TIME="1465836279"
2507 SIZE="31552"
2508 LIBRARY="techmap"
2509 ENDFILE
2510 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
2511 STATE="utd"
2512 TIME="1465836279"
2513 SIZE="11856"
2514 LIBRARY="techmap"
2515 ENDFILE
2516 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
2517 STATE="utd"
2518 TIME="1465836279"
2519 SIZE="3276"
2520 LIBRARY="techmap"
2521 ENDFILE
2522 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
2523 STATE="utd"
2524 TIME="1465836279"
2525 SIZE="9429"
2526 LIBRARY="techmap"
2527 ENDFILE
2528 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
2529 STATE="utd"
2530 TIME="1465836280"
2531 SIZE="1353"
2532 LIBRARY="techmap"
2533 ENDFILE
2534 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
2535 STATE="utd"
2536 TIME="1465836280"
2537 SIZE="3340"
2538 LIBRARY="techmap"
2539 ENDFILE
2540 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
2541 STATE="utd"
2542 TIME="1465836280"
2543 SIZE="3822"
2544 LIBRARY="techmap"
2545 ENDFILE
2546 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
2547 STATE="utd"
2548 TIME="1465836280"
2549 SIZE="2467"
2550 LIBRARY="techmap"
2551 ENDFILE
2552 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
2553 STATE="utd"
2554 TIME="1465836280"
2555 SIZE="4047"
2556 LIBRARY="techmap"
2557 ENDFILE
2558 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
2559 STATE="utd"
2560 TIME="1465836280"
2561 SIZE="55551"
2562 LIBRARY="techmap"
2563 ENDFILE
2564 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
2565 STATE="utd"
2566 TIME="1465836280"
2567 SIZE="2410"
2568 LIBRARY="techmap"
2569 ENDFILE
2570 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
2571 STATE="utd"
2572 TIME="1465836280"
2573 SIZE="2384"
2574 LIBRARY="techmap"
2575 ENDFILE
2576 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
2577 STATE="utd"
2578 TIME="1465836280"
2579 SIZE="5648"
2580 LIBRARY="techmap"
2581 ENDFILE
2582 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
2583 STATE="utd"
2584 TIME="1465836280"
2585 SIZE="6227"
2586 LIBRARY="techmap"
2587 ENDFILE
2588 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
2589 STATE="utd"
2590 TIME="1465836280"
2591 SIZE="41376"
2592 LIBRARY="techmap"
2593 ENDFILE
2594 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
2595 STATE="utd"
2596 TIME="1465836280"
2597 SIZE="4573"
2598 LIBRARY="techmap"
2599 ENDFILE
2600 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
2601 STATE="utd"
2602 TIME="1465836280"
2603 SIZE="3223"
2604 LIBRARY="techmap"
2605 ENDFILE
2606 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
2607 STATE="utd"
2608 TIME="1465836280"
2609 SIZE="3193"
2610 LIBRARY="techmap"
2611 ENDFILE
2612 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
2613 STATE="utd"
2614 TIME="1465836280"
2615 SIZE="4657"
2616 LIBRARY="techmap"
2617 ENDFILE
2618 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
2619 STATE="utd"
2620 TIME="1465836280"
2621 SIZE="6902"
2622 LIBRARY="techmap"
2623 ENDFILE
2624 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
2625 STATE="utd"
2626 TIME="1465836280"
2627 SIZE="4453"
2628 LIBRARY="techmap"
2629 ENDFILE
2630 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
2631 STATE="utd"
2632 TIME="1465836280"
2633 SIZE="4511"
2634 LIBRARY="techmap"
2635 ENDFILE
2636 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
2637 STATE="utd"
2638 TIME="1465836280"
2639 SIZE="3363"
2640 LIBRARY="techmap"
2641 ENDFILE
2642 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
2643 STATE="utd"
2644 TIME="1465836280"
2645 SIZE="24009"
2646 LIBRARY="techmap"
2647 ENDFILE
2648 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
2649 STATE="utd"
2650 TIME="1465836280"
2651 SIZE="3712"
2652 LIBRARY="techmap"
2653 ENDFILE
2654 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
2655 STATE="utd"
2656 TIME="1465836280"
2657 SIZE="1902"
2658 LIBRARY="techmap"
2659 ENDFILE
2660 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
2661 STATE="utd"
2662 TIME="1465836280"
2663 SIZE="5158"
2664 LIBRARY="techmap"
2665 ENDFILE
2666 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
2667 STATE="utd"
2668 TIME="1465836280"
2669 SIZE="5228"
2670 LIBRARY="techmap"
2671 ENDFILE
2672 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
2673 STATE="utd"
2674 TIME="1465836280"
2675 SIZE="3280"
2676 LIBRARY="techmap"
2677 ENDFILE
2678 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
2679 STATE="utd"
2680 TIME="1465836280"
2681 SIZE="3131"
2682 LIBRARY="techmap"
2683 ENDFILE
2684 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
2685 STATE="utd"
2686 TIME="1465836280"
2687 SIZE="3873"
2688 LIBRARY="techmap"
2689 ENDFILE
2690 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
2691 STATE="utd"
2692 TIME="1465836280"
2693 SIZE="1713"
2694 LIBRARY="techmap"
2695 ENDFILE
2696 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
2697 STATE="utd"
2698 TIME="1465836280"
2699 SIZE="7536"
2700 LIBRARY="techmap"
2701 ENDFILE
2702 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
2703 STATE="utd"
2704 TIME="1465836280"
2705 SIZE="2394"
2706 LIBRARY="techmap"
2707 ENDFILE
2708 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
2709 STATE="utd"
2710 TIME="1465836280"
2711 SIZE="1538"
2712 LIBRARY="techmap"
2713 ENDFILE
2714 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
2715 STATE="utd"
2716 TIME="1465836280"
2717 SIZE="5903"
2718 LIBRARY="techmap"
2719 ENDFILE
2720 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
2721 STATE="utd"
2722 TIME="1465836280"
2723 SIZE="2741"
2724 LIBRARY="techmap"
2725 ENDFILE
2726 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
2727 STATE="utd"
2728 TIME="1465836280"
2729 SIZE="10371"
2730 LIBRARY="techmap"
2731 ENDFILE
2732 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
2733 STATE="utd"
2734 TIME="1465836280"
2735 SIZE="5432"
2736 LIBRARY="techmap"
2737 ENDFILE
2738 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
2739 STATE="utd"
2740 TIME="1465836280"
2741 SIZE="5817"
2742 LIBRARY="techmap"
2743 ENDFILE
2744 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
2745 STATE="utd"
2746 TIME="1465836280"
2747 SIZE="6396"
2748 LIBRARY="techmap"
2749 ENDFILE
2750 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
2751 STATE="utd"
2752 TIME="1465836280"
2753 SIZE="6369"
2754 LIBRARY="techmap"
2755 ENDFILE
2756 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
2757 STATE="utd"
2758 TIME="1465836280"
2759 SIZE="7035"
2760 LIBRARY="techmap"
2761 ENDFILE
2762 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
2763 STATE="utd"
2764 TIME="1465836280"
2765 SIZE="4795"
2766 LIBRARY="techmap"
2767 ENDFILE
2768 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
2769 STATE="utd"
2770 TIME="1465836280"
2771 SIZE="14689"
2772 LIBRARY="techmap"
2773 ENDFILE
2774 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
2775 STATE="utd"
2776 TIME="1465836280"
2777 SIZE="8867"
2778 LIBRARY="techmap"
2779 ENDFILE
2780 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
2781 STATE="utd"
2782 TIME="1465836280"
2783 SIZE="8198"
2784 LIBRARY="techmap"
2785 ENDFILE
2786 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
2787 STATE="utd"
2788 TIME="1465836280"
2789 SIZE="1853"
2790 LIBRARY="techmap"
2791 ENDFILE
2792 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\synpe_maps.vhd,hdl"
2793 STATE="utd"
2794 TIME="1465836280"
2795 SIZE="23512"
2796 LIBRARY="techmap"
2797 ENDFILE
2798 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
2799 STATE="utd"
2800 TIME="1465836280"
2801 SIZE="12909"
2802 LIBRARY="techmap"
2803 ENDFILE
2804 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
2805 STATE="utd"
2806 TIME="1465836280"
2807 SIZE="10293"
2808 LIBRARY="techmap"
2809 ENDFILE
2810 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
2811 STATE="utd"
2812 TIME="1465836280"
2813 SIZE="4187"
2814 LIBRARY="techmap"
2815 ENDFILE
2816 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
2817 STATE="utd"
2818 TIME="1465836280"
2819 SIZE="7410"
2820 LIBRARY="techmap"
2821 ENDFILE
2822 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
2823 STATE="utd"
2824 TIME="1465836280"
2825 SIZE="6512"
2826 LIBRARY="techmap"
2827 ENDFILE
2828 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
2829 STATE="utd"
2830 TIME="1465836281"
2831 SIZE="1677"
2832 LIBRARY="techmap"
2833 ENDFILE
2834 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
2835 STATE="utd"
2836 TIME="1465836281"
2837 SIZE="8345"
2838 LIBRARY="techmap"
2839 ENDFILE
2840 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
2841 STATE="utd"
2842 TIME="1465836281"
2843 SIZE="1995"
2844 LIBRARY="techmap"
2845 ENDFILE
2846 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
2847 STATE="utd"
2848 TIME="1465836281"
2849 SIZE="22086"
2850 LIBRARY="techmap"
2851 ENDFILE
2852 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
2853 STATE="utd"
2854 TIME="1465836281"
2855 SIZE="9702"
2856 LIBRARY="techmap"
2857 ENDFILE
2858 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
2859 STATE="utd"
2860 TIME="1465836281"
2861 SIZE="3247"
2862 LIBRARY="techmap"
2863 ENDFILE
2864 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
2865 STATE="utd"
2866 TIME="1465836281"
2867 SIZE="3749"
2868 ENDFILE
2869 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
2870 STATE="utd"
2871 TIME="1465836281"
2872 SIZE="1426"
2873 ENDFILE
2874 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
2875 STATE="utd"
2876 TIME="1465836281"
2877 SIZE="6370"
2878 ENDFILE
2879 VALUE "<project>\..\..\boards\DISCOSPACE\default.pdc,pdc"
2880 STATE="utd"
2881 TIME="1479997712"
2882 SIZE="10350"
2883 ENDFILE
2884 VALUE "<project>\..\..\boards\DISCOSPACE\DISCOSPACE.sdc,sdc"
2885 STATE="utd"
2886 TIME="1480062337"
2887 SIZE="6372"
2888 ENDFILE
2889 VALUE "<project>\DISCOSPACE_top.vhd,hdl"
2890 STATE="utd"
2891 TIME="1479997682"
2892 SIZE="19589"
2893 ENDFILE
2894 ENDLIST
2895 LIST UsedFile
2896 ENDLIST
2897 LIST NewModulesInfo
2898 LIST "DISCOSPACE_top::work"
2899 FILE "<project>\DISCOSPACE_top.vhd,hdl"
2900 LIST ExcludePackageForSynthesis
2901 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
2902 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
2903 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
2904 VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
2905 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
2906 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
2907 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
2908 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
2909 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
2910 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
2911 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
2912 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
2913 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
2914 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
2915 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
2916 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
2917 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
2918 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
2919 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
2920 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
2921 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
2922 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
2923 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
2924 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
2925 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
2926 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
2927 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
2928 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
2929 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
2930 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
2931 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
2932 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
2933 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
2934 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
2935 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
2936 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
2937 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
2938 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
2939 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
2940 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
2941 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
2942 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
2943 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
2944 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
2945 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
2946 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
2947 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
2948 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
2949 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
2950 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
2951 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
2952 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
2953 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
2954 VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
2955 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
2956 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
2957 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
2958 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
2959 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
2960 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
2961 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
2962 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
2963 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
2964 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
2965 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
2966 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
2967 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
2968 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
2969 ENDLIST
2970 LIST UserCustomizedFileList
2971 LIST "ideSYNTHESIS"
2972 USE_LIST=TRUE
2973 FILELIST
2974 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
2975 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
2976 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
2977 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
2978 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\synpe_ftlib.vhd,hdl"
2979 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
2980 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
2981 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
2982 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
2983 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
2984 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
2985 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
2986 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
2987 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
2988 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
2989 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
2990 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
2991 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
2992 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
2993 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
2994 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
2995 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
2996 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
2997 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
2998 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
2999 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
3000 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
3001 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
3002 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
3003 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
3004 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
3005 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
3006 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
3007 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
3008 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
3009 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
3010 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
3011 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
3012 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
3013 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
3014 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
3015 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
3016 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
3017 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
3018 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
3019 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
3020 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
3021 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
3022 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
3023 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
3024 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
3025 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
3026 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
3027 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
3028 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
3029 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
3030 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
3031 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
3032 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
3033 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
3034 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
3035 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
3036 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
3037 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
3038 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
3039 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
3040 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
3041 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
3042 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
3043 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
3044 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
3045 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
3046 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
3047 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
3048 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
3049 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
3050 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
3051 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
3052 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
3053 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
3054 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
3055 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
3056 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
3057 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
3058 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
3059 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
3060 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\synpe_maps.vhd,hdl"
3061 VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
3062 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\synpe_core.vhd,hdl"
3063 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
3064 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
3065 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
3066 VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
3067 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
3068 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
3069 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
3070 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
3071 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
3072 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
3073 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
3074 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
3075 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
3076 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
3077 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
3078 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
3079 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
3080 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
3081 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
3082 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
3083 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
3084 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
3085 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
3086 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
3087 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
3088 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
3089 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
3090 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
3091 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
3092 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
3093 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
3094 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
3095 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
3096 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
3097 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
3098 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
3099 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
3100 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
3101 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\synpe_grlfpu.vhd,hdl"
3102 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\synpe_grlfpc.vhd,hdl"
3103 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
3104 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
3105 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
3106 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
3107 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
3108 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
3109 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
3110 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
3111 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
3112 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
3113 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
3114 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\synpe_leon3v3.vhd,hdl"
3115 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
3116 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
3117 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
3118 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
3119 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
3120 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
3121 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
3122 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
3123 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
3124 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
3125 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
3126 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
3127 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
3128 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
3129 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
3130 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
3131 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
3132 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
3133 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
3134 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
3135 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
3136 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
3137 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
3138 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
3139 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
3140 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
3141 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
3142 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
3143 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
3144 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
3145 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
3146 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
3147 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
3148 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
3149 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
3150 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
3151 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
3152 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
3153 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
3154 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
3155 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
3156 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
3157 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
3158 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
3159 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
3160 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
3161 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
3162 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
3163 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
3164 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
3165 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
3166 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
3167 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
3168 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
3169 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
3170 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
3171 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
3172 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
3173 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
3174 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
3175 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
3176 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
3177 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
3178 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
3179 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
3180 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
3181 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
3182 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
3183 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
3184 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
3185 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
3186 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
3187 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
3188 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
3189 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
3190 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
3191 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
3192 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
3193 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
3194 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
3195 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
3196 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
3197 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
3198 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
3199 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
3200 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
3201 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
3202 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
3203 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
3204 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
3205 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
3206 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
3207 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
3208 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
3209 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
3210 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
3211 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
3212 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
3213 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
3214 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
3215 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
3216 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
3217 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
3218 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
3219 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
3220 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
3221 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
3222 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
3223 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
3224 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
3225 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
3226 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
3227 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
3228 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
3229 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
3230 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
3231 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
3232 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
3233 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
3234 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
3235 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
3236 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
3237 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
3238 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
3239 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
3240 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
3241 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
3242 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
3243 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
3244 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
3245 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
3246 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
3247 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
3248 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
3249 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
3250 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
3251 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
3252 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
3253 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
3254 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
3255 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
3256 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
3257 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
3258 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
3259 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
3260 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
3261 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
3262 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
3263 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
3264 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
3265 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
3266 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
3267 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
3268 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
3269 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
3270 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
3271 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
3272 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
3273 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
3274 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
3275 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
3276 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
3277 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
3278 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
3279 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
3280 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
3281 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
3282 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
3283 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
3284 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
3285 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
3286 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
3287 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
3288 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
3289 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
3290 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
3291 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
3292 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
3293 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
3294 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
3295 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
3296 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
3297 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
3298 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
3299 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
3300 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
3301 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
3302 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
3303 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
3304 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
3305 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
3306 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
3307 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
3308 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
3309 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
3310 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
3311 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
3312 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
3313 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
3314 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
3315 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
3316 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
3317 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
3318 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
3319 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
3320 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
3321 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
3322 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
3323 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
3324 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
3325 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
3326 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
3327 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
3328 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
3329 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
3330 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
3331 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
3332 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
3333 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
3334 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
3335 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
3336 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
3337 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
3338 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
3339 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
3340 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
3341 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
3342 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
3343 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
3344 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
3345 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
3346 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
3347 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
3348 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
3349 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
3350 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
3351 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
3352 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
3353 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
3354 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
3355 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
3356 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
3357 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
3358 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
3359 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
3360 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
3361 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
3362 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
3363 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
3364 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
3365 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
3366 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
3367 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
3368 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
3369 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
3370 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
3371 VALUE "<project>\DISCOSPACE_top.vhd,hdl"
3372 ENDFILELIST
3373 ENDLIST
3374 LIST "ideSIMULATION"
3375 USE_LIST=TRUE
3376 FILELIST
3377 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
3378 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
3379 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
3380 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
3381 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
3382 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
3383 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
3384 VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
3385 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
3386 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
3387 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
3388 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
3389 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
3390 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
3391 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
3392 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
3393 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
3394 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
3395 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
3396 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
3397 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
3398 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
3399 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
3400 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
3401 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
3402 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
3403 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
3404 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
3405 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
3406 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
3407 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
3408 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
3409 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
3410 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
3411 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
3412 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
3413 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
3414 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
3415 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
3416 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
3417 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
3418 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
3419 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
3420 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
3421 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
3422 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
3423 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
3424 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
3425 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
3426 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
3427 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
3428 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
3429 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
3430 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
3431 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
3432 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
3433 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
3434 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
3435 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
3436 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
3437 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
3438 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
3439 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
3440 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
3441 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
3442 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
3443 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
3444 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
3445 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
3446 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
3447 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
3448 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
3449 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
3450 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
3451 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
3452 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
3453 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
3454 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
3455 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
3456 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
3457 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
3458 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
3459 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
3460 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
3461 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
3462 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
3463 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
3464 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
3465 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
3466 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
3467 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
3468 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
3469 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
3470 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
3471 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
3472 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
3473 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
3474 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
3475 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
3476 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
3477 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
3478 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
3479 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
3480 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
3481 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
3482 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
3483 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
3484 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
3485 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
3486 VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
3487 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
3488 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
3489 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
3490 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
3491 VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
3492 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
3493 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
3494 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
3495 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
3496 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
3497 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
3498 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
3499 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
3500 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
3501 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
3502 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
3503 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
3504 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
3505 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
3506 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
3507 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
3508 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
3509 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
3510 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
3511 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
3512 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
3513 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
3514 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
3515 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
3516 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
3517 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
3518 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
3519 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
3520 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
3521 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
3522 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
3523 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
3524 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
3525 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
3526 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
3527 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
3528 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
3529 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
3530 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
3531 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
3532 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
3533 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
3534 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
3535 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
3536 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
3537 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
3538 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
3539 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
3540 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
3541 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
3542 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
3543 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
3544 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
3545 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
3546 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
3547 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
3548 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
3549 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
3550 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
3551 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
3552 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
3553 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
3554 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
3555 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
3556 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
3557 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
3558 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
3559 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
3560 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
3561 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
3562 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
3563 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
3564 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
3565 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
3566 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
3567 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
3568 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
3569 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
3570 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
3571 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
3572 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
3573 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
3574 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
3575 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
3576 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
3577 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
3578 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
3579 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
3580 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
3581 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
3582 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
3583 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
3584 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
3585 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
3586 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
3587 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
3588 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
3589 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
3590 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
3591 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
3592 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
3593 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
3594 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
3595 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
3596 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
3597 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
3598 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
3599 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
3600 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
3601 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
3602 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
3603 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
3604 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
3605 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
3606 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
3607 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
3608 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
3609 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
3610 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
3611 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
3612 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
3613 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
3614 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
3615 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
3616 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
3617 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
3618 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
3619 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
3620 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
3621 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
3622 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
3623 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
3624 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
3625 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
3626 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
3627 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
3628 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
3629 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
3630 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
3631 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
3632 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
3633 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
3634 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
3635 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
3636 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
3637 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
3638 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
3639 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
3640 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
3641 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
3642 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
3643 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
3644 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
3645 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
3646 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
3647 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
3648 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
3649 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
3650 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
3651 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
3652 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
3653 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
3654 VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
3655 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
3656 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
3657 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
3658 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
3659 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
3660 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
3661 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
3662 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
3663 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
3664 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
3665 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
3666 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
3667 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
3668 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
3669 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
3670 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
3671 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
3672 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
3673 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
3674 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
3675 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
3676 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
3677 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
3678 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
3679 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
3680 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
3681 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
3682 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
3683 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
3684 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
3685 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
3686 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
3687 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
3688 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
3689 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
3690 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
3691 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
3692 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
3693 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
3694 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
3695 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
3696 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
3697 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
3698 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
3699 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
3700 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
3701 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
3702 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
3703 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
3704 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
3705 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
3706 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
3707 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
3708 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
3709 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
3710 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
3711 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
3712 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
3713 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
3714 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
3715 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
3716 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
3717 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
3718 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
3719 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
3720 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
3721 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
3722 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
3723 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
3724 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
3725 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
3726 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
3727 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
3728 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
3729 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
3730 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
3731 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
3732 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
3733 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
3734 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
3735 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
3736 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
3737 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
3738 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
3739 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
3740 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
3741 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
3742 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
3743 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
3744 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
3745 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
3746 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
3747 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
3748 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
3749 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
3750 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
3751 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
3752 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
3753 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
3754 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
3755 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
3756 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
3757 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
3758 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
3759 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
3760 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
3761 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
3762 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
3763 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
3764 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
3765 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
3766 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
3767 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
3768 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
3769 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
3770 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
3771 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
3772 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
3773 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
3774 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
3775 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
3776 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
3777 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
3778 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
3779 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
3780 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
3781 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
3782 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
3783 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
3784 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
3785 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
3786 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
3787 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
3788 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
3789 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
3790 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
3791 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
3792 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
3793 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
3794 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
3795 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
3796 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
3797 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
3798 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
3799 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
3800 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
3801 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
3802 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
3803 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
3804 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
3805 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
3806 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
3807 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
3808 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
3809 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
3810 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
3811 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
3812 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
3813 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
3814 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
3815 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
3816 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
3817 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
3818 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
3819 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
3820 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
3821 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
3822 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
3823 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
3824 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
3825 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
3826 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
3827 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
3828 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
3829 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
3830 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
3831 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
3832 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
3833 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
3834 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
3835 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
3836 VALUE "<project>\DISCOSPACE_top.vhd,hdl"
3837 ENDFILELIST
3838 ENDLIST
3839 ENDLIST
3840 ENDLIST
3841 ENDLIST
3842 LIST AssociatedStimulus
3843 ENDLIST
3844 LIST Other_Association
3845 ENDLIST
3846 LIST SimulationOptions
3847 UseAutomaticDoFile=true
3848 IncludeWaveDo=true
3849 Type=max
3850 RunTime=1000ns
3851 Resolution=1ps
3852 VsimOpt=
3853 EntityName=testbench
3854 TopInstanceName=<top>_0
3855 DoFileName=
3856 DoFileName2=wave.do
3857 DoFileParams=
3858 DisplayDUTWave=false
3859 LogAllSignals=false
3860 DumpVCD=false
3861 VCDFileName=power.vcd
3862 ENDLIST
3863 LIST ModelSimLibPath
3864 UseCustomPath=FALSE
3865 LibraryPath=
3866 ENDLIST
3867 LIST GlobalFlowOptions
3868 GenerateHDLAfterSynthesis=FALSE
3869 GenerateHDLAfterPhySynthesis=FALSE
3870 RunDRCAfterSynthesis=FALSE
3871 AutoCheckConstraints=TRUE
3872 UpdateViewDrawIni=TRUE
3873 UpdateModelSimIni=TRUE
3874 EnableFileDetection=FALSE
3875 NoIOMode=FALSE
3876 GenerateHDLFromSchematic=TRUE
3877 FlashProInputFile=stp
3878 SmartGenCompileReport=T
3879 ENDLIST
3880 LIST PhySynthesisOptions
3881 ENDLIST
3882 LIST Profiles
3883 NAME="Synplify 2012-03A-SP1-2"
3884 FUNCTION="Synthesis"
3885 TOOL="Synplify"
3886 LOCATION="C:\Synopsys\synplify_F201203ASP1-2\bin\synplify_pro.exe"
3887 PARAM=""
3888 BATCH=0
3889 EndProfile
3890 NAME="Questa"
3891 FUNCTION="Simulation"
3892 TOOL="ModelSim"
3893 LOCATION="C:\questasim64_10.5c\win64\questasim.exe"
3894 PARAM=""
3895 BATCH=0
3896 EndProfile
3897 NAME="WFL"
3898 FUNCTION="Stimulus"
3899 TOOL="WFL"
3900 LOCATION="syncad.exe"
3901 PARAM="-pwflite"
3902 BATCH=0
3903 EndProfile
3904 NAME="FlashPro"
3905 FUNCTION="Program"
3906 TOOL="FlashPro"
3907 LOCATION="C:\Microsemi\Libero_v9.1\Designer\bin\FlashPro.exe"
3908 PARAM=""
3909 BATCH=0
3910 EndProfile
3911 ENDLIST
3912 LIST ProjectState5.1
3913 ENDLIST
3914 LIST ExcludePackageForSimulation
3915 ENDLIST
3916 LIST ExcludePackageForSynthesis
3917 LIST DISCOSPACE_top
3918 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
3919 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
3920 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
3921 VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
3922 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
3923 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
3924 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
3925 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
3926 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
3927 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
3928 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
3929 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
3930 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
3931 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
3932 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
3933 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
3934 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
3935 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
3936 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
3937 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
3938 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
3939 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
3940 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
3941 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
3942 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
3943 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
3944 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
3945 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
3946 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
3947 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
3948 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
3949 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
3950 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
3951 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
3952 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
3953 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
3954 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
3955 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
3956 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
3957 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
3958 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
3959 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
3960 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
3961 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
3962 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
3963 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
3964 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
3965 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
3966 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
3967 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
3968 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
3969 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
3970 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
3971 VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
3972 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
3973 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
3974 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
3975 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
3976 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
3977 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
3978 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
3979 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
3980 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
3981 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
3982 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
3983 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
3984 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
3985 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
3986 ENDLIST
3987 ENDLIST
3988 LIST IncludeModuleForSimulation
3989 ENDLIST
3990 LIST CDBOrder
3991 ENDLIST
3992 LIST UserCustomizedFileList
3993 LIST "DISCOSPACE_top"
3994 LIST "ideSYNTHESIS"
3995 USE_LIST=TRUE
3996 FILELIST
3997 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
3998 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
3999 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
4000 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
4001 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\synpe_ftlib.vhd,hdl"
4002 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
4003 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
4004 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
4005 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
4006 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
4007 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
4008 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
4009 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
4010 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
4011 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
4012 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
4013 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
4014 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
4015 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
4016 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
4017 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
4018 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
4019 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
4020 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
4021 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
4022 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
4023 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
4024 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
4025 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
4026 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
4027 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
4028 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
4029 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
4030 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
4031 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
4032 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
4033 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
4034 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
4035 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
4036 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
4037 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
4038 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
4039 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
4040 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
4041 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
4042 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
4043 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
4044 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
4045 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
4046 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
4047 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
4048 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
4049 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
4050 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
4051 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
4052 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
4053 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
4054 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
4055 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
4056 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
4057 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
4058 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
4059 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
4060 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
4061 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
4062 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
4063 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
4064 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
4065 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
4066 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
4067 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
4068 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
4069 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
4070 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
4071 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
4072 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
4073 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
4074 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
4075 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
4076 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
4077 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
4078 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
4079 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
4080 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
4081 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
4082 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
4083 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\synpe_maps.vhd,hdl"
4084 VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
4085 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\synpe_core.vhd,hdl"
4086 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
4087 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
4088 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
4089 VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
4090 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
4091 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
4092 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
4093 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
4094 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
4095 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
4096 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
4097 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
4098 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
4099 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
4100 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
4101 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
4102 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
4103 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
4104 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
4105 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
4106 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
4107 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
4108 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
4109 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
4110 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
4111 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
4112 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
4113 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
4114 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
4115 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
4116 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
4117 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
4118 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
4119 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
4120 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
4121 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
4122 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
4123 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
4124 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\synpe_grlfpu.vhd,hdl"
4125 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\synpe_grlfpc.vhd,hdl"
4126 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
4127 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
4128 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
4129 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
4130 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
4131 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
4132 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
4133 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
4134 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
4135 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
4136 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
4137 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\synpe_leon3v3.vhd,hdl"
4138 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
4139 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
4140 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
4141 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
4142 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
4143 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
4144 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
4145 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
4146 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
4147 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
4148 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
4149 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
4150 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
4151 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
4152 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
4153 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
4154 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
4155 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
4156 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
4157 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
4158 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
4159 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
4160 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
4161 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
4162 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
4163 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
4164 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
4165 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
4166 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
4167 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
4168 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
4169 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
4170 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
4171 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
4172 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
4173 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
4174 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
4175 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
4176 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
4177 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
4178 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
4179 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
4180 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
4181 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
4182 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
4183 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
4184 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
4185 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
4186 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
4187 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
4188 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
4189 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
4190 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
4191 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
4192 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
4193 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
4194 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
4195 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
4196 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
4197 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
4198 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
4199 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
4200 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
4201 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
4202 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
4203 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
4204 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
4205 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
4206 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
4207 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
4208 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
4209 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
4210 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
4211 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
4212 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
4213 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
4214 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
4215 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
4216 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
4217 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
4218 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
4219 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
4220 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
4221 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
4222 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
4223 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
4224 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
4225 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
4226 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
4227 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
4228 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
4229 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
4230 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
4231 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
4232 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
4233 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
4234 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
4235 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
4236 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
4237 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
4238 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
4239 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
4240 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
4241 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
4242 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
4243 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
4244 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
4245 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
4246 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
4247 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
4248 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
4249 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
4250 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
4251 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
4252 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
4253 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
4254 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
4255 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
4256 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
4257 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
4258 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
4259 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
4260 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
4261 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
4262 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
4263 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
4264 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
4265 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
4266 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
4267 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
4268 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
4269 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
4270 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
4271 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
4272 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
4273 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
4274 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
4275 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
4276 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
4277 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
4278 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
4279 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
4280 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
4281 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
4282 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
4283 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
4284 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
4285 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
4286 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
4287 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
4288 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
4289 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
4290 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
4291 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
4292 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
4293 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
4294 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
4295 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
4296 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
4297 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
4298 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
4299 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
4300 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
4301 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
4302 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
4303 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
4304 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
4305 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
4306 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
4307 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
4308 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
4309 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
4310 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
4311 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
4312 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
4313 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
4314 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
4315 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
4316 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
4317 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
4318 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
4319 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
4320 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
4321 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
4322 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
4323 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
4324 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
4325 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
4326 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
4327 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
4328 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
4329 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
4330 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
4331 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
4332 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
4333 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
4334 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
4335 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
4336 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
4337 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
4338 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
4339 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
4340 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
4341 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
4342 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
4343 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
4344 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
4345 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
4346 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
4347 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
4348 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
4349 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
4350 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
4351 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
4352 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
4353 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
4354 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
4355 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
4356 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
4357 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
4358 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
4359 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
4360 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
4361 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
4362 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
4363 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
4364 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
4365 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
4366 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
4367 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
4368 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
4369 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
4370 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
4371 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
4372 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
4373 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
4374 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
4375 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
4376 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
4377 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
4378 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
4379 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
4380 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
4381 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
4382 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
4383 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
4384 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
4385 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
4386 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
4387 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
4388 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
4389 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
4390 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
4391 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
4392 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
4393 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
4394 VALUE "<project>\DISCOSPACE_top.vhd,hdl"
4395 ENDFILELIST
4396 ENDLIST
4397 LIST "ideSIMULATION"
4398 USE_LIST=TRUE
4399 FILELIST
4400 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\version.vhd,hdl"
4401 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config_types.vhd,hdl"
4402 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\config.vhd,hdl"
4403 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
4404 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdio.vhd,hdl"
4405 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\testlib.vhd,hdl"
4406 VALUE "<project>\..\..\..\GRLIB\lib\grlib\ftlib\mtie_ftlib.vhd,hdl"
4407 VALUE "<project>\..\..\..\GRLIB\lib\grlib\util\util.vhd,hdl"
4408 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc.vhd,hdl"
4409 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\sparc_disas.vhd,hdl"
4410 VALUE "<project>\..\..\..\GRLIB\lib\grlib\sparc\cpu_disas.vhd,hdl"
4411 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\multlib.vhd,hdl"
4412 VALUE "<project>\..\..\..\GRLIB\lib\grlib\modgen\leaves.vhd,hdl"
4413 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba.vhd,hdl"
4414 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\devices.vhd,hdl"
4415 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\defmst.vhd,hdl"
4416 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbctrl.vhd,hdl"
4417 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
4418 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_pkg.vhd,hdl"
4419 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb.vhd,hdl"
4420 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmst.vhd,hdl"
4421 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbmon.vhd,hdl"
4422 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\apbmon.vhd,hdl"
4423 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ambamon.vhd,hdl"
4424 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\dma2ahb_tp.vhd,hdl"
4425 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\amba_tp.vhd,hdl"
4426 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_pkg.vhd,hdl"
4427 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst_pkg.vhd,hdl"
4428 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv_pkg.vhd,hdl"
4429 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_util.vhd,hdl"
4430 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_mst.vhd,hdl"
4431 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_slv.vhd,hdl"
4432 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahbs.vhd,hdl"
4433 VALUE "<project>\..\..\..\GRLIB\lib\grlib\atf\at_ahb_ctrl.vhd,hdl"
4434 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synplify.vhd,hdl"
4435 VALUE "<project>\..\..\..\GRLIB\lib\synplify\sim\synattr.vhd,hdl"
4436 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\gencomp.vhd,hdl"
4437 VALUE "<project>\..\..\..\GRLIB\lib\techmap\gencomp\netcomp.vhd,hdl"
4438 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\memory_inferred.vhd,hdl"
4439 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\tap_inferred.vhd,hdl"
4440 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_inferred.vhd,hdl"
4441 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\mul_inferred.vhd,hdl"
4442 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddr_phy_inferred.vhd,hdl"
4443 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
4444 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\sim_pll.vhd,hdl"
4445 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\lpddr2_phy_inferred.vhd,hdl"
4446 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
4447 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\clkgen_proasic3e.vhd,hdl"
4448 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\ddr_proasic3e.vhd,hdl"
4449 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\memory_apa3e.vhd,hdl"
4450 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\pads_apa3e.vhd,hdl"
4451 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\tap_proasic3e.vhd,hdl"
4452 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allclkgen.vhd,hdl"
4453 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allddr.vhd,hdl"
4454 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
4455 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmul.vhd,hdl"
4456 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allpads.vhd,hdl"
4457 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\alltap.vhd,hdl"
4458 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkgen.vhd,hdl"
4459 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkmux.vhd,hdl"
4460 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkinv.vhd,hdl"
4461 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
4462 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_ireg.vhd,hdl"
4463 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddr_oreg.vhd,hdl"
4464 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ddrphy.vhd,hdl"
4465 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram.vhd,hdl"
4466 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram64.vhd,hdl"
4467 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2p.vhd,hdl"
4468 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_dp.vhd,hdl"
4469 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncfifo_2p.vhd,hdl"
4470 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\regfile_3p.vhd,hdl"
4471 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\tap.vhd,hdl"
4472 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techbuf.vhd,hdl"
4473 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\nandtree.vhd,hdl"
4474 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad.vhd,hdl"
4475 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkpad_ds.vhd,hdl"
4476 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad.vhd,hdl"
4477 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ds.vhd,hdl"
4478 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iodpad.vhd,hdl"
4479 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad.vhd,hdl"
4480 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ds.vhd,hdl"
4481 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\lvds_combo.vhd,hdl"
4482 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\odpad.vhd,hdl"
4483 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad.vhd,hdl"
4484 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ds.vhd,hdl"
4485 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\toutpad.vhd,hdl"
4486 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\skew_outpad.vhd,hdl"
4487 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mul_61x61.vhd,hdl"
4488 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\cpu_disas_net.vhd,hdl"
4489 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\ringosc.vhd,hdl"
4490 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grpci2_phy_net.vhd,hdl"
4491 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\system_monitor.vhd,hdl"
4492 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\grgates.vhd,hdl"
4493 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\inpad_ddr.vhd,hdl"
4494 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\outpad_ddr.vhd,hdl"
4495 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\iopad_ddr.vhd,hdl"
4496 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128bw.vhd,hdl"
4497 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram256bw.vhd,hdl"
4498 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram128.vhd,hdl"
4499 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram156bw.vhd,hdl"
4500 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\techmult.vhd,hdl"
4501 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\spictrl_net.vhd,hdl"
4502 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncrambw.vhd,hdl"
4503 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncram_2pbw.vhd,hdl"
4504 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\sdram_phy.vhd,hdl"
4505 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\from.vhd,hdl"
4506 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\syncreg.vhd,hdl"
4507 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\serdes.vhd,hdl"
4508 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\mtie_maps.vhd,hdl"
4509 VALUE "<project>\..\..\..\GRLIB\lib\spw\comp\spwcomp.vhd,hdl"
4510 VALUE "<project>\..\..\..\GRLIB\lib\spw\core\mtie_core.vhd,hdl"
4511 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_gen.vhd,hdl"
4512 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw2_gen.vhd,hdl"
4513 VALUE "<project>\..\..\..\GRLIB\lib\spw\wrapper\grspw_codec_gen.vhd,hdl"
4514 VALUE "<project>\..\..\..\GRLIB\lib\eth\comp\ethcomp.vhd,hdl"
4515 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_pkg.vhd,hdl"
4516 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_rstgen.vhd,hdl"
4517 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_edcl_ahb_mst.vhd,hdl"
4518 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst_gbit.vhd,hdl"
4519 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\eth_ahb_mst.vhd,hdl"
4520 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_rx.vhd,hdl"
4521 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_tx.vhd,hdl"
4522 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbit_gtx.vhd,hdl"
4523 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_tx.vhd,hdl"
4524 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_rx.vhd,hdl"
4525 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\greth_gbitc.vhd,hdl"
4526 VALUE "<project>\..\..\..\GRLIB\lib\eth\core\grethc.vhd,hdl"
4527 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gen.vhd,hdl"
4528 VALUE "<project>\..\..\..\GRLIB\lib\eth\wrapper\greth_gbit_gen.vhd,hdl"
4529 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\cancomp.vhd,hdl"
4530 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top.vhd,hdl"
4531 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_sync.vhd,hdl"
4532 VALUE "<project>\..\..\..\GRLIB\lib\opencores\can\can_top_core_sync.vhd,hdl"
4533 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\arith.vhd,hdl"
4534 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\mul32.vhd,hdl"
4535 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\arith\div32.vhd,hdl"
4536 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\memctrl.vhd,hdl"
4537 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl.vhd,hdl"
4538 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdctrl64.vhd,hdl"
4539 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\sdmctrl.vhd,hdl"
4540 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\srctrl.vhd,hdl"
4541 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ssrctrl.vhd,hdl"
4542 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrlc.vhd,hdl"
4543 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl.vhd,hdl"
4544 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl.vhd,hdl"
4545 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsrctrl8.vhd,hdl"
4546 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdmctrl.vhd,hdl"
4547 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftmctrl.vhd,hdl"
4548 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\memctrl\ftsdctrl64.vhd,hdl"
4549 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpu\mtie_grlfpu.vhd,hdl"
4550 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\grlfpc\mtie_grlfpc.vhd,hdl"
4551 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuconfig.vhd,hdl"
4552 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmuiface.vhd,hdl"
4553 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\libmmu.vhd,hdl"
4554 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlbcam.vhd,hdl"
4555 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulrue.vhd,hdl"
4556 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmulru.vhd,hdl"
4557 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutlb.vhd,hdl"
4558 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmutw.vhd,hdl"
4559 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\srmmu\mmu.vhd,hdl"
4560 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\leon3.vhd,hdl"
4561 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3\grfpushwx.vhd,hdl"
4562 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\leon3v3\mtie_leon3v3.vhd,hdl"
4563 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp.vhd,hdl"
4564 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqmp2x.vhd,hdl"
4565 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp.vhd,hdl"
4566 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\irqmp\irqamp2x.vhd,hdl"
4567 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\l2cache\v2-pkg\l2cache.vhd,hdl"
4568 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can.vhd,hdl"
4569 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mod.vhd,hdl"
4570 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc.vhd,hdl"
4571 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_mc.vhd,hdl"
4572 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\canmux.vhd,hdl"
4573 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_rd.vhd,hdl"
4574 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\can_oc_core.vhd,hdl"
4575 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\can\grcan.vhd,hdl"
4576 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\misc.vhd,hdl"
4577 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\rstgen.vhd,hdl"
4578 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gptimer.vhd,hdl"
4579 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbram.vhd,hdl"
4580 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbdpram.vhd,hdl"
4581 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mmb.vhd,hdl"
4582 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace_mb.vhd,hdl"
4583 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbtrace.vhd,hdl"
4584 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpio.vhd,hdl"
4585 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram.vhd,hdl"
4586 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ftahbram2.vhd,hdl"
4587 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbstat.vhd,hdl"
4588 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\logan.vhd,hdl"
4589 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbps2.vhd,hdl"
4590 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom_package.vhd,hdl"
4591 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\charrom.vhd,hdl"
4592 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\apbvga.vhd,hdl"
4593 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb2ahb.vhd,hdl"
4594 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbbridge.vhd,hdl"
4595 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\svgactrl.vhd,hdl"
4596 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grfifo.vhd,hdl"
4597 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gradcdac.vhd,hdl"
4598 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grsysmon.vhd,hdl"
4599 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\gracectrl.vhd,hdl"
4600 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgpreg.vhd,hdl"
4601 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\memscrub.vhd,hdl"
4602 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahb_mst_iface.vhd,hdl"
4603 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grgprbank.vhd,hdl"
4604 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate.vhd,hdl"
4605 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grclkgate2x.vhd,hdl"
4606 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grtimer.vhd,hdl"
4607 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grpulse.vhd,hdl"
4608 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\grversion.vhd,hdl"
4609 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\misc\ahbfrom.vhd,hdl"
4610 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbp.vhd,hdl"
4611 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\ambatest\ahbtbm.vhd,hdl"
4612 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\net\net.vhd,hdl"
4613 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\uart.vhd,hdl"
4614 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\libdcom.vhd,hdl"
4615 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\apbuart.vhd,hdl"
4616 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom.vhd,hdl"
4617 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\dcom_uart.vhd,hdl"
4618 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\uart\ahbuart.vhd,hdl"
4619 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sim.vhd,hdl"
4620 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram.vhd,hdl"
4621 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sramft.vhd,hdl"
4622 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\sram16.vhd,hdl"
4623 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\phy.vhd,hdl"
4624 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ahbrep.vhd,hdl"
4625 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\delay_wire.vhd,hdl"
4626 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\pwm_check.vhd,hdl"
4627 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ramback.vhd,hdl"
4628 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\zbtssram.vhd,hdl"
4629 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\slavecheck.vhd,hdl"
4630 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtrace.vhd,hdl"
4631 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\spwtracev.vhd,hdl"
4632 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddrram.vhd,hdl"
4633 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr2ram.vhd,hdl"
4634 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\sim\ddr3ram.vhd,hdl"
4635 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtag.vhd,hdl"
4636 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\libjtagcom.vhd,hdl"
4637 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom.vhd,hdl"
4638 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag.vhd,hdl"
4639 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\ahbjtag_bsd.vhd,hdl"
4640 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanctrl.vhd,hdl"
4641 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregs.vhd,hdl"
4642 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\bscanregsbd.vhd,hdl"
4643 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagcom2.vhd,hdl"
4644 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\jtag\jtagtst.vhd,hdl"
4645 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\ethernet_mac.vhd,hdl"
4646 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth.vhd,hdl"
4647 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_mb.vhd,hdl"
4648 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit.vhd,hdl"
4649 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\greth_gbit_mb.vhd,hdl"
4650 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\grethm.vhd,hdl"
4651 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\rgmii.vhd,hdl"
4652 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\comma_detect.vhd,hdl"
4653 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\greth\elastic_buffer.vhd,hdl"
4654 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\spacewire.vhd,hdl"
4655 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw.vhd,hdl"
4656 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2.vhd,hdl"
4657 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspwm.vhd,hdl"
4658 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw2_phy.vhd,hdl"
4659 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_codec_clockgate.vhd,hdl"
4660 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\spacewire\grspw_phy.vhd,hdl"
4661 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pkg.vhd,hdl"
4662 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\gr1553b_pads.vhd,hdl"
4663 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\gr1553b\simtrans1553.vhd,hdl"
4664 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandpkg.vhd,hdl"
4665 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrlx.vhd,hdl"
4666 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\nand\nandfctrl.vhd,hdl"
4667 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\clk2x.vhd,hdl"
4668 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod.vhd,hdl"
4669 VALUE "<project>\..\..\..\GRLIB\lib\gaisler\clk2x\qmod_prect.vhd,hdl"
4670 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\memoryctrl.vhd,hdl"
4671 VALUE "<project>\..\..\..\GRLIB\lib\esa\memoryctrl\mctrl.vhd,hdl"
4672 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\conversions.vhd,hdl"
4673 VALUE "<project>\..\..\..\GRLIB\lib\fmf\utilities\gen_utils.vhd,hdl"
4674 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\flash.vhd,hdl"
4675 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\s25fl064a.vhd,hdl"
4676 VALUE "<project>\..\..\..\GRLIB\lib\fmf\flash\m25p80.vhd,hdl"
4677 VALUE "<project>\..\..\..\GRLIB\lib\fmf\fifo\idt7202.vhd,hdl"
4678 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\functions.vhd,hdl"
4679 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\core_burst.vhd,hdl"
4680 VALUE "<project>\..\..\..\GRLIB\lib\gsi\ssram\g880e18bt.vhd,hdl"
4681 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices_list.vhd,hdl"
4682 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\apb_devices\apb_devices.vhd,hdl"
4683 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\memctrlr.vhd,hdl"
4684 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-0ws.vhd,hdl"
4685 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB_NONFREE\lib\iap\.\memctrlr\srctrle-1ws.vhd,hdl"
4686 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\data_type_pkg.vhd,hdl"
4687 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_purpose.vhd,hdl"
4688 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ADDRcntr.vhd,hdl"
4689 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ALU.vhd,hdl"
4690 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Adder.vhd,hdl"
4691 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_Divider2.vhd,hdl"
4692 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
4693 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC.vhd,hdl"
4694 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_CONTROLER.vhd,hdl"
4695 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX.vhd,hdl"
4696 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_MUX2.vhd,hdl"
4697 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MAC_REG.vhd,hdl"
4698 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUX2.vhd,hdl"
4699 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\MUXN.vhd,hdl"
4700 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
4701 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\REG.vhd,hdl"
4702 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_FF.vhd,hdl"
4703 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Shifter.vhd,hdl"
4704 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TwoComplementer.vhd,hdl"
4705 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clock_Divider.vhd,hdl"
4706 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_to_level.vhd,hdl"
4707 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\lpp_front_detection.vhd,hdl"
4708 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\SYNC_VALID_BIT.vhd,hdl"
4709 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\RR_Arbiter_4.vhd,hdl"
4710 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\general_counter.vhd,hdl"
4711 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\ramp_generator.vhd,hdl"
4712 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\TimeGenAdvancedTrigger.vhd,hdl"
4713 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\apb_devices_list.vhd,hdl"
4714 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\lpp_amba.vhd,hdl"
4715 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_amba\APB_ADVANCED_TRIGGER.vhd,hdl"
4716 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
4717 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
4718 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\iir_filter.vhd,hdl"
4719 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\FILTERcfg.vhd,hdl"
4720 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM.vhd,hdl"
4721 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CEL.vhd,hdl"
4722 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\RAM_CTRLR_v2.vhd,hdl"
4723 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_CONTROL.vhd,hdl"
4724 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2_DATAFLOW.vhd,hdl"
4725 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v2.vhd,hdl"
4726 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3_DATAFLOW.vhd,hdl"
4727 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\iir_filter\IIR_CEL_CTRLR_v3.vhd,hdl"
4728 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_pkg.vhd,hdl"
4729 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
4730 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_integrator.vhd,hdl"
4731 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_downsampler.vhd,hdl"
4732 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_comb.vhd,hdl"
4733 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr.vhd,hdl"
4734 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control.vhd,hdl"
4735 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_add_sub.vhd,hdl"
4736 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_address_gen.vhd,hdl"
4737 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_r2.vhd,hdl"
4738 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic_lfr_control_r2.vhd,hdl"
4739 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_downsampling\Downsampling.vhd,hdl"
4740 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function_pkg.vhd,hdl"
4741 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\window_function.vhd,hdl"
4742 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_processing.vhd,hdl"
4743 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\window_function\WF_rom.vhd,hdl"
4744 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_memory.vhd,hdl"
4745 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO.vhd,hdl"
4746 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared.vhd,hdl"
4747 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_control.vhd,hdl"
4748 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_0.vhd,hdl"
4749 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lpp_FIFO_4_Shared_headreg_latency_1.vhd,hdl"
4750 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_memory\lppFIFOxN.vhd,hdl"
4751 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fft_components.vhd,hdl"
4752 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\lpp_fft.vhd,hdl"
4753 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actar.vhd,hdl"
4754 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\actram.vhd,hdl"
4755 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\CoreFFT.vhd,hdl"
4756 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftDp.vhd,hdl"
4757 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\fftSm.vhd,hdl"
4758 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\primitives.vhd,hdl"
4759 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\twiddle.vhd,hdl"
4760 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Driver_FFT.vhd,hdl"
4761 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\FFT.vhd,hdl"
4762 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
4763 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lpp_cna.vhd,hdl"
4764 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\APB_LFR_CAL.vhd,hdl"
4765 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
4766 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_WRITER.vhd,hdl"
4767 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\SPI_DAC_DRIVER.vhd,hdl"
4768 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\dynamic_freq_div.vhd,hdl"
4769 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\lfr_cal_driver.vhd,hdl"
4770 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management.vhd,hdl"
4771 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
4772 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\apb_lfr_management.vhd,hdl"
4773 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
4774 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_counter.vhd,hdl"
4775 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\coarse_time_counter.vhd,hdl"
4776 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\fine_time_max_value_gen.vhd,hdl"
4777 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_ad_Conv.vhd,hdl"
4778 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
4779 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401.vhd,hdl"
4780 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
4781 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
4782 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
4783 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
4784 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
4785 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
4786 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
4787 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
4788 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
4789 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
4790 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
4791 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
4792 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
4793 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
4794 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
4795 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
4796 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
4797 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
4798 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
4799 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
4800 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
4801 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
4802 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
4803 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
4804 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
4805 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
4806 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
4807 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
4808 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
4809 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
4810 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
4811 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
4812 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
4813 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
4814 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
4815 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
4816 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
4817 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
4818 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
4819 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
4820 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
4821 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
4822 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
4823 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
4824 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
4825 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
4826 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
4827 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
4828 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
4829 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
4830 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
4831 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
4832 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
4833 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
4834 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
4835 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
4836 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
4837 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
4838 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
4839 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
4840 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
4841 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
4842 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
4843 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
4844 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
4845 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
4846 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
4847 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
4848 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
4849 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
4850 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
4851 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
4852 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
4853 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
4854 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
4855 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
4856 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
4857 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
4858 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
4859 VALUE "<project>\DISCOSPACE_top.vhd,hdl"
4860 ENDFILELIST
4861 ENDLIST
4862 ENDLIST
4863 ENDLIST
4864 LIST OpenedFileList
4865 ENDLIST
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@@ -0,0 +1,47
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=DISCOSPACE_top
5 BOARD=DISCOSPACE
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= DISCOSPACE_top.vhd
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/DISCOSPACE.sdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/DISCOSPACE.sdc
19 CLEAN=soft-clean
20
21 TECHLIBS = proasic3e
22
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX
25
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 ./lpp_bootloader \
29 ./lpp_uart \
30 ./lpp_usb \
31 ./dsp/lpp_fft_rtax \
32 ./lpp_sim/CY7C1061DV33 \
33
34 FILESKIP =i2cmst.vhd \
35 APB_MULTI_DIODE.vhd \
36 APB_SIMPLE_DIODE.vhd \
37 Top_MatrixSpec.vhd \
38 APB_FFT.vhd \
39 CoreFFT_simu.vhd \
40 lpp_lfr_apbreg_simu.vhd \
41 sgmii.vhd
42
43 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
45
46 ################## project specific targets ##########################
47
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@@ -0,0 +1,128
1 -- TimeGenAdvancedTrigger.vhd
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Alexis Jeandet
21 -- Mail : alexis.jeandet@lpp.polytechnique.fr
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 ENTITY TimeGenAdvancedTrigger IS
28 PORT(
29 clk : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
31
32 SPW_Tickout : IN STD_LOGIC;
33
34 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
35 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
36
37 TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
38 TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
39 Restart : IN STD_LOGIC;
40 StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
41
42 BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
43 -- else Trigger output is driven by advanced trig
44 Trigger : OUT STD_LOGIC
45
46 );
47
48 END TimeGenAdvancedTrigger;
49
50
51 ARCHITECTURE beh OF TimeGenAdvancedTrigger IS
52
53 SIGNAL AdvancedTrigger : STD_LOGIC:='0';
54 SIGNAL AdvancedTrigger_l0 : STD_LOGIC:='0';
55 SIGNAL AdvancedTrigger_l1 : STD_LOGIC:='0';
56 SIGNAL started : STD_LOGIC:='0';
57 SIGNAL periodCntr : STD_LOGIC_VECTOR(3 DOWNTO 0):=(OTHERS=>'0');
58 SIGNAL coarseTime0 : STD_LOGIC:='0';
59
60
61 BEGIN
62
63 Trigger <= SPW_Tickout WHEN BypassTickout = '1' ELSE AdvancedTrigger;
64 AdvancedTrigger <= AdvancedTrigger_l0 AND AdvancedTrigger_l1;
65
66
67 PROCESS(clk,rstn)
68 BEGIN
69 IF rstn = '0' THEN
70 started <= '0';
71 AdvancedTrigger_l0 <='0';
72 AdvancedTrigger_l1 <='0';
73 coarseTime0 <= '0';
74 periodCntr <= (OTHERS => '0');
75
76 ELSIF clk'event AND clk = '1' THEN
77
78 coarseTime0 <= CoarseTime(0);
79
80 -- Detection of start date and handling of Restart
81 IF Restart = '1' THEN
82 started <= '0';
83 ELSIF StartDate = CoarseTime THEN
84 started <= '1';
85 END IF;
86
87 -- Fine time based comparator for phase shift
88 IF TrigShift = FineTime THEN
89 AdvancedTrigger_l0 <='1';
90 ELSE
91 AdvancedTrigger_l0 <='0';
92 END IF;
93
94 -- Second filter, generates a pulse for each N seconds since StartDate
95 IF started = '1' THEN
96 IF periodCntr = "0000" THEN
97 AdvancedTrigger_l1 <='1';
98 periodCntr <= TrigPeriod;
99 ELSIF CoarseTime(0) /= coarseTime0 THEN
100 periodCntr <= STD_LOGIC_VECTOR(SIGNED(periodCntr) - 1);
101 AdvancedTrigger_l1 <='0';
102 END IF;
103 ELSE
104 periodCntr <= (OTHERS => '0');
105 AdvancedTrigger_l1 <='0';
106 END IF;
107
108 END IF;
109 END PROCESS;
110
111 END beh;
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
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@@ -0,0 +1,158
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 --use ieee.numeric_std.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
29 library lpp;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_amba.all;
32 use lpp.general_purpose.TimeGenAdvancedTrigger;
33
34
35 entity APB_ADVANCED_TRIGGER is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 rstn : in std_ulogic;
44 clk : in std_ulogic;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
47
48 SPW_Tickout : IN STD_LOGIC;
49 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
51
52 Trigger : OUT STD_LOGIC
53 );
54 end;
55
56
57 architecture beh of APB_ADVANCED_TRIGGER is
58
59 constant REVISION : integer := 1;
60
61 constant pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask));
64
65
66
67 type adv_trig_type is record
68 TrigPeriod : STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
69 TrigShift : STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
70 Restart : STD_LOGIC;
71 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
72 BypassTickout : STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
73 end record;
74
75 type adv_trig_regs is record
76 CFG : STD_LOGIC_VECTOR(31 DOWNTO 0);
77 Restart : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 end record;
80
81 signal r : adv_trig_regs;
82 signal adv_trig : adv_trig_type;
83 signal Rdata : std_logic_vector(31 downto 0);
84
85
86 begin
87
88
89
90 adv_trig0: TimeGenAdvancedTrigger
91 PORT MAP(
92 clk => clk,
93 rstn => rstn,
94
95 SPW_Tickout => SPW_Tickout,
96
97 CoarseTime => CoarseTime,
98 FineTime => FineTime,
99
100 TrigPeriod => adv_trig.TrigPeriod,
101 TrigShift => adv_trig.TrigShift,
102 Restart => adv_trig.Restart,
103 StartDate => adv_trig.StartDate,
104
105 BypassTickout => adv_trig.BypassTickout,
106 Trigger => Trigger
107
108 );
109
110 adv_trig.BypassTickout <= r.CFG(0);
111 adv_trig.TrigPeriod <= r.CFG(7 downto 4);
112 adv_trig.TrigShift <= r.CFG(31 downto 16);
113 adv_trig.Restart <= r.Restart(0);
114 adv_trig.StartDate <= r.StartDate;
115
116
117 process(rstn,clk)
118 begin
119 if rstn = '0' then
120 r.CFG <= (others=>'0');
121 r.Restart <= (others=>'0');
122 r.StartDate <= (others=>'0');
123 elsif clk'event and clk = '1' then
124
125 --APB Write OP
126 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
127 case apbi.paddr(abits-1 downto 2) is
128 when "000000" =>
129 r.CFG <= apbi.pwdata;
130 when "000001" =>
131 r.Restart <= apbi.pwdata;
132 when "000010" =>
133 r.StartDate <= apbi.pwdata;
134 when others =>
135 null;
136 end case;
137 end if;
138
139 --APB READ OP
140 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
141 case apbi.paddr(abits-1 downto 2) is
142 when "000000" =>
143 Rdata <= r.CFG;
144 when "000001" =>
145 Rdata <= r.Restart;
146 when "000010" =>
147 Rdata <= r.StartDate;
148 when others =>
149 Rdata <= r.Restart;
150 end case;
151 end if;
152
153 end if;
154 apbo.pconfig <= pconfig;
155 end process;
156
157 apbo.prdata <= Rdata when apbi.penable = '1';
158 end beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,420 +1,442
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 --UPDATE
22 --UPDATE
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30 USE IEEE.NUMERIC_STD.ALL;
30 USE IEEE.NUMERIC_STD.ALL;
31
31
32
32
33
33
34 PACKAGE general_purpose IS
34 PACKAGE general_purpose IS
35
35
36 COMPONENT general_counter
36 COMPONENT general_counter
37 GENERIC (
37 GENERIC (
38 CYCLIC : STD_LOGIC;
38 CYCLIC : STD_LOGIC;
39 NB_BITS_COUNTER : INTEGER;
39 NB_BITS_COUNTER : INTEGER;
40 RST_VALUE : INTEGER);
40 RST_VALUE : INTEGER);
41 PORT (
41 PORT (
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
45 set : IN STD_LOGIC;
45 set : IN STD_LOGIC;
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 add1 : IN STD_LOGIC;
47 add1 : IN STD_LOGIC;
48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
49 END COMPONENT;
49 END COMPONENT;
50
50
51 COMPONENT Clk_divider IS
51 COMPONENT Clk_divider IS
52 GENERIC(OSC_freqHz : INTEGER := 50000000;
52 GENERIC(OSC_freqHz : INTEGER := 50000000;
53 TargetFreq_Hz : INTEGER := 50000);
53 TargetFreq_Hz : INTEGER := 50000);
54 PORT (clk : IN STD_LOGIC;
54 PORT (clk : IN STD_LOGIC;
55 reset : IN STD_LOGIC;
55 reset : IN STD_LOGIC;
56 clk_divided : OUT STD_LOGIC);
56 clk_divided : OUT STD_LOGIC);
57 END COMPONENT;
57 END COMPONENT;
58
58
59
59
60 COMPONENT Clk_divider2 IS
60 COMPONENT Clk_divider2 IS
61 GENERIC(N : INTEGER := 16);
61 GENERIC(N : INTEGER := 16);
62 PORT(
62 PORT(
63 clk_in : IN STD_LOGIC;
63 clk_in : IN STD_LOGIC;
64 clk_out : OUT STD_LOGIC);
64 clk_out : OUT STD_LOGIC);
65 END COMPONENT;
65 END COMPONENT;
66
66
67 COMPONENT Adder IS
67 COMPONENT Adder IS
68 GENERIC(
68 GENERIC(
69 Input_SZ_A : INTEGER := 16;
69 Input_SZ_A : INTEGER := 16;
70 Input_SZ_B : INTEGER := 16
70 Input_SZ_B : INTEGER := 16
71
71
72 );
72 );
73 PORT(
73 PORT(
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 reset : IN STD_LOGIC;
75 reset : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
77 load : IN STD_LOGIC;
77 load : IN STD_LOGIC;
78 add : IN STD_LOGIC;
78 add : IN STD_LOGIC;
79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
82 );
82 );
83 END COMPONENT;
83 END COMPONENT;
84
84
85 COMPONENT Adder_V0 IS
85 COMPONENT Adder_V0 IS
86 GENERIC(
86 GENERIC(
87 Input_SZ_A : INTEGER := 16;
87 Input_SZ_A : INTEGER := 16;
88 Input_SZ_B : INTEGER := 16
88 Input_SZ_B : INTEGER := 16
89
89
90 );
90 );
91 PORT(
91 PORT(
92 clk : IN STD_LOGIC;
92 clk : IN STD_LOGIC;
93 reset : IN STD_LOGIC;
93 reset : IN STD_LOGIC;
94 clr : IN STD_LOGIC;
94 clr : IN STD_LOGIC;
95 add : IN STD_LOGIC;
95 add : IN STD_LOGIC;
96 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
96 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
97 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
97 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
98 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
98 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
99 );
99 );
100 END COMPONENT;
100 END COMPONENT;
101
101
102 COMPONENT ADDRcntr IS
102 COMPONENT ADDRcntr IS
103 PORT(
103 PORT(
104 clk : IN STD_LOGIC;
104 clk : IN STD_LOGIC;
105 reset : IN STD_LOGIC;
105 reset : IN STD_LOGIC;
106 count : IN STD_LOGIC;
106 count : IN STD_LOGIC;
107 clr : IN STD_LOGIC;
107 clr : IN STD_LOGIC;
108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
109 );
109 );
110 END COMPONENT;
110 END COMPONENT;
111
111
112 COMPONENT ALU IS
112 COMPONENT ALU IS
113 GENERIC(
113 GENERIC(
114 Arith_en : INTEGER := 1;
114 Arith_en : INTEGER := 1;
115 Logic_en : INTEGER := 1;
115 Logic_en : INTEGER := 1;
116 Input_SZ_1 : INTEGER := 16;
116 Input_SZ_1 : INTEGER := 16;
117 Input_SZ_2 : INTEGER := 9;
117 Input_SZ_2 : INTEGER := 9;
118 COMP_EN : INTEGER := 0 -- 1 => No Comp
118 COMP_EN : INTEGER := 0 -- 1 => No Comp
119
119
120 );
120 );
121 PORT(
121 PORT(
122 clk : IN STD_LOGIC;
122 clk : IN STD_LOGIC;
123 reset : IN STD_LOGIC;
123 reset : IN STD_LOGIC;
124 ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
124 ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
125 comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
125 comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
129 );
129 );
130 END COMPONENT;
130 END COMPONENT;
131
131
132 COMPONENT ALU_V0 IS
132 COMPONENT ALU_V0 IS
133 GENERIC(
133 GENERIC(
134 Arith_en : INTEGER := 1;
134 Arith_en : INTEGER := 1;
135 Logic_en : INTEGER := 1;
135 Logic_en : INTEGER := 1;
136 Input_SZ_1 : INTEGER := 16;
136 Input_SZ_1 : INTEGER := 16;
137 Input_SZ_2 : INTEGER := 9
137 Input_SZ_2 : INTEGER := 9
138
138
139 );
139 );
140 PORT(
140 PORT(
141 clk : IN STD_LOGIC;
141 clk : IN STD_LOGIC;
142 reset : IN STD_LOGIC;
142 reset : IN STD_LOGIC;
143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
147 );
147 );
148 END COMPONENT;
148 END COMPONENT;
149
149
150 COMPONENT MAC_V0 IS
150 COMPONENT MAC_V0 IS
151 GENERIC(
151 GENERIC(
152 Input_SZ_A : INTEGER := 8;
152 Input_SZ_A : INTEGER := 8;
153 Input_SZ_B : INTEGER := 8
153 Input_SZ_B : INTEGER := 8
154
154
155 );
155 );
156 PORT(
156 PORT(
157 clk : IN STD_LOGIC;
157 clk : IN STD_LOGIC;
158 reset : IN STD_LOGIC;
158 reset : IN STD_LOGIC;
159 clr_MAC : IN STD_LOGIC;
159 clr_MAC : IN STD_LOGIC;
160 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
160 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
161 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
161 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
162 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
163 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
163 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
164 );
164 );
165 END COMPONENT;
165 END COMPONENT;
166
166
167 ---------------------------------------------------------
167 ---------------------------------------------------------
168 -------- // Sélection grace a l'entrée "ctrl" \\ --------
168 -------- // Sélection grace a l'entrée "ctrl" \\ --------
169 ---------------------------------------------------------
169 ---------------------------------------------------------
170 CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
170 CONSTANT ctrl_IDLE : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
171 CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
171 CONSTANT ctrl_MAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
172 CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
172 CONSTANT ctrl_MULT : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
173 CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
173 CONSTANT ctrl_ADD : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
174 CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
174 CONSTANT ctrl_CLRMAC : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
175
175
176
176
177 CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
177 CONSTANT IDLE_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
178 CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
178 CONSTANT MAC_op_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
179 CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
179 CONSTANT MULT_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
180 CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
180 CONSTANT ADD_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
181 CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
181 CONSTANT CLR_MAC_V0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
182 ---------------------------------------------------------
182 ---------------------------------------------------------
183
183
184 COMPONENT MAC IS
184 COMPONENT MAC IS
185 GENERIC(
185 GENERIC(
186 Input_SZ_A : INTEGER := 8;
186 Input_SZ_A : INTEGER := 8;
187 Input_SZ_B : INTEGER := 8;
187 Input_SZ_B : INTEGER := 8;
188 COMP_EN : INTEGER := 0 -- 1 => No Comp
188 COMP_EN : INTEGER := 0 -- 1 => No Comp
189 );
189 );
190 PORT(
190 PORT(
191 clk : IN STD_LOGIC;
191 clk : IN STD_LOGIC;
192 reset : IN STD_LOGIC;
192 reset : IN STD_LOGIC;
193 clr_MAC : IN STD_LOGIC;
193 clr_MAC : IN STD_LOGIC;
194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
199 );
199 );
200 END COMPONENT;
200 END COMPONENT;
201
201
202 COMPONENT TwoComplementer IS
202 COMPONENT TwoComplementer IS
203 GENERIC(
203 GENERIC(
204 Input_SZ : INTEGER := 16);
204 Input_SZ : INTEGER := 16);
205 PORT(
205 PORT(
206 clk : IN STD_LOGIC; --! Horloge du composant
206 clk : IN STD_LOGIC; --! Horloge du composant
207 reset : IN STD_LOGIC; --! Reset general du composant
207 reset : IN STD_LOGIC; --! Reset general du composant
208 clr : IN STD_LOGIC; --! Un reset spécifique au programme
208 clr : IN STD_LOGIC; --! Un reset spécifique au programme
209 TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément
209 TwoComp : IN STD_LOGIC; --! Autorise l'utilisation du complément
210 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée
210 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); --! Opérande d'entrée
211 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non
211 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0) --! Résultat, opérande complémenté ou non
212 );
212 );
213 END COMPONENT;
213 END COMPONENT;
214
214
215 COMPONENT MAC_CONTROLER IS
215 COMPONENT MAC_CONTROLER IS
216 PORT(
216 PORT(
217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
218 MULT : OUT STD_LOGIC;
218 MULT : OUT STD_LOGIC;
219 ADD : OUT STD_LOGIC;
219 ADD : OUT STD_LOGIC;
220 -- LOAD_ADDER : out std_logic;
220 -- LOAD_ADDER : out std_logic;
221 MACMUX_sel : OUT STD_LOGIC;
221 MACMUX_sel : OUT STD_LOGIC;
222 MACMUX2_sel : OUT STD_LOGIC
222 MACMUX2_sel : OUT STD_LOGIC
223 );
223 );
224 END COMPONENT;
224 END COMPONENT;
225
225
226 COMPONENT MAC_MUX IS
226 COMPONENT MAC_MUX IS
227 GENERIC(
227 GENERIC(
228 Input_SZ_A : INTEGER := 16;
228 Input_SZ_A : INTEGER := 16;
229 Input_SZ_B : INTEGER := 16
229 Input_SZ_B : INTEGER := 16
230
230
231 );
231 );
232 PORT(
232 PORT(
233 sel : IN STD_LOGIC;
233 sel : IN STD_LOGIC;
234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
240 );
240 );
241 END COMPONENT;
241 END COMPONENT;
242
242
243
243
244 COMPONENT MAC_MUX2 IS
244 COMPONENT MAC_MUX2 IS
245 GENERIC(Input_SZ : INTEGER := 16);
245 GENERIC(Input_SZ : INTEGER := 16);
246 PORT(
246 PORT(
247 sel : IN STD_LOGIC;
247 sel : IN STD_LOGIC;
248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
251 );
251 );
252 END COMPONENT;
252 END COMPONENT;
253
253
254
254
255 COMPONENT MAC_REG IS
255 COMPONENT MAC_REG IS
256 GENERIC(size : INTEGER := 16);
256 GENERIC(size : INTEGER := 16);
257 PORT(
257 PORT(
258 reset : IN STD_LOGIC;
258 reset : IN STD_LOGIC;
259 clk : IN STD_LOGIC;
259 clk : IN STD_LOGIC;
260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
262 );
262 );
263 END COMPONENT;
263 END COMPONENT;
264
264
265
265
266 COMPONENT MUX2 IS
266 COMPONENT MUX2 IS
267 GENERIC(Input_SZ : INTEGER := 16);
267 GENERIC(Input_SZ : INTEGER := 16);
268 PORT(
268 PORT(
269 sel : IN STD_LOGIC;
269 sel : IN STD_LOGIC;
270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
273 );
273 );
274 END COMPONENT;
274 END COMPONENT;
275
275
276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
278
278
279 COMPONENT MUXN
279 COMPONENT MUXN
280 GENERIC (
280 GENERIC (
281 Input_SZ : INTEGER;
281 Input_SZ : INTEGER;
282 NbStage : INTEGER);
282 NbStage : INTEGER);
283 PORT (
283 PORT (
284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0);
285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0);
286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
288 END COMPONENT;
288 END COMPONENT;
289
289
290
290
291
291
292 COMPONENT Multiplier IS
292 COMPONENT Multiplier IS
293 GENERIC(
293 GENERIC(
294 Input_SZ_A : INTEGER := 16;
294 Input_SZ_A : INTEGER := 16;
295 Input_SZ_B : INTEGER := 16
295 Input_SZ_B : INTEGER := 16
296
296
297 );
297 );
298 PORT(
298 PORT(
299 clk : IN STD_LOGIC;
299 clk : IN STD_LOGIC;
300 reset : IN STD_LOGIC;
300 reset : IN STD_LOGIC;
301 mult : IN STD_LOGIC;
301 mult : IN STD_LOGIC;
302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
305 );
305 );
306 END COMPONENT;
306 END COMPONENT;
307
307
308 COMPONENT REG IS
308 COMPONENT REG IS
309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
310 PORT(
310 PORT(
311 reset : IN STD_LOGIC;
311 reset : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
315 );
315 );
316 END COMPONENT;
316 END COMPONENT;
317
317
318
318
319
319
320 COMPONENT RShifter IS
320 COMPONENT RShifter IS
321 GENERIC(
321 GENERIC(
322 Input_SZ : INTEGER := 16;
322 Input_SZ : INTEGER := 16;
323 shift_SZ : INTEGER := 4
323 shift_SZ : INTEGER := 4
324 );
324 );
325 PORT(
325 PORT(
326 clk : IN STD_LOGIC;
326 clk : IN STD_LOGIC;
327 reset : IN STD_LOGIC;
327 reset : IN STD_LOGIC;
328 shift : IN STD_LOGIC;
328 shift : IN STD_LOGIC;
329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
332 );
332 );
333 END COMPONENT;
333 END COMPONENT;
334
334
335 COMPONENT SYNC_FF
335 COMPONENT SYNC_FF
336 GENERIC (
336 GENERIC (
337 NB_FF_OF_SYNC : INTEGER);
337 NB_FF_OF_SYNC : INTEGER);
338 PORT (
338 PORT (
339 clk : IN STD_LOGIC;
339 clk : IN STD_LOGIC;
340 rstn : IN STD_LOGIC;
340 rstn : IN STD_LOGIC;
341 A : IN STD_LOGIC;
341 A : IN STD_LOGIC;
342 A_sync : OUT STD_LOGIC);
342 A_sync : OUT STD_LOGIC);
343 END COMPONENT;
343 END COMPONENT;
344
344
345 COMPONENT lpp_front_to_level
345 COMPONENT lpp_front_to_level
346 PORT (
346 PORT (
347 clk : IN STD_LOGIC;
347 clk : IN STD_LOGIC;
348 rstn : IN STD_LOGIC;
348 rstn : IN STD_LOGIC;
349 sin : IN STD_LOGIC;
349 sin : IN STD_LOGIC;
350 sout : OUT STD_LOGIC);
350 sout : OUT STD_LOGIC);
351 END COMPONENT;
351 END COMPONENT;
352
352
353 COMPONENT lpp_front_detection
353 COMPONENT lpp_front_detection
354 PORT (
354 PORT (
355 clk : IN STD_LOGIC;
355 clk : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
357 sin : IN STD_LOGIC;
357 sin : IN STD_LOGIC;
358 sout : OUT STD_LOGIC);
358 sout : OUT STD_LOGIC);
359 END COMPONENT;
359 END COMPONENT;
360
360
361 COMPONENT lpp_front_positive_detection
361 COMPONENT lpp_front_positive_detection
362 PORT (
362 PORT (
363 clk : IN STD_LOGIC;
363 clk : IN STD_LOGIC;
364 rstn : IN STD_LOGIC;
364 rstn : IN STD_LOGIC;
365 sin : IN STD_LOGIC;
365 sin : IN STD_LOGIC;
366 sout : OUT STD_LOGIC);
366 sout : OUT STD_LOGIC);
367 END COMPONENT;
367 END COMPONENT;
368
368
369 --COMPONENT SYNC_VALID_BIT
369 --COMPONENT SYNC_VALID_BIT
370 -- GENERIC (
370 -- GENERIC (
371 -- NB_FF_OF_SYNC : INTEGER);
371 -- NB_FF_OF_SYNC : INTEGER);
372 -- PORT (
372 -- PORT (
373 -- clk_in : IN STD_LOGIC;
373 -- clk_in : IN STD_LOGIC;
374 -- clk_out : IN STD_LOGIC;
374 -- clk_out : IN STD_LOGIC;
375 -- rstn : IN STD_LOGIC;
375 -- rstn : IN STD_LOGIC;
376 -- sin : IN STD_LOGIC;
376 -- sin : IN STD_LOGIC;
377 -- sout : OUT STD_LOGIC);
377 -- sout : OUT STD_LOGIC);
378 --END COMPONENT;
378 --END COMPONENT;
379
379
380 COMPONENT SYNC_VALID_BIT
380 COMPONENT SYNC_VALID_BIT
381 GENERIC (
381 GENERIC (
382 NB_FF_OF_SYNC : INTEGER);
382 NB_FF_OF_SYNC : INTEGER);
383 PORT (
383 PORT (
384 clk_in : IN STD_LOGIC;
384 clk_in : IN STD_LOGIC;
385 rstn_in : IN STD_LOGIC;
385 rstn_in : IN STD_LOGIC;
386 clk_out : IN STD_LOGIC;
386 clk_out : IN STD_LOGIC;
387 rstn_out : IN STD_LOGIC;
387 rstn_out : IN STD_LOGIC;
388 sin : IN STD_LOGIC;
388 sin : IN STD_LOGIC;
389 sout : OUT STD_LOGIC);
389 sout : OUT STD_LOGIC);
390 END COMPONENT;
390 END COMPONENT;
391
391
392 COMPONENT RR_Arbiter_4
392 COMPONENT RR_Arbiter_4
393 PORT (
393 PORT (
394 clk : IN STD_LOGIC;
394 clk : IN STD_LOGIC;
395 rstn : IN STD_LOGIC;
395 rstn : IN STD_LOGIC;
396 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
396 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
397 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
397 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
398 END COMPONENT;
398 END COMPONENT;
399
399
400 COMPONENT Clock_Divider IS
400 COMPONENT Clock_Divider IS
401 GENERIC(N : INTEGER := 10);
401 GENERIC(N : INTEGER := 10);
402 PORT(
402 PORT(
403 clk, rst : IN STD_LOGIC;
403 clk, rst : IN STD_LOGIC;
404 sclk : OUT STD_LOGIC);
404 sclk : OUT STD_LOGIC);
405 END COMPONENT;
405 END COMPONENT;
406
406
407 COMPONENT ramp_generator
407 COMPONENT ramp_generator
408 GENERIC (
408 GENERIC (
409 DATA_SIZE : INTEGER;
409 DATA_SIZE : INTEGER;
410 VALUE_UNSIGNED_INIT : INTEGER;
410 VALUE_UNSIGNED_INIT : INTEGER;
411 VALUE_UNSIGNED_INCR : INTEGER;
411 VALUE_UNSIGNED_INCR : INTEGER;
412 VALUE_UNSIGNED_MASK : INTEGER);
412 VALUE_UNSIGNED_MASK : INTEGER);
413 PORT (
413 PORT (
414 clk : IN STD_LOGIC;
414 clk : IN STD_LOGIC;
415 rstn : IN STD_LOGIC;
415 rstn : IN STD_LOGIC;
416 new_data : IN STD_LOGIC;
416 new_data : IN STD_LOGIC;
417 output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0));
417 output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0));
418 END COMPONENT;
418 END COMPONENT;
419
419
420 COMPONENT TimeGenAdvancedTrigger
421 PORT(
422 clk : IN STD_LOGIC;
423 rstn : IN STD_LOGIC;
424
425 SPW_Tickout : IN STD_LOGIC;
426
427 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
428 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
429
430 TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
431 TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
432 Restart : IN STD_LOGIC;
433 StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
434
435 BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
436 -- else Trigger output is driven by advanced trig
437 Trigger : OUT STD_LOGIC
438
439 );
440 END COMPONENT;
441
420 END;
442 END;
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@@ -1,27 +1,28
1 data_type_pkg.vhd
1 data_type_pkg.vhd
2 general_purpose.vhd
2 general_purpose.vhd
3 ADDRcntr.vhd
3 ADDRcntr.vhd
4 ALU.vhd
4 ALU.vhd
5 Adder.vhd
5 Adder.vhd
6 Clk_Divider2.vhd
6 Clk_Divider2.vhd
7 Clk_divider.vhd
7 Clk_divider.vhd
8 MAC.vhd
8 MAC.vhd
9 MAC_CONTROLER.vhd
9 MAC_CONTROLER.vhd
10 MAC_MUX.vhd
10 MAC_MUX.vhd
11 MAC_MUX2.vhd
11 MAC_MUX2.vhd
12 MAC_REG.vhd
12 MAC_REG.vhd
13 MUX2.vhd
13 MUX2.vhd
14 MUXN.vhd
14 MUXN.vhd
15 Multiplier.vhd
15 Multiplier.vhd
16 REG.vhd
16 REG.vhd
17 SYNC_FF.vhd
17 SYNC_FF.vhd
18 Shifter.vhd
18 Shifter.vhd
19 TwoComplementer.vhd
19 TwoComplementer.vhd
20 Clock_Divider.vhd
20 Clock_Divider.vhd
21 lpp_front_to_level.vhd
21 lpp_front_to_level.vhd
22 lpp_front_detection.vhd
22 lpp_front_detection.vhd
23 lpp_front_positive_detection.vhd
23 lpp_front_positive_detection.vhd
24 SYNC_VALID_BIT.vhd
24 SYNC_VALID_BIT.vhd
25 RR_Arbiter_4.vhd
25 RR_Arbiter_4.vhd
26 general_counter.vhd
26 general_counter.vhd
27 ramp_generator.vhd
27 ramp_generator.vhd
28 TimeGenAdvancedTrigger.vhd
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@@ -1,48 +1,49
1
1
2 --=================================================================================
2 --=================================================================================
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 --
4 --
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 --=================================================================================
6 --=================================================================================
7
7
8
8
9 LIBRARY ieee;
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.ALL;
10 USE ieee.std_logic_1164.ALL;
11 LIBRARY grlib;
11 LIBRARY grlib;
12 USE grlib.amba.ALL;
12 USE grlib.amba.ALL;
13 USE std.textio.ALL;
13 USE std.textio.ALL;
14
14
15
15
16 PACKAGE apb_devices_list IS
16 PACKAGE apb_devices_list IS
17
17
18
18
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20
20
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
41 CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#;
41 CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#;
42 CONSTANT LPP_LFR_MANAGEMENT : amba_device_type := 16#22#;
42 CONSTANT LPP_LFR_MANAGEMENT : amba_device_type := 16#22#;
43 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
43 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
45 constant APB_ADC_READER : amba_device_type := 16#F1#;
45 constant APB_ADC_READER : amba_device_type := 16#F1#;
46 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
46 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
47 CONSTANT LPP_APB_ADVANCED_TRIGGER : amba_device_type := 16#A3#;
47
48
48 END;
49 END;
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@@ -1,82 +1,86
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27
27
28
28
29
29
30 package lpp_amba is
30 package lpp_amba is
31
31
32 component APB_CHENILLARD is
32 component APB_ADVANCED_TRIGGER is
33 generic (
33 generic (
34 pindex : integer := 0;
34 pindex : integer := 0;
35 paddr : integer := 0;
35 paddr : integer := 0;
36 pmask : integer := 16#fff#;
36 pmask : integer := 16#fff#;
37 pirq : integer := 0;
37 pirq : integer := 0;
38 abits : integer := 8);
38 abits : integer := 8);
39 port (
39 port (
40 rst : in std_ulogic;
40 rstn : in std_ulogic;
41 clk : in std_ulogic;
41 clk : in std_ulogic;
42 RegLed : in std_logic_vector (7 downto 0);
43 apbi : in apb_slv_in_type;
42 apbi : in apb_slv_in_type;
44 apbo : out apb_slv_out_type;
43 apbo : out apb_slv_out_type;
45 Leds : out std_logic_vector (7 downto 0)
44
45 SPW_Tickout : IN STD_LOGIC;
46 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48
49 Trigger : OUT STD_LOGIC
46 );
50 );
47 end component;
51 end component;
48
52
49 component APB_SIMPLE_DIODE is
53 component APB_SIMPLE_DIODE is
50 generic (
54 generic (
51 pindex : integer := 0;
55 pindex : integer := 0;
52 paddr : integer := 0;
56 paddr : integer := 0;
53 pmask : integer := 16#fff#;
57 pmask : integer := 16#fff#;
54 pirq : integer := 0;
58 pirq : integer := 0;
55 abits : integer := 8);
59 abits : integer := 8);
56 port (
60 port (
57 rst : in std_ulogic;
61 rst : in std_ulogic;
58 clk : in std_ulogic;
62 clk : in std_ulogic;
59 apbi : in apb_slv_in_type;
63 apbi : in apb_slv_in_type;
60 apbo : out apb_slv_out_type;
64 apbo : out apb_slv_out_type;
61 LED : out std_ulogic
65 LED : out std_ulogic
62 );
66 );
63 end component;
67 end component;
64
68
65
69
66 component APB_MULTI_DIODE is
70 component APB_MULTI_DIODE is
67 generic (
71 generic (
68 pindex : integer := 0;
72 pindex : integer := 0;
69 paddr : integer := 0;
73 paddr : integer := 0;
70 pmask : integer := 16#fff#;
74 pmask : integer := 16#fff#;
71 pirq : integer := 0;
75 pirq : integer := 0;
72 abits : integer := 8);
76 abits : integer := 8);
73 port (
77 port (
74 rst : in std_ulogic;
78 rst : in std_ulogic;
75 clk : in std_ulogic;
79 clk : in std_ulogic;
76 apbi : in apb_slv_in_type;
80 apbi : in apb_slv_in_type;
77 apbo : out apb_slv_out_type;
81 apbo : out apb_slv_out_type;
78 LED : out std_logic_vector(2 downto 0)
82 LED : out std_logic_vector(2 downto 0)
79 );
83 );
80 end component;
84 end component;
81
85
82 end;
86 end;
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@@ -1,2 +1,3
1 apb_devices_list.vhd
1 apb_devices_list.vhd
2 lpp_amba.vhd
2 lpp_amba.vhd
3 APB_ADVANCED_TRIGGER.vhd
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