@@ -1,198 +1,199 | |||
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1 | 1 | library ieee; |
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2 | 2 | use ieee.std_logic_1164.all; |
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3 | 3 | use IEEE.numeric_std.all; |
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4 | 4 | library grlib, techmap; |
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5 | 5 | use grlib.amba.all; |
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6 | 6 | use grlib.amba.all; |
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7 | 7 | use grlib.stdlib.all; |
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8 | 8 | use techmap.gencomp.all; |
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9 | 9 | use techmap.allclkgen.all; |
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10 | 10 | library gaisler; |
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11 | 11 | use gaisler.memctrl.all; |
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12 | 12 | use gaisler.leon3.all; |
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13 | 13 | use gaisler.uart.all; |
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14 | 14 | use gaisler.misc.all; |
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15 | 15 | library esa; |
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16 | 16 | use esa.memoryctrl.all; |
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17 | 17 | --use gaisler.sim.all; |
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18 | 18 | library lpp; |
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19 | 19 | use lpp.lpp_ad_conv.all; |
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20 | 20 | use lpp.lpp_amba.all; |
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21 | 21 | use lpp.apb_devices_list.all; |
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22 | 22 | use lpp.general_purpose.all; |
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23 | 23 | use lpp.lpp_cna.all; |
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24 | 24 | |
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25 | 25 | Library UNISIM; |
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26 | 26 | use UNISIM.vcomponents.all; |
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27 | 27 | |
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28 | 28 | |
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29 | 29 | use work.config.all; |
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30 | 30 | --================================================================== |
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31 | 31 | -- |
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32 | 32 | -- |
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33 | 33 | -- FPGA FREQ = 100MHz |
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34 | 34 | -- |
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35 | 35 | -- |
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36 | 36 | --================================================================== |
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37 | 37 | |
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38 | 38 | entity BeagleSynth is |
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39 | 39 | generic ( |
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40 | 40 | fabtech : integer := CFG_FABTECH; |
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41 | 41 | memtech : integer := CFG_MEMTECH; |
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42 | 42 | padtech : integer := CFG_PADTECH; |
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43 | 43 | clktech : integer := CFG_CLKTECH |
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44 | 44 | ); |
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45 | 45 | port ( |
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46 | 46 | reset : in std_ulogic; |
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47 | 47 | clk : in std_ulogic; |
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48 | 48 | DAC_nCLR : out std_ulogic; |
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49 | 49 | DAC_nCS : out std_ulogic; |
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50 | 50 | CAL_IN_SCK : out std_ulogic; |
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51 | 51 | DAC_SDI : out std_logic_vector(7 downto 0); |
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52 | 52 | TXD : out std_ulogic; |
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53 | 53 | RXD : in std_ulogic; |
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54 | 54 | urxd1 : in std_ulogic; |
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55 | 55 | utxd1 : out std_ulogic; |
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56 | 56 | LED : out std_ulogic_vector(2 downto 0); |
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57 | 57 | -------------------------------------------------------- |
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58 | 58 | ---- Beaglebone GPMC |
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59 | 59 | -------------------------------------------------------- |
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60 | 60 | GPMC_AD : inout std_logic_vector(15 downto 0); |
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61 | 61 | GPMC_A : in std_logic_vector(19 downto 0); |
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62 | 62 | GPMC_CLK_MUX0 : in std_logic; |
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63 | 63 | GPMC_WEN : in std_logic; |
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64 | 64 | GPMC_OEN_REN : in std_logic; |
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65 | 65 | GPMC_ADVN_ALE : in std_logic; |
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66 | 66 | GPMC_CSN : in std_logic_vector(2 downto 0); |
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67 | 67 | GPMC_BE0N_CLE : in std_logic; |
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68 | 68 | GPMC_BE1N : in std_logic; |
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69 | 69 | GPMC_WAIT0 : out std_logic; |
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70 | 70 | GPMC_WPN : in std_logic; |
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71 | 71 | |
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72 | 72 | -------------------------------------------------------- |
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73 | 73 | ---- SDRAM |
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74 | 74 | ---- For SDRAM config have a look on leon3-altera-ep1c20 |
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75 | 75 | ---- design from GRLIB, the IS42S32400E is similar to |
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76 | 76 | ---- MT48LC4M32B2. |
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77 | 77 | -------------------------------------------------------- |
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78 | 78 | sdcke : out std_logic; -- clk en |
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79 | 79 | sdcsn : out std_logic; -- chip sel |
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80 | 80 | sdwen : out std_logic; -- write en |
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81 | 81 | sdrasn : out std_logic; -- row addr stb |
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82 | 82 | sdcasn : out std_logic; -- col addr stb |
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83 | 83 | sddqm : out std_logic_vector (3 downto 0); -- data i/o mask |
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84 | 84 | sdclk : out std_logic; -- sdram clk output |
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85 | 85 | sdba : out std_logic_vector (1 downto 0); -- bank select address |
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86 | 86 | Address : out std_logic_vector(11 downto 0); -- sdram address |
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87 | 87 | Data : inout std_logic_vector(31 downto 0) -- optional sdram data |
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88 | 88 | ); |
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89 | 89 | end; |
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90 | 90 | |
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91 | 91 | architecture rtl of BeagleSynth is |
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92 | 92 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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93 | 93 | CFG_GRETH+CFG_AHB_JTAG; |
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94 | 94 | constant maxahbm : integer := maxahbmsp; |
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95 | 95 | constant IOAEN : integer := CFG_CAN; |
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96 | 96 | constant boardfreq : integer := 100000; |
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97 | 97 | |
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98 | 98 | signal clk2x : std_ulogic; |
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99 | 99 | signal lclk : std_ulogic; |
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100 | 100 | signal clkm : std_ulogic; |
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101 | 101 | signal rstn : std_ulogic; |
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102 | 102 | signal rst : std_ulogic; |
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103 | 103 | signal rstraw : std_ulogic; |
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104 | 104 | signal pciclk : std_ulogic; |
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105 | 105 | signal sdclkl : std_ulogic; |
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106 | 106 | signal sdclkl_DDR2 : std_ulogic; |
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107 | 107 | signal cgi : clkgen_in_type; |
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108 | 108 | signal cgo : clkgen_out_type; |
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109 | 109 | |
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110 | 110 | |
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111 | 111 | signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); |
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112 | 112 | signal smpclk : std_logic; |
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113 | 113 | signal smpclk_reg : std_logic; |
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114 | 114 | signal DAC_SDO : std_logic; |
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115 | 115 | |
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116 | 116 | signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0); |
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117 | 117 | signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0); |
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118 | 118 | signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0); |
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119 | 119 | signal GPMC_SLAVE_WEN : std_logic; |
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120 | 120 | |
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121 | 121 | signal gpmc_clk : std_logic; |
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122 | 122 | |
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123 | 123 | attribute keep : boolean; |
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124 | 124 | attribute syn_keep : boolean; |
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125 | 125 | attribute syn_preserve : boolean; |
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126 | 126 | attribute syn_keep of clkm : signal is true; |
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127 | 127 | attribute syn_preserve of clkm : signal is true; |
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128 | 128 | attribute keep of clkm : signal is true; |
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129 | 129 | begin |
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130 | 130 | |
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131 | 131 | DAC_nCLR <= '1'; |
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132 | 132 | |
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133 | 133 | |
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134 | 134 | resetn_pad : inpad generic map (tech => padtech) port map (reset, rst); |
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135 | 135 | rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw); |
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136 | 136 | |
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137 | 137 | clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk); |
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138 | 138 | |
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139 | 139 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
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140 | 140 | clkgen0 : clkgen -- clock generator |
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141 | 141 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq) |
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142 | 142 | port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); |
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143 | 143 | |
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144 | 144 | |
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145 | ||
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146 | ||
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147 | 145 | DAC0 : entity work.beagleSigGen |
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148 | 146 | generic map( |
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149 | 147 | memtech, |
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150 | 148 | padtech, |
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151 | 149 | clktech |
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152 | 150 | ) |
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153 | 151 | Port map( |
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154 | 152 | clk => clkm, |
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155 | 153 | rstn => rstn, |
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156 | 154 | CAL_IN_SCK => CAL_IN_SCK, |
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157 | 155 | DAC_nCS => DAC_nCS, |
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158 | 156 | DAC_SDI => DAC_SDI, |
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159 | 157 | address => GPMC_SLAVE_ADDRESS(3 downto 1), |
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160 | 158 | DATA => GPMC_SLAVE_DATA, |
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161 | 159 | WEN => GPMC_SLAVE_WEN, |
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162 |
REN_debug => |
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160 | REN_debug => open, | |
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163 | 161 | FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0), |
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164 | 162 | FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8) |
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165 | 163 | ); |
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166 | 164 | |
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167 | 165 | |
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168 | 166 | |
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169 |
LED(0) <= GPMC_SLAVE_ |
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170 |
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167 | --LED(0) <= GPMC_SLAVE_ADDRESS(1); | |
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168 | --LED(1) <= GPMC_SLAVE_ADDRESS(2); | |
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169 | LED(2) <= GPMC_SLAVE_WEN; | |
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171 | 170 | |
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172 | 171 | gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk); |
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173 | 172 | GPMCS0: entity work.GPMC_SLAVE |
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174 | 173 | generic map(memtech,padtech) |
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175 | 174 | Port map( |
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176 | 175 | clk => clkm, |
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177 | 176 | reset => rstn, |
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178 | 177 | STATUS => GPMC_SLAVE_STATUS, |
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179 | 178 | DATA => GPMC_SLAVE_DATA, |
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180 | 179 | ADDRESS => GPMC_SLAVE_ADDRESS, |
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181 | 180 | WEN => GPMC_SLAVE_WEN, |
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181 | SMP_CKL => LED(0), | |
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182 | SMP_WEN => LED(1), | |
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182 | 183 | GPMC_AD => GPMC_AD, |
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183 | 184 | GPMC_A => GPMC_A, |
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184 | 185 | GPMC_CLK => gpmc_clk, |
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185 | 186 | GPMC_WEN => GPMC_WEN, |
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186 | 187 | GPMC_OEN_REN => GPMC_OEN_REN, |
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187 | 188 | GPMC_ADVN_ALE => GPMC_ADVN_ALE, |
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188 | 189 | GPMC_CSN => GPMC_CSN, |
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189 | 190 | GPMC_BE0N_CLE => GPMC_BE0N_CLE, |
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190 | 191 | GPMC_BE1N => GPMC_BE1N, |
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191 | 192 | GPMC_WAIT0 => GPMC_WAIT0, |
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192 | 193 | GPMC_WPN => GPMC_WPN |
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193 | 194 | ); |
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194 | 195 | |
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195 | 196 | end rtl; |
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196 | 197 | |
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197 | 198 | |
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198 | 199 |
@@ -1,122 +1,162 | |||
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1 | 1 | ---------------------------------------------------------------------------------- |
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2 | 2 | -- Company: |
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3 | 3 | -- Engineer: |
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4 | 4 | -- |
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5 | 5 | -- Create Date: 15:20:11 12/08/2013 |
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6 | 6 | -- Design Name: |
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7 | 7 | -- Module Name: GPMC_SLAVE - Behavioral |
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8 | 8 | -- Project Name: |
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9 | 9 | -- Target Devices: |
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10 | 10 | -- Tool versions: |
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11 | 11 | -- Description: |
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12 | 12 | -- |
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13 | 13 | -- Dependencies: |
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14 | 14 | -- |
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15 | 15 | -- Revision: |
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16 | 16 | -- Revision 0.01 - File Created |
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17 | 17 | -- Additional Comments: |
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18 | 18 | -- |
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19 | 19 | ---------------------------------------------------------------------------------- |
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20 | 20 | library IEEE; |
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21 | 21 | use IEEE.STD_LOGIC_1164.ALL; |
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22 | 22 | use IEEE.numeric_std.all; |
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23 | 23 | library grlib, techmap; |
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24 | 24 | use grlib.stdlib.all; |
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25 | 25 | use techmap.gencomp.all; |
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26 | 26 | use techmap.allclkgen.all; |
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27 | 27 | library lpp; |
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28 | 28 | use lpp.general_purpose.all; |
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29 | 29 | |
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30 | 30 | entity GPMC_SLAVE is |
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31 | 31 | generic ( |
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32 | 32 | memtech : integer := 0; |
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33 | 33 | padtech : integer := 0 |
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34 | 34 | ); |
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35 | 35 | Port ( |
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36 | 36 | clk : in STD_LOGIC; |
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37 | 37 | reset : in STD_LOGIC; |
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38 | 38 | STATUS : in STD_LOGIC_VECTOR(15 downto 0); |
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39 | 39 | DATA : out STD_LOGIC_VECTOR(15 downto 0); |
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40 | 40 | ADDRESS : out std_logic_vector(19 downto 0); |
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41 | 41 | WEN : out STD_LOGIC; |
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42 | SMP_CKL : out STD_LOGIC; | |
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43 | SMP_WEN : out STD_LOGIC; | |
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42 | 44 | GPMC_AD : inout std_logic_vector(15 downto 0); |
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43 | 45 | GPMC_A : in std_logic_vector(19 downto 0); |
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44 | 46 | GPMC_CLK : in std_logic; |
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45 | 47 | GPMC_WEN : in std_logic; |
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46 | 48 | GPMC_OEN_REN : in std_logic; |
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47 | 49 | GPMC_ADVN_ALE : in std_logic; |
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48 | 50 | GPMC_CSN : in std_logic_vector(2 downto 0); |
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49 | 51 | GPMC_BE0N_CLE : in std_logic; |
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50 | 52 | GPMC_BE1N : in std_logic; |
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51 | 53 | GPMC_WAIT0 : out std_logic; |
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52 | 54 | GPMC_WPN : in std_logic |
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53 | 55 | ); |
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54 | 56 | end GPMC_SLAVE; |
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55 | 57 | |
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56 | 58 | architecture Behavioral of GPMC_SLAVE is |
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57 | 59 | |
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58 | 60 | signal data_out : std_logic_vector(15 downto 0) := (others => '0'); |
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59 | 61 | signal data_in : std_logic_vector(15 downto 0) := (others => '0'); |
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62 | signal data_in_reg0 : std_logic_vector(15 downto 0) := (others => '0'); | |
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63 | signal data_in_reg1 : std_logic_vector(15 downto 0) := (others => '0'); | |
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64 | signal data_in_reg2 : std_logic_vector(15 downto 0) := (others => '0'); | |
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65 | signal address_reg0 : std_logic_vector(19 downto 0) := (others => '0'); | |
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66 | signal address_reg1 : std_logic_vector(19 downto 0) := (others => '0'); | |
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67 | signal address_reg2 : std_logic_vector(19 downto 0) := (others => '0'); | |
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68 | signal ADVN_ALE_reg : std_logic_vector(3 downto 0) := (others => '0'); | |
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69 | ||
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60 | 70 | |
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61 | 71 | signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0'); |
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62 | 72 | signal data_r : std_logic_vector(15 downto 0) := (others => '0'); |
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63 | ||
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73 | signal GPMC_WEN_reg : std_logic_vector(3 downto 0) := (others => '0'); | |
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64 | 74 | |
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65 | 75 | signal outen : std_logic := '0'; |
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66 | 76 | |
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67 | 77 | |
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68 | 78 | begin |
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69 | 79 | |
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70 | 80 | outen <= GPMC_OEN_REN or GPMC_CSN(0); |
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71 | 81 | data_out <= STATUS; |
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72 | 82 | |
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73 | 83 | data_pad : iopadv generic map (tech=> padtech,width => 16) |
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74 | 84 | port map ( |
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75 | 85 | pad => GPMC_AD(15 downto 0), |
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76 | 86 | o => data_in(15 downto 0), |
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77 | 87 | en => outen, |
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78 | 88 | i => data_out(15 downto 0) |
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79 | 89 | ); |
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80 | 90 | |
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81 | 91 | GPMC_WAIT0 <= '1'; |
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92 | SMP_CKL <= GPMC_CLK_reg(0); | |
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93 | SMP_WEN <= GPMC_WEN_reg(2); | |
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82 | 94 | |
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95 | process(reset,clk) | |
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96 | begin | |
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97 | if reset = '0' then | |
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98 | GPMC_CLK_reg <= "0000"; | |
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99 | ADDRESS <= (others => '0'); | |
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100 | ADVN_ALE_reg <= (others => '0'); | |
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101 | address_reg0 <= (others => '0'); | |
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102 | address_reg1 <= (others => '0'); | |
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103 | address_reg2 <= (others => '0'); | |
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104 | elsif clk'event and clk = '1' then | |
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105 | GPMC_CLK_reg(0) <= GPMC_CLK; | |
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106 | GPMC_CLK_reg(1) <= GPMC_CLK_reg(0); | |
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107 | GPMC_CLK_reg(2) <= GPMC_CLK_reg(1); | |
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108 | ADVN_ALE_reg(0) <= GPMC_ADVN_ALE; | |
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109 | ADVN_ALE_reg(1) <= ADVN_ALE_reg(0); | |
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110 | ADVN_ALE_reg(2) <= ADVN_ALE_reg(1); | |
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111 | address_reg0 <= GPMC_A; | |
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112 | address_reg1 <= address_reg0; | |
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113 | address_reg2 <= address_reg1; | |
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114 | if GPMC_CLK_reg(1) = '1' and GPMC_CLK_reg(2) = '0' then | |
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115 | if ADVN_ALE_reg(2) = '0' then | |
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116 | ADDRESS <= address_reg2; | |
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117 | end if; | |
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118 | end if; | |
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119 | ||
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120 | end if; | |
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121 | end process; | |
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83 | 122 | |
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84 | 123 | |
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85 | 124 | process(reset,clk) |
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86 | 125 | begin |
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87 | 126 | if reset = '0' then |
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88 | 127 | WEN <= '1'; |
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89 |
GPMC_ |
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90 |
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128 | GPMC_WEN_reg <= "0000"; | |
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129 | data_in_reg0 <= (others => '0'); | |
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130 | data_in_reg1 <= (others => '0'); | |
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131 | data_in_reg2 <= (others => '0'); | |
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91 | 132 | elsif clk'event and clk = '1' then |
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92 |
GPMC_ |
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93 | if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then | |
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94 | if GPMC_WEN = '0' then | |
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133 | GPMC_WEN_reg(0) <= GPMC_WEN; | |
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134 | GPMC_WEN_reg(1) <= GPMC_WEN_reg(0); | |
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135 | GPMC_WEN_reg(2) <= GPMC_WEN_reg(1); | |
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136 | data_in_reg0 <= data_in; | |
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137 | data_in_reg1 <= data_in_reg0; | |
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138 | data_in_reg2 <= data_in_reg1; | |
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139 | if GPMC_WEN_reg(2) = '1' and GPMC_WEN_reg(1) = '0' then | |
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95 | 140 |
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96 |
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97 | end if; | |
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98 | if GPMC_ADVN_ALE = '0' then | |
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99 | ADDRESS <= GPMC_A; | |
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100 | end if; | |
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141 | DATA <= data_in_reg2; | |
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101 | 142 | else |
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102 | 143 |
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103 | 144 | end if; |
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104 | ||
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105 | 145 | end if; |
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106 | 146 | end process; |
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107 | 147 | |
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108 | 148 | end Behavioral; |
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109 | 149 | |
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110 | 150 | |
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111 | 151 | |
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112 | 152 | |
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113 | 153 | |
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114 | 154 | |
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115 | 155 | |
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116 | 156 | |
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117 | 157 | |
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118 | 158 | |
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119 | 159 | |
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120 | 160 | |
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121 | 161 | |
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122 | 162 |
@@ -1,338 +1,330 | |||
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1 | 1 | library ieee; |
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2 | 2 | use ieee.std_logic_1164.all; |
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3 | 3 | use IEEE.numeric_std.all; |
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4 | 4 | library grlib, techmap; |
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5 | 5 | use grlib.amba.all; |
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6 | 6 | use grlib.amba.all; |
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7 | 7 | use grlib.stdlib.all; |
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8 | 8 | use techmap.gencomp.all; |
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9 | 9 | use techmap.allclkgen.all; |
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10 | 10 | library gaisler; |
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11 | 11 | use gaisler.memctrl.all; |
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12 | 12 | use gaisler.leon3.all; |
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13 | 13 | use gaisler.uart.all; |
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14 | 14 | use gaisler.misc.all; |
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15 | 15 | library esa; |
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16 | 16 | use esa.memoryctrl.all; |
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17 | 17 | --use gaisler.sim.all; |
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18 | 18 | library lpp; |
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19 | 19 | use lpp.lpp_ad_conv.all; |
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20 | 20 | use lpp.lpp_amba.all; |
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21 | 21 | use lpp.apb_devices_list.all; |
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22 | 22 | use lpp.general_purpose.all; |
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23 | 23 | use lpp.lpp_cna.all; |
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24 | 24 | use lpp.lpp_memory.all; |
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25 | 25 | |
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26 | 26 | Library UNISIM; |
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27 | 27 | use UNISIM.vcomponents.all; |
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28 | 28 | |
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29 | 29 | use work.config.all; |
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30 | 30 | |
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31 | 31 | entity beagleSigGen is |
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32 | 32 | generic ( |
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33 | 33 | memtech : integer := CFG_MEMTECH; |
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34 | 34 | padtech : integer := CFG_PADTECH; |
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35 | 35 | clktech : integer := CFG_CLKTECH |
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36 | 36 | ); |
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37 | 37 | Port ( |
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38 | 38 | clk : in STD_LOGIC; |
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39 | 39 | rstn : in STD_LOGIC; |
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40 | 40 | CAL_IN_SCK : out std_ulogic; |
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41 | 41 | DAC_nCS : out std_ulogic; |
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42 | 42 | DAC_SDI : out std_logic_vector(7 downto 0); |
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43 | 43 | address : in std_logic_vector(2 downto 0); |
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44 | 44 | DATA : in std_logic_vector(15 downto 0); |
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45 | 45 | REN_debug : out std_logic; |
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46 | 46 | WEN : in std_logic; |
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47 | 47 | FIFO_FULL : out std_logic_vector(7 downto 0); |
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48 | 48 | FIFO_EMPTY : out std_logic_vector(7 downto 0) |
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49 | 49 | ); |
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50 | 50 | end beagleSigGen; |
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51 | 51 | |
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52 | 52 | architecture Behavioral of beagleSigGen is |
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53 | 53 | |
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54 | 54 | |
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55 | 55 | signal FIFO_FULL_net : std_logic_vector(7 downto 0); |
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56 | 56 | signal FIFO_EMPTY_net : std_logic_vector(7 downto 0); |
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57 | 57 | signal FIFO_WEN : std_logic_vector(7 downto 0); |
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58 | 58 | signal FIFO_REN : std_logic; |
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59 | 59 | |
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60 | 60 | |
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61 | 61 | subtype TAB16 is std_logic_vector(15 downto 0); |
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62 | 62 | type FIFOout_t is array(7 downto 0) of TAB16; |
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63 | 63 | |
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64 | 64 | signal FIFO_out : FIFOout_t; |
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65 | 65 | signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); |
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66 | 66 | signal smpclk : std_logic; |
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67 | 67 | signal smpclk_reg : std_logic; |
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68 | 68 | signal DAC_SDO : std_logic; |
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69 | 69 | signal DATA_reg : std_logic_vector(15 downto 0); |
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70 | 70 | |
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71 | 71 | begin |
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72 | 72 | |
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73 | 73 | |
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74 | 74 | |
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75 | 75 | FIFO_FULL <= FIFO_FULL_net; |
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76 | 76 | FIFO_EMPTY <= FIFO_EMPTY_net; |
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78 | fron_fifo1: lpp_fifo | |
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79 | generic map( | |
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80 | tech => memtech, | |
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81 | Mem_use => 1, --use RAM not CELS | |
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82 | DataSz => 16, | |
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83 | AddrSz => 8 | |
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84 | ) | |
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85 | port map( | |
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86 | rstn => rstn, | |
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87 | ReUse => '0', | |
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88 | rclk => clk, | |
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89 | ren => FIFO_REN, | |
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90 | rdata => FIFO_out(0), | |
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91 | empty => FIFO_EMPTY_net(0), | |
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92 | raddr => open, | |
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93 | wclk => clk, | |
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94 | wen => FIFO_WEN(0), | |
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95 | wdata => DATA_reg, | |
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96 | full => FIFO_FULL_net(0), | |
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97 | waddr => open | |
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98 | ); | |
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99 | fron_fifo2: lpp_fifo | |
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100 | generic map( | |
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101 | tech => memtech, | |
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102 | Mem_use => 1, --use RAM not CELS | |
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103 | DataSz => 16, | |
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104 | AddrSz => 8 | |
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105 | ) | |
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106 | port map( | |
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107 | rstn => rstn, | |
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108 | ReUse => '0', | |
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109 | rclk => clk, | |
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110 | ren => FIFO_REN, | |
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111 | rdata => FIFO_out(1), | |
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112 | empty => FIFO_EMPTY_net(1), | |
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113 | raddr => open, | |
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114 | wclk => clk, | |
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115 | wen => FIFO_WEN(1), | |
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116 | wdata => DATA_reg, | |
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117 | full => FIFO_FULL_net(1), | |
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118 | waddr => open | |
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119 | ); | |
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120 | fron_fifo3: lpp_fifo | |
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121 | generic map( | |
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122 | tech => memtech, | |
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123 | Mem_use => 1, --use RAM not CELS | |
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124 | DataSz => 16, | |
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125 | AddrSz => 8 | |
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126 | ) | |
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127 | port map( | |
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128 | rstn => rstn, | |
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129 | ReUse => '0', | |
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130 | rclk => clk, | |
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131 | ren => FIFO_REN, | |
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132 | rdata => FIFO_out(2), | |
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133 | empty => FIFO_EMPTY_net(2), | |
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134 | raddr => open, | |
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135 | wclk => clk, | |
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136 | wen => FIFO_WEN(2), | |
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137 | wdata => DATA_reg, | |
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138 | full => FIFO_FULL_net(2), | |
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139 | waddr => open | |
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140 | ); | |
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141 | fron_fifo4: lpp_fifo | |
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142 | generic map( | |
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143 | tech => memtech, | |
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144 | Mem_use => 1, --use RAM not CELS | |
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145 | DataSz => 16, | |
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146 | AddrSz => 8 | |
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147 | ) | |
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148 | port map( | |
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149 | rstn => rstn, | |
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150 | ReUse => '0', | |
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151 | rclk => clk, | |
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152 | ren => FIFO_REN, | |
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153 | rdata => FIFO_out(3), | |
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154 | empty => FIFO_EMPTY_net(3), | |
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155 | raddr => open, | |
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156 | wclk => clk, | |
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157 | wen => FIFO_WEN(3), | |
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158 | wdata => DATA_reg, | |
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159 | full => FIFO_FULL_net(3), | |
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160 | waddr => open | |
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161 | ); | |
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162 | fron_fifo5: lpp_fifo | |
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163 | generic map( | |
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164 | tech => memtech, | |
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165 | Mem_use => 1, --use RAM not CELS | |
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166 | DataSz => 16, | |
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167 | AddrSz => 8 | |
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168 | ) | |
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169 | port map( | |
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170 | rstn => rstn, | |
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171 | ReUse => '0', | |
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172 | rclk => clk, | |
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173 | ren => FIFO_REN, | |
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174 | rdata => FIFO_out(4), | |
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175 | empty => FIFO_EMPTY_net(4), | |
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176 | raddr => open, | |
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177 | wclk => clk, | |
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178 | wen => FIFO_WEN(4), | |
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179 | wdata => DATA_reg, | |
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180 | full => FIFO_FULL_net(4), | |
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181 | waddr => open | |
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182 | ); | |
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183 | fron_fifo6: lpp_fifo | |
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184 | generic map( | |
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185 | tech => memtech, | |
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186 | Mem_use => 1, --use RAM not CELS | |
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187 | DataSz => 16, | |
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188 | AddrSz => 8 | |
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189 | ) | |
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190 | port map( | |
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191 | rstn => rstn, | |
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192 | ReUse => '0', | |
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193 | rclk => clk, | |
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194 | ren => FIFO_REN, | |
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195 | rdata => FIFO_out(5), | |
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196 | empty => FIFO_EMPTY_net(5), | |
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197 | raddr => open, | |
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198 | wclk => clk, | |
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199 | wen => FIFO_WEN(5), | |
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200 | wdata => DATA_reg, | |
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201 | full => FIFO_FULL_net(5), | |
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202 | waddr => open | |
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203 | ); | |
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204 | fron_fifo7: lpp_fifo | |
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205 | generic map( | |
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206 | tech => memtech, | |
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207 | Mem_use => 1, --use RAM not CELS | |
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208 | DataSz => 16, | |
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209 | AddrSz => 8 | |
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210 | ) | |
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211 | port map( | |
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212 | rstn => rstn, | |
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213 | ReUse => '0', | |
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214 | rclk => clk, | |
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215 | ren => FIFO_REN, | |
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216 | rdata => FIFO_out(6), | |
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217 | empty => FIFO_EMPTY_net(6), | |
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218 | raddr => open, | |
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219 | wclk => clk, | |
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220 | wen => FIFO_WEN(6), | |
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221 | wdata => DATA_reg, | |
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222 | full => FIFO_FULL_net(6), | |
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223 | waddr => open | |
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224 | ); | |
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225 | fron_fifo8: lpp_fifo | |
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226 | generic map( | |
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227 | tech => memtech, | |
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228 | Mem_use => 1, --use RAM not CELS | |
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229 | DataSz => 16, | |
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230 | AddrSz => 8 | |
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231 | ) | |
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232 | port map( | |
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233 | rstn => rstn, | |
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234 | ReUse => '0', | |
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235 | rclk => clk, | |
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236 | ren => FIFO_REN, | |
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237 | rdata => FIFO_out(7), | |
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238 | empty => FIFO_EMPTY_net(7), | |
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239 | raddr => open, | |
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240 | wclk => clk, | |
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241 | wen => FIFO_WEN(7), | |
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242 | wdata => DATA_reg, | |
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243 | full => FIFO_FULL_net(7), | |
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244 | waddr => open | |
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245 | ); | |
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246 | 246 | |
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247 | 247 | REN_debug <= FIFO_REN; |
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248 | 248 | |
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249 | 249 | process(clk,rstn) |
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250 | 250 | begin |
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251 | 251 | if rstn = '0' then |
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252 | 252 | DATA_reg <= (others => '0'); |
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253 | 253 | FIFO_WEN <= (others => '0'); |
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254 | 254 | elsif clk'event and clk = '1' then |
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255 | 255 | if WEN = '0' then |
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256 | 256 | DATA_reg <= DATA; |
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257 | 257 | case address is |
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258 | 258 | when "000"=> |
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259 | 259 | FIFO_WEN <= "11111110"; |
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260 | FIFO_out(0) <= DATA; | |
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261 | 260 | when "001"=> |
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262 | 261 | FIFO_WEN <= "11111101"; |
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263 | FIFO_out(1) <= DATA; | |
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264 | 262 | when "010"=> |
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265 | 263 | FIFO_WEN <= "11111011"; |
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266 | FIFO_out(2) <= DATA; | |
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267 | 264 | when "011"=> |
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268 | 265 | FIFO_WEN <= "11110111"; |
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269 | FIFO_out(3) <= DATA; | |
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270 | 266 | when "100"=> |
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271 | 267 | FIFO_WEN <= "11101111"; |
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272 | FIFO_out(4) <= DATA; | |
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273 | 268 | when "101"=> |
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274 | 269 | FIFO_WEN <= "11011111"; |
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275 | FIFO_out(5) <= DATA; | |
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276 | 270 | when "110"=> |
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277 | 271 | FIFO_WEN <= "10111111"; |
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278 | FIFO_out(6) <= DATA; | |
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279 | 272 | when "111"=> |
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280 | 273 | FIFO_WEN <= "01111111"; |
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281 | FIFO_out(7) <= DATA; | |
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282 | 274 | when others => |
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283 | 275 | FIFO_WEN <= "11111111"; |
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284 | 276 | end case; |
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285 | 277 | end if; |
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286 | 278 | end if; |
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287 | 279 | end process; |
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288 | 280 | |
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289 | 281 | all_bits: FOR I in 15 downto 0 GENERATE |
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290 | 282 | all_chans: FOR J in 7 downto 0 GENERATE |
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291 | 283 | DAC_DATA(J,I) <= FIFO_out(J)(I); |
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292 | 284 | end GENERATE; |
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293 | 285 | end GENERATE; |
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294 | 286 | |
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295 | 287 | |
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296 | 288 | |
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297 | 289 | process(clk,rstn) |
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298 | 290 | begin |
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299 | 291 | if rstn = '0' then |
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300 | 292 | FIFO_REN <= '1'; |
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301 | 293 | smpclk_reg <= '0'; |
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302 | 294 | elsif clk'event and clk = '1' then |
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303 | 295 | smpclk_reg <= smpclk; |
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304 | 296 | if smpclk = '1' and smpclk_reg = '0' then |
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305 | 297 | FIFO_REN <= '0'; |
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306 | 298 | else |
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307 | 299 | FIFO_REN <= '1'; |
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308 | 300 | end if; |
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309 | 301 | end if; |
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310 | 302 | end process; |
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311 | 303 | |
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312 | 304 | |
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313 | 305 | DAC0 : DAC8581 |
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314 | 306 | generic map(150,8) |
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315 | 307 | Port map( |
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316 | 308 | clk => clk, |
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317 | 309 | rstn => rstn, |
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318 | 310 | smpclk => smpclk, |
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319 | 311 | sclk => CAL_IN_SCK, |
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320 | 312 | csn => DAC_nCS, |
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321 | 313 | sdo => DAC_SDI, |
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322 | 314 | smp_in => DAC_DATA |
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323 | 315 | ); |
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324 | 316 | |
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325 | 317 | |
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326 | 318 | |
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327 | 319 | smpclk0: Clk_divider |
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328 | 320 | GENERIC map(OSC_freqHz => 150000000, |
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329 |
TargetFreq_Hz => |
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321 | TargetFreq_Hz => 256000) | |
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330 | 322 | PORT map( |
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331 | 323 | clk => clk, |
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332 | 324 | reset => rstn, |
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333 | 325 | clk_divided => smpclk |
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334 | 326 | ); |
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335 | 327 | |
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336 | 328 | |
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337 | 329 | end Behavioral; |
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338 | 330 |
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