##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

GPMC_interface almost working
Jeandet Alexis -
r281:c293782dc1e1 alexis
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,198 +1,199
1 1 library ieee;
2 2 use ieee.std_logic_1164.all;
3 3 use IEEE.numeric_std.all;
4 4 library grlib, techmap;
5 5 use grlib.amba.all;
6 6 use grlib.amba.all;
7 7 use grlib.stdlib.all;
8 8 use techmap.gencomp.all;
9 9 use techmap.allclkgen.all;
10 10 library gaisler;
11 11 use gaisler.memctrl.all;
12 12 use gaisler.leon3.all;
13 13 use gaisler.uart.all;
14 14 use gaisler.misc.all;
15 15 library esa;
16 16 use esa.memoryctrl.all;
17 17 --use gaisler.sim.all;
18 18 library lpp;
19 19 use lpp.lpp_ad_conv.all;
20 20 use lpp.lpp_amba.all;
21 21 use lpp.apb_devices_list.all;
22 22 use lpp.general_purpose.all;
23 23 use lpp.lpp_cna.all;
24 24
25 25 Library UNISIM;
26 26 use UNISIM.vcomponents.all;
27 27
28 28
29 29 use work.config.all;
30 30 --==================================================================
31 31 --
32 32 --
33 33 -- FPGA FREQ = 100MHz
34 34 --
35 35 --
36 36 --==================================================================
37 37
38 38 entity BeagleSynth is
39 39 generic (
40 40 fabtech : integer := CFG_FABTECH;
41 41 memtech : integer := CFG_MEMTECH;
42 42 padtech : integer := CFG_PADTECH;
43 43 clktech : integer := CFG_CLKTECH
44 44 );
45 45 port (
46 46 reset : in std_ulogic;
47 47 clk : in std_ulogic;
48 48 DAC_nCLR : out std_ulogic;
49 49 DAC_nCS : out std_ulogic;
50 50 CAL_IN_SCK : out std_ulogic;
51 51 DAC_SDI : out std_logic_vector(7 downto 0);
52 52 TXD : out std_ulogic;
53 53 RXD : in std_ulogic;
54 54 urxd1 : in std_ulogic;
55 55 utxd1 : out std_ulogic;
56 56 LED : out std_ulogic_vector(2 downto 0);
57 57 --------------------------------------------------------
58 58 ---- Beaglebone GPMC
59 59 --------------------------------------------------------
60 60 GPMC_AD : inout std_logic_vector(15 downto 0);
61 61 GPMC_A : in std_logic_vector(19 downto 0);
62 62 GPMC_CLK_MUX0 : in std_logic;
63 63 GPMC_WEN : in std_logic;
64 64 GPMC_OEN_REN : in std_logic;
65 65 GPMC_ADVN_ALE : in std_logic;
66 66 GPMC_CSN : in std_logic_vector(2 downto 0);
67 67 GPMC_BE0N_CLE : in std_logic;
68 68 GPMC_BE1N : in std_logic;
69 69 GPMC_WAIT0 : out std_logic;
70 70 GPMC_WPN : in std_logic;
71 71
72 72 --------------------------------------------------------
73 73 ---- SDRAM
74 74 ---- For SDRAM config have a look on leon3-altera-ep1c20
75 75 ---- design from GRLIB, the IS42S32400E is similar to
76 76 ---- MT48LC4M32B2.
77 77 --------------------------------------------------------
78 78 sdcke : out std_logic; -- clk en
79 79 sdcsn : out std_logic; -- chip sel
80 80 sdwen : out std_logic; -- write en
81 81 sdrasn : out std_logic; -- row addr stb
82 82 sdcasn : out std_logic; -- col addr stb
83 83 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
84 84 sdclk : out std_logic; -- sdram clk output
85 85 sdba : out std_logic_vector (1 downto 0); -- bank select address
86 86 Address : out std_logic_vector(11 downto 0); -- sdram address
87 87 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
88 88 );
89 89 end;
90 90
91 91 architecture rtl of BeagleSynth is
92 92 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
93 93 CFG_GRETH+CFG_AHB_JTAG;
94 94 constant maxahbm : integer := maxahbmsp;
95 95 constant IOAEN : integer := CFG_CAN;
96 96 constant boardfreq : integer := 100000;
97 97
98 98 signal clk2x : std_ulogic;
99 99 signal lclk : std_ulogic;
100 100 signal clkm : std_ulogic;
101 101 signal rstn : std_ulogic;
102 102 signal rst : std_ulogic;
103 103 signal rstraw : std_ulogic;
104 104 signal pciclk : std_ulogic;
105 105 signal sdclkl : std_ulogic;
106 106 signal sdclkl_DDR2 : std_ulogic;
107 107 signal cgi : clkgen_in_type;
108 108 signal cgo : clkgen_out_type;
109 109
110 110
111 111 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
112 112 signal smpclk : std_logic;
113 113 signal smpclk_reg : std_logic;
114 114 signal DAC_SDO : std_logic;
115 115
116 116 signal GPMC_SLAVE_STATUS : std_logic_vector(15 downto 0);
117 117 signal GPMC_SLAVE_DATA : std_logic_vector(15 downto 0);
118 118 signal GPMC_SLAVE_ADDRESS : std_logic_vector(19 downto 0);
119 119 signal GPMC_SLAVE_WEN : std_logic;
120 120
121 121 signal gpmc_clk : std_logic;
122 122
123 123 attribute keep : boolean;
124 124 attribute syn_keep : boolean;
125 125 attribute syn_preserve : boolean;
126 126 attribute syn_keep of clkm : signal is true;
127 127 attribute syn_preserve of clkm : signal is true;
128 128 attribute keep of clkm : signal is true;
129 129 begin
130 130
131 131 DAC_nCLR <= '1';
132 132
133 133
134 134 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
135 135 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
136 136
137 137 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
138 138
139 139 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
140 140 clkgen0 : clkgen -- clock generator
141 141 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
142 142 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
143 143
144 144
145
146
147 145 DAC0 : entity work.beagleSigGen
148 146 generic map(
149 147 memtech,
150 148 padtech,
151 149 clktech
152 150 )
153 151 Port map(
154 152 clk => clkm,
155 153 rstn => rstn,
156 154 CAL_IN_SCK => CAL_IN_SCK,
157 155 DAC_nCS => DAC_nCS,
158 156 DAC_SDI => DAC_SDI,
159 157 address => GPMC_SLAVE_ADDRESS(3 downto 1),
160 158 DATA => GPMC_SLAVE_DATA,
161 159 WEN => GPMC_SLAVE_WEN,
162 REN_debug => LED(1),
160 REN_debug => open,
163 161 FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
164 162 FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
165 163 );
166 164
167 165
168 166
169 LED(0) <= GPMC_SLAVE_WEN;
170 LED(2) <= GPMC_WEN;
167 --LED(0) <= GPMC_SLAVE_ADDRESS(1);
168 --LED(1) <= GPMC_SLAVE_ADDRESS(2);
169 LED(2) <= GPMC_SLAVE_WEN;
171 170
172 171 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
173 172 GPMCS0: entity work.GPMC_SLAVE
174 173 generic map(memtech,padtech)
175 174 Port map(
176 175 clk => clkm,
177 176 reset => rstn,
178 177 STATUS => GPMC_SLAVE_STATUS,
179 178 DATA => GPMC_SLAVE_DATA,
180 179 ADDRESS => GPMC_SLAVE_ADDRESS,
181 180 WEN => GPMC_SLAVE_WEN,
181 SMP_CKL => LED(0),
182 SMP_WEN => LED(1),
182 183 GPMC_AD => GPMC_AD,
183 184 GPMC_A => GPMC_A,
184 185 GPMC_CLK => gpmc_clk,
185 186 GPMC_WEN => GPMC_WEN,
186 187 GPMC_OEN_REN => GPMC_OEN_REN,
187 188 GPMC_ADVN_ALE => GPMC_ADVN_ALE,
188 189 GPMC_CSN => GPMC_CSN,
189 190 GPMC_BE0N_CLE => GPMC_BE0N_CLE,
190 191 GPMC_BE1N => GPMC_BE1N,
191 192 GPMC_WAIT0 => GPMC_WAIT0,
192 193 GPMC_WPN => GPMC_WPN
193 194 );
194 195
195 196 end rtl;
196 197
197 198
198 199
Show file before | Show file after | Hide comments
@@ -1,122 +1,162
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 15:20:11 12/08/2013
6 6 -- Design Name:
7 7 -- Module Name: GPMC_SLAVE - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 library IEEE;
21 21 use IEEE.STD_LOGIC_1164.ALL;
22 22 use IEEE.numeric_std.all;
23 23 library grlib, techmap;
24 24 use grlib.stdlib.all;
25 25 use techmap.gencomp.all;
26 26 use techmap.allclkgen.all;
27 27 library lpp;
28 28 use lpp.general_purpose.all;
29 29
30 30 entity GPMC_SLAVE is
31 31 generic (
32 32 memtech : integer := 0;
33 33 padtech : integer := 0
34 34 );
35 35 Port (
36 36 clk : in STD_LOGIC;
37 37 reset : in STD_LOGIC;
38 38 STATUS : in STD_LOGIC_VECTOR(15 downto 0);
39 39 DATA : out STD_LOGIC_VECTOR(15 downto 0);
40 40 ADDRESS : out std_logic_vector(19 downto 0);
41 41 WEN : out STD_LOGIC;
42 SMP_CKL : out STD_LOGIC;
43 SMP_WEN : out STD_LOGIC;
42 44 GPMC_AD : inout std_logic_vector(15 downto 0);
43 45 GPMC_A : in std_logic_vector(19 downto 0);
44 46 GPMC_CLK : in std_logic;
45 47 GPMC_WEN : in std_logic;
46 48 GPMC_OEN_REN : in std_logic;
47 49 GPMC_ADVN_ALE : in std_logic;
48 50 GPMC_CSN : in std_logic_vector(2 downto 0);
49 51 GPMC_BE0N_CLE : in std_logic;
50 52 GPMC_BE1N : in std_logic;
51 53 GPMC_WAIT0 : out std_logic;
52 54 GPMC_WPN : in std_logic
53 55 );
54 56 end GPMC_SLAVE;
55 57
56 58 architecture Behavioral of GPMC_SLAVE is
57 59
58 signal data_out : std_logic_vector(15 downto 0) := (others => '0');
59 signal data_in : std_logic_vector(15 downto 0) := (others => '0');
60 signal data_out : std_logic_vector(15 downto 0) := (others => '0');
61 signal data_in : std_logic_vector(15 downto 0) := (others => '0');
62 signal data_in_reg0 : std_logic_vector(15 downto 0) := (others => '0');
63 signal data_in_reg1 : std_logic_vector(15 downto 0) := (others => '0');
64 signal data_in_reg2 : std_logic_vector(15 downto 0) := (others => '0');
65 signal address_reg0 : std_logic_vector(19 downto 0) := (others => '0');
66 signal address_reg1 : std_logic_vector(19 downto 0) := (others => '0');
67 signal address_reg2 : std_logic_vector(19 downto 0) := (others => '0');
68 signal ADVN_ALE_reg : std_logic_vector(3 downto 0) := (others => '0');
69
60 70
61 71 signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0');
62 72 signal data_r : std_logic_vector(15 downto 0) := (others => '0');
63
73 signal GPMC_WEN_reg : std_logic_vector(3 downto 0) := (others => '0');
64 74
65 75 signal outen : std_logic := '0';
66 76
67 77
68 78 begin
69 79
70 80 outen <= GPMC_OEN_REN or GPMC_CSN(0);
71 81 data_out <= STATUS;
72 82
73 83 data_pad : iopadv generic map (tech=> padtech,width => 16)
74 84 port map (
75 85 pad => GPMC_AD(15 downto 0),
76 86 o => data_in(15 downto 0),
77 87 en => outen,
78 88 i => data_out(15 downto 0)
79 89 );
80 90
81 91 GPMC_WAIT0 <= '1';
92 SMP_CKL <= GPMC_CLK_reg(0);
93 SMP_WEN <= GPMC_WEN_reg(2);
82 94
95 process(reset,clk)
96 begin
97 if reset = '0' then
98 GPMC_CLK_reg <= "0000";
99 ADDRESS <= (others => '0');
100 ADVN_ALE_reg <= (others => '0');
101 address_reg0 <= (others => '0');
102 address_reg1 <= (others => '0');
103 address_reg2 <= (others => '0');
104 elsif clk'event and clk = '1' then
105 GPMC_CLK_reg(0) <= GPMC_CLK;
106 GPMC_CLK_reg(1) <= GPMC_CLK_reg(0);
107 GPMC_CLK_reg(2) <= GPMC_CLK_reg(1);
108 ADVN_ALE_reg(0) <= GPMC_ADVN_ALE;
109 ADVN_ALE_reg(1) <= ADVN_ALE_reg(0);
110 ADVN_ALE_reg(2) <= ADVN_ALE_reg(1);
111 address_reg0 <= GPMC_A;
112 address_reg1 <= address_reg0;
113 address_reg2 <= address_reg1;
114 if GPMC_CLK_reg(1) = '1' and GPMC_CLK_reg(2) = '0' then
115 if ADVN_ALE_reg(2) = '0' then
116 ADDRESS <= address_reg2;
117 end if;
118 end if;
119
120 end if;
121 end process;
83 122
84 123
85 124 process(reset,clk)
86 125 begin
87 126 if reset = '0' then
88 127 WEN <= '1';
89 GPMC_CLK_reg <= "0000";
90 ADDRESS <= (others => '0');
128 GPMC_WEN_reg <= "0000";
129 data_in_reg0 <= (others => '0');
130 data_in_reg1 <= (others => '0');
131 data_in_reg2 <= (others => '0');
91 132 elsif clk'event and clk = '1' then
92 GPMC_CLK_reg(0) <= GPMC_CLK;
93 if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then
94 if GPMC_WEN = '0' then
95 WEN <= '0';
96 DATA <= data_in;
97 end if;
98 if GPMC_ADVN_ALE = '0' then
99 ADDRESS <= GPMC_A;
100 end if;
133 GPMC_WEN_reg(0) <= GPMC_WEN;
134 GPMC_WEN_reg(1) <= GPMC_WEN_reg(0);
135 GPMC_WEN_reg(2) <= GPMC_WEN_reg(1);
136 data_in_reg0 <= data_in;
137 data_in_reg1 <= data_in_reg0;
138 data_in_reg2 <= data_in_reg1;
139 if GPMC_WEN_reg(2) = '1' and GPMC_WEN_reg(1) = '0' then
140 WEN <= '0';
141 DATA <= data_in_reg2;
101 142 else
102 WEN <= '1';
143 WEN <= '1';
103 144 end if;
104
105 145 end if;
106 146 end process;
107 147
108 148 end Behavioral;
109 149
110 150
111 151
112 152
113 153
114 154
115 155
116 156
117 157
118 158
119 159
120 160
121 161
122 162
Show file before | Show file after | Hide comments
@@ -1,338 +1,330
1 1 library ieee;
2 2 use ieee.std_logic_1164.all;
3 3 use IEEE.numeric_std.all;
4 4 library grlib, techmap;
5 5 use grlib.amba.all;
6 6 use grlib.amba.all;
7 7 use grlib.stdlib.all;
8 8 use techmap.gencomp.all;
9 9 use techmap.allclkgen.all;
10 10 library gaisler;
11 11 use gaisler.memctrl.all;
12 12 use gaisler.leon3.all;
13 13 use gaisler.uart.all;
14 14 use gaisler.misc.all;
15 15 library esa;
16 16 use esa.memoryctrl.all;
17 17 --use gaisler.sim.all;
18 18 library lpp;
19 19 use lpp.lpp_ad_conv.all;
20 20 use lpp.lpp_amba.all;
21 21 use lpp.apb_devices_list.all;
22 22 use lpp.general_purpose.all;
23 23 use lpp.lpp_cna.all;
24 24 use lpp.lpp_memory.all;
25 25
26 26 Library UNISIM;
27 27 use UNISIM.vcomponents.all;
28 28
29 29 use work.config.all;
30 30
31 31 entity beagleSigGen is
32 32 generic (
33 33 memtech : integer := CFG_MEMTECH;
34 34 padtech : integer := CFG_PADTECH;
35 35 clktech : integer := CFG_CLKTECH
36 36 );
37 37 Port (
38 38 clk : in STD_LOGIC;
39 39 rstn : in STD_LOGIC;
40 40 CAL_IN_SCK : out std_ulogic;
41 41 DAC_nCS : out std_ulogic;
42 42 DAC_SDI : out std_logic_vector(7 downto 0);
43 43 address : in std_logic_vector(2 downto 0);
44 44 DATA : in std_logic_vector(15 downto 0);
45 45 REN_debug : out std_logic;
46 46 WEN : in std_logic;
47 47 FIFO_FULL : out std_logic_vector(7 downto 0);
48 48 FIFO_EMPTY : out std_logic_vector(7 downto 0)
49 49 );
50 50 end beagleSigGen;
51 51
52 52 architecture Behavioral of beagleSigGen is
53 53
54 54
55 55 signal FIFO_FULL_net : std_logic_vector(7 downto 0);
56 56 signal FIFO_EMPTY_net : std_logic_vector(7 downto 0);
57 57 signal FIFO_WEN : std_logic_vector(7 downto 0);
58 58 signal FIFO_REN : std_logic;
59 59
60 60
61 61 subtype TAB16 is std_logic_vector(15 downto 0);
62 62 type FIFOout_t is array(7 downto 0) of TAB16;
63 63
64 64 signal FIFO_out : FIFOout_t;
65 65 signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
66 66 signal smpclk : std_logic;
67 67 signal smpclk_reg : std_logic;
68 68 signal DAC_SDO : std_logic;
69 69 signal DATA_reg : std_logic_vector(15 downto 0);
70 70
71 71 begin
72 72
73 73
74 74
75 75 FIFO_FULL <= FIFO_FULL_net;
76 76 FIFO_EMPTY <= FIFO_EMPTY_net;
77 77
78 --fron_fifo1: lpp_fifo
79 -- generic map(
80 -- tech => memtech,
81 -- Mem_use => 1, --use RAM not CELS
82 -- DataSz => 16,
83 -- AddrSz => 8
84 -- )
85 -- port map(
86 -- rstn => rstn,
87 -- ReUse => '0',
88 -- rclk => clk,
89 -- ren => FIFO_REN,
90 -- rdata => FIFO_out(0),
91 -- empty => FIFO_EMPTY_net(0),
92 -- raddr => open,
93 -- wclk => clk,
94 -- wen => FIFO_WEN(0),
95 -- wdata => DATA_reg,
96 -- full => FIFO_FULL_net(0),
97 -- waddr => open
98 -- );
99 --fron_fifo2: lpp_fifo
100 -- generic map(
101 -- tech => memtech,
102 -- Mem_use => 1, --use RAM not CELS
103 -- DataSz => 16,
104 -- AddrSz => 8
105 -- )
106 -- port map(
107 -- rstn => rstn,
108 -- ReUse => '0',
109 -- rclk => clk,
110 -- ren => FIFO_REN,
111 -- rdata => FIFO_out(1),
112 -- empty => FIFO_EMPTY_net(1),
113 -- raddr => open,
114 -- wclk => clk,
115 -- wen => FIFO_WEN(1),
116 -- wdata => DATA_reg,
117 -- full => FIFO_FULL_net(1),
118 -- waddr => open
119 -- );
120 --fron_fifo3: lpp_fifo
121 -- generic map(
122 -- tech => memtech,
123 -- Mem_use => 1, --use RAM not CELS
124 -- DataSz => 16,
125 -- AddrSz => 8
126 -- )
127 -- port map(
128 -- rstn => rstn,
129 -- ReUse => '0',
130 -- rclk => clk,
131 -- ren => FIFO_REN,
132 -- rdata => FIFO_out(2),
133 -- empty => FIFO_EMPTY_net(2),
134 -- raddr => open,
135 -- wclk => clk,
136 -- wen => FIFO_WEN(2),
137 -- wdata => DATA_reg,
138 -- full => FIFO_FULL_net(2),
139 -- waddr => open
140 -- );
141 --fron_fifo4: lpp_fifo
142 -- generic map(
143 -- tech => memtech,
144 -- Mem_use => 1, --use RAM not CELS
145 -- DataSz => 16,
146 -- AddrSz => 8
147 -- )
148 -- port map(
149 -- rstn => rstn,
150 -- ReUse => '0',
151 -- rclk => clk,
152 -- ren => FIFO_REN,
153 -- rdata => FIFO_out(3),
154 -- empty => FIFO_EMPTY_net(3),
155 -- raddr => open,
156 -- wclk => clk,
157 -- wen => FIFO_WEN(3),
158 -- wdata => DATA_reg,
159 -- full => FIFO_FULL_net(3),
160 -- waddr => open
161 -- );
162 --fron_fifo5: lpp_fifo
163 -- generic map(
164 -- tech => memtech,
165 -- Mem_use => 1, --use RAM not CELS
166 -- DataSz => 16,
167 -- AddrSz => 8
168 -- )
169 -- port map(
170 -- rstn => rstn,
171 -- ReUse => '0',
172 -- rclk => clk,
173 -- ren => FIFO_REN,
174 -- rdata => FIFO_out(4),
175 -- empty => FIFO_EMPTY_net(4),
176 -- raddr => open,
177 -- wclk => clk,
178 -- wen => FIFO_WEN(4),
179 -- wdata => DATA_reg,
180 -- full => FIFO_FULL_net(4),
181 -- waddr => open
182 -- );
183 --fron_fifo6: lpp_fifo
184 -- generic map(
185 -- tech => memtech,
186 -- Mem_use => 1, --use RAM not CELS
187 -- DataSz => 16,
188 -- AddrSz => 8
189 -- )
190 -- port map(
191 -- rstn => rstn,
192 -- ReUse => '0',
193 -- rclk => clk,
194 -- ren => FIFO_REN,
195 -- rdata => FIFO_out(5),
196 -- empty => FIFO_EMPTY_net(5),
197 -- raddr => open,
198 -- wclk => clk,
199 -- wen => FIFO_WEN(5),
200 -- wdata => DATA_reg,
201 -- full => FIFO_FULL_net(5),
202 -- waddr => open
203 -- );
204 --fron_fifo7: lpp_fifo
205 -- generic map(
206 -- tech => memtech,
207 -- Mem_use => 1, --use RAM not CELS
208 -- DataSz => 16,
209 -- AddrSz => 8
210 -- )
211 -- port map(
212 -- rstn => rstn,
213 -- ReUse => '0',
214 -- rclk => clk,
215 -- ren => FIFO_REN,
216 -- rdata => FIFO_out(6),
217 -- empty => FIFO_EMPTY_net(6),
218 -- raddr => open,
219 -- wclk => clk,
220 -- wen => FIFO_WEN(6),
221 -- wdata => DATA_reg,
222 -- full => FIFO_FULL_net(6),
223 -- waddr => open
224 -- );
225 --fron_fifo8: lpp_fifo
226 -- generic map(
227 -- tech => memtech,
228 -- Mem_use => 1, --use RAM not CELS
229 -- DataSz => 16,
230 -- AddrSz => 8
231 -- )
232 -- port map(
233 -- rstn => rstn,
234 -- ReUse => '0',
235 -- rclk => clk,
236 -- ren => FIFO_REN,
237 -- rdata => FIFO_out(7),
238 -- empty => FIFO_EMPTY_net(7),
239 -- raddr => open,
240 -- wclk => clk,
241 -- wen => FIFO_WEN(7),
242 -- wdata => DATA_reg,
243 -- full => FIFO_FULL_net(7),
244 -- waddr => open
245 -- );
78 fron_fifo1: lpp_fifo
79 generic map(
80 tech => memtech,
81 Mem_use => 1, --use RAM not CELS
82 DataSz => 16,
83 AddrSz => 8
84 )
85 port map(
86 rstn => rstn,
87 ReUse => '0',
88 rclk => clk,
89 ren => FIFO_REN,
90 rdata => FIFO_out(0),
91 empty => FIFO_EMPTY_net(0),
92 raddr => open,
93 wclk => clk,
94 wen => FIFO_WEN(0),
95 wdata => DATA_reg,
96 full => FIFO_FULL_net(0),
97 waddr => open
98 );
99 fron_fifo2: lpp_fifo
100 generic map(
101 tech => memtech,
102 Mem_use => 1, --use RAM not CELS
103 DataSz => 16,
104 AddrSz => 8
105 )
106 port map(
107 rstn => rstn,
108 ReUse => '0',
109 rclk => clk,
110 ren => FIFO_REN,
111 rdata => FIFO_out(1),
112 empty => FIFO_EMPTY_net(1),
113 raddr => open,
114 wclk => clk,
115 wen => FIFO_WEN(1),
116 wdata => DATA_reg,
117 full => FIFO_FULL_net(1),
118 waddr => open
119 );
120 fron_fifo3: lpp_fifo
121 generic map(
122 tech => memtech,
123 Mem_use => 1, --use RAM not CELS
124 DataSz => 16,
125 AddrSz => 8
126 )
127 port map(
128 rstn => rstn,
129 ReUse => '0',
130 rclk => clk,
131 ren => FIFO_REN,
132 rdata => FIFO_out(2),
133 empty => FIFO_EMPTY_net(2),
134 raddr => open,
135 wclk => clk,
136 wen => FIFO_WEN(2),
137 wdata => DATA_reg,
138 full => FIFO_FULL_net(2),
139 waddr => open
140 );
141 fron_fifo4: lpp_fifo
142 generic map(
143 tech => memtech,
144 Mem_use => 1, --use RAM not CELS
145 DataSz => 16,
146 AddrSz => 8
147 )
148 port map(
149 rstn => rstn,
150 ReUse => '0',
151 rclk => clk,
152 ren => FIFO_REN,
153 rdata => FIFO_out(3),
154 empty => FIFO_EMPTY_net(3),
155 raddr => open,
156 wclk => clk,
157 wen => FIFO_WEN(3),
158 wdata => DATA_reg,
159 full => FIFO_FULL_net(3),
160 waddr => open
161 );
162 fron_fifo5: lpp_fifo
163 generic map(
164 tech => memtech,
165 Mem_use => 1, --use RAM not CELS
166 DataSz => 16,
167 AddrSz => 8
168 )
169 port map(
170 rstn => rstn,
171 ReUse => '0',
172 rclk => clk,
173 ren => FIFO_REN,
174 rdata => FIFO_out(4),
175 empty => FIFO_EMPTY_net(4),
176 raddr => open,
177 wclk => clk,
178 wen => FIFO_WEN(4),
179 wdata => DATA_reg,
180 full => FIFO_FULL_net(4),
181 waddr => open
182 );
183 fron_fifo6: lpp_fifo
184 generic map(
185 tech => memtech,
186 Mem_use => 1, --use RAM not CELS
187 DataSz => 16,
188 AddrSz => 8
189 )
190 port map(
191 rstn => rstn,
192 ReUse => '0',
193 rclk => clk,
194 ren => FIFO_REN,
195 rdata => FIFO_out(5),
196 empty => FIFO_EMPTY_net(5),
197 raddr => open,
198 wclk => clk,
199 wen => FIFO_WEN(5),
200 wdata => DATA_reg,
201 full => FIFO_FULL_net(5),
202 waddr => open
203 );
204 fron_fifo7: lpp_fifo
205 generic map(
206 tech => memtech,
207 Mem_use => 1, --use RAM not CELS
208 DataSz => 16,
209 AddrSz => 8
210 )
211 port map(
212 rstn => rstn,
213 ReUse => '0',
214 rclk => clk,
215 ren => FIFO_REN,
216 rdata => FIFO_out(6),
217 empty => FIFO_EMPTY_net(6),
218 raddr => open,
219 wclk => clk,
220 wen => FIFO_WEN(6),
221 wdata => DATA_reg,
222 full => FIFO_FULL_net(6),
223 waddr => open
224 );
225 fron_fifo8: lpp_fifo
226 generic map(
227 tech => memtech,
228 Mem_use => 1, --use RAM not CELS
229 DataSz => 16,
230 AddrSz => 8
231 )
232 port map(
233 rstn => rstn,
234 ReUse => '0',
235 rclk => clk,
236 ren => FIFO_REN,
237 rdata => FIFO_out(7),
238 empty => FIFO_EMPTY_net(7),
239 raddr => open,
240 wclk => clk,
241 wen => FIFO_WEN(7),
242 wdata => DATA_reg,
243 full => FIFO_FULL_net(7),
244 waddr => open
245 );
246 246
247 247 REN_debug <= FIFO_REN;
248 248
249 249 process(clk,rstn)
250 250 begin
251 251 if rstn = '0' then
252 252 DATA_reg <= (others => '0');
253 253 FIFO_WEN <= (others => '0');
254 254 elsif clk'event and clk = '1' then
255 255 if WEN = '0' then
256 256 DATA_reg <= DATA;
257 257 case address is
258 258 when "000"=>
259 259 FIFO_WEN <= "11111110";
260 FIFO_out(0) <= DATA;
261 260 when "001"=>
262 261 FIFO_WEN <= "11111101";
263 FIFO_out(1) <= DATA;
264 262 when "010"=>
265 263 FIFO_WEN <= "11111011";
266 FIFO_out(2) <= DATA;
267 264 when "011"=>
268 265 FIFO_WEN <= "11110111";
269 FIFO_out(3) <= DATA;
270 266 when "100"=>
271 267 FIFO_WEN <= "11101111";
272 FIFO_out(4) <= DATA;
273 268 when "101"=>
274 269 FIFO_WEN <= "11011111";
275 FIFO_out(5) <= DATA;
276 270 when "110"=>
277 271 FIFO_WEN <= "10111111";
278 FIFO_out(6) <= DATA;
279 272 when "111"=>
280 273 FIFO_WEN <= "01111111";
281 FIFO_out(7) <= DATA;
282 274 when others =>
283 275 FIFO_WEN <= "11111111";
284 276 end case;
285 277 end if;
286 278 end if;
287 279 end process;
288 280
289 281 all_bits: FOR I in 15 downto 0 GENERATE
290 282 all_chans: FOR J in 7 downto 0 GENERATE
291 283 DAC_DATA(J,I) <= FIFO_out(J)(I);
292 284 end GENERATE;
293 285 end GENERATE;
294 286
295 287
296 288
297 289 process(clk,rstn)
298 290 begin
299 291 if rstn = '0' then
300 292 FIFO_REN <= '1';
301 293 smpclk_reg <= '0';
302 294 elsif clk'event and clk = '1' then
303 295 smpclk_reg <= smpclk;
304 296 if smpclk = '1' and smpclk_reg = '0' then
305 297 FIFO_REN <= '0';
306 298 else
307 299 FIFO_REN <= '1';
308 300 end if;
309 301 end if;
310 302 end process;
311 303
312 304
313 305 DAC0 : DAC8581
314 306 generic map(150,8)
315 307 Port map(
316 308 clk => clk,
317 309 rstn => rstn,
318 310 smpclk => smpclk,
319 311 sclk => CAL_IN_SCK,
320 312 csn => DAC_nCS,
321 313 sdo => DAC_SDI,
322 314 smp_in => DAC_DATA
323 315 );
324 316
325 317
326 318
327 319 smpclk0: Clk_divider
328 320 GENERIC map(OSC_freqHz => 150000000,
329 TargetFreq_Hz => 32000)
321 TargetFreq_Hz => 256000)
330 322 PORT map(
331 323 clk => clk,
332 324 reset => rstn,
333 325 clk_divided => smpclk
334 326 );
335 327
336 328
337 329 end Behavioral;
338 330
General Comments 0
You need to be logged in to leave comments. Login now