@@ -142,8 +142,6 resetn_pad : inpad generic map (tech => | |||
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142 | 142 | port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open); |
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143 | 143 | |
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144 | 144 | |
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145 | ||
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146 | ||
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147 | 145 | DAC0 : entity work.beagleSigGen |
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148 | 146 | generic map( |
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149 | 147 | memtech, |
@@ -159,15 +157,16 DAC0 : entity work.beagleSigGen | |||
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159 | 157 | address => GPMC_SLAVE_ADDRESS(3 downto 1), |
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160 | 158 | DATA => GPMC_SLAVE_DATA, |
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161 | 159 | WEN => GPMC_SLAVE_WEN, |
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162 |
REN_debug => |
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160 | REN_debug => open, | |
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163 | 161 | FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0), |
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164 | 162 | FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8) |
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165 | 163 | ); |
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166 | 164 | |
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167 | 165 | |
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168 | 166 | |
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169 |
LED(0) <= GPMC_SLAVE_ |
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170 |
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167 | --LED(0) <= GPMC_SLAVE_ADDRESS(1); | |
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168 | --LED(1) <= GPMC_SLAVE_ADDRESS(2); | |
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169 | LED(2) <= GPMC_SLAVE_WEN; | |
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171 | 170 | |
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172 | 171 | gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk); |
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173 | 172 | GPMCS0: entity work.GPMC_SLAVE |
@@ -179,6 +178,8 GPMCS0: entity work.GPMC_SLAVE | |||
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179 | 178 | DATA => GPMC_SLAVE_DATA, |
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180 | 179 | ADDRESS => GPMC_SLAVE_ADDRESS, |
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181 | 180 | WEN => GPMC_SLAVE_WEN, |
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181 | SMP_CKL => LED(0), | |
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182 | SMP_WEN => LED(1), | |
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182 | 183 | GPMC_AD => GPMC_AD, |
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183 | 184 | GPMC_A => GPMC_A, |
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184 | 185 | GPMC_CLK => gpmc_clk, |
@@ -39,6 +39,8 entity GPMC_SLAVE is | |||
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39 | 39 | DATA : out STD_LOGIC_VECTOR(15 downto 0); |
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40 | 40 | ADDRESS : out std_logic_vector(19 downto 0); |
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41 | 41 | WEN : out STD_LOGIC; |
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42 | SMP_CKL : out STD_LOGIC; | |
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43 | SMP_WEN : out STD_LOGIC; | |
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42 | 44 | GPMC_AD : inout std_logic_vector(15 downto 0); |
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43 | 45 | GPMC_A : in std_logic_vector(19 downto 0); |
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44 | 46 | GPMC_CLK : in std_logic; |
@@ -57,10 +59,18 architecture Behavioral of GPMC_SLAVE is | |||
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57 | 59 | |
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58 | 60 | signal data_out : std_logic_vector(15 downto 0) := (others => '0'); |
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59 | 61 | signal data_in : std_logic_vector(15 downto 0) := (others => '0'); |
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62 | signal data_in_reg0 : std_logic_vector(15 downto 0) := (others => '0'); | |
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63 | signal data_in_reg1 : std_logic_vector(15 downto 0) := (others => '0'); | |
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64 | signal data_in_reg2 : std_logic_vector(15 downto 0) := (others => '0'); | |
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65 | signal address_reg0 : std_logic_vector(19 downto 0) := (others => '0'); | |
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66 | signal address_reg1 : std_logic_vector(19 downto 0) := (others => '0'); | |
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67 | signal address_reg2 : std_logic_vector(19 downto 0) := (others => '0'); | |
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68 | signal ADVN_ALE_reg : std_logic_vector(3 downto 0) := (others => '0'); | |
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69 | ||
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60 | 70 | |
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61 | 71 | signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0'); |
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62 | 72 | signal data_r : std_logic_vector(15 downto 0) := (others => '0'); |
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63 | ||
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73 | signal GPMC_WEN_reg : std_logic_vector(3 downto 0) := (others => '0'); | |
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64 | 74 | |
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65 | 75 | signal outen : std_logic := '0'; |
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66 | 76 | |
@@ -79,29 +89,59 port map ( | |||
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79 | 89 | ); |
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80 | 90 | |
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81 | 91 | GPMC_WAIT0 <= '1'; |
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92 | SMP_CKL <= GPMC_CLK_reg(0); | |
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93 | SMP_WEN <= GPMC_WEN_reg(2); | |
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82 | 94 | |
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95 | process(reset,clk) | |
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96 | begin | |
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97 | if reset = '0' then | |
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98 | GPMC_CLK_reg <= "0000"; | |
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99 | ADDRESS <= (others => '0'); | |
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100 | ADVN_ALE_reg <= (others => '0'); | |
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101 | address_reg0 <= (others => '0'); | |
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102 | address_reg1 <= (others => '0'); | |
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103 | address_reg2 <= (others => '0'); | |
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104 | elsif clk'event and clk = '1' then | |
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105 | GPMC_CLK_reg(0) <= GPMC_CLK; | |
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106 | GPMC_CLK_reg(1) <= GPMC_CLK_reg(0); | |
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107 | GPMC_CLK_reg(2) <= GPMC_CLK_reg(1); | |
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108 | ADVN_ALE_reg(0) <= GPMC_ADVN_ALE; | |
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109 | ADVN_ALE_reg(1) <= ADVN_ALE_reg(0); | |
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110 | ADVN_ALE_reg(2) <= ADVN_ALE_reg(1); | |
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111 | address_reg0 <= GPMC_A; | |
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112 | address_reg1 <= address_reg0; | |
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113 | address_reg2 <= address_reg1; | |
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114 | if GPMC_CLK_reg(1) = '1' and GPMC_CLK_reg(2) = '0' then | |
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115 | if ADVN_ALE_reg(2) = '0' then | |
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116 | ADDRESS <= address_reg2; | |
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117 | end if; | |
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118 | end if; | |
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119 | ||
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120 | end if; | |
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121 | end process; | |
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83 | 122 | |
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84 | 123 | |
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85 | 124 | process(reset,clk) |
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86 | 125 | begin |
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87 | 126 | if reset = '0' then |
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88 | 127 | WEN <= '1'; |
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89 |
GPMC_ |
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90 |
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128 | GPMC_WEN_reg <= "0000"; | |
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129 | data_in_reg0 <= (others => '0'); | |
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130 | data_in_reg1 <= (others => '0'); | |
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131 | data_in_reg2 <= (others => '0'); | |
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91 | 132 | elsif clk'event and clk = '1' then |
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92 |
GPMC_ |
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93 | if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then | |
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94 | if GPMC_WEN = '0' then | |
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133 | GPMC_WEN_reg(0) <= GPMC_WEN; | |
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134 | GPMC_WEN_reg(1) <= GPMC_WEN_reg(0); | |
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135 | GPMC_WEN_reg(2) <= GPMC_WEN_reg(1); | |
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136 | data_in_reg0 <= data_in; | |
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137 | data_in_reg1 <= data_in_reg0; | |
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138 | data_in_reg2 <= data_in_reg1; | |
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139 | if GPMC_WEN_reg(2) = '1' and GPMC_WEN_reg(1) = '0' then | |
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95 | 140 |
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96 |
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97 | end if; | |
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98 | if GPMC_ADVN_ALE = '0' then | |
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99 | ADDRESS <= GPMC_A; | |
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100 | end if; | |
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141 | DATA <= data_in_reg2; | |
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101 | 142 | else |
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102 | 143 |
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103 | 144 | end if; |
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104 | ||
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105 | 145 | end if; |
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106 | 146 | end process; |
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107 | 147 |
@@ -75,174 +75,174 begin | |||
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75 | 75 | FIFO_FULL <= FIFO_FULL_net; |
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76 | 76 | FIFO_EMPTY <= FIFO_EMPTY_net; |
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78 | fron_fifo1: lpp_fifo | |
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79 | generic map( | |
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80 | tech => memtech, | |
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81 | Mem_use => 1, --use RAM not CELS | |
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82 | DataSz => 16, | |
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83 | AddrSz => 8 | |
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84 | ) | |
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85 | port map( | |
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86 | rstn => rstn, | |
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87 | ReUse => '0', | |
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88 | rclk => clk, | |
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89 | ren => FIFO_REN, | |
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90 | rdata => FIFO_out(0), | |
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91 | empty => FIFO_EMPTY_net(0), | |
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92 | raddr => open, | |
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93 | wclk => clk, | |
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94 | wen => FIFO_WEN(0), | |
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95 | wdata => DATA_reg, | |
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96 | full => FIFO_FULL_net(0), | |
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97 | waddr => open | |
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98 | ); | |
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99 | fron_fifo2: lpp_fifo | |
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100 | generic map( | |
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101 | tech => memtech, | |
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102 | Mem_use => 1, --use RAM not CELS | |
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103 | DataSz => 16, | |
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104 | AddrSz => 8 | |
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105 | ) | |
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106 | port map( | |
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107 | rstn => rstn, | |
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108 | ReUse => '0', | |
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109 | rclk => clk, | |
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110 | ren => FIFO_REN, | |
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111 | rdata => FIFO_out(1), | |
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112 | empty => FIFO_EMPTY_net(1), | |
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113 | raddr => open, | |
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114 | wclk => clk, | |
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115 | wen => FIFO_WEN(1), | |
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116 | wdata => DATA_reg, | |
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117 | full => FIFO_FULL_net(1), | |
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118 | waddr => open | |
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119 | ); | |
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120 | fron_fifo3: lpp_fifo | |
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121 | generic map( | |
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122 | tech => memtech, | |
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123 | Mem_use => 1, --use RAM not CELS | |
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124 | DataSz => 16, | |
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125 | AddrSz => 8 | |
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126 | ) | |
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127 | port map( | |
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128 | rstn => rstn, | |
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129 | ReUse => '0', | |
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130 | rclk => clk, | |
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131 | ren => FIFO_REN, | |
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132 | rdata => FIFO_out(2), | |
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133 | empty => FIFO_EMPTY_net(2), | |
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134 | raddr => open, | |
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135 | wclk => clk, | |
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136 | wen => FIFO_WEN(2), | |
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137 | wdata => DATA_reg, | |
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138 | full => FIFO_FULL_net(2), | |
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139 | waddr => open | |
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140 | ); | |
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141 | fron_fifo4: lpp_fifo | |
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142 | generic map( | |
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143 | tech => memtech, | |
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144 | Mem_use => 1, --use RAM not CELS | |
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145 | DataSz => 16, | |
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146 | AddrSz => 8 | |
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147 | ) | |
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148 | port map( | |
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149 | rstn => rstn, | |
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150 | ReUse => '0', | |
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151 | rclk => clk, | |
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152 | ren => FIFO_REN, | |
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153 | rdata => FIFO_out(3), | |
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154 | empty => FIFO_EMPTY_net(3), | |
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155 | raddr => open, | |
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156 | wclk => clk, | |
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157 | wen => FIFO_WEN(3), | |
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158 | wdata => DATA_reg, | |
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159 | full => FIFO_FULL_net(3), | |
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160 | waddr => open | |
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161 | ); | |
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162 | fron_fifo5: lpp_fifo | |
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163 | generic map( | |
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164 | tech => memtech, | |
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165 | Mem_use => 1, --use RAM not CELS | |
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166 | DataSz => 16, | |
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167 | AddrSz => 8 | |
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168 | ) | |
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169 | port map( | |
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170 | rstn => rstn, | |
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171 | ReUse => '0', | |
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172 | rclk => clk, | |
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173 | ren => FIFO_REN, | |
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174 | rdata => FIFO_out(4), | |
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175 | empty => FIFO_EMPTY_net(4), | |
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176 | raddr => open, | |
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177 | wclk => clk, | |
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178 | wen => FIFO_WEN(4), | |
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179 | wdata => DATA_reg, | |
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180 | full => FIFO_FULL_net(4), | |
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181 | waddr => open | |
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182 | ); | |
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183 | fron_fifo6: lpp_fifo | |
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184 | generic map( | |
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185 | tech => memtech, | |
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186 | Mem_use => 1, --use RAM not CELS | |
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187 | DataSz => 16, | |
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188 | AddrSz => 8 | |
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189 | ) | |
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190 | port map( | |
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191 | rstn => rstn, | |
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192 | ReUse => '0', | |
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193 | rclk => clk, | |
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194 | ren => FIFO_REN, | |
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195 | rdata => FIFO_out(5), | |
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196 | empty => FIFO_EMPTY_net(5), | |
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197 | raddr => open, | |
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198 | wclk => clk, | |
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199 | wen => FIFO_WEN(5), | |
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200 | wdata => DATA_reg, | |
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201 | full => FIFO_FULL_net(5), | |
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202 | waddr => open | |
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203 | ); | |
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204 | fron_fifo7: lpp_fifo | |
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205 | generic map( | |
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206 | tech => memtech, | |
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207 | Mem_use => 1, --use RAM not CELS | |
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208 | DataSz => 16, | |
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209 | AddrSz => 8 | |
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210 | ) | |
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211 | port map( | |
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212 | rstn => rstn, | |
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213 | ReUse => '0', | |
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214 | rclk => clk, | |
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215 | ren => FIFO_REN, | |
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216 | rdata => FIFO_out(6), | |
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217 | empty => FIFO_EMPTY_net(6), | |
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218 | raddr => open, | |
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219 | wclk => clk, | |
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220 | wen => FIFO_WEN(6), | |
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221 | wdata => DATA_reg, | |
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222 | full => FIFO_FULL_net(6), | |
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223 | waddr => open | |
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224 | ); | |
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225 | fron_fifo8: lpp_fifo | |
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226 | generic map( | |
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227 | tech => memtech, | |
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228 | Mem_use => 1, --use RAM not CELS | |
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229 | DataSz => 16, | |
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230 | AddrSz => 8 | |
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231 | ) | |
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232 | port map( | |
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233 | rstn => rstn, | |
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234 | ReUse => '0', | |
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235 | rclk => clk, | |
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236 | ren => FIFO_REN, | |
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237 | rdata => FIFO_out(7), | |
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238 | empty => FIFO_EMPTY_net(7), | |
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239 | raddr => open, | |
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240 | wclk => clk, | |
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241 | wen => FIFO_WEN(7), | |
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242 | wdata => DATA_reg, | |
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243 | full => FIFO_FULL_net(7), | |
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244 | waddr => open | |
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245 | ); | |
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246 | 246 | |
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247 | 247 | REN_debug <= FIFO_REN; |
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248 | 248 | |
@@ -257,28 +257,20 begin | |||
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257 | 257 | case address is |
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258 | 258 | when "000"=> |
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259 | 259 | FIFO_WEN <= "11111110"; |
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260 | FIFO_out(0) <= DATA; | |
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261 | 260 | when "001"=> |
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262 | 261 | FIFO_WEN <= "11111101"; |
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263 | FIFO_out(1) <= DATA; | |
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264 | 262 | when "010"=> |
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265 | 263 | FIFO_WEN <= "11111011"; |
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266 | FIFO_out(2) <= DATA; | |
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267 | 264 | when "011"=> |
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268 | 265 | FIFO_WEN <= "11110111"; |
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269 | FIFO_out(3) <= DATA; | |
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270 | 266 | when "100"=> |
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271 | 267 | FIFO_WEN <= "11101111"; |
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272 | FIFO_out(4) <= DATA; | |
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273 | 268 | when "101"=> |
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274 | 269 | FIFO_WEN <= "11011111"; |
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275 | FIFO_out(5) <= DATA; | |
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276 | 270 | when "110"=> |
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277 | 271 | FIFO_WEN <= "10111111"; |
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278 | FIFO_out(6) <= DATA; | |
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279 | 272 | when "111"=> |
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280 | 273 | FIFO_WEN <= "01111111"; |
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281 | FIFO_out(7) <= DATA; | |
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282 | 274 | when others => |
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283 | 275 | FIFO_WEN <= "11111111"; |
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284 | 276 | end case; |
@@ -326,7 +318,7 DAC0 : DAC8581 | |||
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326 | 318 | |
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327 | 319 | smpclk0: Clk_divider |
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328 | 320 | GENERIC map(OSC_freqHz => 150000000, |
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329 |
TargetFreq_Hz => |
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321 | TargetFreq_Hz => 256000) | |
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330 | 322 | PORT map( |
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331 | 323 | clk => clk, |
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332 | 324 | reset => rstn, |
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