@@ -192,6 +192,9 ARCHITECTURE beh OF MINI_LFR_top IS | |||
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192 | 192 | |
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193 | 193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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194 | 194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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195 | ||
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196 | -- | |
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197 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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195 | 198 | |
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196 | 199 | BEGIN -- beh |
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197 | 200 | |
@@ -348,7 +351,8 BEGIN -- beh | |||
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348 | 351 | NB_AHB_MASTER => NB_AHB_MASTER, |
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349 | 352 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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350 | 353 | NB_APB_SLAVE => NB_APB_SLAVE, |
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351 |
ADDRESS_SIZE => 20 |
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354 | ADDRESS_SIZE => 20, | |
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355 | USES_IAP_MEMCTRLR => 0) | |
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352 | 356 | PORT MAP ( |
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353 | 357 | clk => clk_25, |
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354 | 358 | reset => rstn_25, |
@@ -364,9 +368,10 BEGIN -- beh | |||
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364 | 368 | nSRAM_BE2 => SRAM_nBE(2), |
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365 | 369 | nSRAM_BE3 => SRAM_nBE(3), |
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366 | 370 | nSRAM_WE => SRAM_nWE, |
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367 | nSRAM_CE => SRAM_CE, | |
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371 | nSRAM_CE => SRAM_CE_s, | |
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368 | 372 | nSRAM_OE => SRAM_nOE, |
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369 | ||
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373 | nSRAM_READY => '0', | |
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374 | SRAM_MBE => OPEN, | |
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370 | 375 | apbi_ext => apbi_ext, |
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371 | 376 | apbo_ext => apbo_ext, |
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372 | 377 | ahbi_s_ext => ahbi_s_ext, |
@@ -374,6 +379,7 BEGIN -- beh | |||
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374 | 379 | ahbi_m_ext => ahbi_m_ext, |
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375 | 380 | ahbo_m_ext => ahbo_m_ext); |
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376 | 381 | |
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382 | SRAM_CE <= SRAM_CE_s(0); | |
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377 | 383 | ------------------------------------------------------------------------------- |
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378 | 384 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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379 | 385 | ------------------------------------------------------------------------------- |
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