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Preliminary working IAP Memctrlr integration....
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r481:bddfa2e2e0fe JC
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@@ -2,8 +2,8
2 # Generated file
2 # Generated file
3
3
4 # Version: 9.1 SP3 9.1.3.4
4 # Version: 9.1 SP3 9.1.3.4
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
5 # Family: ProASIC3E , Die: A3PE3000 , Package: 324 FBGA
6 # Date generated: Tue Oct 18 08:21:45 2011
6 # Date generated: Tue Dec 23 19:40:04 2014
7
7
8
8
9 #
9 #
@@ -15,73 +15,415
15 # I/O constraints
15 # I/O constraints
16 #
16 #
17
17
18 set_io clk_50 \
18 #set_io BP0 \
19 -pinname F7 \
19 # -pinname J12 \
20 -fixed yes \
20 # -fixed yes \
21 -DIRECTION Inout
21 # -DIRECTION Inout
22
22
23 set_io clk_49 \
24 -pinname F8 \
25 -fixed yes \
26 -DIRECTION Inout
27
23
28 set_io reset \
24 #set_io BP1 \
29 -pinname J12 \
25 # -pinname F13 \
30 -fixed yes \
26 # -fixed yes \
31 -DIRECTION Inout
27 # -DIRECTION Inout
32 #====================================================================
33 # BPs
34 #====================================================================
35 set_io BP0 \
36 -pinname F16 \
37 -fixed yes \
38 -DIRECTION Inout
39
28
40 set_io BP1 \
41 -pinname F13 \
42 -fixed yes \
43 -DIRECTION Inout
44
45 #====================================================================
46 # LEDs
47 #====================================================================
48
29
49 set_io LED0 \
30 set_io LED0 \
50 -pinname R13 \
31 -pinname R13 \
51 -fixed yes \
32 -fixed yes \
52 -DIRECTION Inout
33 -DIRECTION Inout
53
34
35
54 set_io LED1 \
36 set_io LED1 \
55 -pinname P13 \
37 -pinname P13 \
56 -fixed yes \
38 -fixed yes \
57 -DIRECTION Inout
39 -DIRECTION Inout
58
40
41
59 set_io LED2 \
42 set_io LED2 \
60 -pinname N11 \
43 -pinname N11 \
61 -fixed yes \
44 -fixed yes \
62 -DIRECTION Inout
45 -DIRECTION Inout
63
46
64 #====================================================================
65 # UARTS
66 #====================================================================
67
68 set_io TXD1 \
69 -pinname N12 \
70 -fixed yes \
71 -DIRECTION Inout
72
47
73 set_io RXD1 \
48 set_io RXD1 \
74 -pinname N10 \
49 -pinname N10 \
75 -fixed yes \
50 -fixed yes \
76 -DIRECTION Inout
51 -DIRECTION Inout
77
52
78 set_io nCTS1 \
53
79 -pinname L13 \
54 set_io RXD2 \
55 -pinname F6 \
56 -fixed yes \
57 -DIRECTION Inout
58
59
60 set_io {SRAM_A[0]} \
61 -pinname T12 \
62 -fixed yes \
63 -DIRECTION Inout \
64 -register yes
65
66
67 set_io {SRAM_A[1]} \
68 -pinname U13 \
69 -fixed yes \
70 -DIRECTION Inout \
71 -register yes
72
73
74 set_io {SRAM_A[2]} \
75 -pinname T13 \
76 -fixed yes \
77 -DIRECTION Inout \
78 -register yes
79
80
81 set_io {SRAM_A[3]} \
82 -pinname N15 \
83 -fixed yes \
84 -DIRECTION Inout \
85 -register yes
86
87
88 set_io {SRAM_A[4]} \
89 -pinname P17 \
90 -fixed yes \
91 -DIRECTION Inout \
92 -register yes
93
94
95 set_io {SRAM_A[5]} \
96 -pinname N13 \
97 -fixed yes \
98 -DIRECTION Inout \
99 -register yes
100
101
102 set_io {SRAM_A[6]} \
103 -pinname M16 \
104 -fixed yes \
105 -DIRECTION Inout \
106 -register yes
107
108
109 set_io {SRAM_A[7]} \
110 -pinname M13 \
111 -fixed yes \
112 -DIRECTION Inout \
113 -register yes
114
115
116 set_io {SRAM_A[8]} \
117 -pinname U12 \
118 -fixed yes \
119 -DIRECTION Inout \
120 -register yes
121
122
123 set_io {SRAM_A[9]} \
124 -pinname V11 \
125 -fixed yes \
126 -DIRECTION Inout \
127 -register yes
128
129
130 set_io {SRAM_A[10]} \
131 -pinname V13 \
132 -fixed yes \
133 -DIRECTION Inout \
134 -register yes
135
136
137 set_io {SRAM_A[11]} \
138 -pinname V14 \
139 -fixed yes \
140 -DIRECTION Inout \
141 -register yes
142
143
144 set_io {SRAM_A[12]} \
145 -pinname V15 \
146 -fixed yes \
147 -DIRECTION Inout \
148 -register yes
149
150
151 set_io {SRAM_A[13]} \
152 -pinname P16 \
153 -fixed yes \
154 -DIRECTION Inout \
155 -register yes
156
157
158 set_io {SRAM_A[14]} \
159 -pinname N16 \
160 -fixed yes \
161 -DIRECTION Inout \
162 -register yes
163
164
165 set_io {SRAM_A[15]} \
166 -pinname V16 \
167 -fixed yes \
168 -DIRECTION Inout \
169 -register yes
170
171
172 set_io {SRAM_A[16]} \
173 -pinname V17 \
174 -fixed yes \
175 -DIRECTION Inout \
176 -register yes
177
178
179 set_io {SRAM_A[17]} \
180 -pinname U18 \
181 -fixed yes \
182 -DIRECTION Inout \
183 -register yes
184
185
186 set_io {SRAM_A[18]} \
187 -pinname R18 \
188 -fixed yes \
189 -DIRECTION Inout \
190 -register yes
191
192
193 set_io {SRAM_DQ[0]} \
194 -pinname T18 \
195 -fixed yes \
196 -DIRECTION Inout
197
198
199 set_io {SRAM_DQ[1]} \
200 -pinname L15 \
201 -fixed yes \
202 -DIRECTION Inout
203
204
205 set_io {SRAM_DQ[2]} \
206 -pinname K18 \
207 -fixed yes \
208 -DIRECTION Inout
209
210
211 set_io {SRAM_DQ[3]} \
212 -pinname G17 \
213 -fixed yes \
214 -DIRECTION Inout
215
216
217 set_io {SRAM_DQ[4]} \
218 -pinname K17 \
219 -fixed yes \
220 -DIRECTION Inout
221
222
223 set_io {SRAM_DQ[5]} \
224 -pinname H18 \
225 -fixed yes \
226 -DIRECTION Inout
227
228
229 set_io {SRAM_DQ[6]} \
230 -pinname L18 \
231 -fixed yes \
232 -DIRECTION Inout
233
234
235 set_io {SRAM_DQ[7]} \
236 -pinname J18 \
80 -fixed yes \
237 -fixed yes \
81 -DIRECTION Inout
238 -DIRECTION Inout
82
239
83 set_io nRTS1 \
240
84 -pinname M9 \
241 set_io {SRAM_DQ[8]} \
242 -pinname M17 \
243 -fixed yes \
244 -DIRECTION Inout
245
246
247 set_io {SRAM_DQ[9]} \
248 -pinname J17 \
249 -fixed yes \
250 -DIRECTION Inout
251
252
253 set_io {SRAM_DQ[10]} \
254 -pinname N18 \
255 -fixed yes \
256 -DIRECTION Inout
257
258
259 set_io {SRAM_DQ[11]} \
260 -pinname J13 \
261 -fixed yes \
262 -DIRECTION Inout
263
264
265 set_io {SRAM_DQ[12]} \
266 -pinname N17 \
267 -fixed yes \
268 -DIRECTION Inout
269
270
271 set_io {SRAM_DQ[13]} \
272 -pinname K13 \
273 -fixed yes \
274 -DIRECTION Inout
275
276
277 set_io {SRAM_DQ[14]} \
278 -pinname P18 \
279 -fixed yes \
280 -DIRECTION Inout
281
282
283 set_io {SRAM_DQ[15]} \
284 -pinname K14 \
285 -fixed yes \
286 -DIRECTION Inout
287
288
289 set_io {SRAM_DQ[16]} \
290 -pinname K15 \
291 -fixed yes \
292 -DIRECTION Inout
293
294
295 set_io {SRAM_DQ[17]} \
296 -pinname B18 \
297 -fixed yes \
298 -DIRECTION Inout
299
300
301 set_io {SRAM_DQ[18]} \
302 -pinname D16 \
303 -fixed yes \
304 -DIRECTION Inout
305
306
307 set_io {SRAM_DQ[19]} \
308 -pinname D15 \
309 -fixed yes \
310 -DIRECTION Inout
311
312
313 set_io {SRAM_DQ[20]} \
314 -pinname C18 \
315 -fixed yes \
316 -DIRECTION Inout
317
318
319 set_io {SRAM_DQ[21]} \
320 -pinname E15 \
321 -fixed yes \
322 -DIRECTION Inout
323
324
325 set_io {SRAM_DQ[22]} \
326 -pinname D18 \
327 -fixed yes \
328 -DIRECTION Inout
329
330
331 set_io {SRAM_DQ[23]} \
332 -pinname F15 \
333 -fixed yes \
334 -DIRECTION Inout
335
336
337 set_io {SRAM_DQ[24]} \
338 -pinname E18 \
339 -fixed yes \
340 -DIRECTION Inout
341
342
343 set_io {SRAM_DQ[25]} \
344 -pinname G15 \
345 -fixed yes \
346 -DIRECTION Inout
347
348
349 set_io {SRAM_DQ[26]} \
350 -pinname F17 \
351 -fixed yes \
352 -DIRECTION Inout
353
354
355 set_io {SRAM_DQ[27]} \
356 -pinname H15 \
357 -fixed yes \
358 -DIRECTION Inout
359
360
361 set_io {SRAM_DQ[28]} \
362 -pinname F18 \
363 -fixed yes \
364 -DIRECTION Inout
365
366
367 set_io {SRAM_DQ[29]} \
368 -pinname J15 \
369 -fixed yes \
370 -DIRECTION Inout
371
372
373 set_io {SRAM_DQ[30]} \
374 -pinname D11 \
375 -fixed yes \
376 -DIRECTION Inout
377
378
379 set_io {SRAM_DQ[31]} \
380 -pinname C16 \
381 -fixed yes \
382 -DIRECTION Inout
383
384
385 set_io SRAM_MBE \
386 -pinname D13 \
387 -fixed yes \
388 -DIRECTION Inout
389
390
391 set_io SRAM_nBUSY \
392 -pinname D12 \
393 -fixed yes \
394 -DIRECTION Inout
395
396
397 set_io SRAM_nCE1 \
398 -pinname C17 \
399 -fixed yes \
400 -DIRECTION Inout \
401 -register yes
402
403
404 set_io SRAM_nCE2 \
405 -pinname B17 \
406 -fixed yes \
407 -DIRECTION Inout \
408 -register yes
409
410
411 set_io SRAM_nOE \
412 -pinname J14 \
413 -fixed yes \
414 -DIRECTION Inout \
415 -register yes
416
417
418 set_io SRAM_nWE \
419 -pinname B16 \
420 -fixed yes \
421 -DIRECTION Inout \
422 -register yes
423
424
425 set_io TXD1 \
426 -pinname N12 \
85 -fixed yes \
427 -fixed yes \
86 -DIRECTION Inout
428 -DIRECTION Inout
87
429
@@ -91,346 +433,116 set_io TXD2 \
91 -fixed yes \
433 -fixed yes \
92 -DIRECTION Inout
434 -DIRECTION Inout
93
435
94 set_io RXD2 \
436
95 -pinname F6 \
437 #set_io clk_49 \
96 -fixed yes \
438 # -pinname F8 \
97 -DIRECTION Inout
439 # -fixed yes \
440 # -DIRECTION Inout
98
441
99
442
100 #====================================================================
443 set_io clk_50 \
101 # SRAM
444 -pinname F7 \
102 #====================================================================
103
104 #================================
105 # SRAM CTRL
106 #================================
107
108 set_io SRAM_nWE \
109 -pinname B16 \
110 -fixed yes \
111 -DIRECTION Inout
112
113 set_io SRAM_nCE1 \
114 -pinname C17 \
115 -fixed yes \
116 -DIRECTION Inout
117
118 set_io SRAM_nCE2 \
119 -pinname B17 \
120 -fixed yes \
121 -DIRECTION Inout
122
123 set_io SRAM_nOE \
124 -pinname J14 \
125 -fixed yes \
126 -DIRECTION Inout
127
128 set_io SRAM_MBE \
129 -pinname D13 \
130 -fixed yes \
131 -DIRECTION Inout
132
133 set_io SRAM_nSCRUB \
134 -pinname E13 \
135 -fixed yes \
136 -DIRECTION Inout
137
138 set_io SRAM_nBUSY \
139 -pinname D12 \
140 -fixed yes \
445 -fixed yes \
141 -DIRECTION Inout
446 -DIRECTION Inout
142
447
143
448
144
449 set_io nCTS1 \
145
450 -pinname L13 \
146 #================================
147 # SRAM ADDRESS
148 #================================
149
150 set_io SRAM_A\[0\] \
151 -pinname T12 \
152 -fixed yes \
153 -DIRECTION Inout
154
155 set_io SRAM_A\[1\] \
156 -pinname U13 \
157 -fixed yes \
158 -DIRECTION Inout
159
160 set_io SRAM_A\[2\] \
161 -pinname T13 \
162 -fixed yes \
163 -DIRECTION Inout
164
165 set_io SRAM_A\[3\] \
166 -pinname N15 \
167 -fixed yes \
168 -DIRECTION Inout
169
170 set_io SRAM_A\[4\] \
171 -pinname P17 \
172 -fixed yes \
173 -DIRECTION Inout
174
175 set_io SRAM_A\[5\] \
176 -pinname N13 \
177 -fixed yes \
178 -DIRECTION Inout
179
180 set_io SRAM_A\[6\] \
181 -pinname M16 \
182 -fixed yes \
183 -DIRECTION Inout
184
185 set_io SRAM_A\[7\] \
186 -pinname M13 \
187 -fixed yes \
451 -fixed yes \
188 -DIRECTION Inout
452 -DIRECTION Inout
189
453
190 set_io SRAM_A\[8\] \
191 -pinname U12 \
192 -fixed yes \
193 -DIRECTION Inout
194
195 set_io SRAM_A\[9\] \
196 -pinname V11 \
197 -fixed yes \
198 -DIRECTION Inout
199
200 set_io SRAM_A\[10\] \
201 -pinname V13 \
202 -fixed yes \
203 -DIRECTION Inout
204
205 set_io SRAM_A\[11\] \
206 -pinname V14 \
207 -fixed yes \
208 -DIRECTION Inout
209
210 set_io SRAM_A\[12\] \
211 -pinname V15 \
212 -fixed yes \
213 -DIRECTION Inout
214
454
215 set_io SRAM_A\[13\] \
455 #set_io nRTS1 \
216 -pinname P16 \
456 # -pinname M9 \
217 -fixed yes \
457 # -fixed yes \
218 -DIRECTION Inout
458 # -DIRECTION Inout
219
220 set_io SRAM_A\[14\] \
221 -pinname N16 \
222 -fixed yes \
223 -DIRECTION Inout
224
459
225 set_io SRAM_A\[15\] \
226 -pinname V16 \
227 -fixed yes \
228 -DIRECTION Inout
229
460
230 set_io SRAM_A\[16\] \
461 set_io reset \
231 -pinname V17 \
462 -pinname F16 \
232 -fixed yes \
233 -DIRECTION Inout
234
235 set_io SRAM_A\[17\] \
236 -pinname U18 \
237 -fixed yes \
238 -DIRECTION Inout
239
240 set_io SRAM_A\[18\] \
241 -pinname R18 \
242 -fixed yes \
463 -fixed yes \
243 -DIRECTION Inout
464 -DIRECTION Inout
244
465
245
466
246
467
247 #================================
468 #
248 # SRAM DATA
469 # Non IO constraints
249 #================================
470 #
250
251 set_io SRAM_DQ\[0\] \
252 -pinname T18 \
253 -fixed yes \
254 -DIRECTION Inout
255
256 set_io SRAM_DQ\[1\] \
257 -pinname L15 \
258 -fixed yes \
259 -DIRECTION Inout
260
261 set_io SRAM_DQ\[2\] \
262 -pinname K18 \
263 -fixed yes \
264 -DIRECTION Inout
265
266 set_io SRAM_DQ\[3\] \
267 -pinname G17 \
268 -fixed yes \
269 -DIRECTION Inout
270
271 set_io SRAM_DQ\[4\] \
272 -pinname K17 \
273 -fixed yes \
274 -DIRECTION Inout
275
276 set_io SRAM_DQ\[5\] \
277 -pinname H18 \
278 -fixed yes \
279 -DIRECTION Inout
280
281 set_io SRAM_DQ\[6\] \
282 -pinname L18 \
283 -fixed yes \
284 -DIRECTION Inout
285
286 set_io SRAM_DQ\[7\] \
287 -pinname J18 \
288 -fixed yes \
289 -DIRECTION Inout
290
291 set_io SRAM_DQ\[8\] \
292 -pinname M17 \
293 -fixed yes \
294 -DIRECTION Inout
295
296 set_io SRAM_DQ\[9\] \
297 -pinname J17 \
298 -fixed yes \
299 -DIRECTION Inout
300
301 set_io SRAM_DQ\[10\] \
302 -pinname N18 \
303 -fixed yes \
304 -DIRECTION Inout
305
306 set_io SRAM_DQ\[11\] \
307 -pinname J13 \
308 -fixed yes \
309 -DIRECTION Inout
310
311 set_io SRAM_DQ\[12\] \
312 -pinname N17 \
313 -fixed yes \
314 -DIRECTION Inout
315
316 set_io SRAM_DQ\[13\] \
317 -pinname K13 \
318 -fixed yes \
319 -DIRECTION Inout
320
321 set_io SRAM_DQ\[14\] \
322 -pinname P18 \
323 -fixed yes \
324 -DIRECTION Inout
325
326 set_io SRAM_DQ\[15\] \
327 -pinname K14 \
328 -fixed yes \
329 -DIRECTION Inout
330
331 set_io SRAM_DQ\[16\] \
332 -pinname K15 \
333 -fixed yes \
334 -DIRECTION Inout
335
336 set_io SRAM_DQ\[17\] \
337 -pinname B18 \
338 -fixed yes \
339 -DIRECTION Inout
340
341 set_io SRAM_DQ\[18\] \
342 -pinname D16 \
343 -fixed yes \
344 -DIRECTION Inout
345
346 set_io SRAM_DQ\[19\] \
347 -pinname D15 \
348 -fixed yes \
349 -DIRECTION Inout
350
351 set_io SRAM_DQ\[20\] \
352 -pinname C18 \
353 -fixed yes \
354 -DIRECTION Inout
355
356 set_io SRAM_DQ\[21\] \
357 -pinname E15 \
358 -fixed yes \
359 -DIRECTION Inout
360
361 set_io SRAM_DQ\[22\] \
362 -pinname D18 \
363 -fixed yes \
364 -DIRECTION Inout
365
366 set_io SRAM_DQ\[23\] \
367 -pinname F15 \
368 -fixed yes \
369 -DIRECTION Inout
370
371 set_io SRAM_DQ\[24\] \
372 -pinname E18 \
373 -fixed yes \
374 -DIRECTION Inout
375
376 set_io SRAM_DQ\[25\] \
377 -pinname G15 \
378 -fixed yes \
379 -DIRECTION Inout
380
381 set_io SRAM_DQ\[26\] \
382 -pinname F17 \
383 -fixed yes \
384 -DIRECTION Inout
385
386 set_io SRAM_DQ\[27\] \
387 -pinname H15 \
388 -fixed yes \
389 -DIRECTION Inout
390
391 set_io SRAM_DQ\[28\] \
392 -pinname F18 \
393 -fixed yes \
394 -DIRECTION Inout
395
396 set_io SRAM_DQ\[29\] \
397 -pinname J15 \
398 -fixed yes \
399 -DIRECTION Inout
400
401 set_io SRAM_DQ\[30\] \
402 -pinname D11 \
403 -fixed yes \
404 -DIRECTION Inout
405
406 set_io SRAM_DQ\[31\] \
407 -pinname C16 \
408 -fixed yes \
409 -DIRECTION Inout
410
471
411
472
412
473 #
413
474 # Old IO constraints, commented out for reference
414
475 #
415
416
417
418
419
420
421
422
423
424
476
425
477 # set_io BP0 -pinname J12 -fixed yes -DIRECTION Inout
426
478 # set_io BP1 -pinname F13 -fixed yes -DIRECTION Inout
427
479 # set_io LED0 -pinname R13 -fixed yes -DIRECTION Inout
428
480 # set_io LED1 -pinname P13 -fixed yes -DIRECTION Inout
429
481 # set_io LED2 -pinname N11 -fixed yes -DIRECTION Inout
430
482 # set_io RXD1 -pinname N10 -fixed yes -DIRECTION Inout
431
483 # set_io RXD2 -pinname F6 -fixed yes -DIRECTION Inout
432
484 # set_io {SRAM_A[0]} -pinname T12 -fixed yes -DIRECTION Inout
433
485 # set_io {SRAM_A[1]} -pinname U13 -fixed yes -DIRECTION Inout
434
486 # set_io {SRAM_A[2]} -pinname T13 -fixed yes -DIRECTION Inout
435
487 # set_io {SRAM_A[3]} -pinname N15 -fixed yes -DIRECTION Inout
436
488 # set_io {SRAM_A[4]} -pinname P17 -fixed yes -DIRECTION Inout
489 # set_io {SRAM_A[5]} -pinname N13 -fixed yes -DIRECTION Inout
490 # set_io {SRAM_A[6]} -pinname M16 -fixed yes -DIRECTION Inout
491 # set_io {SRAM_A[7]} -pinname M13 -fixed yes -DIRECTION Inout
492 # set_io {SRAM_A[8]} -pinname U12 -fixed yes -DIRECTION Inout
493 # set_io {SRAM_A[9]} -pinname V11 -fixed yes -DIRECTION Inout
494 # set_io {SRAM_A[10]} -pinname V13 -fixed yes -DIRECTION Inout
495 # set_io {SRAM_A[11]} -pinname V14 -fixed yes -DIRECTION Inout
496 # set_io {SRAM_A[12]} -pinname V15 -fixed yes -DIRECTION Inout
497 # set_io {SRAM_A[13]} -pinname P16 -fixed yes -DIRECTION Inout
498 # set_io {SRAM_A[14]} -pinname N16 -fixed yes -DIRECTION Inout
499 # set_io {SRAM_A[15]} -pinname V16 -fixed yes -DIRECTION Inout
500 # set_io {SRAM_A[16]} -pinname V17 -fixed yes -DIRECTION Inout
501 # set_io {SRAM_A[17]} -pinname U18 -fixed yes -DIRECTION Inout
502 # set_io {SRAM_A[18]} -pinname R18 -fixed yes -DIRECTION Inout
503 # set_io {SRAM_DQ[0]} -pinname T18 -fixed yes -DIRECTION Inout
504 # set_io {SRAM_DQ[1]} -pinname L15 -fixed yes -DIRECTION Inout
505 # set_io {SRAM_DQ[2]} -pinname K18 -fixed yes -DIRECTION Inout
506 # set_io {SRAM_DQ[3]} -pinname G17 -fixed yes -DIRECTION Inout
507 # set_io {SRAM_DQ[4]} -pinname K17 -fixed yes -DIRECTION Inout
508 # set_io {SRAM_DQ[5]} -pinname H18 -fixed yes -DIRECTION Inout
509 # set_io {SRAM_DQ[6]} -pinname L18 -fixed yes -DIRECTION Inout
510 # set_io {SRAM_DQ[7]} -pinname J18 -fixed yes -DIRECTION Inout
511 # set_io {SRAM_DQ[8]} -pinname M17 -fixed yes -DIRECTION Inout
512 # set_io {SRAM_DQ[9]} -pinname J17 -fixed yes -DIRECTION Inout
513 # set_io {SRAM_DQ[10]} -pinname N18 -fixed yes -DIRECTION Inout
514 # set_io {SRAM_DQ[11]} -pinname J13 -fixed yes -DIRECTION Inout
515 # set_io {SRAM_DQ[12]} -pinname N17 -fixed yes -DIRECTION Inout
516 # set_io {SRAM_DQ[13]} -pinname K13 -fixed yes -DIRECTION Inout
517 # set_io {SRAM_DQ[14]} -pinname P18 -fixed yes -DIRECTION Inout
518 # set_io {SRAM_DQ[15]} -pinname K14 -fixed yes -DIRECTION Inout
519 # set_io {SRAM_DQ[16]} -pinname K15 -fixed yes -DIRECTION Inout
520 # set_io {SRAM_DQ[17]} -pinname B18 -fixed yes -DIRECTION Inout
521 # set_io {SRAM_DQ[18]} -pinname D16 -fixed yes -DIRECTION Inout
522 # set_io {SRAM_DQ[19]} -pinname D15 -fixed yes -DIRECTION Inout
523 # set_io {SRAM_DQ[20]} -pinname C18 -fixed yes -DIRECTION Inout
524 # set_io {SRAM_DQ[21]} -pinname E15 -fixed yes -DIRECTION Inout
525 # set_io {SRAM_DQ[22]} -pinname D18 -fixed yes -DIRECTION Inout
526 # set_io {SRAM_DQ[23]} -pinname F15 -fixed yes -DIRECTION Inout
527 # set_io {SRAM_DQ[24]} -pinname E18 -fixed yes -DIRECTION Inout
528 # set_io {SRAM_DQ[25]} -pinname G15 -fixed yes -DIRECTION Inout
529 # set_io {SRAM_DQ[26]} -pinname F17 -fixed yes -DIRECTION Inout
530 # set_io {SRAM_DQ[27]} -pinname H15 -fixed yes -DIRECTION Inout
531 # set_io {SRAM_DQ[28]} -pinname F18 -fixed yes -DIRECTION Inout
532 # set_io {SRAM_DQ[29]} -pinname J15 -fixed yes -DIRECTION Inout
533 # set_io {SRAM_DQ[30]} -pinname D11 -fixed yes -DIRECTION Inout
534 # set_io {SRAM_DQ[31]} -pinname C16 -fixed yes -DIRECTION Inout
535 # set_io SRAM_MBE -pinname D13 -fixed yes -DIRECTION Inout
536 # set_io SRAM_nBUSY -pinname D12 -fixed yes -DIRECTION Inout
537 # set_io SRAM_nCE1 -pinname C17 -fixed yes -DIRECTION Inout
538 # set_io SRAM_nCE2 -pinname B17 -fixed yes -DIRECTION Inout
539 # set_io SRAM_nOE -pinname J14 -fixed yes -DIRECTION Inout
540 # set_io SRAM_nSCRUB -pinname E13 -fixed yes -DIRECTION Inout
541 # set_io SRAM_nWE -pinname B16 -fixed yes -DIRECTION Inout
542 # set_io TXD1 -pinname N12 -fixed yes -DIRECTION Inout
543 # set_io TXD2 -pinname G6 -fixed yes -DIRECTION Inout
544 # set_io clk_49 -pinname F8 -fixed yes -DIRECTION Inout
545 # set_io clk_50 -pinname F7 -fixed yes -DIRECTION Inout
546 # set_io nCTS1 -pinname L13 -fixed yes -DIRECTION Inout
547 # set_io nRTS1 -pinname M9 -fixed yes -DIRECTION Inout
548 # set_io reset -pinname F16 -fixed yes -DIRECTION Inout
Show file before | Show file after | Hide comments
@@ -41,6 +41,9 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
44 LIBRARY iap;
45 USE iap.memctrl.all;
46
44
47
45 ENTITY leon3_soc IS
48 ENTITY leon3_soc IS
46 GENERIC (
49 GENERIC (
@@ -67,7 +70,9 ENTITY leon3_soc IS
67 NB_AHB_SLAVE : INTEGER := 0;
70 NB_AHB_SLAVE : INTEGER := 0;
68 NB_APB_SLAVE : INTEGER := 0;
71 NB_APB_SLAVE : INTEGER := 0;
69 --
72 --
70 ADDRESS_SIZE : INTEGER := 20
73 ADDRESS_SIZE : INTEGER := 20;
74 USES_IAP_MEMCTRLR : INTEGER := 0
75
71 );
76 );
72 PORT (
77 PORT (
73 clk : IN STD_ULOGIC;
78 clk : IN STD_ULOGIC;
@@ -91,9 +96,10 ENTITY leon3_soc IS
91 nSRAM_BE2 : OUT STD_LOGIC;
96 nSRAM_BE2 : OUT STD_LOGIC;
92 nSRAM_BE3 : OUT STD_LOGIC;
97 nSRAM_BE3 : OUT STD_LOGIC;
93 nSRAM_WE : OUT STD_LOGIC;
98 nSRAM_WE : OUT STD_LOGIC;
94 nSRAM_CE : OUT STD_LOGIC;
99 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
95 nSRAM_OE : OUT STD_LOGIC;
100 nSRAM_OE : OUT STD_LOGIC;
96
101 nSRAM_READY : IN STD_LOGIC;
102 SRAM_MBE : INOUT STD_LOGIC;
97 -- APB --------------------------------------------------------------------
103 -- APB --------------------------------------------------------------------
98 apbi_ext : OUT apb_slv_in_type;
104 apbi_ext : OUT apb_slv_in_type;
99 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
105 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
@@ -225,6 +231,9 ARCHITECTURE Behavioral OF leon3_soc IS
225 SIGNAL memo : memory_out_type;
231 SIGNAL memo : memory_out_type;
226 SIGNAL wpo : wprot_out_type;
232 SIGNAL wpo : wprot_out_type;
227 SIGNAL sdo : sdram_out_type;
233 SIGNAL sdo : sdram_out_type;
234 SIGNAl mbe : std_logic; -- enable memory programming
235 SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal
236 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0);
228 --IRQ
237 --IRQ
229 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
238 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
230 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
239 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
@@ -238,7 +247,7 ARCHITECTURE Behavioral OF leon3_soc IS
238 SIGNAL dsuo : dsu_out_type;
247 SIGNAL dsuo : dsu_out_type;
239 -----------------------------------------------------------------------------
248 -----------------------------------------------------------------------------
240
249
241 SIGNAL nSRAM_CE_s : STD_LOGIC;
250
242 BEGIN
251 BEGIN
243
252
244
253
@@ -305,6 +314,7 BEGIN
305 ----------------------------------------------------------------------
314 ----------------------------------------------------------------------
306 --- Memory controllers ---------------------------------------------
315 --- Memory controllers ---------------------------------------------
307 ----------------------------------------------------------------------
316 ----------------------------------------------------------------------
317 ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
308 memctrlr : mctrl GENERIC MAP (
318 memctrlr : mctrl GENERIC MAP (
309 hindex => 0,
319 hindex => 0,
310 pindex => 0,
320 pindex => 0,
@@ -312,15 +322,59 BEGIN
312 srbanks => 1
322 srbanks => 1
313 )
323 )
314 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
324 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
315
325 memi.bexcn <= '1';
316 memi.brdyn <= '1';
326 memi.brdyn <= '1';
317 memi.bexcn <= '1';
327 END GENERATE;
328
329 IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
330 memctrlr : srctrle_0ws
331 GENERIC MAP(
332 hindex => 0,
333 pindex => 0,
334 paddr => 0,
335 srbanks => 2,
336 banksz => 8, --512k * 32
337 rmw => 1,
338 --Aeroflex memory generics:
339 mprog => 1, -- program memory by default values after reset
340 mpsrate => 12, -- default scrub rate period
341 mpb2s => 4, -- default busy to scrub delay
342 mpapb => 1, -- instantiate apb register
343 mchipcnt => 2,
344 mpenall => 1 -- when 0 program only E1 chip, else program all dies
345 )
346 PORT MAP (
347 rst => rstn,
348 clk => clkm,
349 ahbsi => ahbsi,
350 ahbso => ahbso(0),
351 apbi => apbi,
352 apbo => apbo(0),
353 sri => memi,
354 sro => memo,
355 --Aeroflex memory signals:
356 ucerr => open, -- uncorrectable error signal
357 mbe => mbe, -- enable memory programming
358 mbe_drive => mbe_drive -- drive the MBE memory signal
359 );
360
361 memi.brdyn <= nSRAM_READY;
362
363 mbe_pad : iopad
364 GENERIC MAP(tech => padtech)
365 PORT MAP(pad => SRAM_MBE,
366 i => mbe,
367 en => mbe_drive,
368 o => memi.bexcn );
369 END GENERATE;
370
371
318 memi.writen <= '1';
372 memi.writen <= '1';
319 memi.wrn <= "1111";
373 memi.wrn <= "1111";
320 memi.bwidth <= "10";
374 memi.bwidth <= "10";
321
375
322 bdr : FOR i IN 0 TO 3 GENERATE
376 bdr : FOR i IN 0 TO 3 GENERATE
323 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
377 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
324 PORT MAP (
378 PORT MAP (
325 data(31-i*8 DOWNTO 24-i*8),
379 data(31-i*8 DOWNTO 24-i*8),
326 memo.data(31-i*8 DOWNTO 24-i*8),
380 memo.data(31-i*8 DOWNTO 24-i*8),
@@ -330,15 +384,17 BEGIN
330
384
331 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
385 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
332 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
386 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
333 nSRAM_CE_s <= NOT(memo.ramsn(0));
387 nSRAM_CE_s <= (memo.ramsn(1 downto 0));
334 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
388 rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
335 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
389 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.oen);
336 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
390 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
337 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
391 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
338 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
392 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
339 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
393 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
340 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
394 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
341
395
396
397
342 ----------------------------------------------------------------------
398 ----------------------------------------------------------------------
343 --- AHB CONTROLLER -------------------------------------------------
399 --- AHB CONTROLLER -------------------------------------------------
344 ----------------------------------------------------------------------
400 ----------------------------------------------------------------------
@@ -425,4 +481,4 BEGIN
425
481
426
482
427
483
428 END Behavioral;
484 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -52,15 +52,24 PACKAGE lpp_leon3_soc_pkg IS
52 NB_AHB_MASTER : INTEGER;
52 NB_AHB_MASTER : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER;
55 ADDRESS_SIZE : INTEGER);
55 ADDRESS_SIZE : INTEGER;
56 USES_IAP_MEMCTRLR : INTEGER
57 );
56 PORT (
58 PORT (
57 clk : IN STD_ULOGIC;
59 clk : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
60 reset : IN STD_ULOGIC;
61
59 errorn : OUT STD_ULOGIC;
62 errorn : OUT STD_ULOGIC;
60 ahbrxd : IN STD_ULOGIC;
63
61 ahbtxd : OUT STD_ULOGIC;
64 -- UART AHB ---------------------------------------------------------------
62 urxd1 : IN STD_ULOGIC;
65 ahbrxd : IN STD_ULOGIC; -- DSU rx data
63 utxd1 : OUT STD_ULOGIC;
66 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
67
68 -- UART APB ---------------------------------------------------------------
69 urxd1 : IN STD_ULOGIC; -- UART1 rx data
70 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
71
72 -- RAM --------------------------------------------------------------------
64 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
73 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
65 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 nSRAM_BE0 : OUT STD_LOGIC;
75 nSRAM_BE0 : OUT STD_LOGIC;
@@ -68,12 +77,17 PACKAGE lpp_leon3_soc_pkg IS
68 nSRAM_BE2 : OUT STD_LOGIC;
77 nSRAM_BE2 : OUT STD_LOGIC;
69 nSRAM_BE3 : OUT STD_LOGIC;
78 nSRAM_BE3 : OUT STD_LOGIC;
70 nSRAM_WE : OUT STD_LOGIC;
79 nSRAM_WE : OUT STD_LOGIC;
71 nSRAM_CE : OUT STD_LOGIC;
80 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
72 nSRAM_OE : OUT STD_LOGIC;
81 nSRAM_OE : OUT STD_LOGIC;
82 nSRAM_READY : IN STD_LOGIC;
83 SRAM_MBE : INOUT STD_LOGIC;
84 -- APB --------------------------------------------------------------------
73 apbi_ext : OUT apb_slv_in_type;
85 apbi_ext : OUT apb_slv_in_type;
74 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
86 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
87 -- AHB_Slave --------------------------------------------------------------
75 ahbi_s_ext : OUT ahb_slv_in_type;
88 ahbi_s_ext : OUT ahb_slv_in_type;
76 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
89 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
90 -- AHB_Master -------------------------------------------------------------
77 ahbi_m_ext : OUT AHB_Mst_In_Type;
91 ahbi_m_ext : OUT AHB_Mst_In_Type;
78 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
92 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
79 END COMPONENT;
93 END COMPONENT;
@@ -125,4 +139,4 PACKAGE lpp_leon3_soc_pkg IS
125 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
139 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
126 END COMPONENT;
140 END COMPONENT;
127
141
128 END;
142 END; No newline at end of file
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