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Preliminary working IAP Memctrlr integration....
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1 # Actel Physical design constraints file
1 # Actel Physical design constraints file
2 # Generated file
2 # Generated file
3
3
4 # Version: 9.1 SP3 9.1.3.4
4 # Version: 9.1 SP3 9.1.3.4
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
5 # Family: ProASIC3E , Die: A3PE3000 , Package: 324 FBGA
6 # Date generated: Tue Oct 18 08:21:45 2011
6 # Date generated: Tue Dec 23 19:40:04 2014
7
7
8
8
9 #
9 #
10 # IO banks setting
10 # IO banks setting
11 #
11 #
12
12
13
13
14 #
14 #
15 # I/O constraints
15 # I/O constraints
16 #
16 #
17
17
18 set_io clk_50 \
18 #set_io BP0 \
19 -pinname F7 \
19 # -pinname J12 \
20 -fixed yes \
20 # -fixed yes \
21 -DIRECTION Inout
21 # -DIRECTION Inout
22
22
23 set_io clk_49 \
24 -pinname F8 \
25 -fixed yes \
26 -DIRECTION Inout
27
23
28 set_io reset \
24 #set_io BP1 \
29 -pinname J12 \
25 # -pinname F13 \
30 -fixed yes \
26 # -fixed yes \
31 -DIRECTION Inout
27 # -DIRECTION Inout
32 #====================================================================
33 # BPs
34 #====================================================================
35 set_io BP0 \
36 -pinname F16 \
37 -fixed yes \
38 -DIRECTION Inout
39
28
40 set_io BP1 \
41 -pinname F13 \
42 -fixed yes \
43 -DIRECTION Inout
44
45 #====================================================================
46 # LEDs
47 #====================================================================
48
29
49 set_io LED0 \
30 set_io LED0 \
50 -pinname R13 \
31 -pinname R13 \
51 -fixed yes \
32 -fixed yes \
52 -DIRECTION Inout
33 -DIRECTION Inout
53
34
35
54 set_io LED1 \
36 set_io LED1 \
55 -pinname P13 \
37 -pinname P13 \
56 -fixed yes \
38 -fixed yes \
57 -DIRECTION Inout
39 -DIRECTION Inout
58
40
41
59 set_io LED2 \
42 set_io LED2 \
60 -pinname N11 \
43 -pinname N11 \
61 -fixed yes \
44 -fixed yes \
62 -DIRECTION Inout
45 -DIRECTION Inout
63
46
64 #====================================================================
65 # UARTS
66 #====================================================================
67
68 set_io TXD1 \
69 -pinname N12 \
70 -fixed yes \
71 -DIRECTION Inout
72
47
73 set_io RXD1 \
48 set_io RXD1 \
74 -pinname N10 \
49 -pinname N10 \
75 -fixed yes \
50 -fixed yes \
76 -DIRECTION Inout
51 -DIRECTION Inout
77
52
78 set_io nCTS1 \
53
79 -pinname L13 \
54 set_io RXD2 \
55 -pinname F6 \
56 -fixed yes \
57 -DIRECTION Inout
58
59
60 set_io {SRAM_A[0]} \
61 -pinname T12 \
62 -fixed yes \
63 -DIRECTION Inout \
64 -register yes
65
66
67 set_io {SRAM_A[1]} \
68 -pinname U13 \
69 -fixed yes \
70 -DIRECTION Inout \
71 -register yes
72
73
74 set_io {SRAM_A[2]} \
75 -pinname T13 \
76 -fixed yes \
77 -DIRECTION Inout \
78 -register yes
79
80
81 set_io {SRAM_A[3]} \
82 -pinname N15 \
83 -fixed yes \
84 -DIRECTION Inout \
85 -register yes
86
87
88 set_io {SRAM_A[4]} \
89 -pinname P17 \
90 -fixed yes \
91 -DIRECTION Inout \
92 -register yes
93
94
95 set_io {SRAM_A[5]} \
96 -pinname N13 \
97 -fixed yes \
98 -DIRECTION Inout \
99 -register yes
100
101
102 set_io {SRAM_A[6]} \
103 -pinname M16 \
104 -fixed yes \
105 -DIRECTION Inout \
106 -register yes
107
108
109 set_io {SRAM_A[7]} \
110 -pinname M13 \
111 -fixed yes \
112 -DIRECTION Inout \
113 -register yes
114
115
116 set_io {SRAM_A[8]} \
117 -pinname U12 \
118 -fixed yes \
119 -DIRECTION Inout \
120 -register yes
121
122
123 set_io {SRAM_A[9]} \
124 -pinname V11 \
125 -fixed yes \
126 -DIRECTION Inout \
127 -register yes
128
129
130 set_io {SRAM_A[10]} \
131 -pinname V13 \
132 -fixed yes \
133 -DIRECTION Inout \
134 -register yes
135
136
137 set_io {SRAM_A[11]} \
138 -pinname V14 \
139 -fixed yes \
140 -DIRECTION Inout \
141 -register yes
142
143
144 set_io {SRAM_A[12]} \
145 -pinname V15 \
146 -fixed yes \
147 -DIRECTION Inout \
148 -register yes
149
150
151 set_io {SRAM_A[13]} \
152 -pinname P16 \
153 -fixed yes \
154 -DIRECTION Inout \
155 -register yes
156
157
158 set_io {SRAM_A[14]} \
159 -pinname N16 \
160 -fixed yes \
161 -DIRECTION Inout \
162 -register yes
163
164
165 set_io {SRAM_A[15]} \
166 -pinname V16 \
167 -fixed yes \
168 -DIRECTION Inout \
169 -register yes
170
171
172 set_io {SRAM_A[16]} \
173 -pinname V17 \
174 -fixed yes \
175 -DIRECTION Inout \
176 -register yes
177
178
179 set_io {SRAM_A[17]} \
180 -pinname U18 \
181 -fixed yes \
182 -DIRECTION Inout \
183 -register yes
184
185
186 set_io {SRAM_A[18]} \
187 -pinname R18 \
188 -fixed yes \
189 -DIRECTION Inout \
190 -register yes
191
192
193 set_io {SRAM_DQ[0]} \
194 -pinname T18 \
195 -fixed yes \
196 -DIRECTION Inout
197
198
199 set_io {SRAM_DQ[1]} \
200 -pinname L15 \
201 -fixed yes \
202 -DIRECTION Inout
203
204
205 set_io {SRAM_DQ[2]} \
206 -pinname K18 \
207 -fixed yes \
208 -DIRECTION Inout
209
210
211 set_io {SRAM_DQ[3]} \
212 -pinname G17 \
213 -fixed yes \
214 -DIRECTION Inout
215
216
217 set_io {SRAM_DQ[4]} \
218 -pinname K17 \
219 -fixed yes \
220 -DIRECTION Inout
221
222
223 set_io {SRAM_DQ[5]} \
224 -pinname H18 \
225 -fixed yes \
226 -DIRECTION Inout
227
228
229 set_io {SRAM_DQ[6]} \
230 -pinname L18 \
231 -fixed yes \
232 -DIRECTION Inout
233
234
235 set_io {SRAM_DQ[7]} \
236 -pinname J18 \
80 -fixed yes \
237 -fixed yes \
81 -DIRECTION Inout
238 -DIRECTION Inout
82
239
83 set_io nRTS1 \
240
84 -pinname M9 \
241 set_io {SRAM_DQ[8]} \
242 -pinname M17 \
243 -fixed yes \
244 -DIRECTION Inout
245
246
247 set_io {SRAM_DQ[9]} \
248 -pinname J17 \
249 -fixed yes \
250 -DIRECTION Inout
251
252
253 set_io {SRAM_DQ[10]} \
254 -pinname N18 \
255 -fixed yes \
256 -DIRECTION Inout
257
258
259 set_io {SRAM_DQ[11]} \
260 -pinname J13 \
261 -fixed yes \
262 -DIRECTION Inout
263
264
265 set_io {SRAM_DQ[12]} \
266 -pinname N17 \
267 -fixed yes \
268 -DIRECTION Inout
269
270
271 set_io {SRAM_DQ[13]} \
272 -pinname K13 \
273 -fixed yes \
274 -DIRECTION Inout
275
276
277 set_io {SRAM_DQ[14]} \
278 -pinname P18 \
279 -fixed yes \
280 -DIRECTION Inout
281
282
283 set_io {SRAM_DQ[15]} \
284 -pinname K14 \
285 -fixed yes \
286 -DIRECTION Inout
287
288
289 set_io {SRAM_DQ[16]} \
290 -pinname K15 \
291 -fixed yes \
292 -DIRECTION Inout
293
294
295 set_io {SRAM_DQ[17]} \
296 -pinname B18 \
297 -fixed yes \
298 -DIRECTION Inout
299
300
301 set_io {SRAM_DQ[18]} \
302 -pinname D16 \
303 -fixed yes \
304 -DIRECTION Inout
305
306
307 set_io {SRAM_DQ[19]} \
308 -pinname D15 \
309 -fixed yes \
310 -DIRECTION Inout
311
312
313 set_io {SRAM_DQ[20]} \
314 -pinname C18 \
315 -fixed yes \
316 -DIRECTION Inout
317
318
319 set_io {SRAM_DQ[21]} \
320 -pinname E15 \
321 -fixed yes \
322 -DIRECTION Inout
323
324
325 set_io {SRAM_DQ[22]} \
326 -pinname D18 \
327 -fixed yes \
328 -DIRECTION Inout
329
330
331 set_io {SRAM_DQ[23]} \
332 -pinname F15 \
333 -fixed yes \
334 -DIRECTION Inout
335
336
337 set_io {SRAM_DQ[24]} \
338 -pinname E18 \
339 -fixed yes \
340 -DIRECTION Inout
341
342
343 set_io {SRAM_DQ[25]} \
344 -pinname G15 \
345 -fixed yes \
346 -DIRECTION Inout
347
348
349 set_io {SRAM_DQ[26]} \
350 -pinname F17 \
351 -fixed yes \
352 -DIRECTION Inout
353
354
355 set_io {SRAM_DQ[27]} \
356 -pinname H15 \
357 -fixed yes \
358 -DIRECTION Inout
359
360
361 set_io {SRAM_DQ[28]} \
362 -pinname F18 \
363 -fixed yes \
364 -DIRECTION Inout
365
366
367 set_io {SRAM_DQ[29]} \
368 -pinname J15 \
369 -fixed yes \
370 -DIRECTION Inout
371
372
373 set_io {SRAM_DQ[30]} \
374 -pinname D11 \
375 -fixed yes \
376 -DIRECTION Inout
377
378
379 set_io {SRAM_DQ[31]} \
380 -pinname C16 \
381 -fixed yes \
382 -DIRECTION Inout
383
384
385 set_io SRAM_MBE \
386 -pinname D13 \
387 -fixed yes \
388 -DIRECTION Inout
389
390
391 set_io SRAM_nBUSY \
392 -pinname D12 \
393 -fixed yes \
394 -DIRECTION Inout
395
396
397 set_io SRAM_nCE1 \
398 -pinname C17 \
399 -fixed yes \
400 -DIRECTION Inout \
401 -register yes
402
403
404 set_io SRAM_nCE2 \
405 -pinname B17 \
406 -fixed yes \
407 -DIRECTION Inout \
408 -register yes
409
410
411 set_io SRAM_nOE \
412 -pinname J14 \
413 -fixed yes \
414 -DIRECTION Inout \
415 -register yes
416
417
418 set_io SRAM_nWE \
419 -pinname B16 \
420 -fixed yes \
421 -DIRECTION Inout \
422 -register yes
423
424
425 set_io TXD1 \
426 -pinname N12 \
85 -fixed yes \
427 -fixed yes \
86 -DIRECTION Inout
428 -DIRECTION Inout
87
429
88
430
89 set_io TXD2 \
431 set_io TXD2 \
90 -pinname G6 \
432 -pinname G6 \
433 -fixed yes \
434 -DIRECTION Inout
435
436
437 #set_io clk_49 \
438 # -pinname F8 \
439 # -fixed yes \
440 # -DIRECTION Inout
441
442
443 set_io clk_50 \
444 -pinname F7 \
91 -fixed yes \
445 -fixed yes \
92 -DIRECTION Inout
446 -DIRECTION Inout
93
447
94 set_io RXD2 \
448
95 -pinname F6 \
449 set_io nCTS1 \
450 -pinname L13 \
96 -fixed yes \
451 -fixed yes \
97 -DIRECTION Inout
452 -DIRECTION Inout
98
99
100 #====================================================================
101 # SRAM
102 #====================================================================
103
104 #================================
105 # SRAM CTRL
106 #================================
107
108 set_io SRAM_nWE \
109 -pinname B16 \
110 -fixed yes \
111 -DIRECTION Inout
112
113 set_io SRAM_nCE1 \
114 -pinname C17 \
115 -fixed yes \
116 -DIRECTION Inout
117
118 set_io SRAM_nCE2 \
119 -pinname B17 \
120 -fixed yes \
121 -DIRECTION Inout
122
123 set_io SRAM_nOE \
124 -pinname J14 \
125 -fixed yes \
126 -DIRECTION Inout
127
128 set_io SRAM_MBE \
129 -pinname D13 \
130 -fixed yes \
131 -DIRECTION Inout
132
133 set_io SRAM_nSCRUB \
134 -pinname E13 \
135 -fixed yes \
136 -DIRECTION Inout
137
138 set_io SRAM_nBUSY \
139 -pinname D12 \
140 -fixed yes \
141 -DIRECTION Inout
142
143
144
453
145
454
146 #================================
455 #set_io nRTS1 \
147 # SRAM ADDRESS
456 # -pinname M9 \
148 #================================
457 # -fixed yes \
458 # -DIRECTION Inout
149
459
150 set_io SRAM_A\[0\] \
151 -pinname T12 \
152 -fixed yes \
153 -DIRECTION Inout
154
155 set_io SRAM_A\[1\] \
156 -pinname U13 \
157 -fixed yes \
158 -DIRECTION Inout
159
160 set_io SRAM_A\[2\] \
161 -pinname T13 \
162 -fixed yes \
163 -DIRECTION Inout
164
165 set_io SRAM_A\[3\] \
166 -pinname N15 \
167 -fixed yes \
168 -DIRECTION Inout
169
170 set_io SRAM_A\[4\] \
171 -pinname P17 \
172 -fixed yes \
173 -DIRECTION Inout
174
175 set_io SRAM_A\[5\] \
176 -pinname N13 \
177 -fixed yes \
178 -DIRECTION Inout
179
180 set_io SRAM_A\[6\] \
181 -pinname M16 \
182 -fixed yes \
183 -DIRECTION Inout
184
185 set_io SRAM_A\[7\] \
186 -pinname M13 \
187 -fixed yes \
188 -DIRECTION Inout
189
190 set_io SRAM_A\[8\] \
191 -pinname U12 \
192 -fixed yes \
193 -DIRECTION Inout
194
195 set_io SRAM_A\[9\] \
196 -pinname V11 \
197 -fixed yes \
198 -DIRECTION Inout
199
200 set_io SRAM_A\[10\] \
201 -pinname V13 \
202 -fixed yes \
203 -DIRECTION Inout
204
205 set_io SRAM_A\[11\] \
206 -pinname V14 \
207 -fixed yes \
208 -DIRECTION Inout
209
210 set_io SRAM_A\[12\] \
211 -pinname V15 \
212 -fixed yes \
213 -DIRECTION Inout
214
215 set_io SRAM_A\[13\] \
216 -pinname P16 \
217 -fixed yes \
218 -DIRECTION Inout
219
220 set_io SRAM_A\[14\] \
221 -pinname N16 \
222 -fixed yes \
223 -DIRECTION Inout
224
460
225 set_io SRAM_A\[15\] \
461 set_io reset \
226 -pinname V16 \
462 -pinname F16 \
227 -fixed yes \
463 -fixed yes \
228 -DIRECTION Inout
464 -DIRECTION Inout
229
230 set_io SRAM_A\[16\] \
231 -pinname V17 \
232 -fixed yes \
233 -DIRECTION Inout
234
235 set_io SRAM_A\[17\] \
236 -pinname U18 \
237 -fixed yes \
238 -DIRECTION Inout
239
240 set_io SRAM_A\[18\] \
241 -pinname R18 \
242 -fixed yes \
243 -DIRECTION Inout
244
465
245
466
246
467
247 #================================
468 #
248 # SRAM DATA
469 # Non IO constraints
249 #================================
470 #
250
251 set_io SRAM_DQ\[0\] \
252 -pinname T18 \
253 -fixed yes \
254 -DIRECTION Inout
255
256 set_io SRAM_DQ\[1\] \
257 -pinname L15 \
258 -fixed yes \
259 -DIRECTION Inout
260
261 set_io SRAM_DQ\[2\] \
262 -pinname K18 \
263 -fixed yes \
264 -DIRECTION Inout
265
266 set_io SRAM_DQ\[3\] \
267 -pinname G17 \
268 -fixed yes \
269 -DIRECTION Inout
270
271 set_io SRAM_DQ\[4\] \
272 -pinname K17 \
273 -fixed yes \
274 -DIRECTION Inout
275
276 set_io SRAM_DQ\[5\] \
277 -pinname H18 \
278 -fixed yes \
279 -DIRECTION Inout
280
281 set_io SRAM_DQ\[6\] \
282 -pinname L18 \
283 -fixed yes \
284 -DIRECTION Inout
285
286 set_io SRAM_DQ\[7\] \
287 -pinname J18 \
288 -fixed yes \
289 -DIRECTION Inout
290
291 set_io SRAM_DQ\[8\] \
292 -pinname M17 \
293 -fixed yes \
294 -DIRECTION Inout
295
296 set_io SRAM_DQ\[9\] \
297 -pinname J17 \
298 -fixed yes \
299 -DIRECTION Inout
300
301 set_io SRAM_DQ\[10\] \
302 -pinname N18 \
303 -fixed yes \
304 -DIRECTION Inout
305
306 set_io SRAM_DQ\[11\] \
307 -pinname J13 \
308 -fixed yes \
309 -DIRECTION Inout
310
311 set_io SRAM_DQ\[12\] \
312 -pinname N17 \
313 -fixed yes \
314 -DIRECTION Inout
315
316 set_io SRAM_DQ\[13\] \
317 -pinname K13 \
318 -fixed yes \
319 -DIRECTION Inout
320
321 set_io SRAM_DQ\[14\] \
322 -pinname P18 \
323 -fixed yes \
324 -DIRECTION Inout
325
326 set_io SRAM_DQ\[15\] \
327 -pinname K14 \
328 -fixed yes \
329 -DIRECTION Inout
330
331 set_io SRAM_DQ\[16\] \
332 -pinname K15 \
333 -fixed yes \
334 -DIRECTION Inout
335
336 set_io SRAM_DQ\[17\] \
337 -pinname B18 \
338 -fixed yes \
339 -DIRECTION Inout
340
341 set_io SRAM_DQ\[18\] \
342 -pinname D16 \
343 -fixed yes \
344 -DIRECTION Inout
345
346 set_io SRAM_DQ\[19\] \
347 -pinname D15 \
348 -fixed yes \
349 -DIRECTION Inout
350
351 set_io SRAM_DQ\[20\] \
352 -pinname C18 \
353 -fixed yes \
354 -DIRECTION Inout
355
356 set_io SRAM_DQ\[21\] \
357 -pinname E15 \
358 -fixed yes \
359 -DIRECTION Inout
360
361 set_io SRAM_DQ\[22\] \
362 -pinname D18 \
363 -fixed yes \
364 -DIRECTION Inout
365
366 set_io SRAM_DQ\[23\] \
367 -pinname F15 \
368 -fixed yes \
369 -DIRECTION Inout
370
371 set_io SRAM_DQ\[24\] \
372 -pinname E18 \
373 -fixed yes \
374 -DIRECTION Inout
375
376 set_io SRAM_DQ\[25\] \
377 -pinname G15 \
378 -fixed yes \
379 -DIRECTION Inout
380
381 set_io SRAM_DQ\[26\] \
382 -pinname F17 \
383 -fixed yes \
384 -DIRECTION Inout
385
386 set_io SRAM_DQ\[27\] \
387 -pinname H15 \
388 -fixed yes \
389 -DIRECTION Inout
390
391 set_io SRAM_DQ\[28\] \
392 -pinname F18 \
393 -fixed yes \
394 -DIRECTION Inout
395
396 set_io SRAM_DQ\[29\] \
397 -pinname J15 \
398 -fixed yes \
399 -DIRECTION Inout
400
401 set_io SRAM_DQ\[30\] \
402 -pinname D11 \
403 -fixed yes \
404 -DIRECTION Inout
405
406 set_io SRAM_DQ\[31\] \
407 -pinname C16 \
408 -fixed yes \
409 -DIRECTION Inout
410
471
411
472
412
473 #
413
474 # Old IO constraints, commented out for reference
414
475 #
415
416
417
418
419
420
421
422
423
424
476
425
477 # set_io BP0 -pinname J12 -fixed yes -DIRECTION Inout
426
478 # set_io BP1 -pinname F13 -fixed yes -DIRECTION Inout
427
479 # set_io LED0 -pinname R13 -fixed yes -DIRECTION Inout
428
480 # set_io LED1 -pinname P13 -fixed yes -DIRECTION Inout
429
481 # set_io LED2 -pinname N11 -fixed yes -DIRECTION Inout
430
482 # set_io RXD1 -pinname N10 -fixed yes -DIRECTION Inout
431
483 # set_io RXD2 -pinname F6 -fixed yes -DIRECTION Inout
432
484 # set_io {SRAM_A[0]} -pinname T12 -fixed yes -DIRECTION Inout
433
485 # set_io {SRAM_A[1]} -pinname U13 -fixed yes -DIRECTION Inout
434
486 # set_io {SRAM_A[2]} -pinname T13 -fixed yes -DIRECTION Inout
435
487 # set_io {SRAM_A[3]} -pinname N15 -fixed yes -DIRECTION Inout
436
488 # set_io {SRAM_A[4]} -pinname P17 -fixed yes -DIRECTION Inout
489 # set_io {SRAM_A[5]} -pinname N13 -fixed yes -DIRECTION Inout
490 # set_io {SRAM_A[6]} -pinname M16 -fixed yes -DIRECTION Inout
491 # set_io {SRAM_A[7]} -pinname M13 -fixed yes -DIRECTION Inout
492 # set_io {SRAM_A[8]} -pinname U12 -fixed yes -DIRECTION Inout
493 # set_io {SRAM_A[9]} -pinname V11 -fixed yes -DIRECTION Inout
494 # set_io {SRAM_A[10]} -pinname V13 -fixed yes -DIRECTION Inout
495 # set_io {SRAM_A[11]} -pinname V14 -fixed yes -DIRECTION Inout
496 # set_io {SRAM_A[12]} -pinname V15 -fixed yes -DIRECTION Inout
497 # set_io {SRAM_A[13]} -pinname P16 -fixed yes -DIRECTION Inout
498 # set_io {SRAM_A[14]} -pinname N16 -fixed yes -DIRECTION Inout
499 # set_io {SRAM_A[15]} -pinname V16 -fixed yes -DIRECTION Inout
500 # set_io {SRAM_A[16]} -pinname V17 -fixed yes -DIRECTION Inout
501 # set_io {SRAM_A[17]} -pinname U18 -fixed yes -DIRECTION Inout
502 # set_io {SRAM_A[18]} -pinname R18 -fixed yes -DIRECTION Inout
503 # set_io {SRAM_DQ[0]} -pinname T18 -fixed yes -DIRECTION Inout
504 # set_io {SRAM_DQ[1]} -pinname L15 -fixed yes -DIRECTION Inout
505 # set_io {SRAM_DQ[2]} -pinname K18 -fixed yes -DIRECTION Inout
506 # set_io {SRAM_DQ[3]} -pinname G17 -fixed yes -DIRECTION Inout
507 # set_io {SRAM_DQ[4]} -pinname K17 -fixed yes -DIRECTION Inout
508 # set_io {SRAM_DQ[5]} -pinname H18 -fixed yes -DIRECTION Inout
509 # set_io {SRAM_DQ[6]} -pinname L18 -fixed yes -DIRECTION Inout
510 # set_io {SRAM_DQ[7]} -pinname J18 -fixed yes -DIRECTION Inout
511 # set_io {SRAM_DQ[8]} -pinname M17 -fixed yes -DIRECTION Inout
512 # set_io {SRAM_DQ[9]} -pinname J17 -fixed yes -DIRECTION Inout
513 # set_io {SRAM_DQ[10]} -pinname N18 -fixed yes -DIRECTION Inout
514 # set_io {SRAM_DQ[11]} -pinname J13 -fixed yes -DIRECTION Inout
515 # set_io {SRAM_DQ[12]} -pinname N17 -fixed yes -DIRECTION Inout
516 # set_io {SRAM_DQ[13]} -pinname K13 -fixed yes -DIRECTION Inout
517 # set_io {SRAM_DQ[14]} -pinname P18 -fixed yes -DIRECTION Inout
518 # set_io {SRAM_DQ[15]} -pinname K14 -fixed yes -DIRECTION Inout
519 # set_io {SRAM_DQ[16]} -pinname K15 -fixed yes -DIRECTION Inout
520 # set_io {SRAM_DQ[17]} -pinname B18 -fixed yes -DIRECTION Inout
521 # set_io {SRAM_DQ[18]} -pinname D16 -fixed yes -DIRECTION Inout
522 # set_io {SRAM_DQ[19]} -pinname D15 -fixed yes -DIRECTION Inout
523 # set_io {SRAM_DQ[20]} -pinname C18 -fixed yes -DIRECTION Inout
524 # set_io {SRAM_DQ[21]} -pinname E15 -fixed yes -DIRECTION Inout
525 # set_io {SRAM_DQ[22]} -pinname D18 -fixed yes -DIRECTION Inout
526 # set_io {SRAM_DQ[23]} -pinname F15 -fixed yes -DIRECTION Inout
527 # set_io {SRAM_DQ[24]} -pinname E18 -fixed yes -DIRECTION Inout
528 # set_io {SRAM_DQ[25]} -pinname G15 -fixed yes -DIRECTION Inout
529 # set_io {SRAM_DQ[26]} -pinname F17 -fixed yes -DIRECTION Inout
530 # set_io {SRAM_DQ[27]} -pinname H15 -fixed yes -DIRECTION Inout
531 # set_io {SRAM_DQ[28]} -pinname F18 -fixed yes -DIRECTION Inout
532 # set_io {SRAM_DQ[29]} -pinname J15 -fixed yes -DIRECTION Inout
533 # set_io {SRAM_DQ[30]} -pinname D11 -fixed yes -DIRECTION Inout
534 # set_io {SRAM_DQ[31]} -pinname C16 -fixed yes -DIRECTION Inout
535 # set_io SRAM_MBE -pinname D13 -fixed yes -DIRECTION Inout
536 # set_io SRAM_nBUSY -pinname D12 -fixed yes -DIRECTION Inout
537 # set_io SRAM_nCE1 -pinname C17 -fixed yes -DIRECTION Inout
538 # set_io SRAM_nCE2 -pinname B17 -fixed yes -DIRECTION Inout
539 # set_io SRAM_nOE -pinname J14 -fixed yes -DIRECTION Inout
540 # set_io SRAM_nSCRUB -pinname E13 -fixed yes -DIRECTION Inout
541 # set_io SRAM_nWE -pinname B16 -fixed yes -DIRECTION Inout
542 # set_io TXD1 -pinname N12 -fixed yes -DIRECTION Inout
543 # set_io TXD2 -pinname G6 -fixed yes -DIRECTION Inout
544 # set_io clk_49 -pinname F8 -fixed yes -DIRECTION Inout
545 # set_io clk_50 -pinname F7 -fixed yes -DIRECTION Inout
546 # set_io nCTS1 -pinname L13 -fixed yes -DIRECTION Inout
547 # set_io nRTS1 -pinname M9 -fixed yes -DIRECTION Inout
548 # set_io reset -pinname F16 -fixed yes -DIRECTION Inout
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1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
44
44 LIBRARY iap;
45 ENTITY leon3_soc IS
45 USE iap.memctrl.all;
46 GENERIC (
46
47 fabtech : INTEGER := apa3e;
47
48 memtech : INTEGER := apa3e;
48 ENTITY leon3_soc IS
49 padtech : INTEGER := inferred;
49 GENERIC (
50 clktech : INTEGER := inferred;
50 fabtech : INTEGER := apa3e;
51 disas : INTEGER := 0; -- Enable disassembly to console
51 memtech : INTEGER := apa3e;
52 dbguart : INTEGER := 0; -- Print UART on console
52 padtech : INTEGER := inferred;
53 pclow : INTEGER := 2;
53 clktech : INTEGER := inferred;
54 --
54 disas : INTEGER := 0; -- Enable disassembly to console
55 clk_freq : INTEGER := 25000; --kHz
55 dbguart : INTEGER := 0; -- Print UART on console
56 --
56 pclow : INTEGER := 2;
57 NB_CPU : INTEGER := 1;
57 --
58 ENABLE_FPU : INTEGER := 1;
58 clk_freq : INTEGER := 25000; --kHz
59 FPU_NETLIST : INTEGER := 1;
59 --
60 ENABLE_DSU : INTEGER := 1;
60 NB_CPU : INTEGER := 1;
61 ENABLE_AHB_UART : INTEGER := 1;
61 ENABLE_FPU : INTEGER := 1;
62 ENABLE_APB_UART : INTEGER := 1;
62 FPU_NETLIST : INTEGER := 1;
63 ENABLE_IRQMP : INTEGER := 1;
63 ENABLE_DSU : INTEGER := 1;
64 ENABLE_GPT : INTEGER := 1;
64 ENABLE_AHB_UART : INTEGER := 1;
65 --
65 ENABLE_APB_UART : INTEGER := 1;
66 NB_AHB_MASTER : INTEGER := 0;
66 ENABLE_IRQMP : INTEGER := 1;
67 NB_AHB_SLAVE : INTEGER := 0;
67 ENABLE_GPT : INTEGER := 1;
68 NB_APB_SLAVE : INTEGER := 0;
68 --
69 --
69 NB_AHB_MASTER : INTEGER := 0;
70 ADDRESS_SIZE : INTEGER := 20
70 NB_AHB_SLAVE : INTEGER := 0;
71 );
71 NB_APB_SLAVE : INTEGER := 0;
72 PORT (
72 --
73 clk : IN STD_ULOGIC;
73 ADDRESS_SIZE : INTEGER := 20;
74 reset : IN STD_ULOGIC;
74 USES_IAP_MEMCTRLR : INTEGER := 0
75
75
76 errorn : OUT STD_ULOGIC;
76 );
77
77 PORT (
78 -- UART AHB ---------------------------------------------------------------
78 clk : IN STD_ULOGIC;
79 ahbrxd : IN STD_ULOGIC; -- DSU rx data
79 reset : IN STD_ULOGIC;
80 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
80
81
81 errorn : OUT STD_ULOGIC;
82 -- UART APB ---------------------------------------------------------------
82
83 urxd1 : IN STD_ULOGIC; -- UART1 rx data
83 -- UART AHB ---------------------------------------------------------------
84 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
84 ahbrxd : IN STD_ULOGIC; -- DSU rx data
85
85 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
86 -- RAM --------------------------------------------------------------------
86
87 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
87 -- UART APB ---------------------------------------------------------------
88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 urxd1 : IN STD_ULOGIC; -- UART1 rx data
89 nSRAM_BE0 : OUT STD_LOGIC;
89 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
90 nSRAM_BE1 : OUT STD_LOGIC;
90
91 nSRAM_BE2 : OUT STD_LOGIC;
91 -- RAM --------------------------------------------------------------------
92 nSRAM_BE3 : OUT STD_LOGIC;
92 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
93 nSRAM_WE : OUT STD_LOGIC;
93 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 nSRAM_CE : OUT STD_LOGIC;
94 nSRAM_BE0 : OUT STD_LOGIC;
95 nSRAM_OE : OUT STD_LOGIC;
95 nSRAM_BE1 : OUT STD_LOGIC;
96
96 nSRAM_BE2 : OUT STD_LOGIC;
97 -- APB --------------------------------------------------------------------
97 nSRAM_BE3 : OUT STD_LOGIC;
98 apbi_ext : OUT apb_slv_in_type;
98 nSRAM_WE : OUT STD_LOGIC;
99 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
99 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
100 -- AHB_Slave --------------------------------------------------------------
100 nSRAM_OE : OUT STD_LOGIC;
101 ahbi_s_ext : OUT ahb_slv_in_type;
101 nSRAM_READY : IN STD_LOGIC;
102 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
102 SRAM_MBE : INOUT STD_LOGIC;
103 -- AHB_Master -------------------------------------------------------------
103 -- APB --------------------------------------------------------------------
104 ahbi_m_ext : OUT AHB_Mst_In_Type;
104 apbi_ext : OUT apb_slv_in_type;
105 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
105 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
106
106 -- AHB_Slave --------------------------------------------------------------
107 );
107 ahbi_s_ext : OUT ahb_slv_in_type;
108 END;
108 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
109
109 -- AHB_Master -------------------------------------------------------------
110 ARCHITECTURE Behavioral OF leon3_soc IS
110 ahbi_m_ext : OUT AHB_Mst_In_Type;
111
111 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
112 -----------------------------------------------------------------------------
112
113 -- CONFIG -------------------------------------------------------------------
113 );
114 -----------------------------------------------------------------------------
114 END;
115
115
116 -- Clock generator
116 ARCHITECTURE Behavioral OF leon3_soc IS
117 constant CFG_CLKMUL : integer := (1);
117
118 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
118 -----------------------------------------------------------------------------
119 constant CFG_OCLKDIV : integer := (1);
119 -- CONFIG -------------------------------------------------------------------
120 constant CFG_CLK_NOFB : integer := 0;
120 -----------------------------------------------------------------------------
121 -- LEON3 processor core
121
122 constant CFG_LEON3 : integer := 1;
122 -- Clock generator
123 constant CFG_NCPU : integer := NB_CPU;
123 constant CFG_CLKMUL : integer := (1);
124 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
124 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
125 constant CFG_V8 : integer := 0;
125 constant CFG_OCLKDIV : integer := (1);
126 constant CFG_MAC : integer := 0;
126 constant CFG_CLK_NOFB : integer := 0;
127 constant CFG_SVT : integer := 0;
127 -- LEON3 processor core
128 constant CFG_RSTADDR : integer := 16#00000#;
128 constant CFG_LEON3 : integer := 1;
129 constant CFG_LDDEL : integer := (1);
129 constant CFG_NCPU : integer := NB_CPU;
130 constant CFG_NWP : integer := (0);
130 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
131 constant CFG_PWD : integer := 1*2;
131 constant CFG_V8 : integer := 0;
132 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
132 constant CFG_MAC : integer := 0;
133 -- 1*(8 + 16 * 0) => grfpu-light
133 constant CFG_SVT : integer := 0;
134 -- 1*(8 + 16 * 1) => netlist
134 constant CFG_RSTADDR : integer := 16#00000#;
135 -- 0*(8 + 16 * 0) => No FPU
135 constant CFG_LDDEL : integer := (1);
136 -- 0*(8 + 16 * 1) => No FPU;
136 constant CFG_NWP : integer := (0);
137 constant CFG_ICEN : integer := 1;
137 constant CFG_PWD : integer := 1*2;
138 constant CFG_ISETS : integer := 1;
138 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
139 constant CFG_ISETSZ : integer := 4;
139 -- 1*(8 + 16 * 0) => grfpu-light
140 constant CFG_ILINE : integer := 4;
140 -- 1*(8 + 16 * 1) => netlist
141 constant CFG_IREPL : integer := 0;
141 -- 0*(8 + 16 * 0) => No FPU
142 constant CFG_ILOCK : integer := 0;
142 -- 0*(8 + 16 * 1) => No FPU;
143 constant CFG_ILRAMEN : integer := 0;
143 constant CFG_ICEN : integer := 1;
144 constant CFG_ILRAMADDR: integer := 16#8E#;
144 constant CFG_ISETS : integer := 1;
145 constant CFG_ILRAMSZ : integer := 1;
145 constant CFG_ISETSZ : integer := 4;
146 constant CFG_DCEN : integer := 1;
146 constant CFG_ILINE : integer := 4;
147 constant CFG_DSETS : integer := 1;
147 constant CFG_IREPL : integer := 0;
148 constant CFG_DSETSZ : integer := 4;
148 constant CFG_ILOCK : integer := 0;
149 constant CFG_DLINE : integer := 4;
149 constant CFG_ILRAMEN : integer := 0;
150 constant CFG_DREPL : integer := 0;
150 constant CFG_ILRAMADDR: integer := 16#8E#;
151 constant CFG_DLOCK : integer := 0;
151 constant CFG_ILRAMSZ : integer := 1;
152 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
152 constant CFG_DCEN : integer := 1;
153 constant CFG_DLRAMEN : integer := 0;
153 constant CFG_DSETS : integer := 1;
154 constant CFG_DLRAMADDR: integer := 16#8F#;
154 constant CFG_DSETSZ : integer := 4;
155 constant CFG_DLRAMSZ : integer := 1;
155 constant CFG_DLINE : integer := 4;
156 constant CFG_MMUEN : integer := 0;
156 constant CFG_DREPL : integer := 0;
157 constant CFG_ITLBNUM : integer := 2;
157 constant CFG_DLOCK : integer := 0;
158 constant CFG_DTLBNUM : integer := 2;
158 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
159 constant CFG_TLB_TYPE : integer := 1 + 0*2;
159 constant CFG_DLRAMEN : integer := 0;
160 constant CFG_TLB_REP : integer := 1;
160 constant CFG_DLRAMADDR: integer := 16#8F#;
161
161 constant CFG_DLRAMSZ : integer := 1;
162 constant CFG_DSU : integer := ENABLE_DSU;
162 constant CFG_MMUEN : integer := 0;
163 constant CFG_ITBSZ : integer := 0;
163 constant CFG_ITLBNUM : integer := 2;
164 constant CFG_ATBSZ : integer := 0;
164 constant CFG_DTLBNUM : integer := 2;
165
165 constant CFG_TLB_TYPE : integer := 1 + 0*2;
166 -- AMBA settings
166 constant CFG_TLB_REP : integer := 1;
167 constant CFG_DEFMST : integer := (0);
167
168 constant CFG_RROBIN : integer := 1;
168 constant CFG_DSU : integer := ENABLE_DSU;
169 constant CFG_SPLIT : integer := 0;
169 constant CFG_ITBSZ : integer := 0;
170 constant CFG_AHBIO : integer := 16#FFF#;
170 constant CFG_ATBSZ : integer := 0;
171 constant CFG_APBADDR : integer := 16#800#;
171
172
172 -- AMBA settings
173 -- DSU UART
173 constant CFG_DEFMST : integer := (0);
174 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
174 constant CFG_RROBIN : integer := 1;
175
175 constant CFG_SPLIT : integer := 0;
176 -- LEON2 memory controller
176 constant CFG_AHBIO : integer := 16#FFF#;
177 constant CFG_MCTRL_SDEN : integer := 0;
177 constant CFG_APBADDR : integer := 16#800#;
178
178
179 -- UART 1
179 -- DSU UART
180 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
180 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
181 constant CFG_UART1_FIFO : integer := 1;
181
182
182 -- LEON2 memory controller
183 -- LEON3 interrupt controller
183 constant CFG_MCTRL_SDEN : integer := 0;
184 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
184
185
185 -- UART 1
186 -- Modular timer
186 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
187 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
187 constant CFG_UART1_FIFO : integer := 1;
188 constant CFG_GPT_NTIM : integer := (2);
188
189 constant CFG_GPT_SW : integer := (8);
189 -- LEON3 interrupt controller
190 constant CFG_GPT_TW : integer := (32);
190 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
191 constant CFG_GPT_IRQ : integer := (8);
191
192 constant CFG_GPT_SEPIRQ : integer := 1;
192 -- Modular timer
193 constant CFG_GPT_WDOGEN : integer := 0;
193 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
194 constant CFG_GPT_WDOG : integer := 16#0#;
194 constant CFG_GPT_NTIM : integer := (2);
195 -----------------------------------------------------------------------------
195 constant CFG_GPT_SW : integer := (8);
196
196 constant CFG_GPT_TW : integer := (32);
197 -----------------------------------------------------------------------------
197 constant CFG_GPT_IRQ : integer := (8);
198 -- SIGNALs
198 constant CFG_GPT_SEPIRQ : integer := 1;
199 -----------------------------------------------------------------------------
199 constant CFG_GPT_WDOGEN : integer := 0;
200 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
200 constant CFG_GPT_WDOG : integer := 16#0#;
201 -- CLK & RST --
201 -----------------------------------------------------------------------------
202 SIGNAL clk2x : STD_ULOGIC;
202
203 SIGNAL clkmn : STD_ULOGIC;
203 -----------------------------------------------------------------------------
204 SIGNAL clkm : STD_ULOGIC;
204 -- SIGNALs
205 SIGNAL rstn : STD_ULOGIC;
205 -----------------------------------------------------------------------------
206 SIGNAL rstraw : STD_ULOGIC;
206 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
207 SIGNAL pciclk : STD_ULOGIC;
207 -- CLK & RST --
208 SIGNAL sdclkl : STD_ULOGIC;
208 SIGNAL clk2x : STD_ULOGIC;
209 SIGNAL cgi : clkgen_in_type;
209 SIGNAL clkmn : STD_ULOGIC;
210 SIGNAL cgo : clkgen_out_type;
210 SIGNAL clkm : STD_ULOGIC;
211 --- AHB / APB
211 SIGNAL rstn : STD_ULOGIC;
212 SIGNAL apbi : apb_slv_in_type;
212 SIGNAL rstraw : STD_ULOGIC;
213 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
213 SIGNAL pciclk : STD_ULOGIC;
214 SIGNAL ahbsi : ahb_slv_in_type;
214 SIGNAL sdclkl : STD_ULOGIC;
215 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
215 SIGNAL cgi : clkgen_in_type;
216 SIGNAL ahbmi : ahb_mst_in_type;
216 SIGNAL cgo : clkgen_out_type;
217 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
217 --- AHB / APB
218 --UART
218 SIGNAL apbi : apb_slv_in_type;
219 SIGNAL ahbuarti : uart_in_type;
219 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
220 SIGNAL ahbuarto : uart_out_type;
220 SIGNAL ahbsi : ahb_slv_in_type;
221 SIGNAL apbuarti : uart_in_type;
221 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
222 SIGNAL apbuarto : uart_out_type;
222 SIGNAL ahbmi : ahb_mst_in_type;
223 --MEM CTRLR
223 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
224 SIGNAL memi : memory_in_type;
224 --UART
225 SIGNAL memo : memory_out_type;
225 SIGNAL ahbuarti : uart_in_type;
226 SIGNAL wpo : wprot_out_type;
226 SIGNAL ahbuarto : uart_out_type;
227 SIGNAL sdo : sdram_out_type;
227 SIGNAL apbuarti : uart_in_type;
228 --IRQ
228 SIGNAL apbuarto : uart_out_type;
229 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
229 --MEM CTRLR
230 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
230 SIGNAL memi : memory_in_type;
231 --Timer
231 SIGNAL memo : memory_out_type;
232 SIGNAL gpti : gptimer_in_type;
232 SIGNAL wpo : wprot_out_type;
233 SIGNAL gpto : gptimer_out_type;
233 SIGNAL sdo : sdram_out_type;
234 --DSU
234 SIGNAl mbe : std_logic; -- enable memory programming
235 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
235 SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal
236 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
236 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0);
237 SIGNAL dsui : dsu_in_type;
237 --IRQ
238 SIGNAL dsuo : dsu_out_type;
238 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
239 -----------------------------------------------------------------------------
239 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
240
240 --Timer
241 SIGNAL nSRAM_CE_s : STD_LOGIC;
241 SIGNAL gpti : gptimer_in_type;
242 BEGIN
242 SIGNAL gpto : gptimer_out_type;
243
243 --DSU
244
244 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
245 ----------------------------------------------------------------------
245 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
246 --- Reset and Clock generation -------------------------------------
246 SIGNAL dsui : dsu_in_type;
247 ----------------------------------------------------------------------
247 SIGNAL dsuo : dsu_out_type;
248
248 -----------------------------------------------------------------------------
249 cgi.pllctrl <= "00";
249
250 cgi.pllrst <= rstraw;
250
251
251 BEGIN
252 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
252
253
253
254 clkgen0 : clkgen -- clock generator
254 ----------------------------------------------------------------------
255 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
255 --- Reset and Clock generation -------------------------------------
256 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
256 ----------------------------------------------------------------------
257 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
257
258
258 cgi.pllctrl <= "00";
259 ----------------------------------------------------------------------
259 cgi.pllrst <= rstraw;
260 --- LEON3 processor / DSU / IRQ ------------------------------------
260
261 ----------------------------------------------------------------------
261 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
262
262
263 l3 : IF CFG_LEON3 = 1 GENERATE
263 clkgen0 : clkgen -- clock generator
264 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
264 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
265 u0 : leon3s -- LEON3 processor
265 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
266 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
266 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
267 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
267
268 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
268 ----------------------------------------------------------------------
269 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
269 --- LEON3 processor / DSU / IRQ ------------------------------------
270 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
270 ----------------------------------------------------------------------
271 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
271
272 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
272 l3 : IF CFG_LEON3 = 1 GENERATE
273 irqi(i), irqo(i), dbgi(i), dbgo(i));
273 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
274 END GENERATE;
274 u0 : leon3s -- LEON3 processor
275 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
275 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
276
276 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
277 dsugen : IF CFG_DSU = 1 GENERATE
277 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
278 dsu0 : dsu3 -- LEON3 Debug Support Unit
278 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
279 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
279 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
280 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
280 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
281 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
281 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
282 dsui.enable <= '1';
282 irqi(i), irqo(i), dbgi(i), dbgo(i));
283 dsui.break <= '0';
283 END GENERATE;
284 END GENERATE;
284 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
285 END GENERATE;
285
286
286 dsugen : IF CFG_DSU = 1 GENERATE
287 nodsu : IF CFG_DSU = 0 GENERATE
287 dsu0 : dsu3 -- LEON3 Debug Support Unit
288 ahbso(2) <= ahbs_none;
288 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
289 dsuo.tstop <= '0';
289 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
290 dsuo.active <= '0';
290 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
291 END GENERATE;
291 dsui.enable <= '1';
292
292 dsui.break <= '0';
293 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
293 END GENERATE;
294 irqctrl0 : irqmp -- interrupt controller
294 END GENERATE;
295 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
295
296 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
296 nodsu : IF CFG_DSU = 0 GENERATE
297 END GENERATE;
297 ahbso(2) <= ahbs_none;
298 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
298 dsuo.tstop <= '0';
299 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
299 dsuo.active <= '0';
300 irqi(i).irl <= "0000";
300 END GENERATE;
301 END GENERATE;
301
302 apbo(2) <= apb_none;
302 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
303 END GENERATE;
303 irqctrl0 : irqmp -- interrupt controller
304
304 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
305 ----------------------------------------------------------------------
305 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
306 --- Memory controllers ---------------------------------------------
306 END GENERATE;
307 ----------------------------------------------------------------------
307 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
308 memctrlr : mctrl GENERIC MAP (
308 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
309 hindex => 0,
309 irqi(i).irl <= "0000";
310 pindex => 0,
310 END GENERATE;
311 paddr => 0,
311 apbo(2) <= apb_none;
312 srbanks => 1
312 END GENERATE;
313 )
313
314 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
314 ----------------------------------------------------------------------
315
315 --- Memory controllers ---------------------------------------------
316 memi.brdyn <= '1';
316 ----------------------------------------------------------------------
317 memi.bexcn <= '1';
317 ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
318 memi.writen <= '1';
318 memctrlr : mctrl GENERIC MAP (
319 memi.wrn <= "1111";
319 hindex => 0,
320 memi.bwidth <= "10";
320 pindex => 0,
321
321 paddr => 0,
322 bdr : FOR i IN 0 TO 3 GENERATE
322 srbanks => 1
323 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
323 )
324 PORT MAP (
324 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
325 data(31-i*8 DOWNTO 24-i*8),
325 memi.bexcn <= '1';
326 memo.data(31-i*8 DOWNTO 24-i*8),
326 memi.brdyn <= '1';
327 memo.bdrive(i),
327 END GENERATE;
328 memi.data(31-i*8 DOWNTO 24-i*8));
328
329 END GENERATE;
329 IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
330
330 memctrlr : srctrle_0ws
331 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
331 GENERIC MAP(
332 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
332 hindex => 0,
333 nSRAM_CE_s <= NOT(memo.ramsn(0));
333 pindex => 0,
334 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
334 paddr => 0,
335 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
335 srbanks => 2,
336 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
336 banksz => 8, --512k * 32
337 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
337 rmw => 1,
338 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
338 --Aeroflex memory generics:
339 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
339 mprog => 1, -- program memory by default values after reset
340 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
340 mpsrate => 12, -- default scrub rate period
341
341 mpb2s => 4, -- default busy to scrub delay
342 ----------------------------------------------------------------------
342 mpapb => 1, -- instantiate apb register
343 --- AHB CONTROLLER -------------------------------------------------
343 mchipcnt => 2,
344 ----------------------------------------------------------------------
344 mpenall => 1 -- when 0 program only E1 chip, else program all dies
345 ahb0 : ahbctrl -- AHB arbiter/multiplexer
345 )
346 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
346 PORT MAP (
347 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
347 rst => rstn,
348 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
348 clk => clkm,
349 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
349 ahbsi => ahbsi,
350
350 ahbso => ahbso(0),
351 ----------------------------------------------------------------------
351 apbi => apbi,
352 --- AHB UART -------------------------------------------------------
352 apbo => apbo(0),
353 ----------------------------------------------------------------------
353 sri => memi,
354 dcomgen : IF CFG_AHB_UART = 1 GENERATE
354 sro => memo,
355 dcom0 : ahbuart
355 --Aeroflex memory signals:
356 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
356 ucerr => open, -- uncorrectable error signal
357 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
357 mbe => mbe, -- enable memory programming
358 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
358 mbe_drive => mbe_drive -- drive the MBE memory signal
359 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
359 );
360 END GENERATE;
360
361 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
361 memi.brdyn <= nSRAM_READY;
362
362
363 ----------------------------------------------------------------------
363 mbe_pad : iopad
364 --- APB Bridge -----------------------------------------------------
364 GENERIC MAP(tech => padtech)
365 ----------------------------------------------------------------------
365 PORT MAP(pad => SRAM_MBE,
366 apb0 : apbctrl -- AHB/APB bridge
366 i => mbe,
367 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
367 en => mbe_drive,
368 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
368 o => memi.bexcn );
369
369 END GENERATE;
370 ----------------------------------------------------------------------
370
371 --- GPT Timer ------------------------------------------------------
371
372 ----------------------------------------------------------------------
372 memi.writen <= '1';
373 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
373 memi.wrn <= "1111";
374 timer0 : gptimer -- timer unit
374 memi.bwidth <= "10";
375 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
375
376 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
376 bdr : FOR i IN 0 TO 3 GENERATE
377 nbits => CFG_GPT_TW)
377 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
378 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
378 PORT MAP (
379 gpti.dhalt <= dsuo.tstop;
379 data(31-i*8 DOWNTO 24-i*8),
380 gpti.extclk <= '0';
380 memo.data(31-i*8 DOWNTO 24-i*8),
381 END GENERATE;
381 memo.bdrive(i),
382 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
382 memi.data(31-i*8 DOWNTO 24-i*8));
383
383 END GENERATE;
384
384
385 ----------------------------------------------------------------------
385 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
386 --- APB UART -------------------------------------------------------
386 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
387 ----------------------------------------------------------------------
387 nSRAM_CE_s <= (memo.ramsn(1 downto 0));
388 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
388 rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
389 uart1 : apbuart -- UART 1
389 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.oen);
390 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
390 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
391 fifosize => CFG_UART1_FIFO)
391 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
392 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
392 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
393 apbuarti.rxd <= urxd1;
393 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
394 apbuarti.extclk <= '0';
394 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
395 utxd1 <= apbuarto.txd;
395
396 apbuarti.ctsn <= '0';
396
397 END GENERATE;
397
398 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
398 ----------------------------------------------------------------------
399
399 --- AHB CONTROLLER -------------------------------------------------
400 -------------------------------------------------------------------------------
400 ----------------------------------------------------------------------
401 -- AMBA BUS -------------------------------------------------------------------
401 ahb0 : ahbctrl -- AHB arbiter/multiplexer
402 -------------------------------------------------------------------------------
402 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
403
403 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
404 -- APB --------------------------------------------------------------------
404 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
405 apbi_ext <= apbi;
405 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
406 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
406
407 max_16_apb: IF I + 5 < 16 GENERATE
407 ----------------------------------------------------------------------
408 apbo(I+5)<= apbo_ext(I+5);
408 --- AHB UART -------------------------------------------------------
409 END GENERATE max_16_apb;
409 ----------------------------------------------------------------------
410 END GENERATE all_apb;
410 dcomgen : IF CFG_AHB_UART = 1 GENERATE
411 -- AHB_Slave --------------------------------------------------------------
411 dcom0 : ahbuart
412 ahbi_s_ext <= ahbsi;
412 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
413 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
413 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
414 max_16_ahbs: IF I + 3 < 16 GENERATE
414 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
415 ahbso(I+3) <= ahbo_s_ext(I+3);
415 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
416 END GENERATE max_16_ahbs;
416 END GENERATE;
417 END GENERATE all_ahbs;
417 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
418 -- AHB_Master -------------------------------------------------------------
418
419 ahbi_m_ext <= ahbmi;
419 ----------------------------------------------------------------------
420 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
420 --- APB Bridge -----------------------------------------------------
421 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
421 ----------------------------------------------------------------------
422 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
422 apb0 : apbctrl -- AHB/APB bridge
423 END GENERATE max_16_ahbm;
423 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
424 END GENERATE all_ahbm;
424 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
425
425
426
426 ----------------------------------------------------------------------
427
427 --- GPT Timer ------------------------------------------------------
428 END Behavioral;
428 ----------------------------------------------------------------------
429 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
430 timer0 : gptimer -- timer unit
431 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
432 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
433 nbits => CFG_GPT_TW)
434 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
435 gpti.dhalt <= dsuo.tstop;
436 gpti.extclk <= '0';
437 END GENERATE;
438 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
439
440
441 ----------------------------------------------------------------------
442 --- APB UART -------------------------------------------------------
443 ----------------------------------------------------------------------
444 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
445 uart1 : apbuart -- UART 1
446 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
447 fifosize => CFG_UART1_FIFO)
448 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
449 apbuarti.rxd <= urxd1;
450 apbuarti.extclk <= '0';
451 utxd1 <= apbuarto.txd;
452 apbuarti.ctsn <= '0';
453 END GENERATE;
454 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
455
456 -------------------------------------------------------------------------------
457 -- AMBA BUS -------------------------------------------------------------------
458 -------------------------------------------------------------------------------
459
460 -- APB --------------------------------------------------------------------
461 apbi_ext <= apbi;
462 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
463 max_16_apb: IF I + 5 < 16 GENERATE
464 apbo(I+5)<= apbo_ext(I+5);
465 END GENERATE max_16_apb;
466 END GENERATE all_apb;
467 -- AHB_Slave --------------------------------------------------------------
468 ahbi_s_ext <= ahbsi;
469 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
470 max_16_ahbs: IF I + 3 < 16 GENERATE
471 ahbso(I+3) <= ahbo_s_ext(I+3);
472 END GENERATE max_16_ahbs;
473 END GENERATE all_ahbs;
474 -- AHB_Master -------------------------------------------------------------
475 ahbi_m_ext <= ahbmi;
476 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
477 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
478 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
479 END GENERATE max_16_ahbm;
480 END GENERATE all_ahbm;
481
482
483
484 END Behavioral; No newline at end of file
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@@ -1,128 +1,142
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27
27
28 PACKAGE lpp_leon3_soc_pkg IS
28 PACKAGE lpp_leon3_soc_pkg IS
29
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
33
34 COMPONENT leon3_soc
34 COMPONENT leon3_soc
35 GENERIC (
35 GENERIC (
36 fabtech : INTEGER;
36 fabtech : INTEGER;
37 memtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
43 clk_freq : INTEGER;
44 NB_CPU : INTEGER;
44 NB_CPU : INTEGER;
45 ENABLE_FPU : INTEGER;
45 ENABLE_FPU : INTEGER;
46 FPU_NETLIST : INTEGER;
46 FPU_NETLIST : INTEGER;
47 ENABLE_DSU : INTEGER;
47 ENABLE_DSU : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
50 ENABLE_IRQMP : INTEGER;
50 ENABLE_IRQMP : INTEGER;
51 ENABLE_GPT : INTEGER;
51 ENABLE_GPT : INTEGER;
52 NB_AHB_MASTER : INTEGER;
52 NB_AHB_MASTER : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER;
55 ADDRESS_SIZE : INTEGER);
55 ADDRESS_SIZE : INTEGER;
56 PORT (
56 USES_IAP_MEMCTRLR : INTEGER
57 clk : IN STD_ULOGIC;
57 );
58 reset : IN STD_ULOGIC;
58 PORT (
59 errorn : OUT STD_ULOGIC;
59 clk : IN STD_ULOGIC;
60 ahbrxd : IN STD_ULOGIC;
60 reset : IN STD_ULOGIC;
61 ahbtxd : OUT STD_ULOGIC;
61
62 urxd1 : IN STD_ULOGIC;
62 errorn : OUT STD_ULOGIC;
63 utxd1 : OUT STD_ULOGIC;
63
64 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
64 -- UART AHB ---------------------------------------------------------------
65 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 ahbrxd : IN STD_ULOGIC; -- DSU rx data
66 nSRAM_BE0 : OUT STD_LOGIC;
66 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
67 nSRAM_BE1 : OUT STD_LOGIC;
67
68 nSRAM_BE2 : OUT STD_LOGIC;
68 -- UART APB ---------------------------------------------------------------
69 nSRAM_BE3 : OUT STD_LOGIC;
69 urxd1 : IN STD_ULOGIC; -- UART1 rx data
70 nSRAM_WE : OUT STD_LOGIC;
70 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
71 nSRAM_CE : OUT STD_LOGIC;
71
72 nSRAM_OE : OUT STD_LOGIC;
72 -- RAM --------------------------------------------------------------------
73 apbi_ext : OUT apb_slv_in_type;
73 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
74 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
74 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 ahbi_s_ext : OUT ahb_slv_in_type;
75 nSRAM_BE0 : OUT STD_LOGIC;
76 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
76 nSRAM_BE1 : OUT STD_LOGIC;
77 ahbi_m_ext : OUT AHB_Mst_In_Type;
77 nSRAM_BE2 : OUT STD_LOGIC;
78 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
78 nSRAM_BE3 : OUT STD_LOGIC;
79 nSRAM_WE : OUT STD_LOGIC;
80 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
81 nSRAM_OE : OUT STD_LOGIC;
82 nSRAM_READY : IN STD_LOGIC;
83 SRAM_MBE : INOUT STD_LOGIC;
84 -- APB --------------------------------------------------------------------
85 apbi_ext : OUT apb_slv_in_type;
86 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
87 -- AHB_Slave --------------------------------------------------------------
88 ahbi_s_ext : OUT ahb_slv_in_type;
89 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
90 -- AHB_Master -------------------------------------------------------------
91 ahbi_m_ext : OUT AHB_Mst_In_Type;
92 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
79 END COMPONENT;
93 END COMPONENT;
80
94
81
95
82 COMPONENT leon3ft_soc
96 COMPONENT leon3ft_soc
83 GENERIC (
97 GENERIC (
84 fabtech : INTEGER;
98 fabtech : INTEGER;
85 memtech : INTEGER;
99 memtech : INTEGER;
86 padtech : INTEGER;
100 padtech : INTEGER;
87 clktech : INTEGER;
101 clktech : INTEGER;
88 disas : INTEGER;
102 disas : INTEGER;
89 dbguart : INTEGER;
103 dbguart : INTEGER;
90 pclow : INTEGER;
104 pclow : INTEGER;
91 clk_freq : INTEGER;
105 clk_freq : INTEGER;
92 NB_CPU : INTEGER;
106 NB_CPU : INTEGER;
93 ENABLE_FPU : INTEGER;
107 ENABLE_FPU : INTEGER;
94 FPU_NETLIST : INTEGER;
108 FPU_NETLIST : INTEGER;
95 ENABLE_DSU : INTEGER;
109 ENABLE_DSU : INTEGER;
96 ENABLE_AHB_UART : INTEGER;
110 ENABLE_AHB_UART : INTEGER;
97 ENABLE_APB_UART : INTEGER;
111 ENABLE_APB_UART : INTEGER;
98 ENABLE_IRQMP : INTEGER;
112 ENABLE_IRQMP : INTEGER;
99 ENABLE_GPT : INTEGER;
113 ENABLE_GPT : INTEGER;
100 NB_AHB_MASTER : INTEGER;
114 NB_AHB_MASTER : INTEGER;
101 NB_AHB_SLAVE : INTEGER;
115 NB_AHB_SLAVE : INTEGER;
102 NB_APB_SLAVE : INTEGER);
116 NB_APB_SLAVE : INTEGER);
103 PORT (
117 PORT (
104 clk : IN STD_ULOGIC;
118 clk : IN STD_ULOGIC;
105 reset : IN STD_ULOGIC;
119 reset : IN STD_ULOGIC;
106 errorn : OUT STD_ULOGIC;
120 errorn : OUT STD_ULOGIC;
107 ahbrxd : IN STD_ULOGIC;
121 ahbrxd : IN STD_ULOGIC;
108 ahbtxd : OUT STD_ULOGIC;
122 ahbtxd : OUT STD_ULOGIC;
109 urxd1 : IN STD_ULOGIC;
123 urxd1 : IN STD_ULOGIC;
110 utxd1 : OUT STD_ULOGIC;
124 utxd1 : OUT STD_ULOGIC;
111 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
125 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
112 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
113 nSRAM_BE0 : OUT STD_LOGIC;
127 nSRAM_BE0 : OUT STD_LOGIC;
114 nSRAM_BE1 : OUT STD_LOGIC;
128 nSRAM_BE1 : OUT STD_LOGIC;
115 nSRAM_BE2 : OUT STD_LOGIC;
129 nSRAM_BE2 : OUT STD_LOGIC;
116 nSRAM_BE3 : OUT STD_LOGIC;
130 nSRAM_BE3 : OUT STD_LOGIC;
117 nSRAM_WE : OUT STD_LOGIC;
131 nSRAM_WE : OUT STD_LOGIC;
118 nSRAM_CE : OUT STD_LOGIC;
132 nSRAM_CE : OUT STD_LOGIC;
119 nSRAM_OE : OUT STD_LOGIC;
133 nSRAM_OE : OUT STD_LOGIC;
120 apbi_ext : OUT apb_slv_in_type;
134 apbi_ext : OUT apb_slv_in_type;
121 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
135 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
122 ahbi_s_ext : OUT ahb_slv_in_type;
136 ahbi_s_ext : OUT ahb_slv_in_type;
123 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
137 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
124 ahbi_m_ext : OUT AHB_Mst_In_Type;
138 ahbi_m_ext : OUT AHB_Mst_In_Type;
125 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
139 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
126 END COMPONENT;
140 END COMPONENT;
127
141
128 END;
142 END; No newline at end of file
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