HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r619:b515d4c55e1d

save x.1.85

pellion -

r619:b515d4c55e1d simu_with_Leon3

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r619:b515d4c55e1d

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designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +3 -1

                   ADDRESS_SIZE    => 19,
                   USES_IAP_MEMCTRLR => 1,
                   BYPASS_EDAC_MEMCTRLR => '0',
-                  SRBANKSZ          => 8)
+                  SRBANKSZ          => 8,
+                  SLOW_TIMING_EMULATION => 0
+                  )
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn_25,

designs/LFR-em-WFP_MS/LFR-em.vhd +1 -1

                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
-                  ENABLE_AHB_UART => 1,
+                  ENABLE_AHB_UART => 0,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,

designs/UT8ER1M32-test-board/Makefile +2 -1

             	./lpp_sim \
             	./lpp_lfr_pkg \
             	./lpp_debug_lfr_pkg \
-            	./lpp_top_lfr
+            	./lpp_top_lfr \
+            	./lfr_management
             FILESKIP =lpp_lfr_ms.vhd \
             	i2cmst.vhd \

designs/UT8ER1M32-test-board/UT8ER1M32-test-board_top.vhd +42 -10

               --SRAM-----------------------------------------------------------------------
               SIGNAL  SRAM_CE    :   STD_LOGIC_VECTOR(1 downto 0);
+              SIGNAL rstn_25 : STD_LOGIC;
+              SIGNAL rstn_50 : STD_LOGIC;
+              SIGNAL rstn_49 : STD_LOGIC;
+              SIGNAL clk_lock : STD_LOGIC;
+              SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
+              SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
             BEGIN  -- beh
+              rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN);
+              PROCESS (clk_50, rstn_50)
+              BEGIN  -- PROCESS
+                IF rstn_50 = '0' THEN         -- asynchronous reset (active low)
+                  clk_lock         <= '0';
+                  clk_busy_counter <= (OTHERS => '0');
+                  nSRAM_BUSY_reg    <= '0';
+                ELSIF clk_50'event AND clk_50 = '1' THEN  -- rising clock edge
+                  nSRAM_BUSY_reg <= SRAM_nBUSY;
+                  IF nSRAM_BUSY_reg = '1' AND SRAM_nBUSY = '0' THEN
+                    IF clk_busy_counter = "1111"  THEN
+                      clk_lock <= '1';
+                    ELSE
+                      clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
+                    END IF;
+                  END IF;
+                END IF;
+              END PROCESS;
+              rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               PROCESS(clk_50)
               BEGIN
                 IF clk_50'EVENT AND clk_50 = '1' THEN
               END PROCESS;
               -----------------------------------------------------------------------------
+              PROCESS (clk_49, rstn_49)
-              PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
-                IF reset = '0' THEN                 -- asynchronous reset (active low)
+                IF rstn_49 = '0' THEN                 -- asynchronous reset (active low)
                   I00_s  <= '0';
                 ELSIF clk_49'event AND clk_49 = '1' THEN  -- rising clock edge
                   I00_s  <= NOT I00_s;
               SRAM_nCE2    <=  SRAM_CE(1);
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 19,
-                  USES_IAP_MEMCTRLR => 1)
+                  USES_IAP_MEMCTRLR => 1,
+                  BYPASS_EDAC_MEMCTRLR => '0',
+                  SRBANKSZ          => 8,
+                  SLOW_TIMING_EMULATION => 1
+                  )
                 PORT MAP (
                   clk         => clk_25,
-                  reset       => reset,
+                  reset       => rstn_25,
                   errorn      => errorn,
                   ahbrxd      => TXD1,
                   ahbtxd      => RXD1,
                   urxd1       => TXD2,
                   utxd1       => RXD2,
                   address     => SRAM_A,
                   data        => SRAM_DQ,
                   nSRAM_BE0   => LED0,
-            END beh;
  No newline at end of file
+            END beh;

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +27 -6

                 ADDRESS_SIZE      : INTEGER := 19;
                 USES_IAP_MEMCTRLR : INTEGER := 1;
                 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
-                SRBANKSZ          : INTEGER := 8
+                SRBANKSZ          : INTEGER := 8;
+                SLOW_TIMING_EMULATION : integer := 0
                 );
               PORT (
               SIGNAL   dsui       : dsu_in_type;
               SIGNAL   dsuo       : dsu_out_type;
               -----------------------------------------------------------------------------
+              SIGNAL memo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
+              SIGNAL memi_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
+              -----------------------------------------------------------------------------
+              -- SLOW TIMING EMULATION
+              -----------------------------------------------------------------------------
+              SLOW_TIMING_EMULATION_ON: IF SLOW_TIMING_EMULATION = 1 GENERATE
+                PROCESS (clkm, rstn)
+                BEGIN  -- PROCESS
+                  IF rstn = '0' THEN                -- asynchronous reset (active low)
+                    memi.data <= (OTHERS => '0');
+                    memo_data <= (OTHERS => '0');
+                  ELSIF clkm'event AND clkm = '1' THEN  -- rising clock edge
+                    memi.data <= memi_data;
+                    memo_data <= memo.data;
+                  END IF;
+                END PROCESS;
+              END GENERATE SLOW_TIMING_EMULATION_ON;
+              SLOW_TIMING_EMULATION_OFF: IF SLOW_TIMING_EMULATION = 0 GENERATE
+                memi.data <= memi_data;
+                memo_data <= memo.data;
+              END GENERATE SLOW_TIMING_EMULATION_OFF;
               bdr : FOR i IN 0 TO 3 GENERATE
                 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
-                    memo.data(31-i*8 DOWNTO 24-i*8),
+                    memo_data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
-                    memi.data(31-i*8 DOWNTO 24-i*8));
+                    memi_data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
+              -----------------------------------------------------------------------------
               addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
                 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
               nBWc_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
               nBWd_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------

lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd +2 -1

                   ADDRESS_SIZE    : INTEGER;
                   USES_IAP_MEMCTRLR : INTEGER;
                   BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
-                  SRBANKSZ        : INTEGER := 8
+                  SRBANKSZ        : INTEGER := 8;
+                  SLOW_TIMING_EMULATION : integer := 0
                 );
               PORT (
                 clk    : IN STD_ULOGIC;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +7 -4

                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
-                DEBUG_FORCE_DATA_DMA : INTEGER := 0
+                DEBUG_FORCE_DATA_DMA : INTEGER := 0;
+                RTL_DESIGN_LIGHT     : INTEGER := 0;
+                WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
-                  Mem_use => Mem_use)
+                  Mem_use          => Mem_use,
+                  RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
-                  Mem_use => Mem_use)
+                  Mem_use => Mem_use,
+                  WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,

lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +10 -3

             ENTITY lpp_lfr_filter IS
               GENERIC(
-                Mem_use                 : INTEGER := use_RAM
+                Mem_use                 : INTEGER := use_RAM;
+                RTL_DESIGN_LIGHT        : INTEGER := 0
                 );
               PORT (
                 sample           : IN Samples(7 DOWNTO 0);
                 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
               END GENERATE all_channel_sample_f_cic;
+              NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE
+                sample_f2_filter_val <= sample_f2_cic_val;
+                sample_f2_filter     <= sample_f2_cic_filter;
+                sample_f3_filter_val <= sample_f3_cic_val;
+                sample_f3_filter     <= sample_f3_cic_filter;
+              END GENERATE NO_IIR_FILTER_f2_f3;
+              YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE
                 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
                   GENERIC MAP (
                     tech         => 0,
                     sample_out1     => sample_f2_filter,
                     sample_out2_val => sample_f3_filter_val,
                     sample_out2     => sample_f3_filter);
+              END GENERATE YES_IIR_FILTER_f2_f3;
               all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
                 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
                 END GENERATE all_bit_sample_f_filter;
               END GENERATE all_channel_sample_f_filter;
               -----------------------------------------------------------------------------
               Downsampling_f2 : Downsampling

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +4 -1

             ENTITY lpp_lfr_ms IS
               GENERIC (
-                Mem_use : INTEGER := use_RAM
+                Mem_use : INTEGER := use_RAM;
+                WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
                 );
               PORT (
                 clk  : IN STD_LOGIC;
               -- FFT
               -----------------------------------------------------------------------------
               lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
+                GENERIC MAP (
+                  WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,

lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd +21 -3

             USE lpp.window_function_pkg.ALL;
             ENTITY lpp_lfr_ms_FFT IS
+              GENERIC (
+                WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
+                );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
               SIGNAL data_win       : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_win_valid : STD_LOGIC;
+              SIGNAL data_in_reg       : STD_LOGIC_VECTOR(15 DOWNTO 0);
+              SIGNAL data_in_reg_valid : STD_LOGIC;
             BEGIN
+              PROCESS (clk, rstn)
+              BEGIN  -- PROCESS
+                IF rstn = '0' THEN                  -- asynchronous reset (active low)
+                  data_in_reg       <= (OTHERS => '0');
+                  data_in_reg_valid <= '0';
+                ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                  data_in_reg       <= sample_data;
+                  data_in_reg_valid <= sample_valid;
+                END IF;
+              END PROCESS;
               window_hanning: window_function
                 GENERIC MAP (
                   SIZE_DATA          => 16,
-                  SIZE_PARAM         => 15,
+                  SIZE_PARAM         => WINDOWS_HAANNING_PARAM_SIZE,
                   NB_POINT_BY_WINDOW => 256)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   restart_window => '0',
-                  data_in        => sample_data,
+                  data_in        => data_in_reg,
-                  data_in_valid  => sample_valid,
+                  data_in_valid  => data_in_reg_valid,
                   data_out       => data_win,
                   data_out_valid => data_win_valid);

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +10 -3

               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_ms
                 GENERIC (
-                  Mem_use : INTEGER);
+                  Mem_use : INTEGER;
+                  WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
               END COMPONENT;
               COMPONENT lpp_lfr_ms_FFT
+                GENERIC (
+                  WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
               COMPONENT lpp_lfr_filter
                 GENERIC (
-                  Mem_use : INTEGER);
+                  Mem_use                 : INTEGER;
+                  RTL_DESIGN_LIGHT        : INTEGER
+                  );
                 PORT (
                   sample           : IN  Samples(7 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0);
-                  DEBUG_FORCE_DATA_DMA   : INTEGER
+                  DEBUG_FORCE_DATA_DMA   : INTEGER;
+                  RTL_DESIGN_LIGHT       : INTEGER;
+                  WINDOWS_HAANNING_PARAM_SIZE : INTEGER
                   );
                 PORT (
                   clk             : IN  STD_LOGIC;

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