@@ -265,7 +265,9 BEGIN -- beh | |||
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265 | 265 | ADDRESS_SIZE => 19, |
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266 | 266 | USES_IAP_MEMCTRLR => 1, |
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267 | 267 | BYPASS_EDAC_MEMCTRLR => '0', |
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268 |
SRBANKSZ => 8 |
|
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268 | SRBANKSZ => 8, | |
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269 | SLOW_TIMING_EMULATION => 0 | |
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270 | ) | |
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269 | 271 | PORT MAP ( |
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270 | 272 | clk => clk_25, |
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271 | 273 | reset => rstn_25, |
@@ -225,7 +225,7 BEGIN -- beh | |||
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225 | 225 | ENABLE_FPU => 1, |
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226 | 226 | FPU_NETLIST => 0, |
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227 | 227 | ENABLE_DSU => 1, |
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228 |
ENABLE_AHB_UART => |
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228 | ENABLE_AHB_UART => 0, | |
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229 | 229 | ENABLE_APB_UART => 1, |
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230 | 230 | ENABLE_IRQMP => 1, |
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231 | 231 | ENABLE_GPT => 1, |
@@ -38,7 +38,8 DIRSKIP = b1553 pcif leon2 leon2ft crypt | |||
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38 | 38 | ./lpp_sim \ |
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39 | 39 | ./lpp_lfr_pkg \ |
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40 | 40 | ./lpp_debug_lfr_pkg \ |
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41 | ./lpp_top_lfr | |
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41 | ./lpp_top_lfr \ | |
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42 | ./lfr_management | |
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42 | 43 | |
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43 | 44 | FILESKIP =lpp_lfr_ms.vhd \ |
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44 | 45 | i2cmst.vhd \ |
@@ -110,14 +110,42 ARCHITECTURE beh OF UT8ER1M32_test_board | |||
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110 | 110 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); |
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111 | 111 | --SRAM----------------------------------------------------------------------- |
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112 | 112 | SIGNAL SRAM_CE : STD_LOGIC_VECTOR(1 downto 0); |
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113 | ||
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114 | ||
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115 | SIGNAL rstn_25 : STD_LOGIC; | |
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116 | SIGNAL rstn_50 : STD_LOGIC; | |
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117 | SIGNAL rstn_49 : STD_LOGIC; | |
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118 | ||
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119 | SIGNAL clk_lock : STD_LOGIC; | |
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120 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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121 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; | |
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113 | 122 | |
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114 | 123 | BEGIN -- beh |
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115 | 124 | |
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125 | rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN); | |
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126 | ||
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127 | PROCESS (clk_50, rstn_50) | |
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128 | BEGIN -- PROCESS | |
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129 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |
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130 | clk_lock <= '0'; | |
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131 | clk_busy_counter <= (OTHERS => '0'); | |
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132 | nSRAM_BUSY_reg <= '0'; | |
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133 | ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge | |
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134 | nSRAM_BUSY_reg <= SRAM_nBUSY; | |
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135 | IF nSRAM_BUSY_reg = '1' AND SRAM_nBUSY = '0' THEN | |
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136 | IF clk_busy_counter = "1111" THEN | |
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137 | clk_lock <= '1'; | |
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138 | ELSE | |
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139 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); | |
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140 | END IF; | |
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141 | END IF; | |
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142 | END IF; | |
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143 | END PROCESS; | |
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144 | ||
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145 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); | |
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116 | 146 | ----------------------------------------------------------------------------- |
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117 | 147 | -- CLK |
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118 | 148 | ----------------------------------------------------------------------------- |
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119 | ||
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120 | ||
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121 | 149 | PROCESS(clk_50) |
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122 | 150 | BEGIN |
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123 | 151 | IF clk_50'EVENT AND clk_50 = '1' THEN |
@@ -126,15 +154,13 BEGIN -- beh | |||
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126 | 154 | END PROCESS; |
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127 | 155 | |
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128 | 156 | ----------------------------------------------------------------------------- |
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129 | ||
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130 | ||
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131 | PROCESS (clk_49, reset) | |
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157 | PROCESS (clk_49, rstn_49) | |
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132 | 158 | BEGIN -- PROCESS |
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133 |
IF r |
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159 | IF rstn_49 = '0' THEN -- asynchronous reset (active low) | |
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134 | 160 | I00_s <= '0'; |
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135 | 161 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge |
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136 |
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137 |
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162 | I00_s <= NOT I00_s; | |
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163 | END IF; | |
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138 | 164 | END PROCESS; |
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139 | 165 | |
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140 | 166 | nCTS1 <= '1'; |
@@ -143,7 +169,6 BEGIN -- beh | |||
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143 | 169 | SRAM_nCE2 <= SRAM_CE(1); |
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144 | 170 | |
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145 | 171 | |
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146 | ||
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147 | 172 | leon3_soc_1 : leon3_soc |
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148 | 173 | GENERIC MAP ( |
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149 | 174 | fabtech => apa3e, |
@@ -166,15 +191,20 BEGIN -- beh | |||
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166 | 191 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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167 | 192 | NB_APB_SLAVE => NB_APB_SLAVE, |
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168 | 193 | ADDRESS_SIZE => 19, |
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169 |
USES_IAP_MEMCTRLR => 1 |
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194 | USES_IAP_MEMCTRLR => 1, | |
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195 | BYPASS_EDAC_MEMCTRLR => '0', | |
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196 | SRBANKSZ => 8, | |
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197 | SLOW_TIMING_EMULATION => 1 | |
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198 | ) | |
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170 | 199 | PORT MAP ( |
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171 | 200 | clk => clk_25, |
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172 |
reset => r |
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201 | reset => rstn_25, | |
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173 | 202 | errorn => errorn, |
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174 | 203 | ahbrxd => TXD1, |
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175 | 204 | ahbtxd => RXD1, |
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176 | 205 | urxd1 => TXD2, |
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177 | 206 | utxd1 => RXD2, |
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207 | ||
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178 | 208 |
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179 | 209 | data => SRAM_DQ, |
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180 | 210 | nSRAM_BE0 => LED0, |
@@ -193,7 +223,9 BEGIN -- beh | |||
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193 | 223 | ahbo_s_ext => ahbo_s_ext, |
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194 | 224 | ahbi_m_ext => ahbi_m_ext, |
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195 | 225 | ahbo_m_ext => ahbo_m_ext); |
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226 | ||
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227 | ||
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196 | 228 |
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197 | 229 | |
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198 | ||
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199 | END beh; No newline at end of file | |
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230 | END beh; | |
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231 |
@@ -74,7 +74,8 ENTITY leon3_soc IS | |||
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74 | 74 | ADDRESS_SIZE : INTEGER := 19; |
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75 | 75 | USES_IAP_MEMCTRLR : INTEGER := 1; |
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76 | 76 | BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0'; |
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77 | SRBANKSZ : INTEGER := 8 | |
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77 | SRBANKSZ : INTEGER := 8; | |
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78 | SLOW_TIMING_EMULATION : integer := 0 | |
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78 | 79 | |
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79 | 80 | ); |
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80 | 81 | PORT ( |
@@ -250,7 +251,8 ARCHITECTURE Behavioral OF leon3_soc IS | |||
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250 | 251 | SIGNAL dsui : dsu_in_type; |
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251 | 252 | SIGNAL dsuo : dsu_out_type; |
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252 | 253 | ----------------------------------------------------------------------------- |
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253 | ||
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254 | SIGNAL memo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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255 | SIGNAL memi_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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254 | 256 | |
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255 | 257 | BEGIN |
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256 | 258 | |
@@ -461,16 +463,37 BEGIN | |||
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461 | 463 | memi.writen <= '1'; |
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462 | 464 | memi.wrn <= "1111"; |
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463 | 465 | memi.bwidth <= "10"; |
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464 | ||
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466 | ||
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467 | ----------------------------------------------------------------------------- | |
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468 | -- SLOW TIMING EMULATION | |
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469 | ----------------------------------------------------------------------------- | |
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470 | SLOW_TIMING_EMULATION_ON: IF SLOW_TIMING_EMULATION = 1 GENERATE | |
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471 | PROCESS (clkm, rstn) | |
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472 | BEGIN -- PROCESS | |
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473 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
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474 | memi.data <= (OTHERS => '0'); | |
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475 | memo_data <= (OTHERS => '0'); | |
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476 | ELSIF clkm'event AND clkm = '1' THEN -- rising clock edge | |
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477 | memi.data <= memi_data; | |
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478 | memo_data <= memo.data; | |
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479 | END IF; | |
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480 | END PROCESS; | |
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481 | END GENERATE SLOW_TIMING_EMULATION_ON; | |
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482 | SLOW_TIMING_EMULATION_OFF: IF SLOW_TIMING_EMULATION = 0 GENERATE | |
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483 | memi.data <= memi_data; | |
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484 | memo_data <= memo.data; | |
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485 | END GENERATE SLOW_TIMING_EMULATION_OFF; | |
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486 | ||
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465 | 487 |
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466 | 488 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR) |
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467 | 489 | PORT MAP ( |
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468 | 490 | data(31-i*8 DOWNTO 24-i*8), |
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469 |
memo |
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491 | memo_data(31-i*8 DOWNTO 24-i*8), | |
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470 | 492 | memo.bdrive(i), |
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471 |
memi |
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493 | memi_data(31-i*8 DOWNTO 24-i*8)); | |
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472 | 494 | END GENERATE; |
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473 | ||
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495 | ----------------------------------------------------------------------------- | |
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496 | ||
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474 | 497 |
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475 | 498 | PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2)); |
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476 | 499 | rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s); |
@@ -481,8 +504,6 BEGIN | |||
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481 | 504 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); |
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482 | 505 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); |
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483 | 506 | |
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484 | ||
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485 | ||
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486 | 507 | ---------------------------------------------------------------------- |
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487 | 508 | --- AHB CONTROLLER ------------------------------------------------- |
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488 | 509 | ---------------------------------------------------------------------- |
@@ -56,7 +56,8 PACKAGE lpp_leon3_soc_pkg IS | |||
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56 | 56 | ADDRESS_SIZE : INTEGER; |
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57 | 57 | USES_IAP_MEMCTRLR : INTEGER; |
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58 | 58 | BYPASS_EDAC_MEMCTRLR : STD_LOGIC; |
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59 | SRBANKSZ : INTEGER := 8 | |
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59 | SRBANKSZ : INTEGER := 8; | |
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60 | SLOW_TIMING_EMULATION : integer := 0 | |
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60 | 61 | ); |
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61 | 62 | PORT ( |
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62 | 63 | clk : IN STD_ULOGIC; |
@@ -41,8 +41,9 ENTITY lpp_lfr IS | |||
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41 | 41 | |
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42 | 42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153"; |
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43 | 43 | |
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44 | DEBUG_FORCE_DATA_DMA : INTEGER := 0 | |
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45 | ||
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44 | DEBUG_FORCE_DATA_DMA : INTEGER := 0; | |
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45 | RTL_DESIGN_LIGHT : INTEGER := 0; | |
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46 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15 | |
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46 | 47 | ); |
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47 | 48 | PORT ( |
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48 | 49 | clk : IN STD_LOGIC; |
@@ -189,7 +190,8 BEGIN | |||
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189 | 190 | ----------------------------------------------------------------------------- |
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190 | 191 | lpp_lfr_filter_1 : lpp_lfr_filter |
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191 | 192 | GENERIC MAP ( |
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192 |
Mem_use => Mem_use |
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193 | Mem_use => Mem_use, | |
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194 | RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT) | |
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193 | 195 | PORT MAP ( |
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194 | 196 | sample => sample_s, |
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195 | 197 | sample_val => sample_val, |
@@ -386,7 +388,8 BEGIN | |||
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386 | 388 | ----------------------------------------------------------------------------- |
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387 | 389 | lpp_lfr_ms_1 : lpp_lfr_ms |
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388 | 390 | GENERIC MAP ( |
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389 |
Mem_use => Mem_use |
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391 | Mem_use => Mem_use, | |
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392 | WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE) | |
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390 | 393 | PORT MAP ( |
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391 | 394 | clk => clk, |
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392 | 395 | rstn => rstn, |
@@ -45,7 +45,8 USE GRLIB.DMA2AHB_Package.ALL; | |||
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45 | 45 | |
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46 | 46 | ENTITY lpp_lfr_filter IS |
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47 | 47 | GENERIC( |
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48 | Mem_use : INTEGER := use_RAM | |
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48 | Mem_use : INTEGER := use_RAM; | |
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49 | RTL_DESIGN_LIGHT : INTEGER := 0 | |
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49 | 50 | ); |
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50 | 51 | PORT ( |
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51 | 52 | sample : IN Samples(7 DOWNTO 0); |
@@ -549,34 +550,41 BEGIN | |||
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549 | 550 | sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15); |
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550 | 551 | END GENERATE all_channel_sample_f_cic; |
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551 | 552 | |
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552 | ||
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553 | IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3 | |
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554 | GENERIC MAP ( | |
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555 | tech => 0, | |
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556 | Mem_use => Mem_use, | |
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557 | Sample_SZ => 18, | |
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558 | Coef_SZ => f2_f3_COEFFICIENT_SIZE, | |
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559 | Coef_Nb => f2_f3_CEL_NUMBER*5, | |
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560 | Coef_sel_SZ => 5, | |
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561 | Cels_count => f2_f3_CEL_NUMBER, | |
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562 | ChanelsCount => 6) | |
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563 | PORT MAP ( | |
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564 | rstn => rstn, | |
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565 | clk => clk, | |
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566 | virg_pos => f2_f3_POINT_POSITION, | |
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567 | coefs => coefs_iir_cel_f2_f3, | |
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553 | NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE | |
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554 | sample_f2_filter_val <= sample_f2_cic_val; | |
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555 | sample_f2_filter <= sample_f2_cic_filter; | |
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556 | sample_f3_filter_val <= sample_f3_cic_val; | |
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557 | sample_f3_filter <= sample_f3_cic_filter; | |
|
558 | END GENERATE NO_IIR_FILTER_f2_f3; | |
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568 | 559 | |
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569 | sample_in1_val => sample_f2_cic_val, | |
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570 | sample_in1 => sample_f2_cic_filter, | |
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571 | ||
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572 | sample_in2_val => sample_f3_cic_val, | |
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573 | sample_in2 => sample_f3_cic_filter, | |
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574 | ||
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575 | sample_out1_val => sample_f2_filter_val, | |
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576 | sample_out1 => sample_f2_filter, | |
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577 | sample_out2_val => sample_f3_filter_val, | |
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578 | sample_out2 => sample_f3_filter); | |
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579 | ||
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560 | YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE | |
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561 | IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3 | |
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562 | GENERIC MAP ( | |
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563 | tech => 0, | |
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564 | Mem_use => Mem_use, | |
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565 | Sample_SZ => 18, | |
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566 | Coef_SZ => f2_f3_COEFFICIENT_SIZE, | |
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567 | Coef_Nb => f2_f3_CEL_NUMBER*5, | |
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568 | Coef_sel_SZ => 5, | |
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569 | Cels_count => f2_f3_CEL_NUMBER, | |
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570 | ChanelsCount => 6) | |
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571 | PORT MAP ( | |
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572 | rstn => rstn, | |
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573 | clk => clk, | |
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574 | virg_pos => f2_f3_POINT_POSITION, | |
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575 | coefs => coefs_iir_cel_f2_f3, | |
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576 | ||
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577 | sample_in1_val => sample_f2_cic_val, | |
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578 | sample_in1 => sample_f2_cic_filter, | |
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579 | ||
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580 | sample_in2_val => sample_f3_cic_val, | |
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581 | sample_in2 => sample_f3_cic_filter, | |
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582 | ||
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583 | sample_out1_val => sample_f2_filter_val, | |
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584 | sample_out1 => sample_f2_filter, | |
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585 | sample_out2_val => sample_f3_filter_val, | |
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586 | sample_out2 => sample_f3_filter); | |
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587 | END GENERATE YES_IIR_FILTER_f2_f3; | |
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580 | 588 | |
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581 | 589 | all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE |
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582 | 590 | all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE |
@@ -584,7 +592,6 BEGIN | |||
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584 | 592 | sample_f3_cic_s(J,I) <= sample_f3_filter(J,I); |
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585 | 593 | END GENERATE all_bit_sample_f_filter; |
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586 | 594 | END GENERATE all_channel_sample_f_filter; |
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587 | ||
|
588 | 595 | |
|
589 | 596 | ----------------------------------------------------------------------------- |
|
590 | 597 |
@@ -17,7 +17,8 USE lpp.fft_components.ALL; | |||
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17 | 17 | |
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18 | 18 | ENTITY lpp_lfr_ms IS |
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19 | 19 | GENERIC ( |
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20 | Mem_use : INTEGER := use_RAM | |
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20 | Mem_use : INTEGER := use_RAM; | |
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21 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15 | |
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21 | 22 |
|
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22 | 23 | PORT ( |
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23 | 24 | clk : IN STD_LOGIC; |
@@ -710,6 +711,8 BEGIN | |||
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710 | 711 | -- FFT |
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711 | 712 | ----------------------------------------------------------------------------- |
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712 | 713 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT |
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714 | GENERIC MAP ( | |
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715 | WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE) | |
|
713 | 716 | PORT MAP ( |
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714 | 717 | clk => clk, |
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715 | 718 | rstn => rstn, |
@@ -16,6 +16,10 USE lpp.fft_components.ALL; | |||
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16 | 16 | USE lpp.window_function_pkg.ALL; |
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17 | 17 | |
|
18 | 18 | ENTITY lpp_lfr_ms_FFT IS |
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19 | GENERIC ( | |
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20 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15 | |
|
21 | ); | |
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22 | ||
|
19 | 23 |
|
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20 | 24 | clk : IN STD_LOGIC; |
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21 | 25 | rstn : IN STD_LOGIC; |
@@ -40,20 +44,34 ARCHITECTURE Behavioral OF lpp_lfr_ms_FF | |||
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40 | 44 | SIGNAL data_win : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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41 | 45 | SIGNAL data_win_valid : STD_LOGIC; |
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42 | 46 | |
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47 | SIGNAL data_in_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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48 | SIGNAL data_in_reg_valid : STD_LOGIC; | |
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49 | ||
|
43 | 50 | BEGIN |
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44 | 51 | |
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52 | PROCESS (clk, rstn) | |
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53 | BEGIN -- PROCESS | |
|
54 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
55 | data_in_reg <= (OTHERS => '0'); | |
|
56 | data_in_reg_valid <= '0'; | |
|
57 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
|
58 | data_in_reg <= sample_data; | |
|
59 | data_in_reg_valid <= sample_valid; | |
|
60 | END IF; | |
|
61 | END PROCESS; | |
|
62 | ||
|
45 | 63 |
|
|
46 | 64 | GENERIC MAP ( |
|
47 | 65 | SIZE_DATA => 16, |
|
48 |
SIZE_PARAM => |
|
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66 | SIZE_PARAM => WINDOWS_HAANNING_PARAM_SIZE, | |
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49 | 67 | NB_POINT_BY_WINDOW => 256) |
|
50 | 68 | PORT MAP ( |
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51 | 69 | clk => clk, |
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52 | 70 | rstn => rstn, |
|
53 | 71 | |
|
54 | 72 | restart_window => '0', |
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55 |
data_in => |
|
|
56 |
data_in_valid => |
|
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73 | data_in => data_in_reg, | |
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74 | data_in_valid => data_in_reg_valid, | |
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57 | 75 | |
|
58 | 76 | data_out => data_win, |
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59 | 77 | data_out_valid => data_win_valid); |
@@ -69,7 +69,8 PACKAGE lpp_lfr_pkg IS | |||
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69 | 69 | ----------------------------------------------------------------------------- |
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70 | 70 | COMPONENT lpp_lfr_ms |
|
71 | 71 | GENERIC ( |
|
72 |
Mem_use : INTEGER |
|
|
72 | Mem_use : INTEGER; | |
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73 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER); | |
|
73 | 74 | PORT ( |
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74 | 75 | clk : IN STD_LOGIC; |
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75 | 76 | rstn : IN STD_LOGIC; |
@@ -151,6 +152,8 PACKAGE lpp_lfr_pkg IS | |||
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151 | 152 | END COMPONENT; |
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152 | 153 | |
|
153 | 154 | COMPONENT lpp_lfr_ms_FFT |
|
155 | GENERIC ( | |
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156 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER); | |
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154 | 157 | PORT ( |
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155 | 158 | clk : IN STD_LOGIC; |
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156 | 159 | rstn : IN STD_LOGIC; |
@@ -167,7 +170,9 PACKAGE lpp_lfr_pkg IS | |||
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167 | 170 | |
|
168 | 171 | COMPONENT lpp_lfr_filter |
|
169 | 172 | GENERIC ( |
|
170 |
Mem_use : INTEGER |
|
|
173 | Mem_use : INTEGER; | |
|
174 | RTL_DESIGN_LIGHT : INTEGER | |
|
175 | ); | |
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171 | 176 | PORT ( |
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172 | 177 | sample : IN Samples(7 DOWNTO 0); |
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173 | 178 | sample_val : IN STD_LOGIC; |
@@ -210,7 +215,9 PACKAGE lpp_lfr_pkg IS | |||
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210 | 215 | pirq_wfp : INTEGER; |
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211 | 216 | hindex : INTEGER; |
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212 | 217 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0); |
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213 | DEBUG_FORCE_DATA_DMA : INTEGER | |
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218 | DEBUG_FORCE_DATA_DMA : INTEGER; | |
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219 | RTL_DESIGN_LIGHT : INTEGER; | |
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220 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER | |
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214 | 221 | ); |
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215 | 222 | PORT ( |
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216 | 223 | clk : IN STD_LOGIC; |
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