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LCD Driver fixed but AMBA interface still not implemented.
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19
20 20
21 21 | ABOUT
22 22 | ~~~~~
23 23
24 LPP's VHD_Lib is a VHDL library, which is target independent and includes a set of scripts for integrating into
24 LPP's VHD_Lib is a VHDL library which is target independent and includes a set of scripts for integrating into
25 25 gaisler's grlib and use its features. For setup read instalation section.
26 26
27 27
28 28 | REQUIREMENTS
29 29 | ~~~~~~~~~~~~
30 30
31 31 To use this library you need the grlib and linux shell or mingw for windows users.
32 32
33 33
34 34 | PERSONALIZATION
35 35 | ~~~~~~~~~~~~~~~
36 36
37 37 You can add your IPs to the library, see how_to_improve.pdf(Comming soon).
38 38
39 39
40 40 | INSTALLATION
41 41 | ~~~~~~~~~~~~
42 42
43 43 To set up the VHD_Lib follow this steps:
44 44 -download and setup the grlib
45 45 -create a VARIABLE called GRLIB with value the path to the grlib folder.
46 46 -untar the VHD_Lib and type "make Patch-GRLIB"
47 47 -now you can use the grlib's Makefiles and designs.
48 48 Please note that if you try "make" or "make help" you will see all targets and if the GRLIB variable is correct.
49 49
50 50
51 51 | HACKING
52 52 | ~~~~~~~
53 53
54 54 The first thing you should look at is the Makefile and then all scripts in "scripts" folder.
55 55
56 56
57 57 | LICENSE
58 58 | ~~~~~~~
59 59
60 60 All the programs used by the VHD_Lib are protected by their respective
61 61 license. They all are free software and most of them are covered by the
62 62 GNU General Public License.
63 63
64 The VHD_Lib itself, meaning all the scripts which are used in the building
65 process, are covered by the GNU General Public License.
66 64
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Package File Template
20 20 --
21 21 -- Purpose: This package defines supplemental types, subtypes,
22 22 -- constants, and functions
23 23
24 24
25 25 library IEEE;
26 26 use IEEE.STD_LOGIC_1164.all;
27 27 library lpp;
28 28 use lpp.amba_lcd_16x2_ctrlr.all;
29 29
30 30
31 31
32 32 package LCD_16x2_CFG is
33 33
34 34
35 35 constant ClearDSPLY : std_logic_vector(7 downto 0):= X"01";
36 36 constant FunctionSet : std_logic_vector(7 downto 0):= X"38";
37 37 constant RetHome : std_logic_vector(7 downto 0):= X"02";
38 38 constant SetEntryMode : std_logic_vector(7 downto 0):= X"06";
39 constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0C";
39 constant DSPL_CTRL : std_logic_vector(7 downto 0):= X"0E";
40 40
41 41 constant CursorON : std_logic_vector(7 downto 0):= X"0E";
42 42 constant CursorOFF : std_logic_vector(7 downto 0):= X"0C";
43 43
44 44 --===========================================================|
45 45 --======L C D D R I V E R T I M I N G C O D E=====|
46 46 --===========================================================|
47 47
48 48 constant Duration_4us : std_logic_vector(1 downto 0) := "00";
49 49 constant Duration_100us : std_logic_vector(1 downto 0) := "01";
50 50 constant Duration_4ms : std_logic_vector(1 downto 0) := "10";
51 51 constant Duration_20ms : std_logic_vector(1 downto 0) := "11";
52 52
53 53
54 54 end LCD_16x2_CFG;
55 55
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 ----------------------------------------------------------------------------------
20 20 -- Company:
21 21 -- Engineer:
22 22 --
23 23 -- Create Date: 10:09:57 10/13/2010
24 24 -- Design Name:
25 25 -- Module Name: LCD_2x16_DRIVER - Behavioral
26 26 -- Project Name:
27 27 -- Target Devices:
28 28 -- Tool versions:
29 29 -- Description:
30 30 --
31 31 -- Dependencies:
32 32 --
33 33 -- Revision:
34 34 -- Revision 0.01 - File Created
35 35 -- Additional Comments:
36 36 --
37 37 ----------------------------------------------------------------------------------
38
39 ---TDODO => Clean Enable pulse FSM
38 40 library IEEE;
39 41 use IEEE.STD_LOGIC_1164.ALL;
40 42 use IEEE.NUMERIC_STD.all;
41 43 library lpp;
42 44 use lpp.amba_lcd_16x2_ctrlr.all;
43
45 use lpp.lcd_16x2_cfg.all;
44 46
45 47 entity LCD_16x2_DRIVER is
46 48 generic(
47 OSC_Freq_MHz : integer:=60
49 OSC_Freq_KHz : integer:=50000
48 50 );
49 51 Port(
50 52 reset : in STD_LOGIC;
51 53 clk : in STD_LOGIC;
52 54 LCD_CTRL : out LCD_DRVR_CTRL_BUSS;
53 55 SYNCH : out LCD_DRVR_SYNCH_BUSS;
54 56 DRIVER_CMD : in LCD_DRVR_CMD_BUSS
55 57 );
56 58 end LCD_16x2_DRIVER;
57 59
58 60 architecture Behavioral of LCD_16x2_DRIVER is
59 61
62 type stateT is (idle,Enable0,Enable1,Enable2,tempo);
63 signal state : stateT;
64
65
66 constant trigger_4us : integer := 5;
67 constant trigger_100us : integer := 100;
68 constant trigger_4ms : integer := 4200;
69 constant trigger_20ms : integer := 20000;
70
71
72 signal i : integer :=0;
73 signal reset_i : std_logic := '0';
74 signal tempoTRIG : integer :=0;
75
76 signal clk_1us : std_logic;
77 signal clk_1us_reg : std_logic;
78
60 79 begin
61 80
81
82 CLK0: LCD_CLK_GENERATOR
83 generic map(OSC_Freq_KHz)
84 Port map( clk,reset,clk_1us);
85
86
87
88 process(clk_1us,reset_i)
89 begin
90 if reset_i = '0' then
91 i <= 0;
92 elsif clk_1us'event and clk_1us ='1' then
93 i <= i+1;
94 end if;
95 end process;
96
97 LCD_CTRL.LCD_RW <= '0';
98
99 process(clk,reset)
100 begin
101 if reset = '0' then
102 state <= idle;
103 LCD_CTRL.LCD_E <= '0';
104 SYNCH.DRVR_READY <= '0';
105 SYNCH.LCD_INITIALISED <= '0';
106 reset_i <= '0';
107 elsif clk'event and clk = '1' then
108 case state is
109 when idle =>
110 SYNCH.LCD_INITIALISED <= '1';
111 LCD_CTRL.LCD_E <= '0';
112 if DRIVER_CMD.Exec = '1' then
113 state <= Enable0;
114 reset_i <= '1';
115 SYNCH.DRVR_READY <= '0';
116 LCD_CTRL.LCD_DATA <= DRIVER_CMD.Word;
117 LCD_CTRL.LCD_RS <= DRIVER_CMD.CMD_Data;
118 case DRIVER_CMD.Duration is
119 when Duration_4us =>
120 tempoTRIG <= trigger_4us;
121 when Duration_100us =>
122 tempoTRIG <= trigger_100us;
123 when Duration_4ms =>
124 tempoTRIG <= trigger_4ms;
125 when Duration_20ms =>
126 tempoTRIG <= trigger_20ms;
127 when others =>
128 tempoTRIG <= trigger_20ms;
129 end case;
130 else
131 SYNCH.DRVR_READY <= '1';
132 reset_i <= '0';
133 end if;
134 when Enable0 =>
135 if i = 1 then
136 reset_i <= '0';
137 LCD_CTRL.LCD_E <= '1';
138 state <= Enable1;
139 else
140 reset_i <= '1';
141 LCD_CTRL.LCD_E <= '0';
142 end if;
143 when Enable1 =>
144 if i = 2 then
145 reset_i <= '0';
146 LCD_CTRL.LCD_E <= '0';
147 state <= Enable2;
148 else
149 reset_i <= '1';
150 LCD_CTRL.LCD_E <= '1';
151 end if;
152 when Enable2 =>
153 if i = 1 then
154 reset_i <= '0';
155 LCD_CTRL.LCD_E <= '0';
156 state <= tempo;
157 else
158 reset_i <= '1';
159 LCD_CTRL.LCD_E <= '0';
160 end if;
161 when tempo =>
162 if i = tempoTRIG then
163 reset_i <= '0';
164 state <= idle;
165 else
166 reset_i <= '1';
167 end if;
168 end case;
169 end if;
170 end process;
171
62 172 end Behavioral;
63 173
64 174
65 175
66 176
67 177
178
179
180
181
182
183
184
185
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 ----------------------------------------------------------------------------------
20 20 -- Company:
21 21 -- Engineer:
22 22 --
23 23 -- Create Date: 08:32:21 10/19/2010
24 24 -- Design Name:
25 25 -- Module Name: LCD_16x2_ENGINE - Behavioral
26 26 -- Project Name:
27 27 -- Target Devices:
28 28 -- Tool versions:
29 29 -- Description:
30 30 --
31 31 -- Dependencies:
32 32 --
33 33 -- Revision:
34 34 -- Revision 0.01 - File Created
35 35 -- Additional Comments:
36 36 --
37 37 ----------------------------------------------------------------------------------
38 38 library IEEE;
39 39 use IEEE.STD_LOGIC_1164.ALL;
40 40 use IEEE.NUMERIC_STD.ALL;
41 41
42 42 library lpp;
43 43 use lpp.amba_lcd_16x2_ctrlr.all;
44 44 use lpp.LCD_16x2_CFG.all;
45 45
46 46
47 47 entity LCD_16x2_ENGINE is
48 48 generic(OSC_freqKHz : integer := 50000);
49 49 Port ( clk : in STD_LOGIC;
50 50 reset : in STD_LOGIC;
51 51 DATA : in std_logic_vector(16*2*8-1 downto 0);
52 52 CMD : in std_logic_vector(10 downto 0);
53 53 Exec : in std_logic;
54 54 Ready : out std_logic;
55 55 LCD_CTRL : out LCD_DRVR_CTRL_BUSS
56 56 );
57 57 end LCD_16x2_ENGINE;
58 58
59 59 architecture ar_LCD_16x2_ENGINE of LCD_16x2_ENGINE is
60 60
61 61 constant ConfigTbl : LCD_CFG_Tbl :=(ClearDSPLY,FunctionSet,DSPL_CTRL,SetEntryMode,RetHome);
62 62
63 63
64 64
65 65 signal SYNCH : LCD_DRVR_SYNCH_BUSS;
66 66 signal DRIVER_CMD : LCD_DRVR_CMD_BUSS;
67 67 signal FRAME_CLK : std_logic;
68 68
69 69 signal FRAME_CLK_reg : std_logic;
70 70 signal RefreshFlag : std_logic;
71 71 signal CMD_Flag : std_logic;
72 72 signal Exec_Reg : std_logic;
73 73
74 74 type state_t is (INIT0,INIT1,INIT2,IDLE,Refresh,Refresh0,Refresh1,ReturnHome,GoLine2,GoLine2_0,ExecCMD0,ExecCMD1);
75 75 signal state : state_t;
76 76 signal i : integer range 0 to 32 := 0;
77 77
78 78
79 79
80 80 begin
81 81
82 82 Driver0 : LCD_16x2_DRIVER
83 83 generic map(OSC_freqKHz)
84 84 Port map(reset,clk,LCD_CTRL,SYNCH,DRIVER_CMD);
85 85
86 86 FRAME_CLK_GEN0 : FRAME_CLK_GEN
87 87 generic map(OSC_freqKHz)
88 88 Port map( clk,reset,FRAME_CLK);
89 89
90 90
91 91
92 92 process(reset,clk)
93 93 begin
94 94 if reset = '0' then
95 95 state <= INIT0;
96 96 Ready <= '0';
97 97 RefreshFlag <= '0';
98 98 i <= 0;
99 99 elsif clk'event and clk ='1' then
100 100 FRAME_CLK_reg <= FRAME_CLK;
101 101 Exec_Reg <= Exec;
102 102
103 103 if FRAME_CLK_reg = '0' and FRAME_CLK = '1' then
104 104 RefreshFlag <= '1';
105 105 elsif state = Refresh or state = Refresh0 or state = Refresh1 then
106 106 RefreshFlag <= '0';
107 107 end if;
108 108
109 109 if Exec_Reg = '0' and Exec = '1' then
110 110 CMD_Flag <= '1';
111 111 elsif state = ExecCMD0 or state = ExecCMD1 then
112 112 CMD_Flag <= '0';
113 113 end if;
114 114
115 115 case state is
116 116 when INIT0 =>
117 117 if SYNCH.DRVR_READY = '1' then
118 118 DRIVER_CMD.Exec <= '1';
119 119 DRIVER_CMD.Duration <= Duration_20ms;
120 120 DRIVER_CMD.CMD_Data <= '0';
121 121 DRIVER_CMD.Word <= ConfigTbl(i);
122 122 i <= i + 1;
123 123 state <= INIT1;
124 124 else
125 125 DRIVER_CMD.Exec <= '0';
126 126 end if;
127 127 when INIT1 =>
128 128 state <= INIT2;
129 129 DRIVER_CMD.Exec <= '0';
130 130 when INIT2 =>
131 131 if SYNCH.DRVR_READY = '1' then
132 132 if i = 5 then
133 133 state <= Idle;
134 134 else
135 135 state <= INIT0;
136 136 end if;
137 137 end if;
138 138 when Idle=>
139 139 DRIVER_CMD.Exec <= '0';
140 140 if RefreshFlag = '1' then
141 141 Ready <= '0';
142 142 state <= Refresh;
143 143 elsif CMD_Flag = '1' then
144 144 Ready <= '0';
145 145 state <= ExecCMD0;
146 146 else
147 147 Ready <= '1';
148 148 end if;
149 149 i <= 0;
150 150 when Refresh=>
151 151 if SYNCH.DRVR_READY = '1' then
152 152 DRIVER_CMD.Exec <= '1';
153 153 DRIVER_CMD.Duration <= Duration_100us;
154 154 DRIVER_CMD.CMD_Data <= '1';
155 155 DRIVER_CMD.Word <= DATA(i*8+7 downto i*8);
156 i <= i + 1;
157 156 state <= Refresh0;
158 157 else
159 158 DRIVER_CMD.Exec <= '0';
160 159 end if;
161 160 when Refresh0=>
161 i <= i + 1;
162 162 state <= Refresh1;
163 163 DRIVER_CMD.Exec <= '0';
164 164 when Refresh1=>
165 165 if SYNCH.DRVR_READY = '1' then
166 166 if i = 32 then
167 167 state <= ReturnHome;
168 168 elsif i = 16 then
169 169 state <= GoLine2;
170 170 else
171 171 state <= Refresh;
172 172 end if;
173 173 end if;
174 174
175 175 when ExecCMD0=>
176 176 if SYNCH.DRVR_READY = '1' then
177 177 DRIVER_CMD.Exec <= '1';
178 178 DRIVER_CMD.Duration <= CMD(9 downto 8);
179 179 DRIVER_CMD.CMD_Data <= '0';
180 180 DRIVER_CMD.Word <= CMD(7 downto 0);
181 181 state <= ExecCMD1;
182 182 else
183 183 DRIVER_CMD.Exec <= '0';
184 184 end if;
185 185
186 186 when ExecCMD1=>
187 187 state <= Idle;
188 188 DRIVER_CMD.Exec <= '0';
189 189
190 190 when GoLine2=>
191 191 if SYNCH.DRVR_READY = '1' then
192 192 DRIVER_CMD.Exec <= '1';
193 193 DRIVER_CMD.Duration <= Duration_100us;
194 194 DRIVER_CMD.CMD_Data <= '0';
195 195 DRIVER_CMD.Word <= X"C0";
196 196 state <= GoLine2_0;
197 197 else
198 198 DRIVER_CMD.Exec <= '0';
199 199 end if;
200 200 when GoLine2_0=>
201 201 state <= Refresh;
202 202 DRIVER_CMD.Exec <= '0';
203 203 when ReturnHome=>
204 204 if SYNCH.DRVR_READY = '1' then
205 205 DRIVER_CMD.Exec <= '1';
206 206 DRIVER_CMD.Duration <= Duration_4ms;
207 207 DRIVER_CMD.CMD_Data <= '0';
208 DRIVER_CMD.Word <= X"02";
208 DRIVER_CMD.Word <= RetHome;
209 209 state <= Idle;
210 210 else
211 211 DRIVER_CMD.Exec <= '0';
212 212 end if;
213 213 end case;
214 214 end if;
215 215 end process;
216 216
217 217
218 218 end ar_LCD_16x2_ENGINE;
219 219
220 220
221 221
222 222
223 223
224 224
225 225
226 226
227 227
228 228
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@@ -1,124 +1,123
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 ----------------------------------------------------------------------------------
20 20 -- Company:
21 21 -- Engineer:
22 22 --
23 23 -- Create Date: 08:44:41 10/14/2010
24 24 -- Design Name:
25 25 -- Module Name: Top_LCD - Behavioral
26 26 -- Project Name:
27 27 -- Target Devices:
28 28 -- Tool versions:
29 29 -- Description:
30 30 --
31 31 -- Dependencies:
32 32 --
33 33 -- Revision:
34 34 -- Revision 0.01 - File Created
35 35 -- Additional Comments:
36 36 --
37 37 ----------------------------------------------------------------------------------
38 38 library IEEE;
39 39 use IEEE.STD_LOGIC_1164.ALL;
40 40
41 41 library lpp;
42 42 use lpp.amba_lcd_16x2_ctrlr.all;
43 43 use lpp.LCD_16x2_CFG.all;
44 44
45 45
46 46 entity AMBA_LCD_16x2_DRIVER is
47 47 Port ( reset : in STD_LOGIC;
48 48 clk : in STD_LOGIC;
49 49 Bp0 : in STD_LOGIC;
50 50 Bp1 : in STD_LOGIC;
51 51 Bp2 : in STD_LOGIC;
52 52 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
53 53 LCD_RS : out STD_LOGIC;
54 54 LCD_RW : out STD_LOGIC;
55 55 LCD_E : out STD_LOGIC;
56 56 LCD_RET : out STD_LOGIC;
57 57 LCD_CS1 : out STD_LOGIC;
58 58 LCD_CS2 : out STD_LOGIC;
59 59 SF_CE0 : out std_logic
60 60 );
61 61 end AMBA_LCD_16x2_DRIVER;
62 62
63 63 architecture Behavioral of AMBA_LCD_16x2_DRIVER is
64 64
65 65 signal FramBUFF : STD_LOGIC_VECTOR(16*2*8-1 downto 0);
66 66 signal CMD : std_logic_vector(10 downto 0);
67 67 signal Exec : std_logic;
68 68 signal Ready : std_logic;
69 69 signal rst : std_logic;
70 70 signal LCD_CTRL : LCD_DRVR_CTRL_BUSS;
71 71
72 72 begin
73 73
74 74 LCD_data <= LCD_CTRL.LCD_DATA;
75 75 LCD_RS <= LCD_CTRL.LCD_RS;
76 76 LCD_RW <= LCD_CTRL.LCD_RW;
77 77 LCD_E <= LCD_CTRL.LCD_E;
78 78
79 79
80 80 LCD_RET <= '0';
81 81 LCD_CS1 <= '0';
82 82 LCD_CS2 <= '0';
83 83
84 84 SF_CE0 <= '1';
85 85
86 rst <= not reset;
87 86
88 87
89 88
90 89 Driver0 : LCD_16x2_ENGINE
91 90 generic map(50000)
92 Port map(clk,rst,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
91 Port map(clk,reset,FramBUFF,CMD,Exec,Ready,LCD_CTRL);
93 92
94 93 FramBUFF(0*8+7 downto 0*8) <= X"41" when Bp0 = '1' else
95 94 X"42" when Bp1 = '1' else
96 95 X"43" when Bp2 = '1' else
97 96 X"44";
98 97
99 98 FramBUFF(1*8+7 downto 1*8)<= X"46" when Bp0 = '1' else
100 99 X"47" when Bp1 = '1' else
101 100 X"48" when Bp2 = '1' else
102 101 X"49";
103 102
104 103
105 104 CMD(9 downto 0) <= Duration_100us & CursorON when Bp0 = '1' else
106 105 Duration_100us & CursorOFF;
107 106
108 107
109 108 Exec <= Bp1;
110 109
111 110 FramBUFF(2*8+7 downto 2*8) <= X"23";
112 111 FramBUFF(3*8+7 downto 3*8) <= X"66";
113 112 FramBUFF(4*8+7 downto 4*8) <= X"67";
114 113 FramBUFF(5*8+7 downto 5*8) <= X"68";
115 114 FramBUFF(17*8+7 downto 17*8) <= X"69";
116 115 --FramBUFF(16*2*8-1 downto 16) <= (others => '0');
117 116
118 117 end Behavioral;
119 118
120 119
121 120
122 121
123 122
124 123
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@@ -1,3 +1,4
1 ./dsp/iir_filter
2 1 ./general_purpose
3 2 ./lpp_amba
3 ./dsp/iir_filter
4 ./amba_lcd_16x2_ctrlr
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@@ -1,12 +1,12
1 1 APB_IIR_CEL.vhd
2 FILTER.vhd
3 FILTER_RAM_CTRLR.vhd
4 2 FILTERcfg.vhd
5 3 FilterCTRLR.vhd
4 FILTER_RAM_CTRLR.vhd
5 FILTER.vhd
6 6 IIR_CEL_CTRLR.vhd
7 7 IIR_CEL_FILTER.vhd
8 RAM.vhd
8 iir_filter.vhd
9 9 RAM_CEL.vhd
10 10 RAM_CTRLR2.vhd
11 RAM.vhd
11 12 Top_Filtre_IIR.vhd
12 iir_filter.vhd
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@@ -1,13 +1,13
1 Adder.vhd
1 2 ADDRcntr.vhd
2 3 ALU.vhd
3 Adder.vhd
4 MAC.vhd
4 general_purpose.vhd
5 5 MAC_CONTROLER.vhd
6 MAC_MUX2.vhd
6 7 MAC_MUX.vhd
7 MAC_MUX2.vhd
8 8 MAC_REG.vhd
9 MAC.vhd
10 Multiplier.vhd
9 11 MUX2.vhd
10 Multiplier.vhd
11 12 REG.vhd
12 13 Shifter.vhd
13 general_purpose.vhd
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