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Update SOLO_LFR_LFR-EM timings constraints...
Alexis Jeandet -
r674:b0efa9138022 default draft
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@@ -22,9 +22,9 create_clock -name { clk_25:Q } -period
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23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
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25 create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
25 create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
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27 create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
27 create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
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@@ -83,9 +83,9 set_min_delay 0.000 -from [get_clocks {
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84 ######## Delay Constraints ########
84 ######## Delay Constraints ########
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86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
86 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
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88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
88 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
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91 ######## Delay Constraints ########
91 ######## Delay Constraints ########
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