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1 | ################################################################################ |
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1 | ################################################################################ | |
2 | # SDC WRITER VERSION "3.1"; |
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2 | # SDC WRITER VERSION "3.1"; | |
3 | # DESIGN "LFR_EQM"; |
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3 | # DESIGN "LFR_EQM"; | |
4 | # Timing constraints scenario: "Primary"; |
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4 | # Timing constraints scenario: "Primary"; | |
5 | # DATE "Fri Apr 24 16:02:16 2015"; |
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5 | # DATE "Fri Apr 24 16:02:16 2015"; | |
6 | # VENDOR "Actel"; |
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6 | # VENDOR "Actel"; | |
7 | # PROGRAM "Actel Designer Software Release v9.1 SP5"; |
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7 | # PROGRAM "Actel Designer Software Release v9.1 SP5"; | |
8 | # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. |
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8 | # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. | |
9 | ################################################################################ |
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9 | ################################################################################ | |
10 |
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10 | |||
11 |
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11 | |||
12 | set sdc_version 1.7 |
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12 | set sdc_version 1.7 | |
13 |
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13 | |||
14 |
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14 | |||
15 | ######## Clock Constraints ######## |
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15 | ######## Clock Constraints ######## | |
16 |
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16 | |||
17 | create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz } |
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17 | create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz } | |
18 |
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18 | |||
19 | create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } |
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19 | create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } | |
20 |
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20 | |||
21 | create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } |
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21 | create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } | |
22 |
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22 | |||
23 | create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } |
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23 | create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } | |
24 |
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24 | |||
25 |
create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ |
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25 | create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } | |
26 |
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26 | |||
27 |
create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ |
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27 | create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } | |
28 |
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28 | |||
29 |
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29 | |||
30 |
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30 | |||
31 | ######## Generated Clock Constraints ######## |
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31 | ######## Generated Clock Constraints ######## | |
32 |
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32 | |||
33 |
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33 | |||
34 |
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34 | |||
35 | ######## Clock Source Latency Constraints ######### |
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35 | ######## Clock Source Latency Constraints ######### | |
36 |
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36 | |||
37 |
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37 | |||
38 |
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38 | |||
39 | ######## Input Delay Constraints ######## |
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39 | ######## Input Delay Constraints ######## | |
40 |
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40 | |||
41 | set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] |
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41 | set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
42 | set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ |
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42 | set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ | |
43 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ |
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43 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ | |
44 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ |
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44 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ | |
45 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] |
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45 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] | |
46 | set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ |
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46 | set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ | |
47 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ |
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47 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ | |
48 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ |
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48 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ | |
49 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] |
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49 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] | |
50 |
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50 | |||
51 | #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] |
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51 | #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] | |
52 | #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] |
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52 | #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |
53 | #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] |
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53 | #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |
54 |
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54 | |||
55 |
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55 | |||
56 |
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56 | |||
57 | ######## Output Delay Constraints ######## |
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57 | ######## Output Delay Constraints ######## | |
58 |
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58 | |||
59 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] |
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59 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
60 | set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ |
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60 | set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ | |
61 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ |
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61 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ | |
62 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ |
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62 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ | |
63 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] |
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63 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
64 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ |
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64 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ | |
65 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ |
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65 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ | |
66 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ |
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66 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ | |
67 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] |
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67 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |
68 |
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68 | |||
69 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] |
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69 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] | |
70 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ |
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70 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ | |
71 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ |
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71 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ | |
72 | address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ |
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72 | address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ | |
73 | address[7] address[8] address[9] }] |
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73 | address[7] address[8] address[9] }] | |
74 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ |
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74 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ | |
75 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ |
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75 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ | |
76 | address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ |
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76 | address[18] address[19] address[1] address[2] address[3] address[4] address[5] address[6] \ | |
77 | address[7] address[8] address[9] }] |
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77 | address[7] address[8] address[9] }] | |
78 |
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78 | |||
79 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }] |
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79 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }] | |
80 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] |
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80 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] | |
81 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] |
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81 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] | |
82 |
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82 | |||
83 |
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83 | |||
84 | ######## Delay Constraints ######## |
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84 | ######## Delay Constraints ######## | |
85 |
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85 | |||
86 |
set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ |
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86 | set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] | |
87 |
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87 | |||
88 |
set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ |
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88 | set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] | |
89 |
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89 | |||
90 |
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90 | |||
91 | ######## Delay Constraints ######## |
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91 | ######## Delay Constraints ######## | |
92 |
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92 | |||
93 |
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93 | |||
94 |
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94 | |||
95 | ######## Multicycle Constraints ######## |
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95 | ######## Multicycle Constraints ######## | |
96 |
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96 | |||
97 |
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97 | |||
98 |
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98 | |||
99 | ######## False Path Constraints ######## |
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99 | ######## False Path Constraints ######## | |
100 |
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100 | |||
101 |
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101 | |||
102 |
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102 | |||
103 | ######## Output load Constraints ######## |
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103 | ######## Output load Constraints ######## | |
104 |
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104 | |||
105 |
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105 | |||
106 |
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106 | |||
107 | ######## Disable Timing Constraints ######### |
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107 | ######## Disable Timing Constraints ######### | |
108 |
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108 | |||
109 |
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109 | |||
110 |
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110 | |||
111 | ######## Clock Uncertainty Constraints ######### |
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111 | ######## Clock Uncertainty Constraints ######### | |
112 |
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112 | |||
113 |
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113 | |||
114 |
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114 |
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