@@ -22,9 +22,9 create_clock -name { clk_25:Q } -period | |||
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22 | 22 | |
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23 | 23 | create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } |
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24 | 24 | |
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25 |
create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ |
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25 | create_clock -name { SPW1_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } | |
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26 | 26 | |
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27 |
create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ |
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27 | create_clock -name { SPW0_CLK } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } | |
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28 | 28 | |
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29 | 29 | |
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30 | 30 | |
@@ -83,9 +83,9 set_min_delay 0.000 -from [get_clocks { | |||
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83 | 83 | |
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84 | 84 | ######## Delay Constraints ######## |
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85 | 85 | |
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86 |
set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ |
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86 | set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] | |
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87 | 87 | |
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88 |
set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ |
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88 | set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks { spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] | |
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89 | 89 | |
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90 | 90 | |
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91 | 91 | ######## Delay Constraints ######## |
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