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update : suppression d'une erreur de min-delay au niveau du time managment
pellion -
r555:b0c415521d3c (MINI-LFR) WFP_MS-0-1-66 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 --
200 200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202 202
203 203 BEGIN -- beh
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- CLK
207 207 -----------------------------------------------------------------------------
208 208
209 209 --PROCESS(clk_50)
210 210 --BEGIN
211 211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 212 -- clk_50_s <= NOT clk_50_s;
213 213 -- END IF;
214 214 --END PROCESS;
215 215
216 216 --PROCESS(clk_50_s)
217 217 --BEGIN
218 218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 219 -- clk_25 <= NOT clk_25;
220 220 -- END IF;
221 221 --END PROCESS;
222 222
223 223 --PROCESS(clk_49)
224 224 --BEGIN
225 225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 226 -- clk_24 <= NOT clk_24;
227 227 -- END IF;
228 228 --END PROCESS;
229 229
230 230 --PROCESS(clk_25)
231 231 --BEGIN
232 232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 233 -- rstn_25 <= reset;
234 234 -- END IF;
235 235 --END PROCESS;
236 236
237 237 PROCESS (clk_50, reset)
238 238 BEGIN -- PROCESS
239 239 IF reset = '0' THEN -- asynchronous reset (active low)
240 240 clk_50_s <= '0';
241 241 rstn_50 <= '0';
242 242 rstn_50_d1 <= '0';
243 243 rstn_50_d2 <= '0';
244 244 rstn_50_d3 <= '0';
245 245
246 246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 247 clk_50_s <= NOT clk_50_s;
248 248 rstn_50_d1 <= '1';
249 249 rstn_50_d2 <= rstn_50_d1;
250 250 rstn_50_d3 <= rstn_50_d2;
251 251 rstn_50 <= rstn_50_d3;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 PROCESS (clk_50_s, rstn_50)
256 256 BEGIN -- PROCESS
257 257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 258 clk_25 <= '0';
259 259 rstn_25 <= '0';
260 260 rstn_25_d1 <= '0';
261 261 rstn_25_d2 <= '0';
262 262 rstn_25_d3 <= '0';
263 263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 264 clk_25 <= NOT clk_25;
265 265 rstn_25_d1 <= '1';
266 266 rstn_25_d2 <= rstn_25_d1;
267 267 rstn_25_d3 <= rstn_25_d2;
268 268 rstn_25 <= rstn_25_d3;
269 269 END IF;
270 270 END PROCESS;
271 271
272 272 PROCESS (clk_49, reset)
273 273 BEGIN -- PROCESS
274 274 IF reset = '0' THEN -- asynchronous reset (active low)
275 275 clk_24 <= '0';
276 276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 277 clk_24 <= NOT clk_24;
278 278 END IF;
279 279 END PROCESS;
280 280
281 281 -----------------------------------------------------------------------------
282 282
283 283 PROCESS (clk_25, rstn_25)
284 284 BEGIN -- PROCESS
285 285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 286 LED0 <= '0';
287 287 LED1 <= '0';
288 288 LED2 <= '0';
289 289 --IO1 <= '0';
290 290 --IO2 <= '1';
291 291 --IO3 <= '0';
292 292 --IO4 <= '0';
293 293 --IO5 <= '0';
294 294 --IO6 <= '0';
295 295 --IO7 <= '0';
296 296 --IO8 <= '0';
297 297 --IO9 <= '0';
298 298 --IO10 <= '0';
299 299 --IO11 <= '0';
300 300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 301 LED0 <= '0';
302 302 LED1 <= '1';
303 303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 304 --IO1 <= '1';
305 305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 306 --IO3 <= ADC_SDO(0);
307 307 --IO4 <= ADC_SDO(1);
308 308 --IO5 <= ADC_SDO(2);
309 309 --IO6 <= ADC_SDO(3);
310 310 --IO7 <= ADC_SDO(4);
311 311 --IO8 <= ADC_SDO(5);
312 312 --IO9 <= ADC_SDO(6);
313 313 --IO10 <= ADC_SDO(7);
314 314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 315 END IF;
316 316 END PROCESS;
317 317
318 318 PROCESS (clk_24, rstn_25)
319 319 BEGIN -- PROCESS
320 320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 321 I00_s <= '0';
322 322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 323 I00_s <= NOT I00_s;
324 324 END IF;
325 325 END PROCESS;
326 326 -- IO0 <= I00_s;
327 327
328 328 --UARTs
329 329 nCTS1 <= '1';
330 330 nCTS2 <= '1';
331 331 nDCD2 <= '1';
332 332
333 333 --
334 334
335 335 leon3_soc_1 : leon3_soc
336 336 GENERIC MAP (
337 337 fabtech => apa3e,
338 338 memtech => apa3e,
339 339 padtech => inferred,
340 340 clktech => inferred,
341 341 disas => 0,
342 342 dbguart => 0,
343 343 pclow => 2,
344 344 clk_freq => 25000,
345 345 IS_RADHARD => 0,
346 346 NB_CPU => 1,
347 347 ENABLE_FPU => 1,
348 348 FPU_NETLIST => 0,
349 349 ENABLE_DSU => 1,
350 350 ENABLE_AHB_UART => 1,
351 351 ENABLE_APB_UART => 1,
352 352 ENABLE_IRQMP => 1,
353 353 ENABLE_GPT => 1,
354 354 NB_AHB_MASTER => NB_AHB_MASTER,
355 355 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 356 NB_APB_SLAVE => NB_APB_SLAVE,
357 357 ADDRESS_SIZE => 20,
358 358 USES_IAP_MEMCTRLR => 0)
359 359 PORT MAP (
360 360 clk => clk_25,
361 361 reset => rstn_25,
362 362 errorn => errorn,
363 363 ahbrxd => TXD1,
364 364 ahbtxd => RXD1,
365 365 urxd1 => TXD2,
366 366 utxd1 => RXD2,
367 367 address => SRAM_A,
368 368 data => SRAM_DQ,
369 369 nSRAM_BE0 => SRAM_nBE(0),
370 370 nSRAM_BE1 => SRAM_nBE(1),
371 371 nSRAM_BE2 => SRAM_nBE(2),
372 372 nSRAM_BE3 => SRAM_nBE(3),
373 373 nSRAM_WE => SRAM_nWE,
374 374 nSRAM_CE => SRAM_CE_s,
375 375 nSRAM_OE => SRAM_nOE,
376 376 nSRAM_READY => '0',
377 377 SRAM_MBE => OPEN,
378 378 apbi_ext => apbi_ext,
379 379 apbo_ext => apbo_ext,
380 380 ahbi_s_ext => ahbi_s_ext,
381 381 ahbo_s_ext => ahbo_s_ext,
382 382 ahbi_m_ext => ahbi_m_ext,
383 383 ahbo_m_ext => ahbo_m_ext);
384 384
385 385 SRAM_CE <= SRAM_CE_s(0);
386 386 -------------------------------------------------------------------------------
387 387 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
388 388 -------------------------------------------------------------------------------
389 389 apb_lfr_management_1 : apb_lfr_management
390 390 GENERIC MAP (
391 391 tech => apa3e,
392 392 pindex => 6,
393 393 paddr => 6,
394 394 pmask => 16#fff#,
395 395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 397 PORT MAP (
398 398 clk25MHz => clk_25,
399 399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 400 resetn => rstn_25,
401 401 grspw_tick => swno.tickout,
402 402 apbi => apbi_ext,
403 403 apbo => apbo_ext(6),
404 404 HK_sample => sample_hk,
405 405 HK_val => sample_val,
406 406 HK_sel => HK_SEL,
407 407 DAC_SDO => OPEN,
408 408 DAC_SCK => OPEN,
409 409 DAC_SYNC => OPEN,
410 410 DAC_CAL_EN => OPEN,
411 411 coarse_time => coarse_time,
412 412 fine_time => fine_time,
413 413 LFR_soft_rstn => LFR_soft_rstn
414 414 );
415 415
416 416 -----------------------------------------------------------------------
417 417 --- SpaceWire --------------------------------------------------------
418 418 -----------------------------------------------------------------------
419 419
420 420 SPW_EN <= '1';
421 421
422 422 spw_clk <= clk_50_s;
423 423 spw_rxtxclk <= spw_clk;
424 424 spw_rxclkn <= NOT spw_rxtxclk;
425 425
426 426 -- PADS for SPW1
427 427 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
428 428 PORT MAP (SPW_NOM_DIN, dtmp(0));
429 429 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_NOM_SIN, stmp(0));
431 431 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
432 432 PORT MAP (SPW_NOM_DOUT, swno.d(0));
433 433 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
434 434 PORT MAP (SPW_NOM_SOUT, swno.s(0));
435 435 -- PADS FOR SPW2
436 436 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
437 437 PORT MAP (SPW_RED_SIN, dtmp(1));
438 438 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
439 439 PORT MAP (SPW_RED_DIN, stmp(1));
440 440 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
441 441 PORT MAP (SPW_RED_DOUT, swno.d(1));
442 442 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
443 443 PORT MAP (SPW_RED_SOUT, swno.s(1));
444 444
445 445 -- GRSPW PHY
446 446 --spw1_input: if CFG_SPW_GRSPW = 1 generate
447 447 spw_inputloop : FOR j IN 0 TO 1 GENERATE
448 448 spw_phy0 : grspw_phy
449 449 GENERIC MAP(
450 450 tech => apa3e,
451 451 rxclkbuftype => 1,
452 452 scantest => 0)
453 453 PORT MAP(
454 454 rxrst => swno.rxrst,
455 455 di => dtmp(j),
456 456 si => stmp(j),
457 457 rxclko => spw_rxclk(j),
458 458 do => swni.d(j),
459 459 ndo => swni.nd(j*5+4 DOWNTO j*5),
460 460 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
461 461 END GENERATE spw_inputloop;
462 462
463 463 swni.rmapnodeaddr <= (OTHERS => '0');
464 464
465 465 -- SPW core
466 466 sw0 : grspwm GENERIC MAP(
467 467 tech => apa3e,
468 468 hindex => 1,
469 469 pindex => 5,
470 470 paddr => 5,
471 471 pirq => 11,
472 472 sysfreq => 25000, -- CPU_FREQ
473 473 rmap => 1,
474 474 rmapcrc => 1,
475 475 fifosize1 => 16,
476 476 fifosize2 => 16,
477 477 rxclkbuftype => 1,
478 478 rxunaligned => 0,
479 479 rmapbufs => 4,
480 480 ft => 0,
481 481 netlist => 0,
482 482 ports => 2,
483 483 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
484 484 memtech => apa3e,
485 485 destkey => 2,
486 486 spwcore => 1
487 487 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
488 488 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
489 489 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
490 490 )
491 491 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
492 492 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
493 493 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
494 494 swni, swno);
495 495
496 496 swni.tickin <= '0';
497 497 swni.rmapen <= '1';
498 498 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
499 499 swni.tickinraw <= '0';
500 500 swni.timein <= (OTHERS => '0');
501 501 swni.dcrstval <= (OTHERS => '0');
502 502 swni.timerrstval <= (OTHERS => '0');
503 503
504 504 -------------------------------------------------------------------------------
505 505 -- LFR ------------------------------------------------------------------------
506 506 -------------------------------------------------------------------------------
507 507
508 508
509 509 LFR_rstn <= LFR_soft_rstn AND rstn_25;
510 510 --LFR_rstn <= rstn_25;
511 511
512 512 lpp_lfr_1 : lpp_lfr
513 513 GENERIC MAP (
514 514 Mem_use => use_RAM,
515 515 nb_data_by_buffer_size => 32,
516 516 nb_snapshot_param_size => 32,
517 517 delta_vector_size => 32,
518 518 delta_vector_size_f0_2 => 7, -- log2(96)
519 519 pindex => 15,
520 520 paddr => 15,
521 521 pmask => 16#fff#,
522 522 pirq_ms => 6,
523 523 pirq_wfp => 14,
524 524 hindex => 2,
525 top_lfr_version => X"000141") -- aa.bb.cc version
525 top_lfr_version => X"000142") -- aa.bb.cc version
526 526 PORT MAP (
527 527 clk => clk_25,
528 528 rstn => LFR_rstn,
529 529 sample_B => sample_s(2 DOWNTO 0),
530 530 sample_E => sample_s(7 DOWNTO 3),
531 531 sample_val => sample_val,
532 532 apbi => apbi_ext,
533 533 apbo => apbo_ext(15),
534 534 ahbi => ahbi_m_ext,
535 535 ahbo => ahbo_m_ext(2),
536 536 coarse_time => coarse_time,
537 537 fine_time => fine_time,
538 538 data_shaping_BW => bias_fail_sw_sig,
539 539 debug_vector => lfr_debug_vector,
540 540 debug_vector_ms => lfr_debug_vector_ms
541 541 );
542 542
543 543 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
544 544 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
545 545 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
546 546 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
547 547 IO0 <= rstn_25;
548 548 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
549 549 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
550 550 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
551 551 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
552 552 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
553 553 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
554 554 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
555 555
556 556 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
557 557 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
558 558 END GENERATE all_sample;
559 559
560 560 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
561 561 GENERIC MAP(
562 562 ChannelCount => 8,
563 563 SampleNbBits => 14,
564 564 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
565 565 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
566 566 PORT MAP (
567 567 -- CONV
568 568 cnv_clk => clk_24,
569 569 cnv_rstn => rstn_25,
570 570 cnv => ADC_nCS_sig,
571 571 -- DATA
572 572 clk => clk_25,
573 573 rstn => rstn_25,
574 574 sck => ADC_CLK_sig,
575 575 sdo => ADC_SDO_sig,
576 576 -- SAMPLE
577 577 sample => sample,
578 578 sample_val => sample_val);
579 579
580 580 --IO10 <= ADC_SDO_sig(5);
581 581 --IO9 <= ADC_SDO_sig(4);
582 582 --IO8 <= ADC_SDO_sig(3);
583 583
584 584 ADC_nCS <= ADC_nCS_sig;
585 585 ADC_CLK <= ADC_CLK_sig;
586 586 ADC_SDO_sig <= ADC_SDO;
587 587
588 588 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
589 589 "0010001000100010" WHEN HK_SEL = "01" ELSE
590 590 "0100010001000100" WHEN HK_SEL = "10" ELSE
591 591 (OTHERS => '0');
592 592
593 593
594 594 ----------------------------------------------------------------------
595 595 --- GPIO -----------------------------------------------------------
596 596 ----------------------------------------------------------------------
597 597
598 598 grgpio0 : grgpio
599 599 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
600 600 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
601 601
602 602 gpioi.sig_en <= (OTHERS => '0');
603 603 gpioi.sig_in <= (OTHERS => '0');
604 604 gpioi.din <= (OTHERS => '0');
605 605 --pio_pad_0 : iopad
606 606 -- GENERIC MAP (tech => CFG_PADTECH)
607 607 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
608 608 --pio_pad_1 : iopad
609 609 -- GENERIC MAP (tech => CFG_PADTECH)
610 610 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
611 611 --pio_pad_2 : iopad
612 612 -- GENERIC MAP (tech => CFG_PADTECH)
613 613 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
614 614 --pio_pad_3 : iopad
615 615 -- GENERIC MAP (tech => CFG_PADTECH)
616 616 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
617 617 --pio_pad_4 : iopad
618 618 -- GENERIC MAP (tech => CFG_PADTECH)
619 619 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
620 620 --pio_pad_5 : iopad
621 621 -- GENERIC MAP (tech => CFG_PADTECH)
622 622 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
623 623 --pio_pad_6 : iopad
624 624 -- GENERIC MAP (tech => CFG_PADTECH)
625 625 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
626 626 --pio_pad_7 : iopad
627 627 -- GENERIC MAP (tech => CFG_PADTECH)
628 628 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
629 629
630 630 PROCESS (clk_25, rstn_25)
631 631 BEGIN -- PROCESS
632 632 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
633 633 -- --IO0 <= '0';
634 634 -- IO1 <= '0';
635 635 -- IO2 <= '0';
636 636 -- IO3 <= '0';
637 637 -- IO4 <= '0';
638 638 -- IO5 <= '0';
639 639 -- IO6 <= '0';
640 640 -- IO7 <= '0';
641 641 IO8 <= '0';
642 642 IO9 <= '0';
643 643 IO10 <= '0';
644 644 IO11 <= '0';
645 645 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
646 646 CASE gpioo.dout(2 DOWNTO 0) IS
647 647 WHEN "011" =>
648 648 -- --IO0 <= observation_reg(0 );
649 649 -- IO1 <= observation_reg(1 );
650 650 -- IO2 <= observation_reg(2 );
651 651 -- IO3 <= observation_reg(3 );
652 652 -- IO4 <= observation_reg(4 );
653 653 -- IO5 <= observation_reg(5 );
654 654 -- IO6 <= observation_reg(6 );
655 655 -- IO7 <= observation_reg(7 );
656 656 IO8 <= observation_reg(8);
657 657 IO9 <= observation_reg(9);
658 658 IO10 <= observation_reg(10);
659 659 IO11 <= observation_reg(11);
660 660 WHEN "001" =>
661 661 -- --IO0 <= observation_reg(0 + 12);
662 662 -- IO1 <= observation_reg(1 + 12);
663 663 -- IO2 <= observation_reg(2 + 12);
664 664 -- IO3 <= observation_reg(3 + 12);
665 665 -- IO4 <= observation_reg(4 + 12);
666 666 -- IO5 <= observation_reg(5 + 12);
667 667 -- IO6 <= observation_reg(6 + 12);
668 668 -- IO7 <= observation_reg(7 + 12);
669 669 IO8 <= observation_reg(8 + 12);
670 670 IO9 <= observation_reg(9 + 12);
671 671 IO10 <= observation_reg(10 + 12);
672 672 IO11 <= observation_reg(11 + 12);
673 673 WHEN "010" =>
674 674 -- --IO0 <= observation_reg(0 + 12 + 12);
675 675 -- IO1 <= observation_reg(1 + 12 + 12);
676 676 -- IO2 <= observation_reg(2 + 12 + 12);
677 677 -- IO3 <= observation_reg(3 + 12 + 12);
678 678 -- IO4 <= observation_reg(4 + 12 + 12);
679 679 -- IO5 <= observation_reg(5 + 12 + 12);
680 680 -- IO6 <= observation_reg(6 + 12 + 12);
681 681 -- IO7 <= observation_reg(7 + 12 + 12);
682 682 IO8 <= '0';
683 683 IO9 <= '0';
684 684 IO10 <= '0';
685 685 IO11 <= '0';
686 686 WHEN "000" =>
687 687 -- --IO0 <= observation_vector_0(0 );
688 688 -- IO1 <= observation_vector_0(1 );
689 689 -- IO2 <= observation_vector_0(2 );
690 690 -- IO3 <= observation_vector_0(3 );
691 691 -- IO4 <= observation_vector_0(4 );
692 692 -- IO5 <= observation_vector_0(5 );
693 693 -- IO6 <= observation_vector_0(6 );
694 694 -- IO7 <= observation_vector_0(7 );
695 695 IO8 <= observation_vector_0(8);
696 696 IO9 <= observation_vector_0(9);
697 697 IO10 <= observation_vector_0(10);
698 698 IO11 <= observation_vector_0(11);
699 699 WHEN "100" =>
700 700 -- --IO0 <= observation_vector_1(0 );
701 701 -- IO1 <= observation_vector_1(1 );
702 702 -- IO2 <= observation_vector_1(2 );
703 703 -- IO3 <= observation_vector_1(3 );
704 704 -- IO4 <= observation_vector_1(4 );
705 705 -- IO5 <= observation_vector_1(5 );
706 706 -- IO6 <= observation_vector_1(6 );
707 707 -- IO7 <= observation_vector_1(7 );
708 708 IO8 <= observation_vector_1(8);
709 709 IO9 <= observation_vector_1(9);
710 710 IO10 <= observation_vector_1(10);
711 711 IO11 <= observation_vector_1(11);
712 712 WHEN OTHERS => NULL;
713 713 END CASE;
714 714
715 715 END IF;
716 716 END PROCESS;
717 717 -----------------------------------------------------------------------------
718 718 --
719 719 -----------------------------------------------------------------------------
720 720 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
721 721 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
722 722 apbo_ext(I) <= apb_none;
723 723 END GENERATE apbo_ext_not_used;
724 724 END GENERATE all_apbo_ext;
725 725
726 726
727 727 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
728 728 ahbo_s_ext(I) <= ahbs_none;
729 729 END GENERATE all_ahbo_ext;
730 730
731 731 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
732 732 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
733 733 ahbo_m_ext(I) <= ahbm_none;
734 734 END GENERATE ahbo_m_ext_not_used;
735 735 END GENERATE all_ahbo_m_ext;
736 736
737 737 END beh;
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@@ -1,109 +1,123
1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 3 USE IEEE.NUMERIC_STD.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.general_purpose.ALL;
7 7
8 8 ENTITY coarse_time_counter IS
9 9 GENERIC (
10 10 NB_SECOND_DESYNC : INTEGER := 60);
11 11
12 12 PORT (
13 13 clk : IN STD_LOGIC;
14 14 rstn : IN STD_LOGIC;
15 15
16 16 tick : IN STD_LOGIC;
17 17 set_TCU : IN STD_LOGIC;
18 18 new_TCU : IN STD_LOGIC;
19 19 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
20 20 CT_add1 : IN STD_LOGIC;
21 21 fsm_desync : IN STD_LOGIC;
22 22 FT_max : IN STD_LOGIC;
23 23
24 24 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
25 25 coarse_time_new : OUT STD_LOGIC
26 26
27 27 );
28 28
29 29 END coarse_time_counter;
30 30
31 31 ARCHITECTURE beh OF coarse_time_counter IS
32 32
33 33 SIGNAL add1_bit31 : STD_LOGIC;
34 34 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
35 35 SIGNAL coarse_time_new_counter : STD_LOGIC;
36 36 SIGNAL coarse_time_31 : STD_LOGIC;
37 37 SIGNAL coarse_time_31_reg : STD_LOGIC;
38 38
39 39 SIGNAL set_synchronized : STD_LOGIC;
40 40 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
41 41
42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 ;
43 SIGNAL set_TCU_reg : STD_LOGIC;
44
43 45 BEGIN -- beh
44 46
45 47 -----------------------------------------------------------------------------
46 48 -- COARSE_TIME( 30 DOWNTO 0)
47 49 -----------------------------------------------------------------------------
48 50 counter_1 : general_counter
49 51 GENERIC MAP (
50 52 CYCLIC => '1',
51 53 NB_BITS_COUNTER => 31,
52 54 RST_VALUE => 0)
53 55 PORT MAP (
54 56 clk => clk,
55 57 rstn => rstn,
56 58 MAX_VALUE => "111" & X"FFFFFFF" ,
57 set => set_TCU,
59 set => set_TCU_reg,
58 60 set_value => set_TCU_value(30 DOWNTO 0),
59 61 add1 => CT_add1,
60 62 counter => coarse_time(30 DOWNTO 0));
61 63
62 64
63 65 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
64 66
65 67 -----------------------------------------------------------------------------
66 68 -- COARSE_TIME(31)
67 69 -----------------------------------------------------------------------------
68 70
69 71 --set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
70 72 --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
71 73 -- (OTHERS => '0');
72 74 set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
73 75 set_synchronized_value <= (OTHERS => '0');
74 76
75 77 counter_2 : general_counter
76 78 GENERIC MAP (
77 79 CYCLIC => '0',
78 80 NB_BITS_COUNTER => 6,
79 81 RST_VALUE => NB_SECOND_DESYNC
80 82 )
81 83 PORT MAP (
82 84 clk => clk,
83 85 rstn => rstn,
84 86 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
85 87 set => set_synchronized,
86 88 set_value => set_synchronized_value,
87 89 add1 => add1_bit31,
88 90 counter => nb_second_counter);
89 91
90 92 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
91 93 coarse_time(31) <= coarse_time_31;
92 94 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
93 95
94 96 PROCESS (clk, rstn)
95 97 BEGIN -- PROCESS
96 98 IF rstn = '0' THEN -- asynchronous reset (active low)
97 99 coarse_time_new_counter <= '0';
98 100 coarse_time_31_reg <= '0';
99 101 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
100 102 coarse_time_31_reg <= coarse_time_31;
101 IF set_TCU = '1' OR CT_add1 = '1' THEN
103 IF set_TCU_reg = '1' OR CT_add1 = '1' THEN
102 104 coarse_time_new_counter <= '1';
103 105 ELSE
104 106 coarse_time_new_counter <= '0';
105 107 END IF;
106 108 END IF;
107 109 END PROCESS;
108 110
111 -----------------------------------------------------------------------------
112 -- Just to try to limit the constraint
113 PROCESS (clk, rstn)
114 BEGIN -- PROCESS
115 IF rstn = '0' THEN -- asynchronous reset (active low)
116 set_TCU_reg <= '0';
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 set_TCU_reg <= set_TCU;
119 END IF;
120 END PROCESS;
121 -----------------------------------------------------------------------------
122
109 123 END beh; No newline at end of file
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@@ -1,1249 +1,1248
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5
6 6 LIBRARY lpp;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.iir_filter.ALL;
9 9 USE lpp.spectral_matrix_package.ALL;
10 10 USE lpp.lpp_dma_pkg.ALL;
11 11 USE lpp.lpp_Header.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_matrix.ALL;
14 14 USE lpp.lpp_lfr_pkg.ALL;
15 15 USE lpp.lpp_fft.ALL;
16 16 USE lpp.fft_components.ALL;
17 17
18 18 ENTITY lpp_lfr_ms IS
19 19 GENERIC (
20 20 Mem_use : INTEGER := use_RAM
21 21 );
22 22 PORT (
23 23 clk : IN STD_LOGIC;
24 24 rstn : IN STD_LOGIC;
25 25 run : IN STD_LOGIC;
26 26
27 27 ---------------------------------------------------------------------------
28 28 -- DATA INPUT
29 29 ---------------------------------------------------------------------------
30 30 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
31 31 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
32 32 --fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
33 33 --
34 34 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 35 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 36 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
37 37 --
38 38 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
41 41 --
42 42 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 43 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 44 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
45 45
46 46 ---------------------------------------------------------------------------
47 47 -- DMA
48 48 ---------------------------------------------------------------------------
49 49 dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
50 50 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
51 51 dma_fifo_ren : IN STD_LOGIC; --TODO
52 52 dma_buffer_new : OUT STD_LOGIC; --TODOx
53 53 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
54 54 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
55 55 dma_buffer_full : IN STD_LOGIC; --TODO
56 56 dma_buffer_full_err : IN STD_LOGIC; --TODO
57 57
58 58 -- Reg out
59 59 ready_matrix_f0 : OUT STD_LOGIC; -- TODO
60 60 ready_matrix_f1 : OUT STD_LOGIC; -- TODO
61 61 ready_matrix_f2 : OUT STD_LOGIC; -- TODO
62 62 -- error_bad_component_error : OUT STD_LOGIC; -- TODO
63 63 error_buffer_full : OUT STD_LOGIC; -- TODO
64 64 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
65 65
66 66 -- Reg In
67 67 status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
68 68 status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
69 69 status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
70 70
71 71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
74 74
75 75 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
76 76 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
77 77 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
78 78
79 79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
80 80 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
81 81 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
82 82 ---------------------------------------------------------------------------
83 83 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
84 84 );
85 85 END;
86 86
87 87 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
88 88
89 89 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 90 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 91 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94
95 95 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 96 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 97 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 98 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100
101 101 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102 102 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 103 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 104 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 105
106 106 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107
108 108 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
109 109 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 110 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 111 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 112
113 113 SIGNAL error_wen_f0 : STD_LOGIC;
114 114 SIGNAL error_wen_f1 : STD_LOGIC;
115 115 SIGNAL error_wen_f2 : STD_LOGIC;
116 116
117 117 SIGNAL one_sample_f1_full : STD_LOGIC;
118 118 SIGNAL one_sample_f1_wen : STD_LOGIC;
119 119 SIGNAL one_sample_f2_full : STD_LOGIC;
120 120 SIGNAL one_sample_f2_wen : STD_LOGIC;
121 121
122 122 -----------------------------------------------------------------------------
123 123 -- FSM / SWITCH SELECT CHANNEL
124 124 -----------------------------------------------------------------------------
125 125 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
126 126 SIGNAL state_fsm_select_channel : fsm_select_channel;
127 127 -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
128 128 SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 129 SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 130
131 131 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
133 133 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 134 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
135 135
136 136 -----------------------------------------------------------------------------
137 137 -- FSM LOAD FFT
138 138 -----------------------------------------------------------------------------
139 139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, WAIT_STATE, WAIT_STATE_2);
140 140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
141 141 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
142 142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
144 144
145 145 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
146 146 SIGNAL sample_load : STD_LOGIC;
147 147 SIGNAL sample_valid : STD_LOGIC;
148 148 SIGNAL sample_valid_r : STD_LOGIC;
149 SIGNAL sample_valid_delay : STD_LOGIC;
150 149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
151 150
152 151
153 152 -----------------------------------------------------------------------------
154 153 -- FFT
155 154 -----------------------------------------------------------------------------
156 155 SIGNAL fft_read : STD_LOGIC;
157 156 SIGNAL fft_pong : STD_LOGIC;
158 157 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
159 158 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
160 159 SIGNAL fft_data_valid : STD_LOGIC;
161 160 SIGNAL fft_data_valid_pre : STD_LOGIC;
162 161 SIGNAL fft_ready : STD_LOGIC;
163 162 -----------------------------------------------------------------------------
164 163 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 164 -----------------------------------------------------------------------------
166 165 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
167 166 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
168 167 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 168 SIGNAL current_fifo_empty : STD_LOGIC;
170 169 SIGNAL current_fifo_locked : STD_LOGIC;
171 170 SIGNAL current_fifo_full : STD_LOGIC;
172 171 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 172
174 173 -----------------------------------------------------------------------------
175 174 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
176 175 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
177 176 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
178 177 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
179 178 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
180 179 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
181 180 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
182 181 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
183 182 -----------------------------------------------------------------------------
184 183 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
185 184 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
186 185 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
187 186
188 187 SIGNAL SM_correlation_start : STD_LOGIC;
189 188 SIGNAL SM_correlation_auto : STD_LOGIC;
190 189 SIGNAL SM_correlation_done : STD_LOGIC;
191 190 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
192 191 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
193 192 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
194 193 SIGNAL SM_correlation_begin : STD_LOGIC;
195 194
196 195 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
197 196 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 197 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
199 198
200 199 SIGNAL current_matrix_write : STD_LOGIC;
201 200 SIGNAL current_matrix_wait_empty : STD_LOGIC;
202 201 -----------------------------------------------------------------------------
203 202 SIGNAL fifo_0_ready : STD_LOGIC;
204 203 SIGNAL fifo_1_ready : STD_LOGIC;
205 204 SIGNAL fifo_ongoing : STD_LOGIC;
206 205 SIGNAL fifo_ongoing_reg : STD_LOGIC;
207 206
208 207 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
209 208 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
210 209 SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC;
211 210 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 211 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
213 212 -----------------------------------------------------------------------------
214 213 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
215 214 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
216 215 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
217 216 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
218 217 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
219 218 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
220 219 SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0);
221 220
222 221 -----------------------------------------------------------------------------
223 222 -- TIME REG & INFOs
224 223 -----------------------------------------------------------------------------
225 224 SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
226 225
227 226 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 227 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
229 228 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
230 229 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
231 230
232 231 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 232 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 233 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 234 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 235
237 236 --SIGNAL time_update_f0_A : STD_LOGIC;
238 237 --SIGNAL time_update_f0_B : STD_LOGIC;
239 238 --SIGNAL time_update_f1 : STD_LOGIC;
240 239 --SIGNAL time_update_f2 : STD_LOGIC;
241 240 --
242 241 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
243 242 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
244 243 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
245 244
246 245 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4);
247 246 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4);
248 247 SIGNAL status_component_fifo_0_end : STD_LOGIC;
249 248 SIGNAL status_component_fifo_1_end : STD_LOGIC;
250 249 -----------------------------------------------------------------------------
251 250 SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
252 251
253 252 SIGNAL fft_ready_reg : STD_LOGIC;
254 253 SIGNAL fft_ready_rising_down : STD_LOGIC;
255 254
256 255 SIGNAL sample_load_reg : STD_LOGIC;
257 256 SIGNAL sample_load_rising_down : STD_LOGIC;
258 257
259 258 -----------------------------------------------------------------------------
260 259 SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0);
261 260 SIGNAL sample_f1_wen_head_in : STD_LOGIC;
262 261 SIGNAL sample_f1_wen_head_out : STD_LOGIC;
263 262 SIGNAL sample_f1_full_head_in : STD_LOGIC;
264 263 SIGNAL sample_f1_full_head_out : STD_LOGIC;
265 264 SIGNAL sample_f1_empty_head_in : STD_LOGIC;
266 265
267 266 SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
268 267 -----------------------------------------------------------------------------
269 268 SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
270 269 SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
271 270 SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
272 271 SIGNAL ongoing : STD_LOGIC;
273 272
274 273 BEGIN
275 274
276 275 PROCESS (clk, rstn)
277 276 BEGIN -- PROCESS
278 277 IF rstn = '0' THEN -- asynchronous reset (active low)
279 278 sample_f0_wen_s <= (OTHERS => '1');
280 279 sample_f1_wen_s <= (OTHERS => '1');
281 280 sample_f2_wen_s <= (OTHERS => '1');
282 281 ongoing <= '0';
283 282 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
284 283 IF ongoing = '1' THEN
285 284 sample_f0_wen_s <= sample_f0_wen;
286 285 sample_f1_wen_s <= sample_f1_wen;
287 286 sample_f2_wen_s <= sample_f2_wen;
288 287 ELSE
289 288 IF start_date = coarse_time(30 DOWNTO 0) THEN
290 289 ongoing <= '1';
291 290 END IF;
292 291 sample_f0_wen_s <= (OTHERS => '1');
293 292 sample_f1_wen_s <= (OTHERS => '1');
294 293 sample_f2_wen_s <= (OTHERS => '1');
295 294 END IF;
296 295 END IF;
297 296 END PROCESS;
298 297
299 298
300 299 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
301 300
302 301
303 302 switch_f0_inst : spectral_matrix_switch_f0
304 303 PORT MAP (
305 304 clk => clk,
306 305 rstn => rstn,
307 306
308 307 sample_wen => sample_f0_wen_s,
309 308
310 309 fifo_A_empty => sample_f0_A_empty,
311 310 fifo_A_full => sample_f0_A_full,
312 311 fifo_A_wen => sample_f0_A_wen,
313 312
314 313 fifo_B_empty => sample_f0_B_empty,
315 314 fifo_B_full => sample_f0_B_full,
316 315 fifo_B_wen => sample_f0_B_wen,
317 316
318 317 error_wen => error_wen_f0); -- TODO
319 318
320 319 -----------------------------------------------------------------------------
321 320 -- FIFO IN
322 321 -----------------------------------------------------------------------------
323 322 lppFIFOxN_f0_a : lppFIFOxN
324 323 GENERIC MAP (
325 324 tech => 0,
326 325 Mem_use => Mem_use,
327 326 Data_sz => 16,
328 327 Addr_sz => 8,
329 328 FifoCnt => 5)
330 329 PORT MAP (
331 330 clk => clk,
332 331 rstn => rstn,
333 332
334 333 ReUse => (OTHERS => '0'),
335 334
336 335 run => (OTHERS => '1'),
337 336
338 337 wen => sample_f0_A_wen,
339 338 wdata => sample_f0_wdata,
340 339
341 340 ren => sample_f0_A_ren,
342 341 rdata => sample_f0_A_rdata,
343 342
344 343 empty => sample_f0_A_empty,
345 344 full => sample_f0_A_full,
346 345 almost_full => OPEN);
347 346
348 347 lppFIFOxN_f0_b : lppFIFOxN
349 348 GENERIC MAP (
350 349 tech => 0,
351 350 Mem_use => Mem_use,
352 351 Data_sz => 16,
353 352 Addr_sz => 8,
354 353 FifoCnt => 5)
355 354 PORT MAP (
356 355 clk => clk,
357 356 rstn => rstn,
358 357
359 358 ReUse => (OTHERS => '0'),
360 359 run => (OTHERS => '1'),
361 360
362 361 wen => sample_f0_B_wen,
363 362 wdata => sample_f0_wdata,
364 363 ren => sample_f0_B_ren,
365 364 rdata => sample_f0_B_rdata,
366 365 empty => sample_f0_B_empty,
367 366 full => sample_f0_B_full,
368 367 almost_full => OPEN);
369 368
370 369 -----------------------------------------------------------------------------
371 370 -- sample_f1_wen in
372 371 -- sample_f1_wdata in
373 372 -- sample_f1_full OUT
374 373
375 374 sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
376 375 sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1';
377 376 sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
378 377
379 378 lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
380 379 PORT MAP (
381 380 clk => clk,
382 381 rstn => rstn,
383 382 in_wen => sample_f1_wen_head_in,
384 383 in_data => sample_f1_wdata,
385 384 in_full => sample_f1_full_head_in,
386 385 in_empty => sample_f1_empty_head_in,
387 386 out_write_error => error_wen_f1,
388 387 out_wen => sample_f1_wen_head_out,
389 388 out_data => sample_f1_wdata_head,
390 389 out_full => sample_f1_full_head_out);
391 390
392 391 sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
393 392
394 393
395 394 lppFIFOxN_f1 : lppFIFOxN
396 395 GENERIC MAP (
397 396 tech => 0,
398 397 Mem_use => Mem_use,
399 398 Data_sz => 16,
400 399 Addr_sz => 8,
401 400 FifoCnt => 5)
402 401 PORT MAP (
403 402 clk => clk,
404 403 rstn => rstn,
405 404
406 405 ReUse => (OTHERS => '0'),
407 406 run => (OTHERS => '1'),
408 407
409 408 wen => sample_f1_wen_head,
410 409 wdata => sample_f1_wdata_head,
411 410 ren => sample_f1_ren,
412 411 rdata => sample_f1_rdata,
413 412 empty => sample_f1_empty,
414 413 full => sample_f1_full,
415 414 almost_full => sample_f1_almost_full);
416 415
417 416
418 417 one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
419 418
420 419 PROCESS (clk, rstn)
421 420 BEGIN -- PROCESS
422 421 IF rstn = '0' THEN -- asynchronous reset (active low)
423 422 one_sample_f1_full <= '0';
424 423 --error_wen_f1 <= '0';
425 424 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
426 425 IF sample_f1_full_head_out = '0' THEN
427 426 one_sample_f1_full <= '0';
428 427 ELSE
429 428 one_sample_f1_full <= '1';
430 429 END IF;
431 430 --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
432 431 END IF;
433 432 END PROCESS;
434 433
435 434 -----------------------------------------------------------------------------
436 435
437 436
438 437 lppFIFOxN_f2 : lppFIFOxN
439 438 GENERIC MAP (
440 439 tech => 0,
441 440 Mem_use => Mem_use,
442 441 Data_sz => 16,
443 442 Addr_sz => 8,
444 443 FifoCnt => 5)
445 444 PORT MAP (
446 445 clk => clk,
447 446 rstn => rstn,
448 447
449 448 ReUse => (OTHERS => '0'),
450 449 run => (OTHERS => '1'),
451 450
452 451 wen => sample_f2_wen_s,
453 452 wdata => sample_f2_wdata,
454 453 ren => sample_f2_ren,
455 454 rdata => sample_f2_rdata,
456 455 empty => sample_f2_empty,
457 456 full => sample_f2_full,
458 457 almost_full => OPEN);
459 458
460 459
461 460 one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
462 461
463 462 PROCESS (clk, rstn)
464 463 BEGIN -- PROCESS
465 464 IF rstn = '0' THEN -- asynchronous reset (active low)
466 465 one_sample_f2_full <= '0';
467 466 error_wen_f2 <= '0';
468 467 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
469 468 IF sample_f2_full = "00000" THEN
470 469 one_sample_f2_full <= '0';
471 470 ELSE
472 471 one_sample_f2_full <= '1';
473 472 END IF;
474 473 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
475 474 END IF;
476 475 END PROCESS;
477 476
478 477 -----------------------------------------------------------------------------
479 478 -- FSM SELECT CHANNEL
480 479 -----------------------------------------------------------------------------
481 480 PROCESS (clk, rstn)
482 481 BEGIN
483 482 IF rstn = '0' THEN
484 483 state_fsm_select_channel <= IDLE;
485 484 select_channel <= (OTHERS => '0');
486 485 ELSIF clk'EVENT AND clk = '1' THEN
487 486 CASE state_fsm_select_channel IS
488 487 WHEN IDLE =>
489 488 IF sample_f1_full = "11111" THEN
490 489 state_fsm_select_channel <= SWITCH_F1;
491 490 select_channel <= "10";
492 491 ELSIF sample_f1_almost_full = "00000" THEN
493 492 IF sample_f0_A_full = "11111" THEN
494 493 state_fsm_select_channel <= SWITCH_F0_A;
495 494 select_channel <= "00";
496 495 ELSIF sample_f0_B_full = "11111" THEN
497 496 state_fsm_select_channel <= SWITCH_F0_B;
498 497 select_channel <= "01";
499 498 ELSIF sample_f2_full = "11111" THEN
500 499 state_fsm_select_channel <= SWITCH_F2;
501 500 select_channel <= "11";
502 501 END IF;
503 502 END IF;
504 503
505 504 WHEN SWITCH_F0_A =>
506 505 IF sample_f0_A_empty = "11111" THEN
507 506 state_fsm_select_channel <= IDLE;
508 507 select_channel <= (OTHERS => '0');
509 508 END IF;
510 509 WHEN SWITCH_F0_B =>
511 510 IF sample_f0_B_empty = "11111" THEN
512 511 state_fsm_select_channel <= IDLE;
513 512 select_channel <= (OTHERS => '0');
514 513 END IF;
515 514 WHEN SWITCH_F1 =>
516 515 IF sample_f1_empty = "11111" THEN
517 516 state_fsm_select_channel <= IDLE;
518 517 select_channel <= (OTHERS => '0');
519 518 END IF;
520 519 WHEN SWITCH_F2 =>
521 520 IF sample_f2_empty = "11111" THEN
522 521 state_fsm_select_channel <= IDLE;
523 522 select_channel <= (OTHERS => '0');
524 523 END IF;
525 524 WHEN OTHERS => NULL;
526 525 END CASE;
527 526
528 527 END IF;
529 528 END PROCESS;
530 529
531 530 PROCESS (clk, rstn)
532 531 BEGIN
533 532 IF rstn = '0' THEN
534 533 select_channel_reg <= (OTHERS => '0');
535 534 --pre_state_fsm_select_channel <= IDLE;
536 535 ELSIF clk'EVENT AND clk = '1' THEN
537 536 select_channel_reg <= select_channel;
538 537 --pre_state_fsm_select_channel <= state_fsm_select_channel;
539 538 END IF;
540 539 END PROCESS;
541 540
542 541
543 542 -----------------------------------------------------------------------------
544 543 -- SWITCH SELECT CHANNEL
545 544 -----------------------------------------------------------------------------
546 545 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
547 546 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
548 547 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
549 548 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
550 549 (OTHERS => '1');
551 550
552 551 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
553 552 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
554 553 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
555 554 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
556 555 (OTHERS => '0');
557 556
558 557 --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
559 558 -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
560 559 -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
561 560 -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
562 561 sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
563 562 sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
564 563 sample_f1_rdata WHEN select_channel_reg = "10" ELSE
565 564 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
566 565
567 566
568 567 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
569 568 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
570 569 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
571 570 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
572 571
573 572
574 573 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
575 574 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
576 575 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
577 576 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
578 577
579 578 -----------------------------------------------------------------------------
580 579 -- FSM LOAD FFT
581 580 -----------------------------------------------------------------------------
582 581
583 582 sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
584 583 sample_ren_s WHEN sample_load = '1' ELSE
585 584 (OTHERS => '1');
586 585
587 586 PROCESS (clk, rstn)
588 587 BEGIN
589 588 IF rstn = '0' THEN
590 589 sample_ren_s <= (OTHERS => '1');
591 590 state_fsm_load_FFT <= IDLE;
592 591 status_MS_input <= (OTHERS => '0');
593 592 select_fifo <= "000";
594 593 --next_state_fsm_load_FFT <= IDLE;
595 594 --sample_valid <= '0';
596 595 ELSIF clk'EVENT AND clk = '1' THEN
597 596 CASE state_fsm_load_FFT IS
598 597 WHEN IDLE =>
599 598 --sample_valid <= '0';
600 599 sample_ren_s <= (OTHERS => '1');
601 600 IF sample_full = "11111" AND sample_load = '1' THEN
602 601 sample_ren_s <= "11111";
603 602 state_fsm_load_FFT <= FIFO_1;
604 603 status_MS_input <= status_channel;
605 604 select_fifo <= "000";
606 605 END IF;
607 606
608 607 WHEN FIFO_1 =>
609 608 sample_ren_s <= "1111" & NOT(sample_load);
610 609 IF sample_empty(0) = '1' THEN
611 610 sample_ren_s <= "11111";
612 611 state_fsm_load_FFT <= WAIT_STATE;
613 612 next_state_fsm_load_FFT <= FIFO_2;
614 613 select_fifo <= "001";
615 614 END IF;
616 615
617 616 WHEN FIFO_2 =>
618 617 sample_ren_s <= "111" & NOT(sample_load) & '1';
619 618 IF sample_empty(1) = '1' THEN
620 619 sample_ren_s <= "11111";
621 620 state_fsm_load_FFT <= WAIT_STATE;
622 621 next_state_fsm_load_FFT <= FIFO_3;
623 622 select_fifo <= "010";
624 623 END IF;
625 624
626 625 WHEN FIFO_3 =>
627 626 sample_ren_s <= "11" & NOT(sample_load) & "11";
628 627 IF sample_empty(2) = '1' THEN
629 628 sample_ren_s <= "11111";
630 629 state_fsm_load_FFT <= WAIT_STATE;
631 630 next_state_fsm_load_FFT <= FIFO_4;
632 631 select_fifo <= "011";
633 632 END IF;
634 633
635 634 WHEN FIFO_4 =>
636 635 sample_ren_s <= '1' & NOT(sample_load) & "111";
637 636 IF sample_empty(3) = '1' THEN
638 637 sample_ren_s <= "11111";
639 638 state_fsm_load_FFT <= WAIT_STATE;
640 639 next_state_fsm_load_FFT <= FIFO_5;
641 640 select_fifo <= "100";
642 641 END IF;
643 642
644 643 WHEN FIFO_5 =>
645 644 sample_ren_s <= NOT(sample_load) & "1111";
646 645 IF sample_empty(4) = '1' THEN
647 646 sample_ren_s <= (OTHERS => '1');
648 647 state_fsm_load_FFT <= IDLE;
649 648 select_fifo <= "000";
650 649 END IF;
651 650
652 651 WHEN WAIT_STATE =>
653 652 sample_ren_s <= (OTHERS => '1');
654 653 IF sample_load = '1' THEN
655 654 state_fsm_load_FFT <= WAIT_STATE_2 ;
656 655 END IF;
657 656
658 657 WHEN WAIT_STATE_2 =>
659 658 sample_ren_s <= (OTHERS => '1');
660 659 IF fft_data_valid = '0' AND fft_data_valid_pre = '1' THEN
661 660 state_fsm_load_FFT <= next_state_fsm_load_FFT;
662 661 END IF;
663 662
664 663 WHEN OTHERS => NULL;
665 664 END CASE;
666 665 END IF;
667 666 END PROCESS;
668 667
669 668 PROCESS (clk, rstn)
670 669 BEGIN -- PROCESS
671 670 IF rstn = '0' THEN -- asynchronous reset (active low)
672 671 fft_data_valid_pre <= '0';
673 672 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
674 673 fft_data_valid_pre <= fft_data_valid;
675 674 END IF;
676 675 END PROCESS;
677 676
678 677 PROCESS (clk, rstn)
679 678 BEGIN
680 679 IF rstn = '0' THEN
681 680 sample_valid_r <= '0';
682 681 select_fifo_reg <= (OTHERS => '0');
683 682 --next_state_fsm_load_FFT <= IDLE;
684 683 ELSIF clk'EVENT AND clk = '1' THEN
685 684 select_fifo_reg <= select_fifo;
686 685 --next_state_fsm_load_FFT <= state_fsm_load_FFT;
687 686 IF sample_ren_s = "11111" THEN
688 687 sample_valid_r <= '0';
689 688 ELSE
690 689 sample_valid_r <= '1';
691 690 END IF;
692 691 END IF;
693 692 END PROCESS;
694 693
695 694 sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
696 695
697 696 --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
698 697 -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
699 698 -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
700 699 -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
701 700 -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
702 701 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
703 702 sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
704 703 sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
705 704 sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE
706 705 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
707 706
708 707 -----------------------------------------------------------------------------
709 708 -- FFT
710 709 -----------------------------------------------------------------------------
711 710 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
712 711 PORT MAP (
713 712 clk => clk,
714 713 rstn => rstn,
715 714 sample_valid => sample_valid,
716 715 fft_read => fft_read,
717 716 sample_data => sample_data,
718 717 sample_load => sample_load,
719 718 fft_pong => fft_pong,
720 719 fft_data_im => fft_data_im,
721 720 fft_data_re => fft_data_re,
722 721 fft_data_valid => fft_data_valid,
723 722 fft_ready => fft_ready);
724 723
725 724 debug_vector(0) <= fft_data_valid;
726 725 debug_vector(1) <= fft_ready;
727 726 debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
728 727
729 728
730 729 -----------------------------------------------------------------------------
731 730 fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready;
732 731 sample_load_rising_down <= sample_load_reg AND NOT sample_load;
733 732
734 733 PROCESS (clk, rstn)
735 734 BEGIN
736 735 IF rstn = '0' THEN
737 736 fft_ready_reg <= '0';
738 737 sample_load_reg <= '0';
739 738
740 739 fft_ongoing_counter <= '0';
741 740 ELSIF clk'event AND clk = '1' THEN
742 741 fft_ready_reg <= fft_ready;
743 742 sample_load_reg <= sample_load;
744 743
745 744 IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
746 745 fft_ongoing_counter <= '0';
747 746
748 747 -- CASE fft_ongoing_counter IS
749 748 -- WHEN "01" => fft_ongoing_counter <= "00";
750 749 ---- WHEN "10" => fft_ongoing_counter <= "01";
751 750 -- WHEN OTHERS => NULL;
752 751 -- END CASE;
753 752 ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
754 753 fft_ongoing_counter <= '1';
755 754 -- CASE fft_ongoing_counter IS
756 755 -- WHEN "00" => fft_ongoing_counter <= "01";
757 756 ---- WHEN "01" => fft_ongoing_counter <= "10";
758 757 -- WHEN OTHERS => NULL;
759 758 -- END CASE;
760 759 END IF;
761 760
762 761 END IF;
763 762 END PROCESS;
764 763
765 764 -----------------------------------------------------------------------------
766 765 PROCESS (clk, rstn)
767 766 BEGIN
768 767 IF rstn = '0' THEN
769 768 state_fsm_load_MS_memory <= IDLE;
770 769 current_fifo_load <= "00001";
771 770 ELSIF clk'EVENT AND clk = '1' THEN
772 771 CASE state_fsm_load_MS_memory IS
773 772 WHEN IDLE =>
774 773 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
775 774 state_fsm_load_MS_memory <= LOAD_FIFO;
776 775 END IF;
777 776 WHEN LOAD_FIFO =>
778 777 IF current_fifo_full = '1' THEN
779 778 state_fsm_load_MS_memory <= TRASH_FFT;
780 779 END IF;
781 780 WHEN TRASH_FFT =>
782 781 IF fft_ready = '0' THEN
783 782 state_fsm_load_MS_memory <= IDLE;
784 783 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
785 784 END IF;
786 785 WHEN OTHERS => NULL;
787 786 END CASE;
788 787
789 788 END IF;
790 789 END PROCESS;
791 790
792 791 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
793 792 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
794 793 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
795 794 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
796 795 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
797 796
798 797 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
799 798 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
800 799 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
801 800 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
802 801 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
803 802
804 803 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
805 804 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
806 805 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
807 806 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
808 807 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
809 808
810 809 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
811 810
812 811 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
813 812 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
814 813 AND state_fsm_load_MS_memory = LOAD_FIFO
815 814 AND current_fifo_load(I) = '1'
816 815 ELSE '1';
817 816 END GENERATE all_fifo;
818 817
819 818 PROCESS (clk, rstn)
820 819 BEGIN
821 820 IF rstn = '0' THEN
822 821 MEM_IN_SM_wen <= (OTHERS => '1');
823 822 ELSIF clk'EVENT AND clk = '1' THEN
824 823 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
825 824 END IF;
826 825 END PROCESS;
827 826
828 827 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
829 828 (fft_data_im & fft_data_re) &
830 829 (fft_data_im & fft_data_re) &
831 830 (fft_data_im & fft_data_re) &
832 831 (fft_data_im & fft_data_re);
833 832 -----------------------------------------------------------------------------
834 833
835 834
836 835 -----------------------------------------------------------------------------
837 836 Mem_In_SpectralMatrix : lppFIFOxN
838 837 GENERIC MAP (
839 838 tech => 0,
840 839 Mem_use => Mem_use,
841 840 Data_sz => 32, --16,
842 841 Addr_sz => 7, --8
843 842 FifoCnt => 5)
844 843 PORT MAP (
845 844 clk => clk,
846 845 rstn => rstn,
847 846
848 847 ReUse => MEM_IN_SM_ReUse,
849 848 run => (OTHERS => '1'),
850 849
851 850 wen => MEM_IN_SM_wen,
852 851 wdata => MEM_IN_SM_wData,
853 852
854 853 ren => MEM_IN_SM_ren,
855 854 rdata => MEM_IN_SM_rData,
856 855 full => MEM_IN_SM_Full,
857 856 empty => MEM_IN_SM_Empty,
858 857 almost_full => OPEN);
859 858
860 859
861 860 -----------------------------------------------------------------------------
862 861 MS_control_1 : MS_control
863 862 PORT MAP (
864 863 clk => clk,
865 864 rstn => rstn,
866 865
867 866 current_status_ms => status_MS_input,
868 867
869 868 fifo_in_lock => MEM_IN_SM_locked,
870 869 fifo_in_data => MEM_IN_SM_rdata,
871 870 fifo_in_full => MEM_IN_SM_Full,
872 871 fifo_in_empty => MEM_IN_SM_Empty,
873 872 fifo_in_ren => MEM_IN_SM_ren,
874 873 fifo_in_reuse => MEM_IN_SM_ReUse,
875 874
876 875 fifo_out_data => SM_in_data,
877 876 fifo_out_ren => SM_in_ren,
878 877 fifo_out_empty => SM_in_empty,
879 878
880 879 current_status_component => status_component,
881 880
882 881 correlation_start => SM_correlation_start,
883 882 correlation_auto => SM_correlation_auto,
884 883 correlation_done => SM_correlation_done);
885 884
886 885
887 886 MS_calculation_1 : MS_calculation
888 887 PORT MAP (
889 888 clk => clk,
890 889 rstn => rstn,
891 890
892 891 fifo_in_data => SM_in_data,
893 892 fifo_in_ren => SM_in_ren,
894 893 fifo_in_empty => SM_in_empty,
895 894
896 895 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
897 896 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
898 897 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
899 898
900 899 correlation_start => SM_correlation_start,
901 900 correlation_auto => SM_correlation_auto,
902 901 correlation_begin => SM_correlation_begin,
903 902 correlation_done => SM_correlation_done);
904 903
905 904 -----------------------------------------------------------------------------
906 905 PROCESS (clk, rstn)
907 906 BEGIN -- PROCESS
908 907 IF rstn = '0' THEN -- asynchronous reset (active low)
909 908 current_matrix_write <= '0';
910 909 current_matrix_wait_empty <= '1';
911 910 status_component_fifo_0 <= (OTHERS => '0');
912 911 status_component_fifo_1 <= (OTHERS => '0');
913 912 status_component_fifo_0_end <= '0';
914 913 status_component_fifo_1_end <= '0';
915 914 SM_correlation_done_reg1 <= '0';
916 915 SM_correlation_done_reg2 <= '0';
917 916 SM_correlation_done_reg3 <= '0';
918 917
919 918 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
920 919 SM_correlation_done_reg1 <= SM_correlation_done;
921 920 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
922 921 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
923 922 status_component_fifo_0_end <= '0';
924 923 status_component_fifo_1_end <= '0';
925 924 IF SM_correlation_begin = '1' THEN
926 925 IF current_matrix_write = '0' THEN
927 926 status_component_fifo_0 <= status_component(53 DOWNTO 4);
928 927 ELSE
929 928 status_component_fifo_1 <= status_component(53 DOWNTO 4);
930 929 END IF;
931 930 END IF;
932 931
933 932 IF SM_correlation_done_reg3 = '1' THEN
934 933 IF current_matrix_write = '0' THEN
935 934 status_component_fifo_0_end <= '1';
936 935 ELSE
937 936 status_component_fifo_1_end <= '1';
938 937 END IF;
939 938 current_matrix_wait_empty <= '1';
940 939 current_matrix_write <= NOT current_matrix_write;
941 940 END IF;
942 941
943 942 IF current_matrix_wait_empty <= '1' THEN
944 943 IF current_matrix_write = '0' THEN
945 944 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
946 945 ELSE
947 946 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
948 947 END IF;
949 948 END IF;
950 949
951 950 END IF;
952 951 END PROCESS;
953 952
954 953 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
955 954 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
956 955 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
957 956 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
958 957 '1' WHEN current_matrix_wait_empty = '1' ELSE
959 958 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
960 959 MEM_OUT_SM_Full(1);
961 960
962 961 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
963 962 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
964 963
965 964 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
966 965 -----------------------------------------------------------------------------
967 966
968 967 --Mem_Out_SpectralMatrix : lppFIFOxN
969 968 -- GENERIC MAP (
970 969 -- tech => 0,
971 970 -- Mem_use => Mem_use,
972 971 -- Data_sz => 32,
973 972 -- Addr_sz => 8,
974 973 -- FifoCnt => 2)
975 974 -- PORT MAP (
976 975 -- clk => clk,
977 976 -- rstn => rstn,
978 977
979 978 -- ReUse => (OTHERS => '0'),
980 979 -- run => (OTHERS => '1'),
981 980
982 981 -- wen => MEM_OUT_SM_Write,
983 982 -- wdata => MEM_OUT_SM_Data_in,
984 983
985 984 -- ren => MEM_OUT_SM_Read,
986 985 -- rdata => MEM_OUT_SM_Data_out,
987 986
988 987 -- full => MEM_OUT_SM_Full,
989 988 -- empty => MEM_OUT_SM_Empty,
990 989 -- almost_full => OPEN);
991 990
992 991
993 992 all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
994 993 Mem_Out_SpectralMatrix_I: lpp_fifo
995 994 GENERIC MAP (
996 995 tech => 0,
997 996 Mem_use => Mem_use,
998 997 EMPTY_THRESHOLD_LIMIT => 15,
999 998 FULL_THRESHOLD_LIMIT => 1,
1000 999 DataSz => 32,
1001 1000 AddrSz => 8)
1002 1001 PORT MAP (
1003 1002 clk => clk,
1004 1003 rstn => rstn,
1005 1004 reUse => '0',
1006 1005 run => run,
1007 1006
1008 1007 ren => MEM_OUT_SM_Read(I),
1009 1008 rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
1010 1009
1011 1010 wen => MEM_OUT_SM_Write(I),
1012 1011 wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
1013 1012
1014 1013 empty => MEM_OUT_SM_Empty(I),
1015 1014 full => MEM_OUT_SM_Full(I),
1016 1015 full_almost => OPEN,
1017 1016 empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
1018 1017
1019 1018 full_threshold => OPEN);
1020 1019
1021 1020 END GENERATE all_Mem_Out_SpectralMatrix;
1022 1021
1023 1022 -----------------------------------------------------------------------------
1024 1023 -- MEM_OUT_SM_Read <= "00";
1025 1024 PROCESS (clk, rstn)
1026 1025 BEGIN
1027 1026 IF rstn = '0' THEN
1028 1027 fifo_0_ready <= '0';
1029 1028 fifo_1_ready <= '0';
1030 1029 fifo_ongoing <= '0';
1031 1030 fifo_ongoing_reg <= '0';
1032 1031 ELSIF clk'EVENT AND clk = '1' THEN
1033 1032 fifo_ongoing_reg <= fifo_ongoing;
1034 1033 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
1035 1034 fifo_ongoing <= '1';
1036 1035 fifo_0_ready <= '0';
1037 1036 ELSIF status_component_fifo_0_end = '1' THEN
1038 1037 fifo_0_ready <= '1';
1039 1038 END IF;
1040 1039
1041 1040 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
1042 1041 fifo_ongoing <= '0';
1043 1042 fifo_1_ready <= '0';
1044 1043 ELSIF status_component_fifo_1_end = '1' THEN
1045 1044 fifo_1_ready <= '1';
1046 1045 END IF;
1047 1046
1048 1047 END IF;
1049 1048 END PROCESS;
1050 1049
1051 1050 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
1052 1051 '1' WHEN fifo_0_ready = '0' ELSE
1053 1052 FSM_DMA_fifo_ren;
1054 1053
1055 1054 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
1056 1055 '1' WHEN fifo_1_ready = '0' ELSE
1057 1056 FSM_DMA_fifo_ren;
1058 1057
1059 1058 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1060 1059 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1061 1060 '1';
1062 1061
1063 1062 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
1064 1063 status_component_fifo_1;
1065 1064
1066 1065 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
1067 1066 MEM_OUT_SM_Data_out(63 DOWNTO 32);
1068 1067
1069 1068
1070 1069 FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
1071 1070 MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
1072 1071 '1';
1073 1072
1074 1073 -----------------------------------------------------------------------------
1075 1074 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN
1076 1075 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN
1077 1076 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN
1078 1077 -- fifo_data => FSM_DMA_fifo_data, --IN
1079 1078 -- fifo_empty => FSM_DMA_fifo_empty, --IN
1080 1079 -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN
1081 1080 -- fifo_ren => FSM_DMA_fifo_ren, --OUT
1082 1081
1083 1082
1084 1083 lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
1085 1084 PORT MAP (
1086 1085 clk => clk,
1087 1086 rstn => rstn,
1088 1087 run => run,
1089 1088
1090 1089 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1091 1090 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1092 1091 fifo_data => FSM_DMA_fifo_data,
1093 1092 fifo_empty => FSM_DMA_fifo_empty,
1094 1093 fifo_empty_threshold => FSM_DMA_fifo_empty_threshold,
1095 1094 fifo_ren => FSM_DMA_fifo_ren,
1096 1095
1097 1096 dma_fifo_valid_burst => dma_fifo_burst_valid,
1098 1097 dma_fifo_data => dma_fifo_data,
1099 1098 dma_fifo_ren => dma_fifo_ren,
1100 1099 dma_buffer_new => dma_buffer_new,
1101 1100 dma_buffer_addr => dma_buffer_addr,
1102 1101 dma_buffer_length => dma_buffer_length,
1103 1102 dma_buffer_full => dma_buffer_full,
1104 1103 dma_buffer_full_err => dma_buffer_full_err,
1105 1104
1106 1105 status_ready_matrix_f0 => status_ready_matrix_f0,
1107 1106 status_ready_matrix_f1 => status_ready_matrix_f1,
1108 1107 status_ready_matrix_f2 => status_ready_matrix_f2,
1109 1108 addr_matrix_f0 => addr_matrix_f0,
1110 1109 addr_matrix_f1 => addr_matrix_f1,
1111 1110 addr_matrix_f2 => addr_matrix_f2,
1112 1111 length_matrix_f0 => length_matrix_f0,
1113 1112 length_matrix_f1 => length_matrix_f1,
1114 1113 length_matrix_f2 => length_matrix_f2,
1115 1114 ready_matrix_f0 => ready_matrix_f0,
1116 1115 ready_matrix_f1 => ready_matrix_f1,
1117 1116 ready_matrix_f2 => ready_matrix_f2,
1118 1117 matrix_time_f0 => matrix_time_f0,
1119 1118 matrix_time_f1 => matrix_time_f1,
1120 1119 matrix_time_f2 => matrix_time_f2,
1121 1120 error_buffer_full => error_buffer_full);
1122 1121
1123 1122
1124 1123
1125 1124
1126 1125
1127 1126 --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO
1128 1127 --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1129 1128 --dma_fifo_ren : IN STD_LOGIC; --TODO
1130 1129 --dma_buffer_new : OUT STD_LOGIC; --TODO
1131 1130 --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO
1132 1131 --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO
1133 1132 --dma_buffer_full : IN STD_LOGIC; --TODO
1134 1133 --dma_buffer_full_err : IN STD_LOGIC; --TODO
1135 1134
1136 1135 ---- Reg out
1137 1136 --ready_matrix_f0 : OUT STD_LOGIC; -- TODO
1138 1137 --ready_matrix_f1 : OUT STD_LOGIC; -- TODO
1139 1138 --ready_matrix_f2 : OUT STD_LOGIC; -- TODO
1140 1139 --error_bad_component_error : OUT STD_LOGIC; -- TODO
1141 1140 --error_buffer_full : OUT STD_LOGIC; -- TODO
1142 1141
1143 1142 ---- Reg In
1144 1143 --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO
1145 1144 --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO
1146 1145 --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO
1147 1146
1148 1147 --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1149 1148 --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1150 1149 --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
1151 1150
1152 1151 --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1153 1152 --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
1154 1153 --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO
1155 1154 -----------------------------------------------------------------------------
1156 1155
1157 1156 -----------------------------------------------------------------------------
1158 1157 --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
1159 1158 -- PORT MAP (
1160 1159 -- HCLK => clk,
1161 1160 -- HRESETn => rstn,
1162 1161
1163 1162 -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
1164 1163 -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
1165 1164 -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
1166 1165 -- fifo_data => FSM_DMA_fifo_data,
1167 1166 -- fifo_empty => FSM_DMA_fifo_empty,
1168 1167 -- fifo_ren => FSM_DMA_fifo_ren,
1169 1168
1170 1169 -- dma_addr => dma_addr,
1171 1170 -- dma_data => dma_data,
1172 1171 -- dma_valid => dma_valid,
1173 1172 -- dma_valid_burst => dma_valid_burst,
1174 1173 -- dma_ren => dma_ren,
1175 1174 -- dma_done => dma_done,
1176 1175
1177 1176 -- ready_matrix_f0 => ready_matrix_f0,
1178 1177 -- ready_matrix_f1 => ready_matrix_f1,
1179 1178 -- ready_matrix_f2 => ready_matrix_f2,
1180 1179
1181 1180 -- error_bad_component_error => error_bad_component_error,
1182 1181 -- error_buffer_full => error_buffer_full,
1183 1182
1184 1183 -- debug_reg => debug_reg,
1185 1184 -- status_ready_matrix_f0 => status_ready_matrix_f0,
1186 1185 -- status_ready_matrix_f1 => status_ready_matrix_f1,
1187 1186 -- status_ready_matrix_f2 => status_ready_matrix_f2,
1188 1187
1189 1188 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
1190 1189 -- config_active_interruption_onError => config_active_interruption_onError,
1191 1190
1192 1191 -- addr_matrix_f0 => addr_matrix_f0,
1193 1192 -- addr_matrix_f1 => addr_matrix_f1,
1194 1193 -- addr_matrix_f2 => addr_matrix_f2,
1195 1194
1196 1195 -- matrix_time_f0 => matrix_time_f0,
1197 1196 -- matrix_time_f1 => matrix_time_f1,
1198 1197 -- matrix_time_f2 => matrix_time_f2
1199 1198 -- );
1200 1199 -----------------------------------------------------------------------------
1201 1200
1202 1201
1203 1202
1204 1203
1205 1204
1206 1205
1207 1206 -----------------------------------------------------------------------------
1208 1207 -- TIME MANAGMENT
1209 1208 -----------------------------------------------------------------------------
1210 1209 all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
1211 1210 --all_time <= coarse_time & fine_time;
1212 1211 --
1213 1212 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
1214 1213 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
1215 1214 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
1216 1215 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
1217 1216
1218 1217 all_time_reg: FOR I IN 0 TO 3 GENERATE
1219 1218
1220 1219 PROCESS (clk, rstn)
1221 1220 BEGIN
1222 1221 IF rstn = '0' THEN
1223 1222 f_empty_reg(I) <= '1';
1224 1223 ELSIF clk'event AND clk = '1' THEN
1225 1224 f_empty_reg(I) <= f_empty(I);
1226 1225 END IF;
1227 1226 END PROCESS;
1228 1227
1229 1228 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
1230 1229
1231 1230 s_m_t_m_f0_A : spectral_matrix_time_managment
1232 1231 PORT MAP (
1233 1232 clk => clk,
1234 1233 rstn => rstn,
1235 1234 time_in => all_time((I+1)*48-1 DOWNTO I*48),
1236 1235 update_1 => time_update_f(I),
1237 1236 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
1238 1237 );
1239 1238
1240 1239 END GENERATE all_time_reg;
1241 1240
1242 1241 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
1243 1242 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
1244 1243 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
1245 1244 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
1246 1245
1247 1246 -----------------------------------------------------------------------------
1248 1247
1249 1248 END Behavioral;
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