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LFR-em
pellion -
r460:afe9a0bfb35f (LFR-EM) WFP_MS_1-1-33 JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
27
28 LIBRARY lpp;
29 USE lpp.cic_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31
32 ENTITY cic_lfr_address_gen IS
33 PORT (
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
37
38 addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
39 addr_init : IN STD_LOGIC;
40 addr_add_1 : IN STD_LOGIC;
41
42 addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
43 );
44 END cic_lfr_address_gen;
45
46 ARCHITECTURE beh OF cic_lfr_address_gen IS
47 SIGNAL address_reg_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
48 SIGNAL address_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);
49 BEGIN
50
51 PROCESS (clk, rstn)
52 BEGIN -- PROCESS
53 IF rstn = '0' THEN -- asynchronous reset (active low)
54 address_reg <= (OTHERS => '0');
55 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
56 address_reg <= address_reg_s;
57 END IF;
58 END PROCESS;
59
60 address_reg_s <= (OTHERS => '0') WHEN run = '0' ELSE
61 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '0' ELSE
62 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '1' ELSE
63 addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE
64 address_reg;
65
66 addr <= address_reg WHEN addr_init = '0' ELSE addr_base;
67
68 END beh;
69
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
88 );
89
89
90 END LFR_em;
90 END LFR_em;
91
91
92
92
93 ARCHITECTURE beh OF LFR_em IS
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
100
101 -- CONSTANTS
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
106
107 SIGNAL apbi_ext : apb_slv_in_type;
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
113
114 -- Spacewire signals
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
122 SIGNAL swno : grspw_out_type;
123
123
124 --GPIO
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
126 SIGNAL gpioo : gpio_out_type;
127
127
128 -- AD Converter ADS7886
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
131 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL sample_val : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138
138
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 SIGNAL rstn : STD_LOGIC;
140 SIGNAL rstn : STD_LOGIC;
141
141
142 SIGNAL ADC_smpclk_s : STD_LOGIC;
142 SIGNAL ADC_smpclk_s : STD_LOGIC;
143
143
144 BEGIN -- beh
144 BEGIN -- beh
145
145
146 -----------------------------------------------------------------------------
146 -----------------------------------------------------------------------------
147 -- CLK
147 -- CLK
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
149 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
150
150
151 PROCESS(clk100MHz)
151 PROCESS(clk100MHz)
152 BEGIN
152 BEGIN
153 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
153 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
154 clk_50_s <= NOT clk_50_s;
154 clk_50_s <= NOT clk_50_s;
155 END IF;
155 END IF;
156 END PROCESS;
156 END PROCESS;
157
157
158 PROCESS(clk_50_s)
158 PROCESS(clk_50_s)
159 BEGIN
159 BEGIN
160 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
160 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
161 clk_25 <= NOT clk_25;
161 clk_25 <= NOT clk_25;
162 END IF;
162 END IF;
163 END PROCESS;
163 END PROCESS;
164
164
165 PROCESS(clk49_152MHz)
165 PROCESS(clk49_152MHz)
166 BEGIN
166 BEGIN
167 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
167 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
168 clk_24 <= NOT clk_24;
168 clk_24 <= NOT clk_24;
169 END IF;
169 END IF;
170 END PROCESS;
170 END PROCESS;
171
171
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173
173
174 PROCESS (clk_25, rstn)
174 PROCESS (clk_25, rstn)
175 BEGIN -- PROCESS
175 BEGIN -- PROCESS
176 IF rstn = '0' THEN -- asynchronous reset (active low)
176 IF rstn = '0' THEN -- asynchronous reset (active low)
177 led(0) <= '0';
177 led(0) <= '0';
178 led(1) <= '0';
178 led(1) <= '0';
179 led(2) <= '0';
179 led(2) <= '0';
180 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
180 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
181 led(0) <= '0';
181 led(0) <= '0';
182 led(1) <= '1';
182 led(1) <= '1';
183 led(2) <= '1';
183 led(2) <= '1';
184 END IF;
184 END IF;
185 END PROCESS;
185 END PROCESS;
186
186
187 --
187 --
188 leon3_soc_1 : leon3_soc
188 leon3_soc_1 : leon3_soc
189 GENERIC MAP (
189 GENERIC MAP (
190 fabtech => apa3e,
190 fabtech => apa3e,
191 memtech => apa3e,
191 memtech => apa3e,
192 padtech => inferred,
192 padtech => inferred,
193 clktech => inferred,
193 clktech => inferred,
194 disas => 0,
194 disas => 0,
195 dbguart => 0,
195 dbguart => 0,
196 pclow => 2,
196 pclow => 2,
197 clk_freq => 25000,
197 clk_freq => 25000,
198 NB_CPU => 1,
198 NB_CPU => 1,
199 ENABLE_FPU => 1,
199 ENABLE_FPU => 1,
200 FPU_NETLIST => 0,
200 FPU_NETLIST => 0,
201 ENABLE_DSU => 1,
201 ENABLE_DSU => 1,
202 ENABLE_AHB_UART => 1,
202 ENABLE_AHB_UART => 1,
203 ENABLE_APB_UART => 1,
203 ENABLE_APB_UART => 1,
204 ENABLE_IRQMP => 1,
204 ENABLE_IRQMP => 1,
205 ENABLE_GPT => 1,
205 ENABLE_GPT => 1,
206 NB_AHB_MASTER => NB_AHB_MASTER,
206 NB_AHB_MASTER => NB_AHB_MASTER,
207 NB_AHB_SLAVE => NB_AHB_SLAVE,
207 NB_AHB_SLAVE => NB_AHB_SLAVE,
208 NB_APB_SLAVE => NB_APB_SLAVE)
208 NB_APB_SLAVE => NB_APB_SLAVE)
209 PORT MAP (
209 PORT MAP (
210 clk => clk_25,
210 clk => clk_25,
211 reset => rstn,
211 reset => rstn,
212 errorn => OPEN,
212 errorn => OPEN,
213
213
214 ahbrxd => TAG1,
214 ahbrxd => TAG1,
215 ahbtxd => TAG3,
215 ahbtxd => TAG3,
216 urxd1 => TAG2,
216 urxd1 => TAG2,
217 utxd1 => TAG4,
217 utxd1 => TAG4,
218
218
219 address => address,
219 address => address,
220 data => data,
220 data => data,
221 nSRAM_BE0 => nSRAM_BE0,
221 nSRAM_BE0 => nSRAM_BE0,
222 nSRAM_BE1 => nSRAM_BE1,
222 nSRAM_BE1 => nSRAM_BE1,
223 nSRAM_BE2 => nSRAM_BE2,
223 nSRAM_BE2 => nSRAM_BE2,
224 nSRAM_BE3 => nSRAM_BE3,
224 nSRAM_BE3 => nSRAM_BE3,
225 nSRAM_WE => nSRAM_WE,
225 nSRAM_WE => nSRAM_WE,
226 nSRAM_CE => nSRAM_CE,
226 nSRAM_CE => nSRAM_CE,
227 nSRAM_OE => nSRAM_OE,
227 nSRAM_OE => nSRAM_OE,
228
228
229 apbi_ext => apbi_ext,
229 apbi_ext => apbi_ext,
230 apbo_ext => apbo_ext,
230 apbo_ext => apbo_ext,
231 ahbi_s_ext => ahbi_s_ext,
231 ahbi_s_ext => ahbi_s_ext,
232 ahbo_s_ext => ahbo_s_ext,
232 ahbo_s_ext => ahbo_s_ext,
233 ahbi_m_ext => ahbi_m_ext,
233 ahbi_m_ext => ahbi_m_ext,
234 ahbo_m_ext => ahbo_m_ext);
234 ahbo_m_ext => ahbo_m_ext);
235
235
236
236
237 -------------------------------------------------------------------------------
237 -------------------------------------------------------------------------------
238 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
238 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
239 -------------------------------------------------------------------------------
239 -------------------------------------------------------------------------------
240 apb_lfr_time_management_1 : apb_lfr_time_management
240 apb_lfr_time_management_1 : apb_lfr_time_management
241 GENERIC MAP (
241 GENERIC MAP (
242 pindex => 6,
242 pindex => 6,
243 paddr => 6,
243 paddr => 6,
244 pmask => 16#fff#,
244 pmask => 16#fff#,
245 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
245 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
246 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
246 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
247 PORT MAP (
247 PORT MAP (
248 clk25MHz => clk_25,
248 clk25MHz => clk_25,
249 clk24_576MHz => clk_24, -- 49.152MHz/2
249 clk24_576MHz => clk_24, -- 49.152MHz/2
250 resetn => rstn,
250 resetn => rstn,
251 grspw_tick => swno.tickout,
251 grspw_tick => swno.tickout,
252 apbi => apbi_ext,
252 apbi => apbi_ext,
253 apbo => apbo_ext(6),
253 apbo => apbo_ext(6),
254 coarse_time => coarse_time,
254 coarse_time => coarse_time,
255 fine_time => fine_time);
255 fine_time => fine_time);
256
256
257 -----------------------------------------------------------------------
257 -----------------------------------------------------------------------
258 --- SpaceWire --------------------------------------------------------
258 --- SpaceWire --------------------------------------------------------
259 -----------------------------------------------------------------------
259 -----------------------------------------------------------------------
260
260
261 -- SPW_EN <= '1';
261 -- SPW_EN <= '1';
262
262
263 spw_clk <= clk_50_s;
263 spw_clk <= clk_50_s;
264 spw_rxtxclk <= spw_clk;
264 spw_rxtxclk <= spw_clk;
265 spw_rxclkn <= NOT spw_rxtxclk;
265 spw_rxclkn <= NOT spw_rxtxclk;
266
266
267 -- PADS for SPW1
267 -- PADS for SPW1
268 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
268 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
269 PORT MAP (spw1_din, dtmp(0));
269 PORT MAP (spw1_din, dtmp(0));
270 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
270 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
271 PORT MAP (spw1_sin, stmp(0));
271 PORT MAP (spw1_sin, stmp(0));
272 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
272 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
273 PORT MAP (spw1_dout, swno.d(0));
273 PORT MAP (spw1_dout, swno.d(0));
274 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
274 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
275 PORT MAP (spw1_sout, swno.s(0));
275 PORT MAP (spw1_sout, swno.s(0));
276 -- PADS FOR SPW2
276 -- PADS FOR SPW2
277 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
277 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
278 PORT MAP (spw2_din, dtmp(1));
278 PORT MAP (spw2_din, dtmp(1));
279 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
279 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
280 PORT MAP (spw2_sin, stmp(1));
280 PORT MAP (spw2_sin, stmp(1));
281 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
281 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
282 PORT MAP (spw2_dout, swno.d(1));
282 PORT MAP (spw2_dout, swno.d(1));
283 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
283 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
284 PORT MAP (spw2_sout, swno.s(1));
284 PORT MAP (spw2_sout, swno.s(1));
285
285
286 -- GRSPW PHY
286 -- GRSPW PHY
287 --spw1_input: if CFG_SPW_GRSPW = 1 generate
287 --spw1_input: if CFG_SPW_GRSPW = 1 generate
288 spw_inputloop : FOR j IN 0 TO 1 GENERATE
288 spw_inputloop : FOR j IN 0 TO 1 GENERATE
289 spw_phy0 : grspw_phy
289 spw_phy0 : grspw_phy
290 GENERIC MAP(
290 GENERIC MAP(
291 tech => apa3e,
291 tech => apa3e,
292 rxclkbuftype => 1,
292 rxclkbuftype => 1,
293 scantest => 0)
293 scantest => 0)
294 PORT MAP(
294 PORT MAP(
295 rxrst => swno.rxrst,
295 rxrst => swno.rxrst,
296 di => dtmp(j),
296 di => dtmp(j),
297 si => stmp(j),
297 si => stmp(j),
298 rxclko => spw_rxclk(j),
298 rxclko => spw_rxclk(j),
299 do => swni.d(j),
299 do => swni.d(j),
300 ndo => swni.nd(j*5+4 DOWNTO j*5),
300 ndo => swni.nd(j*5+4 DOWNTO j*5),
301 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
301 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
302 END GENERATE spw_inputloop;
302 END GENERATE spw_inputloop;
303
303
304 -- SPW core
304 -- SPW core
305 sw0 : grspwm GENERIC MAP(
305 sw0 : grspwm GENERIC MAP(
306 tech => apa3e,
306 tech => apa3e,
307 hindex => 1,
307 hindex => 1,
308 pindex => 5,
308 pindex => 5,
309 paddr => 5,
309 paddr => 5,
310 pirq => 11,
310 pirq => 11,
311 sysfreq => 25000, -- CPU_FREQ
311 sysfreq => 25000, -- CPU_FREQ
312 rmap => 1,
312 rmap => 1,
313 rmapcrc => 1,
313 rmapcrc => 1,
314 fifosize1 => 16,
314 fifosize1 => 16,
315 fifosize2 => 16,
315 fifosize2 => 16,
316 rxclkbuftype => 1,
316 rxclkbuftype => 1,
317 rxunaligned => 0,
317 rxunaligned => 0,
318 rmapbufs => 4,
318 rmapbufs => 4,
319 ft => 0,
319 ft => 0,
320 netlist => 0,
320 netlist => 0,
321 ports => 2,
321 ports => 2,
322 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
322 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
323 memtech => apa3e,
323 memtech => apa3e,
324 destkey => 2,
324 destkey => 2,
325 spwcore => 1
325 spwcore => 1
326 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
326 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
327 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
327 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
328 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
328 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
329 )
329 )
330 PORT MAP(rstn, clk_25, spw_rxclk(0),
330 PORT MAP(rstn, clk_25, spw_rxclk(0),
331 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
331 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
332 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
332 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
333 swni, swno);
333 swni, swno);
334
334
335 swni.tickin <= '0';
335 swni.tickin <= '0';
336 swni.rmapen <= '1';
336 swni.rmapen <= '1';
337 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
337 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
338 swni.tickinraw <= '0';
338 swni.tickinraw <= '0';
339 swni.timein <= (OTHERS => '0');
339 swni.timein <= (OTHERS => '0');
340 swni.dcrstval <= (OTHERS => '0');
340 swni.dcrstval <= (OTHERS => '0');
341 swni.timerrstval <= (OTHERS => '0');
341 swni.timerrstval <= (OTHERS => '0');
342
342
343 -------------------------------------------------------------------------------
343 -------------------------------------------------------------------------------
344 -- LFR ------------------------------------------------------------------------
344 -- LFR ------------------------------------------------------------------------
345 -------------------------------------------------------------------------------
345 -------------------------------------------------------------------------------
346 lpp_lfr_1 : lpp_lfr
346 lpp_lfr_1 : lpp_lfr
347 GENERIC MAP (
347 GENERIC MAP (
348 Mem_use => use_RAM,
348 Mem_use => use_RAM,
349 nb_data_by_buffer_size => 32,
349 nb_data_by_buffer_size => 32,
350 nb_word_by_buffer_size => 30,
350 --nb_word_by_buffer_size => 30,
351 nb_snapshot_param_size => 32,
351 nb_snapshot_param_size => 32,
352 delta_vector_size => 32,
352 delta_vector_size => 32,
353 delta_vector_size_f0_2 => 7, -- log2(96)
353 delta_vector_size_f0_2 => 7, -- log2(96)
354 pindex => 15,
354 pindex => 15,
355 paddr => 15,
355 paddr => 15,
356 pmask => 16#fff#,
356 pmask => 16#fff#,
357 pirq_ms => 6,
357 pirq_ms => 6,
358 pirq_wfp => 14,
358 pirq_wfp => 14,
359 hindex => 2,
359 hindex => 2,
360 top_lfr_version => X"01011A") -- aa.bb.cc version
360 top_lfr_version => X"010121") -- aa.bb.cc version
361 -- AA : BOARD NUMBER
361 -- AA : BOARD NUMBER
362 -- 0 => MINI_LFR
362 -- 0 => MINI_LFR
363 -- 1 => EM
363 -- 1 => EM
364 PORT MAP (
364 PORT MAP (
365 clk => clk_25,
365 clk => clk_25,
366 rstn => rstn,
366 rstn => rstn,
367 sample_B => sample_s(2 DOWNTO 0),
367 sample_B => sample_s(2 DOWNTO 0),
368 sample_E => sample_s(7 DOWNTO 3),
368 sample_E => sample_s(7 DOWNTO 3),
369 sample_val => sample_val,
369 sample_val => sample_val,
370 apbi => apbi_ext,
370 apbi => apbi_ext,
371 apbo => apbo_ext(15),
371 apbo => apbo_ext(15),
372 ahbi => ahbi_m_ext,
372 ahbi => ahbi_m_ext,
373 ahbo => ahbo_m_ext(2),
373 ahbo => ahbo_m_ext(2),
374 coarse_time => coarse_time,
374 coarse_time => coarse_time,
375 fine_time => fine_time,
375 fine_time => fine_time,
376 data_shaping_BW => bias_fail_sw,
376 data_shaping_BW => bias_fail_sw);--,
377 observation_vector_0 => OPEN,
377 --observation_vector_0 => OPEN,
378 observation_vector_1 => OPEN,
378 --observation_vector_1 => OPEN,
379 observation_reg => observation_reg);
379 --observation_reg => observation_reg);
380
380
381
381
382 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
382 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
383 sample_s(I) <= sample(I) & '0' & '0';
383 sample_s(I) <= sample(I) & '0' & '0';
384 END GENERATE all_sample;
384 END GENERATE all_sample;
385
385
386 -----------------------------------------------------------------------------
386 -----------------------------------------------------------------------------
387 --
387 --
388 -----------------------------------------------------------------------------
388 -----------------------------------------------------------------------------
389 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
389 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
390 GENERIC MAP (
390 GENERIC MAP (
391 ChanelCount => 8,
391 ChanelCount => 8,
392 ncycle_cnv_high => 13,
392 ncycle_cnv_high => 13,
393 ncycle_cnv => 25)
393 ncycle_cnv => 25)
394 PORT MAP (
394 PORT MAP (
395 cnv_clk => clk_24,
395 cnv_clk => clk_24,
396 cnv_rstn => rstn,
396 cnv_rstn => rstn,
397 cnv => ADC_smpclk_s,
397 cnv => ADC_smpclk_s,
398 clk => clk_25,
398 clk => clk_25,
399 rstn => rstn,
399 rstn => rstn,
400 ADC_data => ADC_data,
400 ADC_data => ADC_data,
401 ADC_nOE => ADC_OEB_bar_CH,
401 ADC_nOE => ADC_OEB_bar_CH,
402 sample => sample,
402 sample => sample,
403 sample_val => sample_val);
403 sample_val => sample_val);
404
404
405
405
406
406
407
407
408 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
408 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
409 -- GENERIC MAP (
409 -- GENERIC MAP (
410 -- ChanelCount => 8,
410 -- ChanelCount => 8,
411 -- ncycle_cnv_high => 40, -- TODO : 79
411 -- ncycle_cnv_high => 40, -- TODO : 79
412 -- ncycle_cnv => 250) -- TODO : 500
412 -- ncycle_cnv => 250) -- TODO : 500
413 -- PORT MAP (
413 -- PORT MAP (
414 -- cnv_clk => clk_24, -- TODO : 49.152
414 -- cnv_clk => clk_24, -- TODO : 49.152
415 -- cnv_rstn => rstn, -- ok
415 -- cnv_rstn => rstn, -- ok
416 -- cnv => ADC_smpclk_s, -- ok
416 -- cnv => ADC_smpclk_s, -- ok
417 -- clk => clk_25, -- ok
417 -- clk => clk_25, -- ok
418 -- rstn => rstn, -- ok
418 -- rstn => rstn, -- ok
419 -- ADC_data => ADC_data, -- ok
419 -- ADC_data => ADC_data, -- ok
420 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
420 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
421 -- sample => sample, -- ok
421 -- sample => sample, -- ok
422 -- sample_val => sample_val); -- ok
422 -- sample_val => sample_val); -- ok
423
423
424 ADC_smpclk <= ADC_smpclk_s;
424 ADC_smpclk <= ADC_smpclk_s;
425
425
426 TAG8 <= ADC_smpclk_s;
426 TAG8 <= ADC_smpclk_s;
427
427
428 END beh;
428 END beh;
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@@ -1,56 +1,56
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
5 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 #VHDLSIMFILES=testbench.vhd
17 #VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
22
22
23 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
25
25
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
27 CLEAN=soft-clean
27 CLEAN=soft-clean
28
28
29 TECHLIBS = proasic3e
29 TECHLIBS = proasic3e
30
30
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
32 tmtc openchip hynix ihp gleichmann micron usbhc
32 tmtc openchip hynix ihp gleichmann micron usbhc
33
33
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
36 ./amba_lcd_16x2_ctrlr \
36 ./amba_lcd_16x2_ctrlr \
37 ./general_purpose/lpp_AMR \
37 ./general_purpose/lpp_AMR \
38 ./general_purpose/lpp_balise \
38 ./general_purpose/lpp_balise \
39 ./general_purpose/lpp_delay \
39 ./general_purpose/lpp_delay \
40 ./lpp_bootloader \
40 ./lpp_bootloader \
41 ./lpp_cna \
41 ./lpp_cna \
42 ./dsp/lpp_fft_rtax \
42 ./dsp/lpp_fft_rtax \
43 ./lpp_uart \
43 ./lpp_uart \
44 ./lpp_usb \
44 ./lpp_usb \
45
45
46 FILESKIP = i2cmst.vhd \
46 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
47 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
49 Top_MatrixSpec.vhd \
50 APB_FFT.vhd
50 APB_FFT.vhd
51
51
52 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/bin/Makefile
53 include $(GRLIB)/software/leon3/Makefile
53 include $(GRLIB)/software/leon3/Makefile
54
54
55 ################## project specific targets ##########################
55 ################## project specific targets ##########################
56
56
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@@ -1,629 +1,691
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
182
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
181
187
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
182 BEGIN -- beh
192 BEGIN -- beh
183
193
184 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
185 -- CLK
195 -- CLK
186 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
187
197
188 PROCESS(clk_50)
198 --PROCESS(clk_50)
189 BEGIN
199 --BEGIN
190 IF clk_50'EVENT AND clk_50 = '1' THEN
200 -- IF clk_50'EVENT AND clk_50 = '1' THEN
191 clk_50_s <= NOT clk_50_s;
201 -- clk_50_s <= NOT clk_50_s;
202 -- END IF;
203 --END PROCESS;
204
205 --PROCESS(clk_50_s)
206 --BEGIN
207 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
208 -- clk_25 <= NOT clk_25;
209 -- END IF;
210 --END PROCESS;
211
212 --PROCESS(clk_49)
213 --BEGIN
214 -- IF clk_49'EVENT AND clk_49 = '1' THEN
215 -- clk_24 <= NOT clk_24;
216 -- END IF;
217 --END PROCESS;
218
219 --PROCESS(clk_25)
220 --BEGIN
221 -- IF clk_25'EVENT AND clk_25 = '1' THEN
222 -- rstn_25 <= reset;
223 -- END IF;
224 --END PROCESS;
225
226 PROCESS (clk_50, reset)
227 BEGIN -- PROCESS
228 IF reset = '0' THEN -- asynchronous reset (active low)
229 clk_50_s <= '0';
230 rstn_50 <= '0';
231 rstn_50_d1 <= '0';
232 rstn_50_d2 <= '0';
233 rstn_50_d3 <= '0';
234
235 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
236 clk_50_s <= NOT clk_50_s;
237 rstn_50_d1 <= '1';
238 rstn_50_d2 <= rstn_50_d1;
239 rstn_50_d3 <= rstn_50_d2;
240 rstn_50 <= rstn_50_d3;
192 END IF;
241 END IF;
193 END PROCESS;
242 END PROCESS;
194
243
195 PROCESS(clk_50_s)
244 PROCESS (clk_50_s, rstn_50)
196 BEGIN
245 BEGIN -- PROCESS
197 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
246 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
198 clk_25 <= NOT clk_25;
247 clk_25 <= '0';
248 rstn_25 <= '0';
249 rstn_25_d1 <= '0';
250 rstn_25_d2 <= '0';
251 rstn_25_d3 <= '0';
252 ELSIF clk_50_s'event AND clk_50_s = '1' THEN -- rising clock edge
253 clk_25 <= NOT clk_25;
254 rstn_25_d1 <= '1';
255 rstn_25_d2 <= rstn_25_d1;
256 rstn_25_d3 <= rstn_25_d2;
257 rstn_25 <= rstn_25_d3;
199 END IF;
258 END IF;
200 END PROCESS;
259 END PROCESS;
201
260
202 PROCESS(clk_49)
261 PROCESS (clk_49, reset)
203 BEGIN
262 BEGIN -- PROCESS
204 IF clk_49'EVENT AND clk_49 = '1' THEN
263 IF reset = '0' THEN -- asynchronous reset (active low)
205 clk_24 <= NOT clk_24;
264 clk_24 <= '0';
265 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
266 clk_24 <= NOT clk_24;
206 END IF;
267 END IF;
207 END PROCESS;
268 END PROCESS;
208
269
209 -----------------------------------------------------------------------------
270 -----------------------------------------------------------------------------
210
271
211 PROCESS (clk_25, reset)
272 PROCESS (clk_25, rstn_25)
212 BEGIN -- PROCESS
273 BEGIN -- PROCESS
213 IF reset = '0' THEN -- asynchronous reset (active low)
274 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
214 LED0 <= '0';
275 LED0 <= '0';
215 LED1 <= '0';
276 LED1 <= '0';
216 LED2 <= '0';
277 LED2 <= '0';
217 --IO1 <= '0';
278 --IO1 <= '0';
218 --IO2 <= '1';
279 --IO2 <= '1';
219 --IO3 <= '0';
280 --IO3 <= '0';
220 --IO4 <= '0';
281 --IO4 <= '0';
221 --IO5 <= '0';
282 --IO5 <= '0';
222 --IO6 <= '0';
283 --IO6 <= '0';
223 --IO7 <= '0';
284 --IO7 <= '0';
224 --IO8 <= '0';
285 --IO8 <= '0';
225 --IO9 <= '0';
286 --IO9 <= '0';
226 --IO10 <= '0';
287 --IO10 <= '0';
227 --IO11 <= '0';
288 --IO11 <= '0';
228 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
289 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
229 LED0 <= '0';
290 LED0 <= '0';
230 LED1 <= '1';
291 LED1 <= '1';
231 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
292 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
232 --IO1 <= '1';
293 --IO1 <= '1';
233 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
294 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
234 --IO3 <= ADC_SDO(0);
295 --IO3 <= ADC_SDO(0);
235 --IO4 <= ADC_SDO(1);
296 --IO4 <= ADC_SDO(1);
236 --IO5 <= ADC_SDO(2);
297 --IO5 <= ADC_SDO(2);
237 --IO6 <= ADC_SDO(3);
298 --IO6 <= ADC_SDO(3);
238 --IO7 <= ADC_SDO(4);
299 --IO7 <= ADC_SDO(4);
239 --IO8 <= ADC_SDO(5);
300 --IO8 <= ADC_SDO(5);
240 --IO9 <= ADC_SDO(6);
301 --IO9 <= ADC_SDO(6);
241 --IO10 <= ADC_SDO(7);
302 --IO10 <= ADC_SDO(7);
242 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
303 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
243 END IF;
304 END IF;
244 END PROCESS;
305 END PROCESS;
245
306
246 PROCESS (clk_24, reset)
307 PROCESS (clk_24, rstn_25)
247 BEGIN -- PROCESS
308 BEGIN -- PROCESS
248 IF reset = '0' THEN -- asynchronous reset (active low)
309 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
249 I00_s <= '0';
310 I00_s <= '0';
250 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
311 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
251 I00_s <= NOT I00_s ;
312 I00_s <= NOT I00_s ;
252 END IF;
313 END IF;
253 END PROCESS;
314 END PROCESS;
254 -- IO0 <= I00_s;
315 -- IO0 <= I00_s;
255
316
256 --UARTs
317 --UARTs
257 nCTS1 <= '1';
318 nCTS1 <= '1';
258 nCTS2 <= '1';
319 nCTS2 <= '1';
259 nDCD2 <= '1';
320 nDCD2 <= '1';
260
321
261 --EXT CONNECTOR
322 --EXT CONNECTOR
262
323
263 --SPACE WIRE
324 --SPACE WIRE
264
325
265 leon3_soc_1 : leon3_soc
326 leon3_soc_1 : leon3_soc
266 GENERIC MAP (
327 GENERIC MAP (
267 fabtech => apa3e,
328 fabtech => apa3e,
268 memtech => apa3e,
329 memtech => apa3e,
269 padtech => inferred,
330 padtech => inferred,
270 clktech => inferred,
331 clktech => inferred,
271 disas => 0,
332 disas => 0,
272 dbguart => 0,
333 dbguart => 0,
273 pclow => 2,
334 pclow => 2,
274 clk_freq => 25000,
335 clk_freq => 25000,
275 NB_CPU => 1,
336 NB_CPU => 1,
276 ENABLE_FPU => 1,
337 ENABLE_FPU => 1,
277 FPU_NETLIST => 0,
338 FPU_NETLIST => 0,
278 ENABLE_DSU => 1,
339 ENABLE_DSU => 1,
279 ENABLE_AHB_UART => 1,
340 ENABLE_AHB_UART => 1,
280 ENABLE_APB_UART => 1,
341 ENABLE_APB_UART => 1,
281 ENABLE_IRQMP => 1,
342 ENABLE_IRQMP => 1,
282 ENABLE_GPT => 1,
343 ENABLE_GPT => 1,
283 NB_AHB_MASTER => NB_AHB_MASTER,
344 NB_AHB_MASTER => NB_AHB_MASTER,
284 NB_AHB_SLAVE => NB_AHB_SLAVE,
345 NB_AHB_SLAVE => NB_AHB_SLAVE,
285 NB_APB_SLAVE => NB_APB_SLAVE,
346 NB_APB_SLAVE => NB_APB_SLAVE,
286 ADDRESS_SIZE => 20)
347 ADDRESS_SIZE => 20)
287 PORT MAP (
348 PORT MAP (
288 clk => clk_25,
349 clk => clk_25,
289 reset => reset,
350 reset => rstn_25,
290 errorn => errorn,
351 errorn => errorn,
291 ahbrxd => TXD1,
352 ahbrxd => TXD1,
292 ahbtxd => RXD1,
353 ahbtxd => RXD1,
293 urxd1 => TXD2,
354 urxd1 => TXD2,
294 utxd1 => RXD2,
355 utxd1 => RXD2,
295 address => SRAM_A,
356 address => SRAM_A,
296 data => SRAM_DQ,
357 data => SRAM_DQ,
297 nSRAM_BE0 => SRAM_nBE(0),
358 nSRAM_BE0 => SRAM_nBE(0),
298 nSRAM_BE1 => SRAM_nBE(1),
359 nSRAM_BE1 => SRAM_nBE(1),
299 nSRAM_BE2 => SRAM_nBE(2),
360 nSRAM_BE2 => SRAM_nBE(2),
300 nSRAM_BE3 => SRAM_nBE(3),
361 nSRAM_BE3 => SRAM_nBE(3),
301 nSRAM_WE => SRAM_nWE,
362 nSRAM_WE => SRAM_nWE,
302 nSRAM_CE => SRAM_CE,
363 nSRAM_CE => SRAM_CE,
303 nSRAM_OE => SRAM_nOE,
364 nSRAM_OE => SRAM_nOE,
304
365
305 apbi_ext => apbi_ext,
366 apbi_ext => apbi_ext,
306 apbo_ext => apbo_ext,
367 apbo_ext => apbo_ext,
307 ahbi_s_ext => ahbi_s_ext,
368 ahbi_s_ext => ahbi_s_ext,
308 ahbo_s_ext => ahbo_s_ext,
369 ahbo_s_ext => ahbo_s_ext,
309 ahbi_m_ext => ahbi_m_ext,
370 ahbi_m_ext => ahbi_m_ext,
310 ahbo_m_ext => ahbo_m_ext);
371 ahbo_m_ext => ahbo_m_ext);
311
372
312 -------------------------------------------------------------------------------
373 -------------------------------------------------------------------------------
313 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
314 -------------------------------------------------------------------------------
375 -------------------------------------------------------------------------------
315 apb_lfr_time_management_1 : apb_lfr_time_management
376 apb_lfr_time_management_1 : apb_lfr_time_management
316 GENERIC MAP (
377 GENERIC MAP (
317 pindex => 6,
378 pindex => 6,
318 paddr => 6,
379 paddr => 6,
319 pmask => 16#fff#,
380 pmask => 16#fff#,
320 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
381 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
321 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
382 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
322 PORT MAP (
383 PORT MAP (
323 clk25MHz => clk_25,
384 clk25MHz => clk_25,
324 clk24_576MHz => clk_24, -- 49.152MHz/2
385 clk24_576MHz => clk_24, -- 49.152MHz/2
325 resetn => reset,
386 resetn => rstn_25,
326 grspw_tick => swno.tickout,
387 grspw_tick => swno.tickout,
327 apbi => apbi_ext,
388 apbi => apbi_ext,
328 apbo => apbo_ext(6),
389 apbo => apbo_ext(6),
329 coarse_time => coarse_time,
390 coarse_time => coarse_time,
330 fine_time => fine_time,
391 fine_time => fine_time,
331 LFR_soft_rstn => LFR_soft_rstn
392 LFR_soft_rstn => LFR_soft_rstn
332 );
393 );
333
394
334 -----------------------------------------------------------------------
395 -----------------------------------------------------------------------
335 --- SpaceWire --------------------------------------------------------
396 --- SpaceWire --------------------------------------------------------
336 -----------------------------------------------------------------------
397 -----------------------------------------------------------------------
337
398
338 SPW_EN <= '1';
399 SPW_EN <= '1';
339
400
340 spw_clk <= clk_50_s;
401 spw_clk <= clk_50_s;
341 spw_rxtxclk <= spw_clk;
402 spw_rxtxclk <= spw_clk;
342 spw_rxclkn <= NOT spw_rxtxclk;
403 spw_rxclkn <= NOT spw_rxtxclk;
343
404
344 -- PADS for SPW1
405 -- PADS for SPW1
345 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
406 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_DIN, dtmp(0));
407 PORT MAP (SPW_NOM_DIN, dtmp(0));
347 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
408 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
348 PORT MAP (SPW_NOM_SIN, stmp(0));
409 PORT MAP (SPW_NOM_SIN, stmp(0));
349 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
410 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
350 PORT MAP (SPW_NOM_DOUT, swno.d(0));
411 PORT MAP (SPW_NOM_DOUT, swno.d(0));
351 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
412 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
352 PORT MAP (SPW_NOM_SOUT, swno.s(0));
413 PORT MAP (SPW_NOM_SOUT, swno.s(0));
353 -- PADS FOR SPW2
414 -- PADS FOR SPW2
354 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
415 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
355 PORT MAP (SPW_RED_SIN, dtmp(1));
416 PORT MAP (SPW_RED_SIN, dtmp(1));
356 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
417 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
357 PORT MAP (SPW_RED_DIN, stmp(1));
418 PORT MAP (SPW_RED_DIN, stmp(1));
358 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
419 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
359 PORT MAP (SPW_RED_DOUT, swno.d(1));
420 PORT MAP (SPW_RED_DOUT, swno.d(1));
360 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
421 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
361 PORT MAP (SPW_RED_SOUT, swno.s(1));
422 PORT MAP (SPW_RED_SOUT, swno.s(1));
362
423
363 -- GRSPW PHY
424 -- GRSPW PHY
364 --spw1_input: if CFG_SPW_GRSPW = 1 generate
425 --spw1_input: if CFG_SPW_GRSPW = 1 generate
365 spw_inputloop : FOR j IN 0 TO 1 GENERATE
426 spw_inputloop : FOR j IN 0 TO 1 GENERATE
366 spw_phy0 : grspw_phy
427 spw_phy0 : grspw_phy
367 GENERIC MAP(
428 GENERIC MAP(
368 tech => apa3e,
429 tech => apa3e,
369 rxclkbuftype => 1,
430 rxclkbuftype => 1,
370 scantest => 0)
431 scantest => 0)
371 PORT MAP(
432 PORT MAP(
372 rxrst => swno.rxrst,
433 rxrst => swno.rxrst,
373 di => dtmp(j),
434 di => dtmp(j),
374 si => stmp(j),
435 si => stmp(j),
375 rxclko => spw_rxclk(j),
436 rxclko => spw_rxclk(j),
376 do => swni.d(j),
437 do => swni.d(j),
377 ndo => swni.nd(j*5+4 DOWNTO j*5),
438 ndo => swni.nd(j*5+4 DOWNTO j*5),
378 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
439 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
379 END GENERATE spw_inputloop;
440 END GENERATE spw_inputloop;
380
441
381 -- SPW core
442 -- SPW core
382 sw0 : grspwm GENERIC MAP(
443 sw0 : grspwm GENERIC MAP(
383 tech => apa3e,
444 tech => apa3e,
384 hindex => 1,
445 hindex => 1,
385 pindex => 5,
446 pindex => 5,
386 paddr => 5,
447 paddr => 5,
387 pirq => 11,
448 pirq => 11,
388 sysfreq => 25000, -- CPU_FREQ
449 sysfreq => 25000, -- CPU_FREQ
389 rmap => 1,
450 rmap => 1,
390 rmapcrc => 1,
451 rmapcrc => 1,
391 fifosize1 => 16,
452 fifosize1 => 16,
392 fifosize2 => 16,
453 fifosize2 => 16,
393 rxclkbuftype => 1,
454 rxclkbuftype => 1,
394 rxunaligned => 0,
455 rxunaligned => 0,
395 rmapbufs => 4,
456 rmapbufs => 4,
396 ft => 0,
457 ft => 0,
397 netlist => 0,
458 netlist => 0,
398 ports => 2,
459 ports => 2,
399 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
460 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
400 memtech => apa3e,
461 memtech => apa3e,
401 destkey => 2,
462 destkey => 2,
402 spwcore => 1
463 spwcore => 1
403 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
464 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
404 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
465 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
405 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
466 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
406 )
467 )
407 PORT MAP(reset, clk_25, spw_rxclk(0),
468 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
408 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
469 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
409 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
470 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
410 swni, swno);
471 swni, swno);
411
472
412 swni.tickin <= '0';
473 swni.tickin <= '0';
413 swni.rmapen <= '1';
474 swni.rmapen <= '1';
414 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
475 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
415 swni.tickinraw <= '0';
476 swni.tickinraw <= '0';
416 swni.timein <= (OTHERS => '0');
477 swni.timein <= (OTHERS => '0');
417 swni.dcrstval <= (OTHERS => '0');
478 swni.dcrstval <= (OTHERS => '0');
418 swni.timerrstval <= (OTHERS => '0');
479 swni.timerrstval <= (OTHERS => '0');
419
480
420 -------------------------------------------------------------------------------
481 -------------------------------------------------------------------------------
421 -- LFR ------------------------------------------------------------------------
482 -- LFR ------------------------------------------------------------------------
422 -------------------------------------------------------------------------------
483 -------------------------------------------------------------------------------
423
484
424
485
425 LFR_rstn <= LFR_soft_rstn AND reset;
486 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
487 LFR_rstn <= rstn_25;
426
488
427 lpp_lfr_1 : lpp_lfr
489 lpp_lfr_1 : lpp_lfr
428 GENERIC MAP (
490 GENERIC MAP (
429 Mem_use => use_RAM,
491 Mem_use => use_RAM,
430 nb_data_by_buffer_size => 32,
492 nb_data_by_buffer_size => 32,
431 nb_snapshot_param_size => 32,
493 nb_snapshot_param_size => 32,
432 delta_vector_size => 32,
494 delta_vector_size => 32,
433 delta_vector_size_f0_2 => 7, -- log2(96)
495 delta_vector_size_f0_2 => 7, -- log2(96)
434 pindex => 15,
496 pindex => 15,
435 paddr => 15,
497 paddr => 15,
436 pmask => 16#fff#,
498 pmask => 16#fff#,
437 pirq_ms => 6,
499 pirq_ms => 6,
438 pirq_wfp => 14,
500 pirq_wfp => 14,
439 hindex => 2,
501 hindex => 2,
440 top_lfr_version => X"000121") -- aa.bb.cc version
502 top_lfr_version => X"000122") -- aa.bb.cc version
441 PORT MAP (
503 PORT MAP (
442 clk => clk_25,
504 clk => clk_25,
443 rstn => LFR_rstn,
505 rstn => LFR_rstn,
444 sample_B => sample_s(2 DOWNTO 0),
506 sample_B => sample_s(2 DOWNTO 0),
445 sample_E => sample_s(7 DOWNTO 3),
507 sample_E => sample_s(7 DOWNTO 3),
446 sample_val => sample_val,
508 sample_val => sample_val,
447 apbi => apbi_ext,
509 apbi => apbi_ext,
448 apbo => apbo_ext(15),
510 apbo => apbo_ext(15),
449 ahbi => ahbi_m_ext,
511 ahbi => ahbi_m_ext,
450 ahbo => ahbo_m_ext(2),
512 ahbo => ahbo_m_ext(2),
451 coarse_time => coarse_time,
513 coarse_time => coarse_time,
452 fine_time => fine_time,
514 fine_time => fine_time,
453 data_shaping_BW => bias_fail_sw_sig);
515 data_shaping_BW => bias_fail_sw_sig);
454
516
455 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
517 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
456 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
518 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
457 END GENERATE all_sample;
519 END GENERATE all_sample;
458
520
459
521
460
522
461 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
523 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
462 GENERIC MAP(
524 GENERIC MAP(
463 ChannelCount => 8,
525 ChannelCount => 8,
464 SampleNbBits => 14,
526 SampleNbBits => 14,
465 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
527 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
466 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
528 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
467 PORT MAP (
529 PORT MAP (
468 -- CONV
530 -- CONV
469 cnv_clk => clk_24,
531 cnv_clk => clk_24,
470 cnv_rstn => reset,
532 cnv_rstn => rstn_25,
471 cnv => ADC_nCS_sig,
533 cnv => ADC_nCS_sig,
472 -- DATA
534 -- DATA
473 clk => clk_25,
535 clk => clk_25,
474 rstn => reset,
536 rstn => rstn_25,
475 sck => ADC_CLK_sig,
537 sck => ADC_CLK_sig,
476 sdo => ADC_SDO_sig,
538 sdo => ADC_SDO_sig,
477 -- SAMPLE
539 -- SAMPLE
478 sample => sample,
540 sample => sample,
479 sample_val => sample_val);
541 sample_val => sample_val);
480
542
481 --IO10 <= ADC_SDO_sig(5);
543 --IO10 <= ADC_SDO_sig(5);
482 --IO9 <= ADC_SDO_sig(4);
544 --IO9 <= ADC_SDO_sig(4);
483 --IO8 <= ADC_SDO_sig(3);
545 --IO8 <= ADC_SDO_sig(3);
484
546
485 ADC_nCS <= ADC_nCS_sig;
547 ADC_nCS <= ADC_nCS_sig;
486 ADC_CLK <= ADC_CLK_sig;
548 ADC_CLK <= ADC_CLK_sig;
487 ADC_SDO_sig <= ADC_SDO;
549 ADC_SDO_sig <= ADC_SDO;
488
550
489 ----------------------------------------------------------------------
551 ----------------------------------------------------------------------
490 --- GPIO -----------------------------------------------------------
552 --- GPIO -----------------------------------------------------------
491 ----------------------------------------------------------------------
553 ----------------------------------------------------------------------
492
554
493 grgpio0 : grgpio
555 grgpio0 : grgpio
494 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
556 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
495 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
557 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
496
558
497 --pio_pad_0 : iopad
559 --pio_pad_0 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
560 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
561 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
500 --pio_pad_1 : iopad
562 --pio_pad_1 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
563 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
564 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
503 --pio_pad_2 : iopad
565 --pio_pad_2 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
566 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
567 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
506 --pio_pad_3 : iopad
568 --pio_pad_3 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
569 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
570 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
509 --pio_pad_4 : iopad
571 --pio_pad_4 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
572 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
573 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
512 --pio_pad_5 : iopad
574 --pio_pad_5 : iopad
513 -- GENERIC MAP (tech => CFG_PADTECH)
575 -- GENERIC MAP (tech => CFG_PADTECH)
514 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
576 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
515 --pio_pad_6 : iopad
577 --pio_pad_6 : iopad
516 -- GENERIC MAP (tech => CFG_PADTECH)
578 -- GENERIC MAP (tech => CFG_PADTECH)
517 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
579 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
518 --pio_pad_7 : iopad
580 --pio_pad_7 : iopad
519 -- GENERIC MAP (tech => CFG_PADTECH)
581 -- GENERIC MAP (tech => CFG_PADTECH)
520 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
582 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
521
583
522 PROCESS (clk_25, reset)
584 PROCESS (clk_25, rstn_25)
523 BEGIN -- PROCESS
585 BEGIN -- PROCESS
524 IF reset = '0' THEN -- asynchronous reset (active low)
586 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
525 IO0 <= '0';
587 IO0 <= '0';
526 IO1 <= '0';
588 IO1 <= '0';
527 IO2 <= '0';
589 IO2 <= '0';
528 IO3 <= '0';
590 IO3 <= '0';
529 IO4 <= '0';
591 IO4 <= '0';
530 IO5 <= '0';
592 IO5 <= '0';
531 IO6 <= '0';
593 IO6 <= '0';
532 IO7 <= '0';
594 IO7 <= '0';
533 IO8 <= '0';
595 IO8 <= '0';
534 IO9 <= '0';
596 IO9 <= '0';
535 IO10 <= '0';
597 IO10 <= '0';
536 IO11 <= '0';
598 IO11 <= '0';
537 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
599 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
538 CASE gpioo.dout(2 DOWNTO 0) IS
600 CASE gpioo.dout(2 DOWNTO 0) IS
539 WHEN "011" =>
601 WHEN "011" =>
540 IO0 <= observation_reg(0 );
602 IO0 <= observation_reg(0 );
541 IO1 <= observation_reg(1 );
603 IO1 <= observation_reg(1 );
542 IO2 <= observation_reg(2 );
604 IO2 <= observation_reg(2 );
543 IO3 <= observation_reg(3 );
605 IO3 <= observation_reg(3 );
544 IO4 <= observation_reg(4 );
606 IO4 <= observation_reg(4 );
545 IO5 <= observation_reg(5 );
607 IO5 <= observation_reg(5 );
546 IO6 <= observation_reg(6 );
608 IO6 <= observation_reg(6 );
547 IO7 <= observation_reg(7 );
609 IO7 <= observation_reg(7 );
548 IO8 <= observation_reg(8 );
610 IO8 <= observation_reg(8 );
549 IO9 <= observation_reg(9 );
611 IO9 <= observation_reg(9 );
550 IO10 <= observation_reg(10);
612 IO10 <= observation_reg(10);
551 IO11 <= observation_reg(11);
613 IO11 <= observation_reg(11);
552 WHEN "001" =>
614 WHEN "001" =>
553 IO0 <= observation_reg(0 + 12);
615 IO0 <= observation_reg(0 + 12);
554 IO1 <= observation_reg(1 + 12);
616 IO1 <= observation_reg(1 + 12);
555 IO2 <= observation_reg(2 + 12);
617 IO2 <= observation_reg(2 + 12);
556 IO3 <= observation_reg(3 + 12);
618 IO3 <= observation_reg(3 + 12);
557 IO4 <= observation_reg(4 + 12);
619 IO4 <= observation_reg(4 + 12);
558 IO5 <= observation_reg(5 + 12);
620 IO5 <= observation_reg(5 + 12);
559 IO6 <= observation_reg(6 + 12);
621 IO6 <= observation_reg(6 + 12);
560 IO7 <= observation_reg(7 + 12);
622 IO7 <= observation_reg(7 + 12);
561 IO8 <= observation_reg(8 + 12);
623 IO8 <= observation_reg(8 + 12);
562 IO9 <= observation_reg(9 + 12);
624 IO9 <= observation_reg(9 + 12);
563 IO10 <= observation_reg(10 + 12);
625 IO10 <= observation_reg(10 + 12);
564 IO11 <= observation_reg(11 + 12);
626 IO11 <= observation_reg(11 + 12);
565 WHEN "010" =>
627 WHEN "010" =>
566 IO0 <= observation_reg(0 + 12 + 12);
628 IO0 <= observation_reg(0 + 12 + 12);
567 IO1 <= observation_reg(1 + 12 + 12);
629 IO1 <= observation_reg(1 + 12 + 12);
568 IO2 <= observation_reg(2 + 12 + 12);
630 IO2 <= observation_reg(2 + 12 + 12);
569 IO3 <= observation_reg(3 + 12 + 12);
631 IO3 <= observation_reg(3 + 12 + 12);
570 IO4 <= observation_reg(4 + 12 + 12);
632 IO4 <= observation_reg(4 + 12 + 12);
571 IO5 <= observation_reg(5 + 12 + 12);
633 IO5 <= observation_reg(5 + 12 + 12);
572 IO6 <= observation_reg(6 + 12 + 12);
634 IO6 <= observation_reg(6 + 12 + 12);
573 IO7 <= observation_reg(7 + 12 + 12);
635 IO7 <= observation_reg(7 + 12 + 12);
574 IO8 <= '0';
636 IO8 <= '0';
575 IO9 <= '0';
637 IO9 <= '0';
576 IO10 <= '0';
638 IO10 <= '0';
577 IO11 <= '0';
639 IO11 <= '0';
578 WHEN "000" =>
640 WHEN "000" =>
579 IO0 <= observation_vector_0(0 );
641 IO0 <= observation_vector_0(0 );
580 IO1 <= observation_vector_0(1 );
642 IO1 <= observation_vector_0(1 );
581 IO2 <= observation_vector_0(2 );
643 IO2 <= observation_vector_0(2 );
582 IO3 <= observation_vector_0(3 );
644 IO3 <= observation_vector_0(3 );
583 IO4 <= observation_vector_0(4 );
645 IO4 <= observation_vector_0(4 );
584 IO5 <= observation_vector_0(5 );
646 IO5 <= observation_vector_0(5 );
585 IO6 <= observation_vector_0(6 );
647 IO6 <= observation_vector_0(6 );
586 IO7 <= observation_vector_0(7 );
648 IO7 <= observation_vector_0(7 );
587 IO8 <= observation_vector_0(8 );
649 IO8 <= observation_vector_0(8 );
588 IO9 <= observation_vector_0(9 );
650 IO9 <= observation_vector_0(9 );
589 IO10 <= observation_vector_0(10);
651 IO10 <= observation_vector_0(10);
590 IO11 <= observation_vector_0(11);
652 IO11 <= observation_vector_0(11);
591 WHEN "100" =>
653 WHEN "100" =>
592 IO0 <= observation_vector_1(0 );
654 IO0 <= observation_vector_1(0 );
593 IO1 <= observation_vector_1(1 );
655 IO1 <= observation_vector_1(1 );
594 IO2 <= observation_vector_1(2 );
656 IO2 <= observation_vector_1(2 );
595 IO3 <= observation_vector_1(3 );
657 IO3 <= observation_vector_1(3 );
596 IO4 <= observation_vector_1(4 );
658 IO4 <= observation_vector_1(4 );
597 IO5 <= observation_vector_1(5 );
659 IO5 <= observation_vector_1(5 );
598 IO6 <= observation_vector_1(6 );
660 IO6 <= observation_vector_1(6 );
599 IO7 <= observation_vector_1(7 );
661 IO7 <= observation_vector_1(7 );
600 IO8 <= observation_vector_1(8 );
662 IO8 <= observation_vector_1(8 );
601 IO9 <= observation_vector_1(9 );
663 IO9 <= observation_vector_1(9 );
602 IO10 <= observation_vector_1(10);
664 IO10 <= observation_vector_1(10);
603 IO11 <= observation_vector_1(11);
665 IO11 <= observation_vector_1(11);
604 WHEN OTHERS => NULL;
666 WHEN OTHERS => NULL;
605 END CASE;
667 END CASE;
606
668
607 END IF;
669 END IF;
608 END PROCESS;
670 END PROCESS;
609 -----------------------------------------------------------------------------
671 -----------------------------------------------------------------------------
610 --
672 --
611 -----------------------------------------------------------------------------
673 -----------------------------------------------------------------------------
612 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
674 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
613 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
675 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
614 apbo_ext(I) <= apb_none;
676 apbo_ext(I) <= apb_none;
615 END GENERATE apbo_ext_not_used;
677 END GENERATE apbo_ext_not_used;
616 END GENERATE all_apbo_ext;
678 END GENERATE all_apbo_ext;
617
679
618
680
619 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
681 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
620 ahbo_s_ext(I) <= ahbs_none;
682 ahbo_s_ext(I) <= ahbs_none;
621 END GENERATE all_ahbo_ext;
683 END GENERATE all_ahbo_ext;
622
684
623 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
685 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
624 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
686 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
625 ahbo_m_ext(I) <= ahbm_none;
687 ahbo_m_ext(I) <= ahbm_none;
626 END GENERATE ahbo_m_ext_not_used;
688 END GENERATE ahbo_m_ext_not_used;
627 END GENERATE all_ahbo_m_ext;
689 END GENERATE all_ahbo_m_ext;
628
690
629 END beh;
691 END beh;
Show file before | Show file after | Hide comments
@@ -1,52 +1,53
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14 VHDLSIMFILES= testbench.vhd
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
15 SIMTOP=testbench
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 CLEAN=soft-clean
21 CLEAN=soft-clean
22
22
23 TECHLIBS = proasic3e
23 TECHLIBS = proasic3e
24
24
25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 tmtc openchip hynix ihp gleichmann micron usbhc
26 tmtc openchip hynix ihp gleichmann micron usbhc
27
27
28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 ./amba_lcd_16x2_ctrlr \
30 ./amba_lcd_16x2_ctrlr \
31 ./general_purpose/lpp_AMR \
31 ./general_purpose/lpp_AMR \
32 ./general_purpose/lpp_balise \
32 ./general_purpose/lpp_balise \
33 ./general_purpose/lpp_delay \
33 ./general_purpose/lpp_delay \
34 ./lpp_bootloader \
34 ./lpp_bootloader \
35 ./lpp_cna \
35 ./lpp_cna \
36 ./lpp_uart \
36 ./lpp_uart \
37 ./lpp_usb \
37 ./lpp_usb \
38 ./dsp/lpp_fft_rtax \
38 ./dsp/lpp_fft_rtax \
39 ./lpp_sim/CY7C1061DV33 \
39 ./lpp_sim/CY7C1061DV33 \
40
40
41 FILESKIP =i2cmst.vhd \
41 FILESKIP =i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd \
44 Top_MatrixSpec.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
45 APB_FFT.vhd \
46 CoreFFT_simu.vhd
46 CoreFFT_simu.vhd \
47 lpp_lfr_apbreg_simu.vhd
47
48
48 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/bin/Makefile
49 include $(GRLIB)/software/leon3/Makefile
50 include $(GRLIB)/software/leon3/Makefile
50
51
51 ################## project specific targets ##########################
52 ################## project specific targets ##########################
52
53
Show file before | Show file after | Hide comments
@@ -1,258 +1,270
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
5 LIBRARY STD;
6 use std.textio.all;
6 use std.textio.all;
7
7
8 LIBRARY grlib;
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
19 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21
21
22 ENTITY testbench IS
22 ENTITY testbench IS
23 END;
23 END;
24
24
25 ARCHITECTURE behav OF testbench IS
25 ARCHITECTURE behav OF testbench IS
26
26
27 COMPONENT MINI_LFR_top
27 COMPONENT MINI_LFR_top
28 PORT (
28 PORT (
29 clk_50 : IN STD_LOGIC;
29 clk_50 : IN STD_LOGIC;
30 clk_49 : IN STD_LOGIC;
30 clk_49 : IN STD_LOGIC;
31 reset : IN STD_LOGIC;
31 reset : IN STD_LOGIC;
32 BP0 : IN STD_LOGIC;
32 BP0 : IN STD_LOGIC;
33 BP1 : IN STD_LOGIC;
33 BP1 : IN STD_LOGIC;
34 LED0 : OUT STD_LOGIC;
34 LED0 : OUT STD_LOGIC;
35 LED1 : OUT STD_LOGIC;
35 LED1 : OUT STD_LOGIC;
36 LED2 : OUT STD_LOGIC;
36 LED2 : OUT STD_LOGIC;
37 TXD1 : IN STD_LOGIC;
37 TXD1 : IN STD_LOGIC;
38 RXD1 : OUT STD_LOGIC;
38 RXD1 : OUT STD_LOGIC;
39 nCTS1 : OUT STD_LOGIC;
39 nCTS1 : OUT STD_LOGIC;
40 nRTS1 : IN STD_LOGIC;
40 nRTS1 : IN STD_LOGIC;
41 TXD2 : IN STD_LOGIC;
41 TXD2 : IN STD_LOGIC;
42 RXD2 : OUT STD_LOGIC;
42 RXD2 : OUT STD_LOGIC;
43 nCTS2 : OUT STD_LOGIC;
43 nCTS2 : OUT STD_LOGIC;
44 nDTR2 : IN STD_LOGIC;
44 nDTR2 : IN STD_LOGIC;
45 nRTS2 : IN STD_LOGIC;
45 nRTS2 : IN STD_LOGIC;
46 nDCD2 : OUT STD_LOGIC;
46 nDCD2 : OUT STD_LOGIC;
47 IO0 : INOUT STD_LOGIC;
47 IO0 : INOUT STD_LOGIC;
48 IO1 : INOUT STD_LOGIC;
48 IO1 : INOUT STD_LOGIC;
49 IO2 : INOUT STD_LOGIC;
49 IO2 : INOUT STD_LOGIC;
50 IO3 : INOUT STD_LOGIC;
50 IO3 : INOUT STD_LOGIC;
51 IO4 : INOUT STD_LOGIC;
51 IO4 : INOUT STD_LOGIC;
52 IO5 : INOUT STD_LOGIC;
52 IO5 : INOUT STD_LOGIC;
53 IO6 : INOUT STD_LOGIC;
53 IO6 : INOUT STD_LOGIC;
54 IO7 : INOUT STD_LOGIC;
54 IO7 : INOUT STD_LOGIC;
55 IO8 : INOUT STD_LOGIC;
55 IO8 : INOUT STD_LOGIC;
56 IO9 : INOUT STD_LOGIC;
56 IO9 : INOUT STD_LOGIC;
57 IO10 : INOUT STD_LOGIC;
57 IO10 : INOUT STD_LOGIC;
58 IO11 : INOUT STD_LOGIC;
58 IO11 : INOUT STD_LOGIC;
59 SPW_EN : OUT STD_LOGIC;
59 SPW_EN : OUT STD_LOGIC;
60 SPW_NOM_DIN : IN STD_LOGIC;
60 SPW_NOM_DIN : IN STD_LOGIC;
61 SPW_NOM_SIN : IN STD_LOGIC;
61 SPW_NOM_SIN : IN STD_LOGIC;
62 SPW_NOM_DOUT : OUT STD_LOGIC;
62 SPW_NOM_DOUT : OUT STD_LOGIC;
63 SPW_NOM_SOUT : OUT STD_LOGIC;
63 SPW_NOM_SOUT : OUT STD_LOGIC;
64 SPW_RED_DIN : IN STD_LOGIC;
64 SPW_RED_DIN : IN STD_LOGIC;
65 SPW_RED_SIN : IN STD_LOGIC;
65 SPW_RED_SIN : IN STD_LOGIC;
66 SPW_RED_DOUT : OUT STD_LOGIC;
66 SPW_RED_DOUT : OUT STD_LOGIC;
67 SPW_RED_SOUT : OUT STD_LOGIC;
67 SPW_RED_SOUT : OUT STD_LOGIC;
68 ADC_nCS : OUT STD_LOGIC;
68 ADC_nCS : OUT STD_LOGIC;
69 ADC_CLK : OUT STD_LOGIC;
69 ADC_CLK : OUT STD_LOGIC;
70 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
70 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
71 SRAM_nWE : OUT STD_LOGIC;
71 SRAM_nWE : OUT STD_LOGIC;
72 SRAM_CE : OUT STD_LOGIC;
72 SRAM_CE : OUT STD_LOGIC;
73 SRAM_nOE : OUT STD_LOGIC;
73 SRAM_nOE : OUT STD_LOGIC;
74 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
74 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
75 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
75 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
76 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
76 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
77 END COMPONENT;
77 END COMPONENT;
78
78
79 -----------------------------------------------------------------------------
79 -----------------------------------------------------------------------------
80 SIGNAL clk_50 : STD_LOGIC := '0';
80 SIGNAL clk_50 : STD_LOGIC := '0';
81 SIGNAL clk_49 : STD_LOGIC := '0';
81 SIGNAL clk_49 : STD_LOGIC := '0';
82 SIGNAL reset : STD_LOGIC;
82 SIGNAL reset : STD_LOGIC;
83 SIGNAL BP0 : STD_LOGIC;
83 SIGNAL BP0 : STD_LOGIC;
84 SIGNAL BP1 : STD_LOGIC;
84 SIGNAL BP1 : STD_LOGIC;
85 SIGNAL LED0 : STD_LOGIC;
85 SIGNAL LED0 : STD_LOGIC;
86 SIGNAL LED1 : STD_LOGIC;
86 SIGNAL LED1 : STD_LOGIC;
87 SIGNAL LED2 : STD_LOGIC;
87 SIGNAL LED2 : STD_LOGIC;
88 SIGNAL TXD1 : STD_LOGIC;
88 SIGNAL TXD1 : STD_LOGIC;
89 SIGNAL RXD1 : STD_LOGIC;
89 SIGNAL RXD1 : STD_LOGIC;
90 SIGNAL nCTS1 : STD_LOGIC;
90 SIGNAL nCTS1 : STD_LOGIC;
91 SIGNAL nRTS1 : STD_LOGIC;
91 SIGNAL nRTS1 : STD_LOGIC;
92 SIGNAL TXD2 : STD_LOGIC;
92 SIGNAL TXD2 : STD_LOGIC;
93 SIGNAL RXD2 : STD_LOGIC;
93 SIGNAL RXD2 : STD_LOGIC;
94 SIGNAL nCTS2 : STD_LOGIC;
94 SIGNAL nCTS2 : STD_LOGIC;
95 SIGNAL nDTR2 : STD_LOGIC;
95 SIGNAL nDTR2 : STD_LOGIC;
96 SIGNAL nRTS2 : STD_LOGIC;
96 SIGNAL nRTS2 : STD_LOGIC;
97 SIGNAL nDCD2 : STD_LOGIC;
97 SIGNAL nDCD2 : STD_LOGIC;
98 SIGNAL IO0 : STD_LOGIC;
98 SIGNAL IO0 : STD_LOGIC;
99 SIGNAL IO1 : STD_LOGIC;
99 SIGNAL IO1 : STD_LOGIC;
100 SIGNAL IO2 : STD_LOGIC;
100 SIGNAL IO2 : STD_LOGIC;
101 SIGNAL IO3 : STD_LOGIC;
101 SIGNAL IO3 : STD_LOGIC;
102 SIGNAL IO4 : STD_LOGIC;
102 SIGNAL IO4 : STD_LOGIC;
103 SIGNAL IO5 : STD_LOGIC;
103 SIGNAL IO5 : STD_LOGIC;
104 SIGNAL IO6 : STD_LOGIC;
104 SIGNAL IO6 : STD_LOGIC;
105 SIGNAL IO7 : STD_LOGIC;
105 SIGNAL IO7 : STD_LOGIC;
106 SIGNAL IO8 : STD_LOGIC;
106 SIGNAL IO8 : STD_LOGIC;
107 SIGNAL IO9 : STD_LOGIC;
107 SIGNAL IO9 : STD_LOGIC;
108 SIGNAL IO10 : STD_LOGIC;
108 SIGNAL IO10 : STD_LOGIC;
109 SIGNAL IO11 : STD_LOGIC;
109 SIGNAL IO11 : STD_LOGIC;
110 SIGNAL SPW_EN : STD_LOGIC;
110 SIGNAL SPW_EN : STD_LOGIC;
111 SIGNAL SPW_NOM_DIN : STD_LOGIC;
111 SIGNAL SPW_NOM_DIN : STD_LOGIC;
112 SIGNAL SPW_NOM_SIN : STD_LOGIC;
112 SIGNAL SPW_NOM_SIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
113 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
114 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
114 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
115 SIGNAL SPW_RED_DIN : STD_LOGIC;
115 SIGNAL SPW_RED_DIN : STD_LOGIC;
116 SIGNAL SPW_RED_SIN : STD_LOGIC;
116 SIGNAL SPW_RED_SIN : STD_LOGIC;
117 SIGNAL SPW_RED_DOUT : STD_LOGIC;
117 SIGNAL SPW_RED_DOUT : STD_LOGIC;
118 SIGNAL SPW_RED_SOUT : STD_LOGIC;
118 SIGNAL SPW_RED_SOUT : STD_LOGIC;
119 SIGNAL ADC_nCS : STD_LOGIC;
119 SIGNAL ADC_nCS : STD_LOGIC;
120 SIGNAL ADC_CLK : STD_LOGIC;
120 SIGNAL ADC_CLK : STD_LOGIC;
121 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
121 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
122 SIGNAL SRAM_nWE : STD_LOGIC;
122 SIGNAL SRAM_nWE : STD_LOGIC;
123 SIGNAL SRAM_CE : STD_LOGIC;
123 SIGNAL SRAM_CE : STD_LOGIC;
124 SIGNAL SRAM_nOE : STD_LOGIC;
124 SIGNAL SRAM_nOE : STD_LOGIC;
125 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
126 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
127 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 -----------------------------------------------------------------------------
128 -----------------------------------------------------------------------------
129
129
130 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
130 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
131 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
131 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
132 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
132 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
133
133
134
134
135 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
135 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
136
136
137 BEGIN
137 BEGIN
138
138
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 -- TB
140 -- TB
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142 PROCESS
142 PROCESS
143 CONSTANT txp : TIME := 320 ns;
143 CONSTANT txp : TIME := 320 ns;
144 BEGIN -- PROCESS
144 BEGIN -- PROCESS
145 TXD1 <= '1';
145 TXD1 <= '1';
146 reset <= '0';
146 reset <= '0';
147 WAIT FOR 500 ns;
147 WAIT FOR 500 ns;
148 reset <= '1';
148 reset <= '1';
149 WAIT FOR 10000 ns;
149 WAIT FOR 10000 ns;
150 message_simu <= "0 - UART init ";
150 message_simu <= "0 - UART init ";
151 UART_INIT(TXD1,txp);
151 UART_INIT(TXD1,txp);
152
152
153 message_simu <= "1 - UART test ";
153 message_simu <= "1 - UART test ";
154 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
154 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
155 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
155 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
156 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
156 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
157
157
158 -- UNSET the LFR reset
158 -- UNSET the LFR reset
159 message_simu <= "2 - LFR UNRESET";
159 message_simu <= "2 - LFR UNRESET";
160 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
160 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
161 UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
162 --
162 --
163 message_simu <= "3 - LFR CONFIG ";
163 message_simu <= "3 - LFR CONFIG ";
164 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
164 UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
165
165
166 WAIT;
166 WAIT;
167 END PROCESS;
167 END PROCESS;
168
168
169 -----------------------------------------------------------------------------
169 -----------------------------------------------------------------------------
170 -- CLOCK
170 -- CLOCK
171 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
172 clk_50 <= NOT clk_50 AFTER 5 ns;
172 clk_50 <= NOT clk_50 AFTER 5 ns;
173 clk_49 <= NOT clk_49 AFTER 10172 ps;
173 clk_49 <= NOT clk_49 AFTER 10172 ps;
174
174
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176 -- DON'T CARE
176 -- DON'T CARE
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178 BP0 <= '0';
178 BP0 <= '0';
179 BP1 <= '0';
179 BP1 <= '0';
180 nRTS1 <= '0' ;
180 nRTS1 <= '0' ;
181
181
182 TXD2 <= '1';
182 TXD2 <= '1';
183 nRTS2 <= '1';
183 nRTS2 <= '1';
184 nDTR2 <= '1';
184 nDTR2 <= '1';
185
185
186 SPW_NOM_DIN <= '1';
186 SPW_NOM_DIN <= '1';
187 SPW_NOM_SIN <= '1';
187 SPW_NOM_SIN <= '1';
188 SPW_RED_DIN <= '1';
188 SPW_RED_DIN <= '1';
189 SPW_RED_SIN <= '1';
189 SPW_RED_SIN <= '1';
190
190
191 ADC_SDO <= x"AA";
191 ADC_SDO <= x"AA";
192
192
193 SRAM_DQ <= (OTHERS => 'Z');
193 SRAM_DQ <= (OTHERS => 'Z');
194 IO0 <= 'Z';
195 IO1 <= 'Z';
196 IO2 <= 'Z';
197 IO3 <= 'Z';
198 IO4 <= 'Z';
199 IO5 <= 'Z';
200 IO6 <= 'Z';
201 IO7 <= 'Z';
202 IO8 <= 'Z';
203 IO9 <= 'Z';
204 IO10 <= 'Z';
205 IO11 <= 'Z';
194
206
195 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
196 -- DUT
208 -- DUT
197 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
198 MINI_LFR_top_1: MINI_LFR_top
210 MINI_LFR_top_1: MINI_LFR_top
199 PORT MAP (
211 PORT MAP (
200 clk_50 => clk_50,
212 clk_50 => clk_50,
201 clk_49 => clk_49,
213 clk_49 => clk_49,
202 reset => reset,
214 reset => reset,
203
215
204 BP0 => BP0,
216 BP0 => BP0,
205 BP1 => BP1,
217 BP1 => BP1,
206
218
207 LED0 => LED0,
219 LED0 => LED0,
208 LED1 => LED1,
220 LED1 => LED1,
209 LED2 => LED2,
221 LED2 => LED2,
210
222
211 TXD1 => TXD1,
223 TXD1 => TXD1,
212 RXD1 => RXD1,
224 RXD1 => RXD1,
213 nCTS1 => nCTS1,
225 nCTS1 => nCTS1,
214 nRTS1 => nRTS1,
226 nRTS1 => nRTS1,
215
227
216 TXD2 => TXD2,
228 TXD2 => TXD2,
217 RXD2 => RXD2,
229 RXD2 => RXD2,
218 nCTS2 => nCTS2,
230 nCTS2 => nCTS2,
219 nDTR2 => nDTR2,
231 nDTR2 => nDTR2,
220 nRTS2 => nRTS2,
232 nRTS2 => nRTS2,
221 nDCD2 => nDCD2,
233 nDCD2 => nDCD2,
222
234
223 IO0 => IO0,
235 IO0 => IO0,
224 IO1 => IO1,
236 IO1 => IO1,
225 IO2 => IO2,
237 IO2 => IO2,
226 IO3 => IO3,
238 IO3 => IO3,
227 IO4 => IO4,
239 IO4 => IO4,
228 IO5 => IO5,
240 IO5 => IO5,
229 IO6 => IO6,
241 IO6 => IO6,
230 IO7 => IO7,
242 IO7 => IO7,
231 IO8 => IO8,
243 IO8 => IO8,
232 IO9 => IO9,
244 IO9 => IO9,
233 IO10 => IO10,
245 IO10 => IO10,
234 IO11 => IO11,
246 IO11 => IO11,
235
247
236 SPW_EN => SPW_EN,
248 SPW_EN => SPW_EN,
237 SPW_NOM_DIN => SPW_NOM_DIN,
249 SPW_NOM_DIN => SPW_NOM_DIN,
238 SPW_NOM_SIN => SPW_NOM_SIN,
250 SPW_NOM_SIN => SPW_NOM_SIN,
239 SPW_NOM_DOUT => SPW_NOM_DOUT,
251 SPW_NOM_DOUT => SPW_NOM_DOUT,
240 SPW_NOM_SOUT => SPW_NOM_SOUT,
252 SPW_NOM_SOUT => SPW_NOM_SOUT,
241 SPW_RED_DIN => SPW_RED_DIN,
253 SPW_RED_DIN => SPW_RED_DIN,
242 SPW_RED_SIN => SPW_RED_SIN,
254 SPW_RED_SIN => SPW_RED_SIN,
243 SPW_RED_DOUT => SPW_RED_DOUT,
255 SPW_RED_DOUT => SPW_RED_DOUT,
244 SPW_RED_SOUT => SPW_RED_SOUT,
256 SPW_RED_SOUT => SPW_RED_SOUT,
245
257
246 ADC_nCS => ADC_nCS,
258 ADC_nCS => ADC_nCS,
247 ADC_CLK => ADC_CLK,
259 ADC_CLK => ADC_CLK,
248 ADC_SDO => ADC_SDO,
260 ADC_SDO => ADC_SDO,
249
261
250 SRAM_nWE => SRAM_nWE,
262 SRAM_nWE => SRAM_nWE,
251 SRAM_CE => SRAM_CE,
263 SRAM_CE => SRAM_CE,
252 SRAM_nOE => SRAM_nOE,ddr_buffer_f
264 SRAM_nOE => SRAM_nOE,
253 SRAM_nBE => SRAM_nBE,
265 SRAM_nBE => SRAM_nBE,
254 SRAM_A => SRAM_A,
266 SRAM_A => SRAM_A,
255 SRAM_DQ => SRAM_DQ);
267 SRAM_DQ => SRAM_DQ);
256
268
257
269
258 END;
270 END;
Show file before | Show file after | Hide comments
@@ -1,567 +1,509
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 -- nb_word_by_buffer_size : INTEGER := 11; -- TODO
30 nb_snapshot_param_size : INTEGER := 11;
29 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
30 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
31 delta_vector_size_f0_2 : INTEGER := 7;
33
32
34 pindex : INTEGER := 4;
33 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
34 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
35 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
36 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
37 pirq_wfp : INTEGER := 1;
39
38
40 hindex : INTEGER := 2;
39 hindex : INTEGER := 2;
41
40
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
42
44 );
43 );
45 PORT (
44 PORT (
46 clk : IN STD_LOGIC;
45 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
48 -- SAMPLE
47 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
48 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
49 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
50 sample_val : IN STD_LOGIC;
52 -- APB
51 -- APB
53 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
55 -- AHB
54 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
55 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
56 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
57 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
60 --
62 data_shaping_BW : OUT STD_LOGIC
61 data_shaping_BW : OUT STD_LOGIC
63 --
64 --
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
70 --debug
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f0_data_valid : OUT STD_LOGIC;
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f1_data_valid : OUT STD_LOGIC;
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 --debug_f2_data_valid : OUT STD_LOGIC;
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 --debug_f3_data_valid : OUT STD_LOGIC;
79
80 ---- debug FIFO_IN
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
90 ----debug FIFO OUT
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
100 ----debug DMA IN
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 );
62 );
110 END lpp_lfr;
63 END lpp_lfr;
111
64
112 ARCHITECTURE beh OF lpp_lfr IS
65 ARCHITECTURE beh OF lpp_lfr IS
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
66 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 --
67 --
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
68 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
69 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
70 SIGNAL data_shaping_R0 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
71 SIGNAL data_shaping_R1 : STD_LOGIC;
120 SIGNAL data_shaping_R2 : STD_LOGIC;
72 SIGNAL data_shaping_R2 : STD_LOGIC;
121 --
73 --
122 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 --
77 --
126 SIGNAL sample_f0_val : STD_LOGIC;
78 SIGNAL sample_f0_val : STD_LOGIC;
127 SIGNAL sample_f1_val : STD_LOGIC;
79 SIGNAL sample_f1_val : STD_LOGIC;
128 SIGNAL sample_f2_val : STD_LOGIC;
80 SIGNAL sample_f2_val : STD_LOGIC;
129 SIGNAL sample_f3_val : STD_LOGIC;
81 SIGNAL sample_f3_val : STD_LOGIC;
130 --
82 --
131 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
83 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
84 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
135 --
87 --
136 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
139
91
140 -- SM
92 -- SM
141 SIGNAL ready_matrix_f0 : STD_LOGIC;
93 SIGNAL ready_matrix_f0 : STD_LOGIC;
142 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 SIGNAL ready_matrix_f1 : STD_LOGIC;
95 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 SIGNAL ready_matrix_f2 : STD_LOGIC;
96 SIGNAL ready_matrix_f2 : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
97 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
98 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
99 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
100 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
156 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
101 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
104 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
160 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
105 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
161 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
106 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
162
107
163 -- WFP
108 -- WFP
164 --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
109 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
112 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
171 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173
115
174 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
116 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
175 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
117 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
176 SIGNAL enable_f0 : STD_LOGIC;
118 SIGNAL enable_f0 : STD_LOGIC;
177 SIGNAL enable_f1 : STD_LOGIC;
119 SIGNAL enable_f1 : STD_LOGIC;
178 SIGNAL enable_f2 : STD_LOGIC;
120 SIGNAL enable_f2 : STD_LOGIC;
179 SIGNAL enable_f3 : STD_LOGIC;
121 SIGNAL enable_f3 : STD_LOGIC;
180 SIGNAL burst_f0 : STD_LOGIC;
122 SIGNAL burst_f0 : STD_LOGIC;
181 SIGNAL burst_f1 : STD_LOGIC;
123 SIGNAL burst_f1 : STD_LOGIC;
182 SIGNAL burst_f2 : STD_LOGIC;
124 SIGNAL burst_f2 : STD_LOGIC;
183
125
184 --SIGNAL run : STD_LOGIC;
126 --SIGNAL run : STD_LOGIC;
185 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
127 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
186
128
187 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
188 --
130 --
189 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
190 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
133 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
134 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
193 --f1
135 --f1
194 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
137 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
196 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
138 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
197 --f2
139 --f2
198 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
141 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
142 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
201 --f3
143 --f3
202 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
145 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
204 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
146 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
205
147
206 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
207 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
149 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
208 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
150 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
209 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
210 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
152 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
211 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
212 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
213 -- DMA RR
155 -- DMA RR
214 -----------------------------------------------------------------------------
156 -----------------------------------------------------------------------------
215 SIGNAL dma_sel_valid : STD_LOGIC;
157 SIGNAL dma_sel_valid : STD_LOGIC;
216 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
217 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
218 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
219 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
220
162
221 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
223
165
224 -----------------------------------------------------------------------------
166 -----------------------------------------------------------------------------
225 -- DMA_REG
167 -- DMA_REG
226 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
227 SIGNAL ongoing_reg : STD_LOGIC;
169 SIGNAL ongoing_reg : STD_LOGIC;
228 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
229 SIGNAL dma_send_reg : STD_LOGIC;
171 SIGNAL dma_send_reg : STD_LOGIC;
230 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
172 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
231 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
233
175
234
176
235 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
236 -- DMA
178 -- DMA
237 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
238 SIGNAL dma_send : STD_LOGIC;
180 SIGNAL dma_send : STD_LOGIC;
239 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
181 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
240 SIGNAL dma_done : STD_LOGIC;
182 SIGNAL dma_done : STD_LOGIC;
241 SIGNAL dma_ren : STD_LOGIC;
183 SIGNAL dma_ren : STD_LOGIC;
242 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
245
187
246 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
247 -- MS
189 -- MS
248 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
249
191
250 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL data_ms_valid : STD_LOGIC;
194 SIGNAL data_ms_valid : STD_LOGIC;
253 SIGNAL data_ms_valid_burst : STD_LOGIC;
195 SIGNAL data_ms_valid_burst : STD_LOGIC;
254 SIGNAL data_ms_ren : STD_LOGIC;
196 SIGNAL data_ms_ren : STD_LOGIC;
255 SIGNAL data_ms_done : STD_LOGIC;
197 SIGNAL data_ms_done : STD_LOGIC;
256 SIGNAL dma_ms_ongoing : STD_LOGIC;
198 SIGNAL dma_ms_ongoing : STD_LOGIC;
257
199
258 -- SIGNAL run_ms : STD_LOGIC;
200 -- SIGNAL run_ms : STD_LOGIC;
259 SIGNAL ms_softandhard_rstn : STD_LOGIC;
201 SIGNAL ms_softandhard_rstn : STD_LOGIC;
260
202
261 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
203 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
262 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
204 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
263 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
205 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
264 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
206 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
265
207
266
208
267 SIGNAL error_buffer_full : STD_LOGIC;
209 SIGNAL error_buffer_full : STD_LOGIC;
268 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
210 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
269
211
270 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
272
214
273 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
274 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
216 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
275 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
217 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
276 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
218 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
277 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
219 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
278 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
220 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
279 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
221 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
280 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
281 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
282 SIGNAL dma_grant_error : STD_LOGIC;
224 SIGNAL dma_grant_error : STD_LOGIC;
283
225
284 -----------------------------------------------------------------------------
226 -----------------------------------------------------------------------------
285 -- SIGNAL run_dma : STD_LOGIC;
227 -- SIGNAL run_dma : STD_LOGIC;
286 BEGIN
228 BEGIN
287
229
288 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
230 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
289 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
231 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
290
232
291 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
233 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
292 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
234 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
293 --END GENERATE all_channel;
235 --END GENERATE all_channel;
294
236
295 -----------------------------------------------------------------------------
237 -----------------------------------------------------------------------------
296 lpp_lfr_filter_1 : lpp_lfr_filter
238 lpp_lfr_filter_1 : lpp_lfr_filter
297 GENERIC MAP (
239 GENERIC MAP (
298 Mem_use => Mem_use)
240 Mem_use => Mem_use)
299 PORT MAP (
241 PORT MAP (
300 sample => sample_s,
242 sample => sample_s,
301 sample_val => sample_val,
243 sample_val => sample_val,
302 clk => clk,
244 clk => clk,
303 rstn => rstn,
245 rstn => rstn,
304 data_shaping_SP0 => data_shaping_SP0,
246 data_shaping_SP0 => data_shaping_SP0,
305 data_shaping_SP1 => data_shaping_SP1,
247 data_shaping_SP1 => data_shaping_SP1,
306 data_shaping_R0 => data_shaping_R0,
248 data_shaping_R0 => data_shaping_R0,
307 data_shaping_R1 => data_shaping_R1,
249 data_shaping_R1 => data_shaping_R1,
308 data_shaping_R2 => data_shaping_R2,
250 data_shaping_R2 => data_shaping_R2,
309 sample_f0_val => sample_f0_val,
251 sample_f0_val => sample_f0_val,
310 sample_f1_val => sample_f1_val,
252 sample_f1_val => sample_f1_val,
311 sample_f2_val => sample_f2_val,
253 sample_f2_val => sample_f2_val,
312 sample_f3_val => sample_f3_val,
254 sample_f3_val => sample_f3_val,
313 sample_f0_wdata => sample_f0_data,
255 sample_f0_wdata => sample_f0_data,
314 sample_f1_wdata => sample_f1_data,
256 sample_f1_wdata => sample_f1_data,
315 sample_f2_wdata => sample_f2_data,
257 sample_f2_wdata => sample_f2_data,
316 sample_f3_wdata => sample_f3_data);
258 sample_f3_wdata => sample_f3_data);
317
259
318 -----------------------------------------------------------------------------
260 -----------------------------------------------------------------------------
319 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
261 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
320 GENERIC MAP (
262 GENERIC MAP (
321 nb_data_by_buffer_size => nb_data_by_buffer_size,
263 nb_data_by_buffer_size => nb_data_by_buffer_size,
322 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
264 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
323 nb_snapshot_param_size => nb_snapshot_param_size,
265 nb_snapshot_param_size => nb_snapshot_param_size,
324 delta_vector_size => delta_vector_size,
266 delta_vector_size => delta_vector_size,
325 delta_vector_size_f0_2 => delta_vector_size_f0_2,
267 delta_vector_size_f0_2 => delta_vector_size_f0_2,
326 pindex => pindex,
268 pindex => pindex,
327 paddr => paddr,
269 paddr => paddr,
328 pmask => pmask,
270 pmask => pmask,
329 pirq_ms => pirq_ms,
271 pirq_ms => pirq_ms,
330 pirq_wfp => pirq_wfp,
272 pirq_wfp => pirq_wfp,
331 top_lfr_version => top_lfr_version)
273 top_lfr_version => top_lfr_version)
332 PORT MAP (
274 PORT MAP (
333 HCLK => clk,
275 HCLK => clk,
334 HRESETn => rstn,
276 HRESETn => rstn,
335 apbi => apbi,
277 apbi => apbi,
336 apbo => apbo,
278 apbo => apbo,
337
279
338 run_ms => OPEN,--run_ms,
280 run_ms => OPEN,--run_ms,
339
281
340 ready_matrix_f0 => ready_matrix_f0,
282 ready_matrix_f0 => ready_matrix_f0,
341 ready_matrix_f1 => ready_matrix_f1,
283 ready_matrix_f1 => ready_matrix_f1,
342 ready_matrix_f2 => ready_matrix_f2,
284 ready_matrix_f2 => ready_matrix_f2,
343 error_buffer_full => error_buffer_full, -- TODO
285 error_buffer_full => error_buffer_full, -- TODO
344 error_input_fifo_write => error_input_fifo_write, -- TODO
286 error_input_fifo_write => error_input_fifo_write, -- TODO
345 status_ready_matrix_f0 => status_ready_matrix_f0,
287 status_ready_matrix_f0 => status_ready_matrix_f0,
346 status_ready_matrix_f1 => status_ready_matrix_f1,
288 status_ready_matrix_f1 => status_ready_matrix_f1,
347 status_ready_matrix_f2 => status_ready_matrix_f2,
289 status_ready_matrix_f2 => status_ready_matrix_f2,
348
290
349 matrix_time_f0 => matrix_time_f0,
291 matrix_time_f0 => matrix_time_f0,
350 matrix_time_f1 => matrix_time_f1,
292 matrix_time_f1 => matrix_time_f1,
351 matrix_time_f2 => matrix_time_f2,
293 matrix_time_f2 => matrix_time_f2,
352
294
353 addr_matrix_f0 => addr_matrix_f0,
295 addr_matrix_f0 => addr_matrix_f0,
354 addr_matrix_f1 => addr_matrix_f1,
296 addr_matrix_f1 => addr_matrix_f1,
355 addr_matrix_f2 => addr_matrix_f2,
297 addr_matrix_f2 => addr_matrix_f2,
356
298
357 length_matrix_f0 => length_matrix_f0,
299 length_matrix_f0 => length_matrix_f0,
358 length_matrix_f1 => length_matrix_f1,
300 length_matrix_f1 => length_matrix_f1,
359 length_matrix_f2 => length_matrix_f2,
301 length_matrix_f2 => length_matrix_f2,
360 -------------------------------------------------------------------------
302 -------------------------------------------------------------------------
361 --status_full => status_full, -- TODo
303 --status_full => status_full, -- TODo
362 --status_full_ack => status_full_ack, -- TODo
304 --status_full_ack => status_full_ack, -- TODo
363 --status_full_err => status_full_err, -- TODo
305 --status_full_err => status_full_err, -- TODo
364 status_new_err => status_new_err,
306 status_new_err => status_new_err,
365 data_shaping_BW => data_shaping_BW,
307 data_shaping_BW => data_shaping_BW,
366 data_shaping_SP0 => data_shaping_SP0,
308 data_shaping_SP0 => data_shaping_SP0,
367 data_shaping_SP1 => data_shaping_SP1,
309 data_shaping_SP1 => data_shaping_SP1,
368 data_shaping_R0 => data_shaping_R0,
310 data_shaping_R0 => data_shaping_R0,
369 data_shaping_R1 => data_shaping_R1,
311 data_shaping_R1 => data_shaping_R1,
370 data_shaping_R2 => data_shaping_R2,
312 data_shaping_R2 => data_shaping_R2,
371 delta_snapshot => delta_snapshot,
313 delta_snapshot => delta_snapshot,
372 delta_f0 => delta_f0,
314 delta_f0 => delta_f0,
373 delta_f0_2 => delta_f0_2,
315 delta_f0_2 => delta_f0_2,
374 delta_f1 => delta_f1,
316 delta_f1 => delta_f1,
375 delta_f2 => delta_f2,
317 delta_f2 => delta_f2,
376 nb_data_by_buffer => nb_data_by_buffer,
318 nb_data_by_buffer => nb_data_by_buffer,
377 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
319 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
378 nb_snapshot_param => nb_snapshot_param,
320 nb_snapshot_param => nb_snapshot_param,
379 enable_f0 => enable_f0,
321 enable_f0 => enable_f0,
380 enable_f1 => enable_f1,
322 enable_f1 => enable_f1,
381 enable_f2 => enable_f2,
323 enable_f2 => enable_f2,
382 enable_f3 => enable_f3,
324 enable_f3 => enable_f3,
383 burst_f0 => burst_f0,
325 burst_f0 => burst_f0,
384 burst_f1 => burst_f1,
326 burst_f1 => burst_f1,
385 burst_f2 => burst_f2,
327 burst_f2 => burst_f2,
386 run => OPEN, --run,
328 run => OPEN, --run,
387 start_date => start_date,
329 start_date => start_date,
388 -- debug_signal => debug_signal,
330 -- debug_signal => debug_signal,
389 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
331 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
390 wfp_addr_buffer => wfp_addr_buffer,-- TODO
332 wfp_addr_buffer => wfp_addr_buffer,-- TODO
391 wfp_length_buffer => wfp_length_buffer,-- TODO
333 wfp_length_buffer => wfp_length_buffer,-- TODO
392
334
393 wfp_ready_buffer => wfp_ready_buffer,-- TODO
335 wfp_ready_buffer => wfp_ready_buffer,-- TODO
394 wfp_buffer_time => wfp_buffer_time,-- TODO
336 wfp_buffer_time => wfp_buffer_time,-- TODO
395 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
337 wfp_error_buffer_full => wfp_error_buffer_full -- TODO
396 );
338 );
397
339
398 -----------------------------------------------------------------------------
340 -----------------------------------------------------------------------------
399 -----------------------------------------------------------------------------
341 -----------------------------------------------------------------------------
400 lpp_waveform_1 : lpp_waveform
342 lpp_waveform_1 : lpp_waveform
401 GENERIC MAP (
343 GENERIC MAP (
402 tech => inferred,
344 tech => inferred,
403 data_size => 6*16,
345 data_size => 6*16,
404 nb_data_by_buffer_size => nb_data_by_buffer_size,
346 nb_data_by_buffer_size => nb_data_by_buffer_size,
405 nb_snapshot_param_size => nb_snapshot_param_size,
347 nb_snapshot_param_size => nb_snapshot_param_size,
406 delta_vector_size => delta_vector_size,
348 delta_vector_size => delta_vector_size,
407 delta_vector_size_f0_2 => delta_vector_size_f0_2
349 delta_vector_size_f0_2 => delta_vector_size_f0_2
408 )
350 )
409 PORT MAP (
351 PORT MAP (
410 clk => clk,
352 clk => clk,
411 rstn => rstn,
353 rstn => rstn,
412
354
413 reg_run => '1',--run,
355 reg_run => '1',--run,
414 reg_start_date => start_date,
356 reg_start_date => start_date,
415 reg_delta_snapshot => delta_snapshot,
357 reg_delta_snapshot => delta_snapshot,
416 reg_delta_f0 => delta_f0,
358 reg_delta_f0 => delta_f0,
417 reg_delta_f0_2 => delta_f0_2,
359 reg_delta_f0_2 => delta_f0_2,
418 reg_delta_f1 => delta_f1,
360 reg_delta_f1 => delta_f1,
419 reg_delta_f2 => delta_f2,
361 reg_delta_f2 => delta_f2,
420
362
421 enable_f0 => enable_f0,
363 enable_f0 => enable_f0,
422 enable_f1 => enable_f1,
364 enable_f1 => enable_f1,
423 enable_f2 => enable_f2,
365 enable_f2 => enable_f2,
424 enable_f3 => enable_f3,
366 enable_f3 => enable_f3,
425 burst_f0 => burst_f0,
367 burst_f0 => burst_f0,
426 burst_f1 => burst_f1,
368 burst_f1 => burst_f1,
427 burst_f2 => burst_f2,
369 burst_f2 => burst_f2,
428
370
429 nb_data_by_buffer => nb_data_by_buffer,
371 nb_data_by_buffer => nb_data_by_buffer,
430 nb_snapshot_param => nb_snapshot_param,
372 nb_snapshot_param => nb_snapshot_param,
431 status_new_err => status_new_err,
373 status_new_err => status_new_err,
432
374
433 status_buffer_ready => wfp_status_buffer_ready,
375 status_buffer_ready => wfp_status_buffer_ready,
434 addr_buffer => wfp_addr_buffer,
376 addr_buffer => wfp_addr_buffer,
435 length_buffer => wfp_length_buffer,
377 length_buffer => wfp_length_buffer,
436 ready_buffer => wfp_ready_buffer,
378 ready_buffer => wfp_ready_buffer,
437 buffer_time => wfp_buffer_time,
379 buffer_time => wfp_buffer_time,
438 error_buffer_full => wfp_error_buffer_full,
380 error_buffer_full => wfp_error_buffer_full,
439
381
440 coarse_time => coarse_time,
382 coarse_time => coarse_time,
441 fine_time => fine_time,
383 fine_time => fine_time,
442
384
443 --f0
385 --f0
444 data_f0_in_valid => sample_f0_val,
386 data_f0_in_valid => sample_f0_val,
445 data_f0_in => sample_f0_data,
387 data_f0_in => sample_f0_data,
446 --f1
388 --f1
447 data_f1_in_valid => sample_f1_val,
389 data_f1_in_valid => sample_f1_val,
448 data_f1_in => sample_f1_data,
390 data_f1_in => sample_f1_data,
449 --f2
391 --f2
450 data_f2_in_valid => sample_f2_val,
392 data_f2_in_valid => sample_f2_val,
451 data_f2_in => sample_f2_data,
393 data_f2_in => sample_f2_data,
452 --f3
394 --f3
453 data_f3_in_valid => sample_f3_val,
395 data_f3_in_valid => sample_f3_val,
454 data_f3_in => sample_f3_data,
396 data_f3_in => sample_f3_data,
455 -- OUTPUT -- DMA interface
397 -- OUTPUT -- DMA interface
456
398
457 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
399 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
458 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
400 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
459 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
401 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
460 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
402 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
461 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
403 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
462 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
404 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
463 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
405 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
464 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
406 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
465
407
466 );
408 );
467
409
468 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
469 -- Matrix Spectral
411 -- Matrix Spectral
470 -----------------------------------------------------------------------------
412 -----------------------------------------------------------------------------
471 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
413 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
472 NOT(sample_f0_val) & NOT(sample_f0_val);
414 NOT(sample_f0_val) & NOT(sample_f0_val);
473 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
415 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
474 NOT(sample_f1_val) & NOT(sample_f1_val);
416 NOT(sample_f1_val) & NOT(sample_f1_val);
475 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
417 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
476 NOT(sample_f2_val) & NOT(sample_f2_val);
418 NOT(sample_f2_val) & NOT(sample_f2_val);
477
419
478 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
420 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
479 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
421 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
480 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
422 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
481
423
482 -------------------------------------------------------------------------------
424 -------------------------------------------------------------------------------
483
425
484 --ms_softandhard_rstn <= rstn AND run_ms AND run;
426 --ms_softandhard_rstn <= rstn AND run_ms AND run;
485
427
486 -----------------------------------------------------------------------------
428 -----------------------------------------------------------------------------
487 lpp_lfr_ms_1 : lpp_lfr_ms
429 lpp_lfr_ms_1 : lpp_lfr_ms
488 GENERIC MAP (
430 GENERIC MAP (
489 Mem_use => Mem_use)
431 Mem_use => Mem_use)
490 PORT MAP (
432 PORT MAP (
491 clk => clk,
433 clk => clk,
492 --rstn => ms_softandhard_rstn, --rstn,
434 --rstn => ms_softandhard_rstn, --rstn,
493 rstn => rstn,
435 rstn => rstn,
494
436
495 run => '1',--run_ms,
437 run => '1',--run_ms,
496
438
497 start_date => start_date,
439 start_date => start_date,
498
440
499 coarse_time => coarse_time,
441 coarse_time => coarse_time,
500 fine_time => fine_time,
442 fine_time => fine_time,
501
443
502 sample_f0_wen => sample_f0_wen,
444 sample_f0_wen => sample_f0_wen,
503 sample_f0_wdata => sample_f0_wdata,
445 sample_f0_wdata => sample_f0_wdata,
504 sample_f1_wen => sample_f1_wen,
446 sample_f1_wen => sample_f1_wen,
505 sample_f1_wdata => sample_f1_wdata,
447 sample_f1_wdata => sample_f1_wdata,
506 sample_f2_wen => sample_f2_wen,
448 sample_f2_wen => sample_f2_wen,
507 sample_f2_wdata => sample_f2_wdata,
449 sample_f2_wdata => sample_f2_wdata,
508
450
509 --DMA
451 --DMA
510 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
452 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
511 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
453 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
512 dma_fifo_ren => dma_fifo_ren(4), -- IN
454 dma_fifo_ren => dma_fifo_ren(4), -- IN
513 dma_buffer_new => dma_buffer_new(4), -- OUT
455 dma_buffer_new => dma_buffer_new(4), -- OUT
514 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
456 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
515 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
457 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
516 dma_buffer_full => dma_buffer_full(4), -- IN
458 dma_buffer_full => dma_buffer_full(4), -- IN
517 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
459 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
518
460
519
461
520
462
521 --REG
463 --REG
522 ready_matrix_f0 => ready_matrix_f0,
464 ready_matrix_f0 => ready_matrix_f0,
523 ready_matrix_f1 => ready_matrix_f1,
465 ready_matrix_f1 => ready_matrix_f1,
524 ready_matrix_f2 => ready_matrix_f2,
466 ready_matrix_f2 => ready_matrix_f2,
525 error_buffer_full => error_buffer_full,
467 error_buffer_full => error_buffer_full,
526 error_input_fifo_write => error_input_fifo_write,
468 error_input_fifo_write => error_input_fifo_write,
527
469
528 status_ready_matrix_f0 => status_ready_matrix_f0,
470 status_ready_matrix_f0 => status_ready_matrix_f0,
529 status_ready_matrix_f1 => status_ready_matrix_f1,
471 status_ready_matrix_f1 => status_ready_matrix_f1,
530 status_ready_matrix_f2 => status_ready_matrix_f2,
472 status_ready_matrix_f2 => status_ready_matrix_f2,
531 addr_matrix_f0 => addr_matrix_f0,
473 addr_matrix_f0 => addr_matrix_f0,
532 addr_matrix_f1 => addr_matrix_f1,
474 addr_matrix_f1 => addr_matrix_f1,
533 addr_matrix_f2 => addr_matrix_f2,
475 addr_matrix_f2 => addr_matrix_f2,
534
476
535 length_matrix_f0 => length_matrix_f0,
477 length_matrix_f0 => length_matrix_f0,
536 length_matrix_f1 => length_matrix_f1,
478 length_matrix_f1 => length_matrix_f1,
537 length_matrix_f2 => length_matrix_f2,
479 length_matrix_f2 => length_matrix_f2,
538
480
539 matrix_time_f0 => matrix_time_f0,
481 matrix_time_f0 => matrix_time_f0,
540 matrix_time_f1 => matrix_time_f1,
482 matrix_time_f1 => matrix_time_f1,
541 matrix_time_f2 => matrix_time_f2);
483 matrix_time_f2 => matrix_time_f2);
542
484
543 -----------------------------------------------------------------------------
485 -----------------------------------------------------------------------------
544 --run_dma <= run_ms OR run;
486 --run_dma <= run_ms OR run;
545
487
546 DMA_SubSystem_1 : DMA_SubSystem
488 DMA_SubSystem_1 : DMA_SubSystem
547 GENERIC MAP (
489 GENERIC MAP (
548 hindex => hindex)
490 hindex => hindex)
549 PORT MAP (
491 PORT MAP (
550 clk => clk,
492 clk => clk,
551 rstn => rstn,
493 rstn => rstn,
552 run => '1',--run_dma,
494 run => '1',--run_dma,
553 ahbi => ahbi,
495 ahbi => ahbi,
554 ahbo => ahbo,
496 ahbo => ahbo,
555
497
556 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
498 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
557 fifo_data => dma_fifo_data, --fifo_data,
499 fifo_data => dma_fifo_data, --fifo_data,
558 fifo_ren => dma_fifo_ren, --fifo_ren,
500 fifo_ren => dma_fifo_ren, --fifo_ren,
559
501
560 buffer_new => dma_buffer_new, --buffer_new,
502 buffer_new => dma_buffer_new, --buffer_new,
561 buffer_addr => dma_buffer_addr, --buffer_addr,
503 buffer_addr => dma_buffer_addr, --buffer_addr,
562 buffer_length => dma_buffer_length, --buffer_length,
504 buffer_length => dma_buffer_length, --buffer_length,
563 buffer_full => dma_buffer_full, --buffer_full,
505 buffer_full => dma_buffer_full, --buffer_full,
564 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
506 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
565 grant_error => dma_grant_error); --grant_error);
507 grant_error => dma_grant_error); --grant_error);
566
508
567 END beh;
509 END beh;
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