diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd --- a/designs/LFR-em-WFP_MS/LFR-em.vhd +++ b/designs/LFR-em-WFP_MS/LFR-em.vhd @@ -347,7 +347,7 @@ BEGIN -- beh GENERIC MAP ( Mem_use => use_RAM, nb_data_by_buffer_size => 32, - nb_word_by_buffer_size => 30, + --nb_word_by_buffer_size => 30, nb_snapshot_param_size => 32, delta_vector_size => 32, delta_vector_size_f0_2 => 7, -- log2(96) @@ -357,7 +357,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"01011A") -- aa.bb.cc version + top_lfr_version => X"010121") -- aa.bb.cc version -- AA : BOARD NUMBER -- 0 => MINI_LFR -- 1 => EM @@ -373,10 +373,10 @@ BEGIN -- beh ahbo => ahbo_m_ext(2), coarse_time => coarse_time, fine_time => fine_time, - data_shaping_BW => bias_fail_sw, - observation_vector_0 => OPEN, - observation_vector_1 => OPEN, - observation_reg => observation_reg); + data_shaping_BW => bias_fail_sw);--, + --observation_vector_0 => OPEN, + --observation_vector_1 => OPEN, + --observation_reg => observation_reg); all_sample: FOR I IN 7 DOWNTO 0 GENERATE diff --git a/designs/LFR-em-WFP_MS/Makefile b/designs/LFR-em-WFP_MS/Makefile --- a/designs/LFR-em-WFP_MS/Makefile +++ b/designs/LFR-em-WFP_MS/Makefile @@ -20,7 +20,7 @@ VHDLSYNFILES=LFR-em.vhd #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc -SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc +#SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -178,39 +178,100 @@ ARCHITECTURE beh OF MINI_LFR_top IS SIGNAL LFR_soft_rstn : STD_LOGIC; SIGNAL LFR_rstn : STD_LOGIC; + + + SIGNAL rstn_25 : STD_LOGIC; + SIGNAL rstn_25_d1 : STD_LOGIC; + SIGNAL rstn_25_d2 : STD_LOGIC; + SIGNAL rstn_25_d3 : STD_LOGIC; + SIGNAL rstn_50 : STD_LOGIC; + SIGNAL rstn_50_d1 : STD_LOGIC; + SIGNAL rstn_50_d2 : STD_LOGIC; + SIGNAL rstn_50_d3 : STD_LOGIC; BEGIN -- beh ----------------------------------------------------------------------------- -- CLK ----------------------------------------------------------------------------- - PROCESS(clk_50) - BEGIN - IF clk_50'EVENT AND clk_50 = '1' THEN - clk_50_s <= NOT clk_50_s; + --PROCESS(clk_50) + --BEGIN + -- IF clk_50'EVENT AND clk_50 = '1' THEN + -- clk_50_s <= NOT clk_50_s; + -- END IF; + --END PROCESS; + + --PROCESS(clk_50_s) + --BEGIN + -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN + -- clk_25 <= NOT clk_25; + -- END IF; + --END PROCESS; + + --PROCESS(clk_49) + --BEGIN + -- IF clk_49'EVENT AND clk_49 = '1' THEN + -- clk_24 <= NOT clk_24; + -- END IF; + --END PROCESS; + + --PROCESS(clk_25) + --BEGIN + -- IF clk_25'EVENT AND clk_25 = '1' THEN + -- rstn_25 <= reset; + -- END IF; + --END PROCESS; + + PROCESS (clk_50, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + clk_50_s <= '0'; + rstn_50 <= '0'; + rstn_50_d1 <= '0'; + rstn_50_d2 <= '0'; + rstn_50_d3 <= '0'; + + ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge + clk_50_s <= NOT clk_50_s; + rstn_50_d1 <= '1'; + rstn_50_d2 <= rstn_50_d1; + rstn_50_d3 <= rstn_50_d2; + rstn_50 <= rstn_50_d3; END IF; END PROCESS; - PROCESS(clk_50_s) - BEGIN - IF clk_50_s'EVENT AND clk_50_s = '1' THEN - clk_25 <= NOT clk_25; + PROCESS (clk_50_s, rstn_50) + BEGIN -- PROCESS + IF rstn_50 = '0' THEN -- asynchronous reset (active low) + clk_25 <= '0'; + rstn_25 <= '0'; + rstn_25_d1 <= '0'; + rstn_25_d2 <= '0'; + rstn_25_d3 <= '0'; + ELSIF clk_50_s'event AND clk_50_s = '1' THEN -- rising clock edge + clk_25 <= NOT clk_25; + rstn_25_d1 <= '1'; + rstn_25_d2 <= rstn_25_d1; + rstn_25_d3 <= rstn_25_d2; + rstn_25 <= rstn_25_d3; END IF; END PROCESS; - PROCESS(clk_49) - BEGIN - IF clk_49'EVENT AND clk_49 = '1' THEN - clk_24 <= NOT clk_24; + PROCESS (clk_49, reset) + BEGIN -- PROCESS + IF reset = '0' THEN -- asynchronous reset (active low) + clk_24 <= '0'; + ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge + clk_24 <= NOT clk_24; END IF; END PROCESS; - + ----------------------------------------------------------------------------- - PROCESS (clk_25, reset) + PROCESS (clk_25, rstn_25) BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) + IF rstn_25 = '0' THEN -- asynchronous reset (active low) LED0 <= '0'; LED1 <= '0'; LED2 <= '0'; @@ -243,9 +304,9 @@ BEGIN -- beh END IF; END PROCESS; - PROCESS (clk_24, reset) + PROCESS (clk_24, rstn_25) BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) + IF rstn_25 = '0' THEN -- asynchronous reset (active low) I00_s <= '0'; ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge I00_s <= NOT I00_s ; @@ -286,7 +347,7 @@ BEGIN -- beh ADDRESS_SIZE => 20) PORT MAP ( clk => clk_25, - reset => reset, + reset => rstn_25, errorn => errorn, ahbrxd => TXD1, ahbtxd => RXD1, @@ -322,7 +383,7 @@ BEGIN -- beh PORT MAP ( clk25MHz => clk_25, clk24_576MHz => clk_24, -- 49.152MHz/2 - resetn => reset, + resetn => rstn_25, grspw_tick => swno.tickout, apbi => apbi_ext, apbo => apbo_ext(6), @@ -404,7 +465,7 @@ BEGIN -- beh --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 ) - PORT MAP(reset, clk_25, spw_rxclk(0), + PORT MAP(rstn_25, clk_25, spw_rxclk(0), spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), swni, swno); @@ -422,7 +483,8 @@ BEGIN -- beh ------------------------------------------------------------------------------- - LFR_rstn <= LFR_soft_rstn AND reset; + --LFR_rstn <= LFR_soft_rstn AND rstn_25; + LFR_rstn <= rstn_25; lpp_lfr_1 : lpp_lfr GENERIC MAP ( @@ -437,7 +499,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000121") -- aa.bb.cc version + top_lfr_version => X"000122") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, @@ -467,11 +529,11 @@ BEGIN -- beh PORT MAP ( -- CONV cnv_clk => clk_24, - cnv_rstn => reset, + cnv_rstn => rstn_25, cnv => ADC_nCS_sig, -- DATA clk => clk_25, - rstn => reset, + rstn => rstn_25, sck => ADC_CLK_sig, sdo => ADC_SDO_sig, -- SAMPLE @@ -492,7 +554,7 @@ BEGIN -- beh grgpio0 : grgpio GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) - PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); + PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); --pio_pad_0 : iopad -- GENERIC MAP (tech => CFG_PADTECH) @@ -519,9 +581,9 @@ BEGIN -- beh -- GENERIC MAP (tech => CFG_PADTECH) -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); - PROCESS (clk_25, reset) + PROCESS (clk_25, rstn_25) BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) + IF rstn_25 = '0' THEN -- asynchronous reset (active low) IO0 <= '0'; IO1 <= '0'; IO2 <= '0'; diff --git a/designs/MINI-LFR_WFP_MS/Makefile b/designs/MINI-LFR_WFP_MS/Makefile --- a/designs/MINI-LFR_WFP_MS/Makefile +++ b/designs/MINI-LFR_WFP_MS/Makefile @@ -43,7 +43,8 @@ FILESKIP =i2cmst.vhd \ APB_SIMPLE_DIODE.vhd \ Top_MatrixSpec.vhd \ APB_FFT.vhd \ - CoreFFT_simu.vhd + CoreFFT_simu.vhd \ + lpp_lfr_apbreg_simu.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/MINI-LFR_WFP_MS/testbench.vhd b/designs/MINI-LFR_WFP_MS/testbench.vhd --- a/designs/MINI-LFR_WFP_MS/testbench.vhd +++ b/designs/MINI-LFR_WFP_MS/testbench.vhd @@ -191,6 +191,18 @@ BEGIN ADC_SDO <= x"AA"; SRAM_DQ <= (OTHERS => 'Z'); + IO0 <= 'Z'; + IO1 <= 'Z'; + IO2 <= 'Z'; + IO3 <= 'Z'; + IO4 <= 'Z'; + IO5 <= 'Z'; + IO6 <= 'Z'; + IO7 <= 'Z'; + IO8 <= 'Z'; + IO9 <= 'Z'; + IO10 <= 'Z'; + IO11 <= 'Z'; ----------------------------------------------------------------------------- -- DUT @@ -249,7 +261,7 @@ BEGIN SRAM_nWE => SRAM_nWE, SRAM_CE => SRAM_CE, - SRAM_nOE => SRAM_nOE,ddr_buffer_f + SRAM_nOE => SRAM_nOE, SRAM_nBE => SRAM_nBE, SRAM_A => SRAM_A, SRAM_DQ => SRAM_DQ); diff --git a/lib/lpp/dsp/cic/cic_lfr_address_gen.vhd b/lib/lpp/dsp/cic/cic_lfr_address_gen.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/dsp/cic/cic_lfr_address_gen.vhd @@ -0,0 +1,69 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.all; + +LIBRARY lpp; +USE lpp.cic_pkg.ALL; +USE lpp.data_type_pkg.ALL; + +ENTITY cic_lfr_address_gen IS + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + addr_init : IN STD_LOGIC; + addr_add_1 : IN STD_LOGIC; + + addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END cic_lfr_address_gen; + +ARCHITECTURE beh OF cic_lfr_address_gen IS + SIGNAL address_reg_s : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL address_reg : STD_LOGIC_VECTOR(7 DOWNTO 0); +BEGIN + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + address_reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + address_reg <= address_reg_s; + END IF; + END PROCESS; + + address_reg_s <= (OTHERS => '0') WHEN run = '0' ELSE + STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '0' ELSE + STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '1' ELSE + addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE + address_reg; + + addr <= address_reg WHEN addr_init = '0' ELSE addr_base; + +END beh; + diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd @@ -26,7 +26,6 @@ ENTITY lpp_lfr IS GENERIC ( Mem_use : INTEGER := use_RAM; nb_data_by_buffer_size : INTEGER := 11; --- nb_word_by_buffer_size : INTEGER := 11; -- TODO nb_snapshot_param_size : INTEGER := 11; delta_vector_size : INTEGER := 20; delta_vector_size_f0_2 : INTEGER := 7; @@ -60,57 +59,10 @@ ENTITY lpp_lfr IS fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo -- data_shaping_BW : OUT STD_LOGIC - -- - -- --- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); - --- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) - - --debug - --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - --debug_f0_data_valid : OUT STD_LOGIC; - --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - --debug_f1_data_valid : OUT STD_LOGIC; - --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - --debug_f2_data_valid : OUT STD_LOGIC; - --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); - --debug_f3_data_valid : OUT STD_LOGIC; - - ---- debug FIFO_IN - --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; - --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; - - ----debug FIFO OUT - --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; - --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; - --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; - --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; - - ----debug DMA IN - --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f0_data_dma_in_valid : OUT STD_LOGIC; - --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f1_data_dma_in_valid : OUT STD_LOGIC; - --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f2_data_dma_in_valid : OUT STD_LOGIC; - --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - --debug_f3_data_dma_in_valid : OUT STD_LOGIC ); END lpp_lfr; ARCHITECTURE beh OF lpp_lfr IS - --SIGNAL sample : Samples14v(7 DOWNTO 0); SIGNAL sample_s : Samples(7 DOWNTO 0); -- SIGNAL data_shaping_SP0 : STD_LOGIC; @@ -142,17 +94,10 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL ready_matrix_f0_1 : STD_LOGIC; SIGNAL ready_matrix_f1 : STD_LOGIC; SIGNAL ready_matrix_f2 : STD_LOGIC; --- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; --- SIGNAL error_bad_component_error : STD_LOGIC; --- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL status_ready_matrix_f0 : STD_LOGIC; SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; SIGNAL status_ready_matrix_f1 : STD_LOGIC; SIGNAL status_ready_matrix_f2 : STD_LOGIC; --- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; --- SIGNAL status_error_bad_component_error : STD_LOGIC; - --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; --- SIGNAL config_active_interruption_onError : STD_LOGIC; SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -161,9 +106,6 @@ ARCHITECTURE beh OF lpp_lfr IS SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0); -- WFP - --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);