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WaveFormPicker :Correction du registre Status et de l'arbitre en entree de la FIFO
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r240:af3a90f3ec47 LPP-LFR-em-WaveFormPicker-0-0-5 JC
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1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
44
45 ENTITY leon3mp IS
45 ENTITY leon3mp IS
46 GENERIC (
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
53 pclow : INTEGER := CFG_PCLOW
54 );
54 );
55 PORT (
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
59
60 errorn : OUT STD_ULOGIC;
60 errorn : OUT STD_ULOGIC;
61
61
62 -- UART AHB ---------------------------------------------------------------
62 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
65
66 -- UART APB ---------------------------------------------------------------
66 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
69
70 -- RAM --------------------------------------------------------------------
70 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
73 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
80
80
81 -- SPW --------------------------------------------------------------------
81 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
82 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
86
86
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
91
91
92 -- ADC --------------------------------------------------------------------
92 -- ADC --------------------------------------------------------------------
93 bias_fail_sw : OUT STD_LOGIC;
93 bias_fail_sw : OUT STD_LOGIC;
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
95 ADC_smpclk : OUT STD_LOGIC;
95 ADC_smpclk : OUT STD_LOGIC;
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
97
97
98 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
100 );
100 );
101 END;
101 END;
102
102
103 ARCHITECTURE Behavioral OF leon3mp IS
103 ARCHITECTURE Behavioral OF leon3mp IS
104
104
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
106 -- CFG_GRETH+CFG_AHB_JTAG;
106 -- CFG_GRETH+CFG_AHB_JTAG;
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
108 CFG_AHB_UART
108 CFG_AHB_UART
109 +2;
109 +2;
110 -- 1 is for the SpaceWire module grspw, which is a master
110 -- 1 is for the SpaceWire module grspw, which is a master
111 -- 1 is for the LFR
111 -- 1 is for the LFR
112
112
113 CONSTANT maxahbm : INTEGER := maxahbmsp;
113 CONSTANT maxahbm : INTEGER := maxahbmsp;
114
114
115 --Clk & Rst gοΏ½nοΏ½
115 --Clk & Rst gοΏ½nοΏ½
116 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL resetnl : STD_ULOGIC;
118 SIGNAL resetnl : STD_ULOGIC;
119 SIGNAL clk2x : STD_ULOGIC;
119 SIGNAL clk2x : STD_ULOGIC;
120 SIGNAL lclk2x : STD_ULOGIC;
120 SIGNAL lclk2x : STD_ULOGIC;
121 SIGNAL lclk25MHz : STD_ULOGIC;
121 SIGNAL lclk25MHz : STD_ULOGIC;
122 SIGNAL lclk50MHz : STD_ULOGIC;
122 SIGNAL lclk50MHz : STD_ULOGIC;
123 SIGNAL lclk100MHz : STD_ULOGIC;
123 SIGNAL lclk100MHz : STD_ULOGIC;
124 SIGNAL clkm : STD_ULOGIC;
124 SIGNAL clkm : STD_ULOGIC;
125 SIGNAL rstn : STD_ULOGIC;
125 SIGNAL rstn : STD_ULOGIC;
126 SIGNAL rstraw : STD_ULOGIC;
126 SIGNAL rstraw : STD_ULOGIC;
127 SIGNAL pciclk : STD_ULOGIC;
127 SIGNAL pciclk : STD_ULOGIC;
128 SIGNAL sdclkl : STD_ULOGIC;
128 SIGNAL sdclkl : STD_ULOGIC;
129 SIGNAL cgi : clkgen_in_type;
129 SIGNAL cgi : clkgen_in_type;
130 SIGNAL cgo : clkgen_out_type;
130 SIGNAL cgo : clkgen_out_type;
131 --- AHB / APB
131 --- AHB / APB
132 SIGNAL apbi : apb_slv_in_type;
132 SIGNAL apbi : apb_slv_in_type;
133 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
133 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
134 SIGNAL ahbsi : ahb_slv_in_type;
134 SIGNAL ahbsi : ahb_slv_in_type;
135 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
135 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
136 SIGNAL ahbmi : ahb_mst_in_type;
136 SIGNAL ahbmi : ahb_mst_in_type;
137 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
137 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
138 --UART
138 --UART
139 SIGNAL ahbuarti : uart_in_type;
139 SIGNAL ahbuarti : uart_in_type;
140 SIGNAL ahbuarto : uart_out_type;
140 SIGNAL ahbuarto : uart_out_type;
141 SIGNAL apbuarti : uart_in_type;
141 SIGNAL apbuarti : uart_in_type;
142 SIGNAL apbuarto : uart_out_type;
142 SIGNAL apbuarto : uart_out_type;
143 --MEM CTRLR
143 --MEM CTRLR
144 SIGNAL memi : memory_in_type;
144 SIGNAL memi : memory_in_type;
145 SIGNAL memo : memory_out_type;
145 SIGNAL memo : memory_out_type;
146 SIGNAL wpo : wprot_out_type;
146 SIGNAL wpo : wprot_out_type;
147 SIGNAL sdo : sdram_out_type;
147 SIGNAL sdo : sdram_out_type;
148 SIGNAL ramcs : STD_ULOGIC;
148 SIGNAL ramcs : STD_ULOGIC;
149 --IRQ
149 --IRQ
150 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
150 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
152 --Timer
152 --Timer
153 SIGNAL gpti : gptimer_in_type;
153 SIGNAL gpti : gptimer_in_type;
154 SIGNAL gpto : gptimer_out_type;
154 SIGNAL gpto : gptimer_out_type;
155 --GPIO
155 --GPIO
156 SIGNAL gpioi : gpio_in_type;
156 SIGNAL gpioi : gpio_in_type;
157 SIGNAL gpioo : gpio_out_type;
157 SIGNAL gpioo : gpio_out_type;
158 --DSU
158 --DSU
159 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
159 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
161 SIGNAL dsui : dsu_in_type;
161 SIGNAL dsui : dsu_in_type;
162 SIGNAL dsuo : dsu_out_type;
162 SIGNAL dsuo : dsu_out_type;
163
163
164 ---------------------------------------------------------------------
164 ---------------------------------------------------------------------
165 --- AJOUT TEST ------------------------Signaux----------------------
165 --- AJOUT TEST ------------------------Signaux----------------------
166 ---------------------------------------------------------------------
166 ---------------------------------------------------------------------
167
167
168 ---------------------------------------------------------------------
168 ---------------------------------------------------------------------
169 CONSTANT IOAEN : INTEGER := CFG_CAN;
169 CONSTANT IOAEN : INTEGER := CFG_CAN;
170 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
170 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
171
171
172 -- time management signal
172 -- time management signal
173 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
174 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
175
175
176 -- Spacewire signals
176 -- Spacewire signals
177 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
177 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
178 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
178 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
179 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
179 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
180 SIGNAL spw_rxtxclk : STD_ULOGIC;
180 SIGNAL spw_rxtxclk : STD_ULOGIC;
181 SIGNAL spw_rxclkn : STD_ULOGIC;
181 SIGNAL spw_rxclkn : STD_ULOGIC;
182 SIGNAL spw_clk : STD_LOGIC;
182 SIGNAL spw_clk : STD_LOGIC;
183 SIGNAL swni : grspw_in_type; -- PLE
183 SIGNAL swni : grspw_in_type; -- PLE
184 SIGNAL swno : grspw_out_type; -- PLE
184 SIGNAL swno : grspw_out_type; -- PLE
185 SIGNAL clkmn : STD_ULOGIC; -- PLE
185 SIGNAL clkmn : STD_ULOGIC; -- PLE
186 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
186 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
187
187
188 -- AD Converter RHF1401
188 -- AD Converter RHF1401
189 SIGNAL sample : Samples14v(7 DOWNTO 0);
189 SIGNAL sample : Samples14v(7 DOWNTO 0);
190 SIGNAL sample_val : STD_LOGIC;
190 SIGNAL sample_val : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
193
193
194 BEGIN
194 BEGIN
195
195
196
196
197 ----------------------------------------------------------------------
197 ----------------------------------------------------------------------
198 --- Reset and Clock generation -------------------------------------
198 --- Reset and Clock generation -------------------------------------
199 ----------------------------------------------------------------------
199 ----------------------------------------------------------------------
200
200
201 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
201 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
202 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
202 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
203
203
204 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
204 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
205
205
206
206
207 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
207 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
208
208
209 clkgen0 : clkgen -- clock generator
209 clkgen0 : clkgen -- clock generator
210 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
210 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
211 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
211 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
212 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
212 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
213
213
214 PROCESS(lclk100MHz)
214 PROCESS(lclk100MHz)
215 BEGIN
215 BEGIN
216 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
216 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
217 lclk50MHz <= NOT lclk50MHz;
217 lclk50MHz <= NOT lclk50MHz;
218 END IF;
218 END IF;
219 END PROCESS;
219 END PROCESS;
220
220
221 PROCESS(lclk50MHz)
221 PROCESS(lclk50MHz)
222 BEGIN
222 BEGIN
223 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
223 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
224 lclk25MHz <= NOT lclk25MHz;
224 lclk25MHz <= NOT lclk25MHz;
225 END IF;
225 END IF;
226 END PROCESS;
226 END PROCESS;
227
227
228 lclk2x <= lclk50MHz;
228 lclk2x <= lclk50MHz;
229 spw_clk <= lclk50MHz;
229 spw_clk <= lclk50MHz;
230
230
231 ----------------------------------------------------------------------
231 ----------------------------------------------------------------------
232 --- LEON3 processor / DSU / IRQ ------------------------------------
232 --- LEON3 processor / DSU / IRQ ------------------------------------
233 ----------------------------------------------------------------------
233 ----------------------------------------------------------------------
234
234
235 l3 : IF CFG_LEON3 = 1 GENERATE
235 l3 : IF CFG_LEON3 = 1 GENERATE
236 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
236 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
237 u0 : leon3s -- LEON3 processor
237 u0 : leon3s -- LEON3 processor
238 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
238 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
239 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
239 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
240 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
240 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
241 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
241 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
242 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
242 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
243 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
243 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
244 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
244 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
245 irqi(i), irqo(i), dbgi(i), dbgo(i));
245 irqi(i), irqo(i), dbgi(i), dbgo(i));
246 END GENERATE;
246 END GENERATE;
247 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
247 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
248
248
249 dsugen : IF CFG_DSU = 1 GENERATE
249 dsugen : IF CFG_DSU = 1 GENERATE
250 dsu0 : dsu3 -- LEON3 Debug Support Unit
250 dsu0 : dsu3 -- LEON3 Debug Support Unit
251 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
251 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
252 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
252 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
253 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
253 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
254 dsui.enable <= '1';
254 dsui.enable <= '1';
255 dsui.break <= '0';
255 dsui.break <= '0';
256 led(2) <= dsuo.active;
256 led(2) <= dsuo.active;
257 END GENERATE;
257 END GENERATE;
258 END GENERATE;
258 END GENERATE;
259
259
260 nodsu : IF CFG_DSU = 0 GENERATE
260 nodsu : IF CFG_DSU = 0 GENERATE
261 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
261 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
262 END GENERATE;
262 END GENERATE;
263
263
264 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
264 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
265 irqctrl0 : irqmp -- interrupt controller
265 irqctrl0 : irqmp -- interrupt controller
266 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
266 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
267 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
267 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
268 END GENERATE;
268 END GENERATE;
269 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
269 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
270 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
270 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
271 irqi(i).irl <= "0000";
271 irqi(i).irl <= "0000";
272 END GENERATE;
272 END GENERATE;
273 apbo(2) <= apb_none;
273 apbo(2) <= apb_none;
274 END GENERATE;
274 END GENERATE;
275
275
276 ----------------------------------------------------------------------
276 ----------------------------------------------------------------------
277 --- Memory controllers ---------------------------------------------
277 --- Memory controllers ---------------------------------------------
278 ----------------------------------------------------------------------
278 ----------------------------------------------------------------------
279 memctrlr : mctrl GENERIC MAP (
279 memctrlr : mctrl GENERIC MAP (
280 hindex => 0,
280 hindex => 0,
281 pindex => 0,
281 pindex => 0,
282 paddr => 0,
282 paddr => 0,
283 srbanks => 1
283 srbanks => 1
284 )
284 )
285 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
285 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
286
286
287 memi.brdyn <= '1';
287 memi.brdyn <= '1';
288 memi.bexcn <= '1';
288 memi.bexcn <= '1';
289 memi.writen <= '1';
289 memi.writen <= '1';
290 memi.wrn <= "1111";
290 memi.wrn <= "1111";
291 memi.bwidth <= "10";
291 memi.bwidth <= "10";
292
292
293 bdr : FOR i IN 0 TO 3 GENERATE
293 bdr : FOR i IN 0 TO 3 GENERATE
294 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
294 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
295 PORT MAP (
295 PORT MAP (
296 data(31-i*8 DOWNTO 24-i*8),
296 data(31-i*8 DOWNTO 24-i*8),
297 memo.data(31-i*8 DOWNTO 24-i*8),
297 memo.data(31-i*8 DOWNTO 24-i*8),
298 memo.bdrive(i),
298 memo.bdrive(i),
299 memi.data(31-i*8 DOWNTO 24-i*8));
299 memi.data(31-i*8 DOWNTO 24-i*8));
300 END GENERATE;
300 END GENERATE;
301
301
302 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
302 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
303 PORT MAP (address, memo.address(21 DOWNTO 2));
303 PORT MAP (address, memo.address(21 DOWNTO 2));
304
304
305 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
305 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
306 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
306 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
307 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
307 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
308 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
308 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
309 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
309 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
310 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
310 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
311 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
311 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
312
312
313 ----------------------------------------------------------------------
313 ----------------------------------------------------------------------
314 --- AHB CONTROLLER -------------------------------------------------
314 --- AHB CONTROLLER -------------------------------------------------
315 ----------------------------------------------------------------------
315 ----------------------------------------------------------------------
316 ahb0 : ahbctrl -- AHB arbiter/multiplexer
316 ahb0 : ahbctrl -- AHB arbiter/multiplexer
317 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
317 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
318 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
318 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
319 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
319 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
320 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
320 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
321
321
322 ----------------------------------------------------------------------
322 ----------------------------------------------------------------------
323 --- AHB UART -------------------------------------------------------
323 --- AHB UART -------------------------------------------------------
324 ----------------------------------------------------------------------
324 ----------------------------------------------------------------------
325 dcomgen : IF CFG_AHB_UART = 1 GENERATE
325 dcomgen : IF CFG_AHB_UART = 1 GENERATE
326 dcom0 : ahbuart
326 dcom0 : ahbuart
327 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
327 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
328 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
328 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
329 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
329 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
330 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
330 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
331 led(0) <= NOT ahbuarti.rxd;
331 led(0) <= NOT ahbuarti.rxd;
332 led(1) <= NOT ahbuarto.txd;
332 led(1) <= NOT ahbuarto.txd;
333 END GENERATE;
333 END GENERATE;
334 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
334 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
335
335
336 ----------------------------------------------------------------------
336 ----------------------------------------------------------------------
337 --- APB Bridge -----------------------------------------------------
337 --- APB Bridge -----------------------------------------------------
338 ----------------------------------------------------------------------
338 ----------------------------------------------------------------------
339 apb0 : apbctrl -- AHB/APB bridge
339 apb0 : apbctrl -- AHB/APB bridge
340 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
340 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
341 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
341 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
342
342
343 ----------------------------------------------------------------------
343 ----------------------------------------------------------------------
344 --- GPT Timer ------------------------------------------------------
344 --- GPT Timer ------------------------------------------------------
345 ----------------------------------------------------------------------
345 ----------------------------------------------------------------------
346 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
346 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
347 timer0 : gptimer -- timer unit
347 timer0 : gptimer -- timer unit
348 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
348 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
349 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
349 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
350 nbits => CFG_GPT_TW)
350 nbits => CFG_GPT_TW)
351 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
351 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
352 gpti.dhalt <= dsuo.tstop;
352 gpti.dhalt <= dsuo.tstop;
353 gpti.extclk <= '0';
353 gpti.extclk <= '0';
354 END GENERATE;
354 END GENERATE;
355 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
355 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
356
356
357
357
358 ----------------------------------------------------------------------
358 ----------------------------------------------------------------------
359 --- APB UART -------------------------------------------------------
359 --- APB UART -------------------------------------------------------
360 ----------------------------------------------------------------------
360 ----------------------------------------------------------------------
361 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
361 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
362 uart1 : apbuart -- UART 1
362 uart1 : apbuart -- UART 1
363 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
363 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
364 fifosize => CFG_UART1_FIFO)
364 fifosize => CFG_UART1_FIFO)
365 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
365 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
366 apbuarti.rxd <= urxd1;
366 apbuarti.rxd <= urxd1;
367 apbuarti.extclk <= '0';
367 apbuarti.extclk <= '0';
368 utxd1 <= apbuarto.txd;
368 utxd1 <= apbuarto.txd;
369 apbuarti.ctsn <= '0';
369 apbuarti.ctsn <= '0';
370 END GENERATE;
370 END GENERATE;
371 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
371 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
372
372
373 -------------------------------------------------------------------------------
373 -------------------------------------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 -------------------------------------------------------------------------------
375 -------------------------------------------------------------------------------
376 apb_lfr_time_management_1: apb_lfr_time_management
376 apb_lfr_time_management_1: apb_lfr_time_management
377 GENERIC MAP (
377 GENERIC MAP (
378 pindex => 6,
378 pindex => 6,
379 paddr => 6,
379 paddr => 6,
380 pmask => 16#fff#,
380 pmask => 16#fff#,
381 pirq => 12)
381 pirq => 12)
382 PORT MAP (
382 PORT MAP (
383 clk25MHz => clkm,
383 clk25MHz => clkm,
384 clk49_152MHz => clk49_152MHz,
384 clk49_152MHz => clk49_152MHz,
385 resetn => rstn,
385 resetn => rstn,
386 grspw_tick => swno.tickout,
386 grspw_tick => swno.tickout,
387 apbi => apbi,
387 apbi => apbi,
388 apbo => apbo(6),
388 apbo => apbo(6),
389 coarse_time => coarse_time,
389 coarse_time => coarse_time,
390 fine_time => fine_time);
390 fine_time => fine_time);
391
391
392 -----------------------------------------------------------------------
392 -----------------------------------------------------------------------
393 --- SpaceWire --------------------------------------------------------
393 --- SpaceWire --------------------------------------------------------
394 -----------------------------------------------------------------------
394 -----------------------------------------------------------------------
395
395
396 spw_rxtxclk <= spw_clk;
396 spw_rxtxclk <= spw_clk;
397 spw_rxclkn <= NOT spw_rxtxclk;
397 spw_rxclkn <= NOT spw_rxtxclk;
398
398
399 -- PADS for SPW1
399 -- PADS for SPW1
400 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
400 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
401 PORT MAP (spw1_din, dtmp(0));
401 PORT MAP (spw1_din, dtmp(0));
402 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
402 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
403 PORT MAP (spw1_sin, stmp(0));
403 PORT MAP (spw1_sin, stmp(0));
404 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
404 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
405 PORT MAP (spw1_dout, swno.d(0));
405 PORT MAP (spw1_dout, swno.d(0));
406 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
406 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
407 PORT MAP (spw1_sout, swno.s(0));
407 PORT MAP (spw1_sout, swno.s(0));
408 -- PADS FOR SPW2
408 -- PADS FOR SPW2
409 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
409 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
410 PORT MAP (spw2_din, dtmp(1));
410 PORT MAP (spw2_din, dtmp(1));
411 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
411 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
412 PORT MAP (spw2_sin, stmp(1));
412 PORT MAP (spw2_sin, stmp(1));
413 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
413 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
414 PORT MAP (spw2_dout, swno.d(1));
414 PORT MAP (spw2_dout, swno.d(1));
415 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
415 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
416 PORT MAP (spw2_sout, swno.s(1));
416 PORT MAP (spw2_sout, swno.s(1));
417
417
418 -- GRSPW PHY
418 -- GRSPW PHY
419 --spw1_input: if CFG_SPW_GRSPW = 1 generate
419 --spw1_input: if CFG_SPW_GRSPW = 1 generate
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
421 spw_phy0 : grspw_phy
422 GENERIC MAP(
422 GENERIC MAP(
423 tech => fabtech,
423 tech => fabtech,
424 rxclkbuftype => 1,
424 rxclkbuftype => 1,
425 scantest => 0)
425 scantest => 0)
426 PORT MAP(
426 PORT MAP(
427 rxrst => swno.rxrst,
427 rxrst => swno.rxrst,
428 di => dtmp(j),
428 di => dtmp(j),
429 si => stmp(j),
429 si => stmp(j),
430 rxclko => spw_rxclk(j),
430 rxclko => spw_rxclk(j),
431 do => swni.d(j),
431 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
434 END GENERATE spw_inputloop;
435
435
436 -- SPW core
436 -- SPW core
437 sw0 : grspwm
437 sw0 : grspwm
438 GENERIC MAP(
438 GENERIC MAP(
439 tech => apa3e,
439 tech => apa3e,
440 hindex => 1,
440 hindex => 1,
441 pindex => 5,
441 pindex => 5,
442 paddr => 5,
442 paddr => 5,
443 pirq => 11,
443 pirq => 11,
444 sysfreq => 25000, -- CPU_FREQ
444 sysfreq => 25000, -- CPU_FREQ
445 rmap => 1,
445 rmap => 1,
446 rmapcrc => 1,
446 rmapcrc => 1,
447 fifosize1 => 16,
447 fifosize1 => 16,
448 fifosize2 => 16,
448 fifosize2 => 16,
449 rxclkbuftype => 1,
449 rxclkbuftype => 1,
450 rxunaligned => 0,
450 rxunaligned => 0,
451 rmapbufs => 4,
451 rmapbufs => 4,
452 ft => 0,
452 ft => 0,
453 netlist => 0,
453 netlist => 0,
454 ports => 2,
454 ports => 2,
455 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
455 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
456 memtech => apa3e,
456 memtech => apa3e,
457 destkey => 2,
457 destkey => 2,
458 spwcore => 1
458 spwcore => 1
459 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
459 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
460 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
460 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
461 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
461 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
462 )
462 )
463 PORT MAP(rstn, clkm, spw_rxclk(0),
463 PORT MAP(rstn, clkm, spw_rxclk(0),
464 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
464 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
465 ahbmi, ahbmo(1), apbi, apbo(5),
465 ahbmi, ahbmo(1), apbi, apbo(5),
466 swni, swno);
466 swni, swno);
467
467
468 swni.tickin <= '0';
468 swni.tickin <= '0';
469 swni.rmapen <= '1';
469 swni.rmapen <= '1';
470 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
470 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
471 swni.tickinraw <= '0';
471 swni.tickinraw <= '0';
472 swni.timein <= (OTHERS => '0');
472 swni.timein <= (OTHERS => '0');
473 swni.dcrstval <= (OTHERS => '0');
473 swni.dcrstval <= (OTHERS => '0');
474 swni.timerrstval <= (OTHERS => '0');
474 swni.timerrstval <= (OTHERS => '0');
475
475
476 -------------------------------------------------------------------------------
476 -------------------------------------------------------------------------------
477 -- LFR
477 -- LFR
478 -------------------------------------------------------------------------------
478 -------------------------------------------------------------------------------
479 lpp_lfr_1 : lpp_lfr
479 lpp_lfr_1 : lpp_lfr
480 GENERIC MAP (
480 GENERIC MAP (
481 Mem_use => use_RAM,
481 Mem_use => use_RAM,
482 nb_data_by_buffer_size => 32,
482 nb_data_by_buffer_size => 32,
483 nb_word_by_buffer_size => 30,
483 nb_word_by_buffer_size => 30,
484 nb_snapshot_param_size => 32,
484 nb_snapshot_param_size => 32,
485 delta_vector_size => 32,
485 delta_vector_size => 32,
486 delta_vector_size_f0_2 => 7, -- log2(96)
486 delta_vector_size_f0_2 => 7, -- log2(96)
487 pindex => 15,
487 pindex => 15,
488 paddr => 15,
488 paddr => 15,
489 pmask => 16#fff#,
489 pmask => 16#fff#,
490 pirq_ms => 6,
490 pirq_ms => 6,
491 pirq_wfp => 14,
491 pirq_wfp => 14,
492 hindex => 2,
492 hindex => 2,
493 top_lfr_version => X"00000003")
493 top_lfr_version => X"00000005")
494 PORT MAP (
494 PORT MAP (
495 clk => clkm,
495 clk => clkm,
496 rstn => rstn,
496 rstn => rstn,
497 sample_B => sample(2 DOWNTO 0),
497 sample_B => sample(2 DOWNTO 0),
498 sample_E => sample(7 DOWNTO 3),
498 sample_E => sample(7 DOWNTO 3),
499 sample_val => sample_val,
499 sample_val => sample_val,
500 apbi => apbi,
500 apbi => apbi,
501 apbo => apbo(15),
501 apbo => apbo(15),
502 ahbi => ahbmi,
502 ahbi => ahbmi,
503 ahbo => ahbmo(2),
503 ahbo => ahbmo(2),
504 coarse_time => coarse_time,
504 coarse_time => coarse_time,
505 fine_time => fine_time,
505 fine_time => fine_time,
506 data_shaping_BW => bias_fail_sw);
506 data_shaping_BW => bias_fail_sw);
507
507
508 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
508 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
509 GENERIC MAP (
509 GENERIC MAP (
510 ChanelCount => 8,
510 ChanelCount => 8,
511 ncycle_cnv_high => 79,
511 ncycle_cnv_high => 79,
512 ncycle_cnv => 500)
512 ncycle_cnv => 500)
513 PORT MAP (
513 PORT MAP (
514 cnv_clk => clk49_152MHz,
514 cnv_clk => clk49_152MHz,
515 cnv_rstn => rstn,
515 cnv_rstn => rstn,
516 cnv => ADC_smpclk,
516 cnv => ADC_smpclk,
517 clk => clkm,
517 clk => clkm,
518 rstn => rstn,
518 rstn => rstn,
519 ADC_data => ADC_data,
519 ADC_data => ADC_data,
520 ADC_nOE => ADC_OEB_bar_CH,
520 ADC_nOE => ADC_OEB_bar_CH,
521 sample => sample,
521 sample => sample,
522 sample_val => sample_val);
522 sample_val => sample_val);
523
523
524 END Behavioral;
524 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,176 +1,176
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_dma_singleOrBurst IS
45 ENTITY lpp_dma_singleOrBurst IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
48 hindex : INTEGER := 2
49 );
49 );
50 PORT (
50 PORT (
51 -- AMBA AHB system signals
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
54 --
55 run : IN STD_LOGIC;
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 send : IN STD_LOGIC;
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
66 );
66 );
67 END;
67 END;
68
68
69 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
69 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
70 -----------------------------------------------------------------------------
70 -----------------------------------------------------------------------------
71 SIGNAL DMAIn : DMA_In_Type;
71 SIGNAL DMAIn : DMA_In_Type;
72 SIGNAL DMAOut : DMA_OUt_Type;
72 SIGNAL DMAOut : DMA_OUt_Type;
73 -----------------------------------------------------------------------------
73 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
75 -- CONTROL
75 -- CONTROL
76 SIGNAL single_send : STD_LOGIC;
76 SIGNAL single_send : STD_LOGIC;
77 SIGNAL burst_send : STD_LOGIC;
77 SIGNAL burst_send : STD_LOGIC;
78
78
79 -----------------------------------------------------------------------------
79 -----------------------------------------------------------------------------
80 -- SEND SINGLE MODULE
80 -- SEND SINGLE MODULE
81 SIGNAL single_dmai : DMA_In_Type;
81 SIGNAL single_dmai : DMA_In_Type;
82
82
83 SIGNAL single_send_ok : STD_LOGIC;
83 SIGNAL single_send_ok : STD_LOGIC;
84 SIGNAL single_send_ko : STD_LOGIC;
84 SIGNAL single_send_ko : STD_LOGIC;
85 SIGNAL single_ren : STD_LOGIC;
85 SIGNAL single_ren : STD_LOGIC;
86 -----------------------------------------------------------------------------
86 -----------------------------------------------------------------------------
87 -- SEND SINGLE MODULE
87 -- SEND SINGLE MODULE
88 SIGNAL burst_dmai : DMA_In_Type;
88 SIGNAL burst_dmai : DMA_In_Type;
89
89
90 SIGNAL burst_send_ok : STD_LOGIC;
90 SIGNAL burst_send_ok : STD_LOGIC;
91 SIGNAL burst_send_ko : STD_LOGIC;
91 SIGNAL burst_send_ko : STD_LOGIC;
92 SIGNAL burst_ren : STD_LOGIC;
92 SIGNAL burst_ren : STD_LOGIC;
93 -----------------------------------------------------------------------------
93 -----------------------------------------------------------------------------
94 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
95 BEGIN
95 BEGIN
96
96
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 -- DMA to AHB interface
98 -- DMA to AHB interface
99 DMA2AHB_1 : DMA2AHB
99 DMA2AHB_1 : DMA2AHB
100 GENERIC MAP (
100 GENERIC MAP (
101 hindex => hindex,
101 hindex => hindex,
102 vendorid => VENDOR_LPP,
102 vendorid => VENDOR_LPP,
103 deviceid => 10,
103 deviceid => 10,
104 version => 0,
104 version => 0,
105 syncrst => 1,
105 syncrst => 1,
106 boundary => 1) -- FIX 11/01/2013
106 boundary => 1) -- FIX 11/01/2013
107 PORT MAP (
107 PORT MAP (
108 HCLK => HCLK,
108 HCLK => HCLK,
109 HRESETn => HRESETn,
109 HRESETn => HRESETn,
110 DMAIn => DMAIn,
110 DMAIn => DMAIn,
111 DMAOut => DMAOut,
111 DMAOut => DMAOut,
112
112
113 AHBIn => AHB_Master_In,
113 AHBIn => AHB_Master_In,
114 AHBOut => AHB_Master_Out);
114 AHBOut => AHB_Master_Out);
115 -----------------------------------------------------------------------------
115 -----------------------------------------------------------------------------
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
119 -- LE PROBLEME EST LA !!!!!
119 -- LE PROBLEME EST LA !!!!!
120 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 -- C'est le signal valid_burst qui n'est pas assez long.
122 -- C'est le signal valid_burst qui n'est pas assez long.
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124 single_send <= send WHEN valid_burst = '0' ELSE '0';
124 single_send <= send WHEN valid_burst = '0' ELSE '0';
125 burst_send <= send WHEN valid_burst = '1' ELSE '0';
125 burst_send <= send WHEN valid_burst = '1' ELSE '0';
126 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
126 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
127
127
128 -- TODO : verifier
128 -- TODO : verifier
129 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
129 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
130 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
130 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
131 -- burst_send_ok OR burst_send_ko;
131 -- burst_send_ok OR burst_send_ko;
132
132
133 --ren <= burst_ren WHEN valid_burst = '1' ELSE
133 --ren <= burst_ren WHEN valid_burst = '1' ELSE
134 -- NOT single_send_ok;
134 -- NOT single_send_ok;
135 ren <= burst_ren AND single_ren;
135 ren <= burst_ren AND single_ren;
136
136
137 -----------------------------------------------------------------------------
137 -----------------------------------------------------------------------------
138 -- SEND 1 word by DMA
138 -- SEND 1 word by DMA
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 lpp_dma_send_1word_1 : lpp_dma_send_1word
140 lpp_dma_send_1word_1 : lpp_dma_send_1word
141 PORT MAP (
141 PORT MAP (
142 HCLK => HCLK,
142 HCLK => HCLK,
143 HRESETn => HRESETn,
143 HRESETn => HRESETn,
144 DMAIn => single_dmai,
144 DMAIn => single_dmai,
145 DMAOut => DMAOut,
145 DMAOut => DMAOut,
146
146
147 send => single_send,
147 send => single_send,
148 address => address,
148 address => address,
149 data => data,
149 data => data_2_halfword,
150 ren => single_ren,
150 ren => single_ren,
151
151
152 send_ok => single_send_ok, -- TODO
152 send_ok => single_send_ok, -- TODO
153 send_ko => single_send_ko -- TODO
153 send_ko => single_send_ko -- TODO
154 );
154 );
155
155
156 -----------------------------------------------------------------------------
156 -----------------------------------------------------------------------------
157 -- SEND 16 word by DMA (in burst mode)
157 -- SEND 16 word by DMA (in burst mode)
158 -----------------------------------------------------------------------------
158 -----------------------------------------------------------------------------
159 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
159 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
160
160
161 lpp_dma_send_16word_1 : lpp_dma_send_16word
161 lpp_dma_send_16word_1 : lpp_dma_send_16word
162 PORT MAP (
162 PORT MAP (
163 HCLK => HCLK,
163 HCLK => HCLK,
164 HRESETn => HRESETn,
164 HRESETn => HRESETn,
165 DMAIn => burst_dmai,
165 DMAIn => burst_dmai,
166 DMAOut => DMAOut,
166 DMAOut => DMAOut,
167
167
168 send => burst_send,
168 send => burst_send,
169 address => address,
169 address => address,
170 data => data_2_halfword,
170 data => data_2_halfword,
171 ren => burst_ren,
171 ren => burst_ren,
172
172
173 send_ok => burst_send_ok,
173 send_ok => burst_send_ok,
174 send_ko => burst_send_ko);
174 send_ko => burst_send_ko);
175
175
176 END Behavioral;
176 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,638 +1,658
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC
62 data_shaping_BW : OUT STD_LOGIC;
63
64 --debug
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 debug_f0_data_valid : OUT STD_LOGIC;
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 debug_f1_data_valid : OUT STD_LOGIC;
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 debug_f2_data_valid : OUT STD_LOGIC;
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC
63 );
73 );
64 END lpp_lfr;
74 END lpp_lfr;
65
75
66 ARCHITECTURE beh OF lpp_lfr IS
76 ARCHITECTURE beh OF lpp_lfr IS
67 SIGNAL sample : Samples14v(7 DOWNTO 0);
77 SIGNAL sample : Samples14v(7 DOWNTO 0);
68 SIGNAL sample_s : Samples(7 DOWNTO 0);
78 SIGNAL sample_s : Samples(7 DOWNTO 0);
69 --
79 --
70 SIGNAL data_shaping_SP0 : STD_LOGIC;
80 SIGNAL data_shaping_SP0 : STD_LOGIC;
71 SIGNAL data_shaping_SP1 : STD_LOGIC;
81 SIGNAL data_shaping_SP1 : STD_LOGIC;
72 SIGNAL data_shaping_R0 : STD_LOGIC;
82 SIGNAL data_shaping_R0 : STD_LOGIC;
73 SIGNAL data_shaping_R1 : STD_LOGIC;
83 SIGNAL data_shaping_R1 : STD_LOGIC;
74 --
84 --
75 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 --
88 --
79 SIGNAL sample_f0_val : STD_LOGIC;
89 SIGNAL sample_f0_val : STD_LOGIC;
80 SIGNAL sample_f1_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
81 SIGNAL sample_f2_val : STD_LOGIC;
91 SIGNAL sample_f2_val : STD_LOGIC;
82 SIGNAL sample_f3_val : STD_LOGIC;
92 SIGNAL sample_f3_val : STD_LOGIC;
83 --
93 --
84 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
85 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
86 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
96 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
87 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
97 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
88 --
98 --
89 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
92
102
93 -- SM
103 -- SM
94 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
104 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
95 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
105 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
96 SIGNAL ready_matrix_f1 : STD_LOGIC;
106 SIGNAL ready_matrix_f1 : STD_LOGIC;
97 SIGNAL ready_matrix_f2 : STD_LOGIC;
107 SIGNAL ready_matrix_f2 : STD_LOGIC;
98 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
108 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
99 SIGNAL error_bad_component_error : STD_LOGIC;
109 SIGNAL error_bad_component_error : STD_LOGIC;
100 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
101 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
102 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
104 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
114 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
105 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
115 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
106 SIGNAL status_error_bad_component_error : STD_LOGIC;
116 SIGNAL status_error_bad_component_error : STD_LOGIC;
107 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
117 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
108 SIGNAL config_active_interruption_onError : STD_LOGIC;
118 SIGNAL config_active_interruption_onError : STD_LOGIC;
109 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
113
123
114 -- WFP
124 -- WFP
115 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
125 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
129 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
130 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
131 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
122 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
132 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
133 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
124
134
125 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
135 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
126 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
136 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
127 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
137 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
128 SIGNAL enable_f0 : STD_LOGIC;
138 SIGNAL enable_f0 : STD_LOGIC;
129 SIGNAL enable_f1 : STD_LOGIC;
139 SIGNAL enable_f1 : STD_LOGIC;
130 SIGNAL enable_f2 : STD_LOGIC;
140 SIGNAL enable_f2 : STD_LOGIC;
131 SIGNAL enable_f3 : STD_LOGIC;
141 SIGNAL enable_f3 : STD_LOGIC;
132 SIGNAL burst_f0 : STD_LOGIC;
142 SIGNAL burst_f0 : STD_LOGIC;
133 SIGNAL burst_f1 : STD_LOGIC;
143 SIGNAL burst_f1 : STD_LOGIC;
134 SIGNAL burst_f2 : STD_LOGIC;
144 SIGNAL burst_f2 : STD_LOGIC;
135 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
136 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
138 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
139
149
140 SIGNAL run : STD_LOGIC;
150 SIGNAL run : STD_LOGIC;
141 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
151 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
142
152
143 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 SIGNAL data_f0_data_out_valid : STD_LOGIC;
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
146 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
147 SIGNAL data_f0_data_out_ren : STD_LOGIC;
157 SIGNAL data_f0_data_out_ren : STD_LOGIC;
148 --f1
158 --f1
149 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL data_f1_data_out_valid : STD_LOGIC;
161 SIGNAL data_f1_data_out_valid : STD_LOGIC;
152 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
162 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
153 SIGNAL data_f1_data_out_ren : STD_LOGIC;
163 SIGNAL data_f1_data_out_ren : STD_LOGIC;
154 --f2
164 --f2
155 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL data_f2_data_out_valid : STD_LOGIC;
167 SIGNAL data_f2_data_out_valid : STD_LOGIC;
158 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
168 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
159 SIGNAL data_f2_data_out_ren : STD_LOGIC;
169 SIGNAL data_f2_data_out_ren : STD_LOGIC;
160 --f3
170 --f3
161 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 SIGNAL data_f3_data_out_valid : STD_LOGIC;
173 SIGNAL data_f3_data_out_valid : STD_LOGIC;
164 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
174 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
165 SIGNAL data_f3_data_out_ren : STD_LOGIC;
175 SIGNAL data_f3_data_out_ren : STD_LOGIC;
166
176
167 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
168 --
178 --
169 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
170 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
181 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
172 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
182 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
173 --f1
183 --f1
174 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
185 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
176 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
186 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
177 --f2
187 --f2
178 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
189 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
180 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
190 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
181 --f3
191 --f3
182 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
193 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
184 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
194 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
185
195
186 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
187 -- DMA RR
197 -- DMA RR
188 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
189 SIGNAL dma_sel_valid : STD_LOGIC;
199 SIGNAL dma_sel_valid : STD_LOGIC;
190 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
191 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
192 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
202 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
193
203
194 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
195 -- DMA_REG
205 -- DMA_REG
196 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
197 SIGNAL ongoing_reg : STD_LOGIC;
207 SIGNAL ongoing_reg : STD_LOGIC;
198 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
208 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 SIGNAL dma_send_reg : STD_LOGIC;
209 SIGNAL dma_send_reg : STD_LOGIC;
200 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
210 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
201 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
203
213
204
214
205 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
206 -- DMA
216 -- DMA
207 -----------------------------------------------------------------------------
217 -----------------------------------------------------------------------------
208 SIGNAL dma_send : STD_LOGIC;
218 SIGNAL dma_send : STD_LOGIC;
209 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
219 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
210 SIGNAL dma_done : STD_LOGIC;
220 SIGNAL dma_done : STD_LOGIC;
211 SIGNAL dma_ren : STD_LOGIC;
221 SIGNAL dma_ren : STD_LOGIC;
212 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
215
225
216 BEGIN
226 BEGIN
217
227
218 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
228 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
219 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
229 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
220
230
221 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
231 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
222 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
232 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
223 END GENERATE all_channel;
233 END GENERATE all_channel;
224
234
225 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
226 lpp_lfr_filter_1 : lpp_lfr_filter
236 lpp_lfr_filter_1 : lpp_lfr_filter
227 GENERIC MAP (
237 GENERIC MAP (
228 Mem_use => Mem_use)
238 Mem_use => Mem_use)
229 PORT MAP (
239 PORT MAP (
230 sample => sample_s,
240 sample => sample_s,
231 sample_val => sample_val,
241 sample_val => sample_val,
232 clk => clk,
242 clk => clk,
233 rstn => rstn,
243 rstn => rstn,
234 data_shaping_SP0 => data_shaping_SP0,
244 data_shaping_SP0 => data_shaping_SP0,
235 data_shaping_SP1 => data_shaping_SP1,
245 data_shaping_SP1 => data_shaping_SP1,
236 data_shaping_R0 => data_shaping_R0,
246 data_shaping_R0 => data_shaping_R0,
237 data_shaping_R1 => data_shaping_R1,
247 data_shaping_R1 => data_shaping_R1,
238 sample_f0_val => sample_f0_val,
248 sample_f0_val => sample_f0_val,
239 sample_f1_val => sample_f1_val,
249 sample_f1_val => sample_f1_val,
240 sample_f2_val => sample_f2_val,
250 sample_f2_val => sample_f2_val,
241 sample_f3_val => sample_f3_val,
251 sample_f3_val => sample_f3_val,
242 sample_f0_wdata => sample_f0_data,
252 sample_f0_wdata => sample_f0_data,
243 sample_f1_wdata => sample_f1_data,
253 sample_f1_wdata => sample_f1_data,
244 sample_f2_wdata => sample_f2_data,
254 sample_f2_wdata => sample_f2_data,
245 sample_f3_wdata => sample_f3_data);
255 sample_f3_wdata => sample_f3_data);
246
256
247 -----------------------------------------------------------------------------
257 -----------------------------------------------------------------------------
248 lpp_lfr_apbreg_1: lpp_lfr_apbreg
258 lpp_lfr_apbreg_1: lpp_lfr_apbreg
249 GENERIC MAP (
259 GENERIC MAP (
250 nb_data_by_buffer_size => nb_data_by_buffer_size,
260 nb_data_by_buffer_size => nb_data_by_buffer_size,
251 nb_word_by_buffer_size => nb_word_by_buffer_size,
261 nb_word_by_buffer_size => nb_word_by_buffer_size,
252 nb_snapshot_param_size => nb_snapshot_param_size,
262 nb_snapshot_param_size => nb_snapshot_param_size,
253 delta_vector_size => delta_vector_size,
263 delta_vector_size => delta_vector_size,
254 delta_vector_size_f0_2 => delta_vector_size_f0_2,
264 delta_vector_size_f0_2 => delta_vector_size_f0_2,
255 pindex => pindex,
265 pindex => pindex,
256 paddr => paddr,
266 paddr => paddr,
257 pmask => pmask,
267 pmask => pmask,
258 pirq_ms => pirq_ms,
268 pirq_ms => pirq_ms,
259 pirq_wfp => pirq_wfp,
269 pirq_wfp => pirq_wfp,
260 top_lfr_version => top_lfr_version)
270 top_lfr_version => top_lfr_version)
261 PORT MAP (
271 PORT MAP (
262 HCLK => clk,
272 HCLK => clk,
263 HRESETn => rstn,
273 HRESETn => rstn,
264 apbi => apbi,
274 apbi => apbi,
265 apbo => apbo,
275 apbo => apbo,
266 ready_matrix_f0_0 => ready_matrix_f0_0,
276 ready_matrix_f0_0 => ready_matrix_f0_0,
267 ready_matrix_f0_1 => ready_matrix_f0_1,
277 ready_matrix_f0_1 => ready_matrix_f0_1,
268 ready_matrix_f1 => ready_matrix_f1,
278 ready_matrix_f1 => ready_matrix_f1,
269 ready_matrix_f2 => ready_matrix_f2,
279 ready_matrix_f2 => ready_matrix_f2,
270 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
280 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
271 error_bad_component_error => error_bad_component_error,
281 error_bad_component_error => error_bad_component_error,
272 debug_reg => debug_reg,
282 debug_reg => debug_reg,
273 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
283 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
274 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
284 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
275 status_ready_matrix_f1 => status_ready_matrix_f1,
285 status_ready_matrix_f1 => status_ready_matrix_f1,
276 status_ready_matrix_f2 => status_ready_matrix_f2,
286 status_ready_matrix_f2 => status_ready_matrix_f2,
277 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
287 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
278 status_error_bad_component_error => status_error_bad_component_error,
288 status_error_bad_component_error => status_error_bad_component_error,
279 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
289 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
280 config_active_interruption_onError => config_active_interruption_onError,
290 config_active_interruption_onError => config_active_interruption_onError,
281 addr_matrix_f0_0 => addr_matrix_f0_0,
291 addr_matrix_f0_0 => addr_matrix_f0_0,
282 addr_matrix_f0_1 => addr_matrix_f0_1,
292 addr_matrix_f0_1 => addr_matrix_f0_1,
283 addr_matrix_f1 => addr_matrix_f1,
293 addr_matrix_f1 => addr_matrix_f1,
284 addr_matrix_f2 => addr_matrix_f2,
294 addr_matrix_f2 => addr_matrix_f2,
285 status_full => status_full,
295 status_full => status_full,
286 status_full_ack => status_full_ack,
296 status_full_ack => status_full_ack,
287 status_full_err => status_full_err,
297 status_full_err => status_full_err,
288 status_new_err => status_new_err,
298 status_new_err => status_new_err,
289 data_shaping_BW => data_shaping_BW,
299 data_shaping_BW => data_shaping_BW,
290 data_shaping_SP0 => data_shaping_SP0,
300 data_shaping_SP0 => data_shaping_SP0,
291 data_shaping_SP1 => data_shaping_SP1,
301 data_shaping_SP1 => data_shaping_SP1,
292 data_shaping_R0 => data_shaping_R0,
302 data_shaping_R0 => data_shaping_R0,
293 data_shaping_R1 => data_shaping_R1,
303 data_shaping_R1 => data_shaping_R1,
294 delta_snapshot => delta_snapshot,
304 delta_snapshot => delta_snapshot,
295 delta_f0 => delta_f0,
305 delta_f0 => delta_f0,
296 delta_f0_2 => delta_f0_2,
306 delta_f0_2 => delta_f0_2,
297 delta_f1 => delta_f1,
307 delta_f1 => delta_f1,
298 delta_f2 => delta_f2,
308 delta_f2 => delta_f2,
299 nb_data_by_buffer => nb_data_by_buffer,
309 nb_data_by_buffer => nb_data_by_buffer,
300 nb_word_by_buffer => nb_word_by_buffer,
310 nb_word_by_buffer => nb_word_by_buffer,
301 nb_snapshot_param => nb_snapshot_param,
311 nb_snapshot_param => nb_snapshot_param,
302 enable_f0 => enable_f0,
312 enable_f0 => enable_f0,
303 enable_f1 => enable_f1,
313 enable_f1 => enable_f1,
304 enable_f2 => enable_f2,
314 enable_f2 => enable_f2,
305 enable_f3 => enable_f3,
315 enable_f3 => enable_f3,
306 burst_f0 => burst_f0,
316 burst_f0 => burst_f0,
307 burst_f1 => burst_f1,
317 burst_f1 => burst_f1,
308 burst_f2 => burst_f2,
318 burst_f2 => burst_f2,
309 run => run,
319 run => run,
310 addr_data_f0 => addr_data_f0,
320 addr_data_f0 => addr_data_f0,
311 addr_data_f1 => addr_data_f1,
321 addr_data_f1 => addr_data_f1,
312 addr_data_f2 => addr_data_f2,
322 addr_data_f2 => addr_data_f2,
313 addr_data_f3 => addr_data_f3,
323 addr_data_f3 => addr_data_f3,
314 start_date => start_date);
324 start_date => start_date);
315
325
316 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
317 lpp_waveform_1: lpp_waveform
327 lpp_waveform_1: lpp_waveform
318 GENERIC MAP (
328 GENERIC MAP (
319 tech => inferred,
329 tech => inferred,
320 data_size => 6*16,
330 data_size => 6*16,
321 nb_data_by_buffer_size => nb_data_by_buffer_size,
331 nb_data_by_buffer_size => nb_data_by_buffer_size,
322 nb_word_by_buffer_size => nb_word_by_buffer_size,
332 nb_word_by_buffer_size => nb_word_by_buffer_size,
323 nb_snapshot_param_size => nb_snapshot_param_size,
333 nb_snapshot_param_size => nb_snapshot_param_size,
324 delta_vector_size => delta_vector_size,
334 delta_vector_size => delta_vector_size,
325 delta_vector_size_f0_2 => delta_vector_size_f0_2
335 delta_vector_size_f0_2 => delta_vector_size_f0_2
326 )
336 )
327 PORT MAP (
337 PORT MAP (
328 clk => clk,
338 clk => clk,
329 rstn => rstn,
339 rstn => rstn,
330
340
331 reg_run => run,
341 reg_run => run,
332 reg_start_date => start_date,
342 reg_start_date => start_date,
333 reg_delta_snapshot => delta_snapshot,
343 reg_delta_snapshot => delta_snapshot,
334 reg_delta_f0 => delta_f0,
344 reg_delta_f0 => delta_f0,
335 reg_delta_f0_2 => delta_f0_2,
345 reg_delta_f0_2 => delta_f0_2,
336 reg_delta_f1 => delta_f1,
346 reg_delta_f1 => delta_f1,
337 reg_delta_f2 => delta_f2,
347 reg_delta_f2 => delta_f2,
338
348
339 enable_f0 => enable_f0,
349 enable_f0 => enable_f0,
340 enable_f1 => enable_f1,
350 enable_f1 => enable_f1,
341 enable_f2 => enable_f2,
351 enable_f2 => enable_f2,
342 enable_f3 => enable_f3,
352 enable_f3 => enable_f3,
343 burst_f0 => burst_f0,
353 burst_f0 => burst_f0,
344 burst_f1 => burst_f1,
354 burst_f1 => burst_f1,
345 burst_f2 => burst_f2,
355 burst_f2 => burst_f2,
346
356
347 nb_data_by_buffer => nb_data_by_buffer,
357 nb_data_by_buffer => nb_data_by_buffer,
348 nb_word_by_buffer => nb_word_by_buffer,
358 nb_word_by_buffer => nb_word_by_buffer,
349 nb_snapshot_param => nb_snapshot_param,
359 nb_snapshot_param => nb_snapshot_param,
350 status_full => status_full,
360 status_full => status_full,
351 status_full_ack => status_full_ack,
361 status_full_ack => status_full_ack,
352 status_full_err => status_full_err,
362 status_full_err => status_full_err,
353 status_new_err => status_new_err,
363 status_new_err => status_new_err,
354
364
355 coarse_time => coarse_time,
365 coarse_time => coarse_time,
356 fine_time => fine_time,
366 fine_time => fine_time,
357
367
358 --f0
368 --f0
359 addr_data_f0 => addr_data_f0,
369 addr_data_f0 => addr_data_f0,
360 data_f0_in_valid => sample_f0_val,
370 data_f0_in_valid => sample_f0_val,
361 data_f0_in => sample_f0_data,
371 data_f0_in => sample_f0_data,
362 --f1
372 --f1
363 addr_data_f1 => addr_data_f1,
373 addr_data_f1 => addr_data_f1,
364 data_f1_in_valid => sample_f1_val,
374 data_f1_in_valid => sample_f1_val,
365 data_f1_in => sample_f1_data,
375 data_f1_in => sample_f1_data,
366 --f2
376 --f2
367 addr_data_f2 => addr_data_f2,
377 addr_data_f2 => addr_data_f2,
368 data_f2_in_valid => sample_f2_val,
378 data_f2_in_valid => sample_f2_val,
369 data_f2_in => sample_f2_data,
379 data_f2_in => sample_f2_data,
370 --f3
380 --f3
371 addr_data_f3 => addr_data_f3,
381 addr_data_f3 => addr_data_f3,
372 data_f3_in_valid => sample_f3_val,
382 data_f3_in_valid => sample_f3_val,
373 data_f3_in => sample_f3_data,
383 data_f3_in => sample_f3_data,
374 -- OUTPUT -- DMA interface
384 -- OUTPUT -- DMA interface
375 --f0
385 --f0
376 data_f0_addr_out => data_f0_addr_out_s,
386 data_f0_addr_out => data_f0_addr_out_s,
377 data_f0_data_out => data_f0_data_out,
387 data_f0_data_out => data_f0_data_out,
378 data_f0_data_out_valid => data_f0_data_out_valid_s,
388 data_f0_data_out_valid => data_f0_data_out_valid_s,
379 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
389 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
380 data_f0_data_out_ren => data_f0_data_out_ren,
390 data_f0_data_out_ren => data_f0_data_out_ren,
381 --f1
391 --f1
382 data_f1_addr_out => data_f1_addr_out_s,
392 data_f1_addr_out => data_f1_addr_out_s,
383 data_f1_data_out => data_f1_data_out,
393 data_f1_data_out => data_f1_data_out,
384 data_f1_data_out_valid => data_f1_data_out_valid_s,
394 data_f1_data_out_valid => data_f1_data_out_valid_s,
385 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
395 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
386 data_f1_data_out_ren => data_f1_data_out_ren,
396 data_f1_data_out_ren => data_f1_data_out_ren,
387 --f2
397 --f2
388 data_f2_addr_out => data_f2_addr_out_s,
398 data_f2_addr_out => data_f2_addr_out_s,
389 data_f2_data_out => data_f2_data_out,
399 data_f2_data_out => data_f2_data_out,
390 data_f2_data_out_valid => data_f2_data_out_valid_s,
400 data_f2_data_out_valid => data_f2_data_out_valid_s,
391 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
401 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
392 data_f2_data_out_ren => data_f2_data_out_ren,
402 data_f2_data_out_ren => data_f2_data_out_ren,
393 --f3
403 --f3
394 data_f3_addr_out => data_f3_addr_out_s,
404 data_f3_addr_out => data_f3_addr_out_s,
395 data_f3_data_out => data_f3_data_out,
405 data_f3_data_out => data_f3_data_out,
396 data_f3_data_out_valid => data_f3_data_out_valid_s,
406 data_f3_data_out_valid => data_f3_data_out_valid_s,
397 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
407 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
398 data_f3_data_out_ren => data_f3_data_out_ren
408 data_f3_data_out_ren => data_f3_data_out_ren,
409
410 --debug
411 debug_f0_data => debug_f0_data,
412 debug_f0_data_valid => debug_f0_data_valid ,
413 debug_f1_data => debug_f1_data ,
414 debug_f1_data_valid => debug_f1_data_valid,
415 debug_f2_data => debug_f2_data ,
416 debug_f2_data_valid => debug_f2_data_valid ,
417 debug_f3_data => debug_f3_data ,
418 debug_f3_data_valid => debug_f3_data_valid
399
419
400 );
420 );
401
421
402
422
403 -----------------------------------------------------------------------------
423 -----------------------------------------------------------------------------
404 -- TEMP
424 -- TEMP
405 -----------------------------------------------------------------------------
425 -----------------------------------------------------------------------------
406
426
407 PROCESS (clk, rstn)
427 PROCESS (clk, rstn)
408 BEGIN -- PROCESS
428 BEGIN -- PROCESS
409 IF rstn = '0' THEN -- asynchronous reset (active low)
429 IF rstn = '0' THEN -- asynchronous reset (active low)
410 data_f0_data_out_valid <= '0';
430 data_f0_data_out_valid <= '0';
411 data_f0_data_out_valid_burst <= '0';
431 data_f0_data_out_valid_burst <= '0';
412 data_f1_data_out_valid <= '0';
432 data_f1_data_out_valid <= '0';
413 data_f1_data_out_valid_burst <= '0';
433 data_f1_data_out_valid_burst <= '0';
414 data_f2_data_out_valid <= '0';
434 data_f2_data_out_valid <= '0';
415 data_f2_data_out_valid_burst <= '0';
435 data_f2_data_out_valid_burst <= '0';
416 data_f3_data_out_valid <= '0';
436 data_f3_data_out_valid <= '0';
417 data_f3_data_out_valid_burst <= '0';
437 data_f3_data_out_valid_burst <= '0';
418 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
438 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
419 data_f0_data_out_valid <= data_f0_data_out_valid_s;
439 data_f0_data_out_valid <= data_f0_data_out_valid_s;
420 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
440 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
421 data_f1_data_out_valid <= data_f1_data_out_valid_s;
441 data_f1_data_out_valid <= data_f1_data_out_valid_s;
422 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
442 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
423 data_f2_data_out_valid <= data_f2_data_out_valid_s;
443 data_f2_data_out_valid <= data_f2_data_out_valid_s;
424 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
444 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
425 data_f3_data_out_valid <= data_f3_data_out_valid_s;
445 data_f3_data_out_valid <= data_f3_data_out_valid_s;
426 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
446 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
427 END IF;
447 END IF;
428 END PROCESS;
448 END PROCESS;
429
449
430 data_f0_addr_out <= data_f0_addr_out_s;
450 data_f0_addr_out <= data_f0_addr_out_s;
431 data_f1_addr_out <= data_f1_addr_out_s;
451 data_f1_addr_out <= data_f1_addr_out_s;
432 data_f2_addr_out <= data_f2_addr_out_s;
452 data_f2_addr_out <= data_f2_addr_out_s;
433 data_f3_addr_out <= data_f3_addr_out_s;
453 data_f3_addr_out <= data_f3_addr_out_s;
434
454
435 -----------------------------------------------------------------------------
455 -----------------------------------------------------------------------------
436 -- RoundRobin Selection For DMA
456 -- RoundRobin Selection For DMA
437 -----------------------------------------------------------------------------
457 -----------------------------------------------------------------------------
438
458
439 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
459 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
440 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
460 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
441 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
461 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
442 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
462 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
443
463
444 RR_Arbiter_4_1: RR_Arbiter_4
464 RR_Arbiter_4_1: RR_Arbiter_4
445 PORT MAP (
465 PORT MAP (
446 clk => clk,
466 clk => clk,
447 rstn => rstn,
467 rstn => rstn,
448 in_valid => dma_rr_valid,
468 in_valid => dma_rr_valid,
449 out_grant => dma_rr_grant);
469 out_grant => dma_rr_grant);
450
470
451
471
452 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
453 -- in : dma_rr_grant
473 -- in : dma_rr_grant
454 -- send
474 -- send
455 -- out : dma_sel
475 -- out : dma_sel
456 -- dma_valid_burst
476 -- dma_valid_burst
457 -- dma_sel_valid
477 -- dma_sel_valid
458 -----------------------------------------------------------------------------
478 -----------------------------------------------------------------------------
459 PROCESS (clk, rstn)
479 PROCESS (clk, rstn)
460 BEGIN -- PROCESS
480 BEGIN -- PROCESS
461 IF rstn = '0' THEN -- asynchronous reset (active low)
481 IF rstn = '0' THEN -- asynchronous reset (active low)
462 dma_sel <= (OTHERS => '0');
482 dma_sel <= (OTHERS => '0');
463 dma_send <= '0';
483 dma_send <= '0';
464 dma_valid_burst <= '0';
484 dma_valid_burst <= '0';
465 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
485 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
466 -- IF dma_sel = "0000" OR dma_send = '1' THEN
486 -- IF dma_sel = "0000" OR dma_send = '1' THEN
467 IF dma_sel = "0000" OR dma_done = '1' THEN
487 IF dma_sel = "0000" OR dma_done = '1' THEN
468 dma_sel <= dma_rr_grant;
488 dma_sel <= dma_rr_grant;
469 IF dma_rr_grant(0) = '1' THEN
489 IF dma_rr_grant(0) = '1' THEN
470 dma_send <= '1';
490 dma_send <= '1';
471 dma_valid_burst <= data_f0_data_out_valid_burst;
491 dma_valid_burst <= data_f0_data_out_valid_burst;
472 dma_sel_valid <= data_f0_data_out_valid;
492 dma_sel_valid <= data_f0_data_out_valid;
473 ELSIF dma_rr_grant(1) = '1' THEN
493 ELSIF dma_rr_grant(1) = '1' THEN
474 dma_send <= '1';
494 dma_send <= '1';
475 dma_valid_burst <= data_f1_data_out_valid_burst;
495 dma_valid_burst <= data_f1_data_out_valid_burst;
476 dma_sel_valid <= data_f1_data_out_valid;
496 dma_sel_valid <= data_f1_data_out_valid;
477 ELSIF dma_rr_grant(2) = '1' THEN
497 ELSIF dma_rr_grant(2) = '1' THEN
478 dma_send <= '1';
498 dma_send <= '1';
479 dma_valid_burst <= data_f2_data_out_valid_burst;
499 dma_valid_burst <= data_f2_data_out_valid_burst;
480 dma_sel_valid <= data_f2_data_out_valid;
500 dma_sel_valid <= data_f2_data_out_valid;
481 ELSIF dma_rr_grant(3) = '1' THEN
501 ELSIF dma_rr_grant(3) = '1' THEN
482 dma_send <= '1';
502 dma_send <= '1';
483 dma_valid_burst <= data_f3_data_out_valid_burst;
503 dma_valid_burst <= data_f3_data_out_valid_burst;
484 dma_sel_valid <= data_f3_data_out_valid;
504 dma_sel_valid <= data_f3_data_out_valid;
485 END IF;
505 END IF;
486 ELSE
506 ELSE
487 dma_sel <= dma_sel;
507 dma_sel <= dma_sel;
488 dma_send <= '0';
508 dma_send <= '0';
489 END IF;
509 END IF;
490 END IF;
510 END IF;
491 END PROCESS;
511 END PROCESS;
492
512
493
513
494 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
514 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
495 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
515 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
496 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
516 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
497 data_f3_addr_out ;
517 data_f3_addr_out ;
498
518
499 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
519 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
500 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
520 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
501 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
521 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
502 data_f3_data_out ;
522 data_f3_data_out ;
503
523
504 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
524 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
505 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
525 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
506 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
526 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
507 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
527 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
508 -- '0';
528 -- '0';
509
529
510 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
530 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
511 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
531 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
512 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
532 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
513 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
533 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
514 -- '0';
534 -- '0';
515
535
516 -- TODO
536 -- TODO
517 --dma_send <= dma_sel_valid OR dma_valid_burst;
537 --dma_send <= dma_sel_valid OR dma_valid_burst;
518
538
519 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
539 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
520 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
540 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
521 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
541 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
522 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
542 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
523
543
524 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
544 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
525 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
545 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
526 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
546 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
527 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
547 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
528
548
529
549
530 --PROCESS (clk, rstn)
550 --PROCESS (clk, rstn)
531 --BEGIN -- PROCESS
551 --BEGIN -- PROCESS
532 -- IF rstn = '0' THEN -- asynchronous reset (active low)
552 -- IF rstn = '0' THEN -- asynchronous reset (active low)
533 -- ongoing_reg <= '0';
553 -- ongoing_reg <= '0';
534 -- dma_sel_reg <= (OTHERS => '0');
554 -- dma_sel_reg <= (OTHERS => '0');
535 -- dma_send_reg <= '0';
555 -- dma_send_reg <= '0';
536 -- dma_valid_burst_reg <= '0';
556 -- dma_valid_burst_reg <= '0';
537 -- dma_address_reg <= (OTHERS => '0');
557 -- dma_address_reg <= (OTHERS => '0');
538 -- dma_data_reg <= (OTHERS => '0');
558 -- dma_data_reg <= (OTHERS => '0');
539 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
559 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
540 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
560 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
541 -- ongoing_reg <= '1';
561 -- ongoing_reg <= '1';
542 -- dma_valid_burst_reg <= dma_valid_burst;
562 -- dma_valid_burst_reg <= dma_valid_burst;
543 -- dma_sel_reg <= dma_sel;
563 -- dma_sel_reg <= dma_sel;
544 -- ELSE
564 -- ELSE
545 -- IF dma_done = '1' THEN
565 -- IF dma_done = '1' THEN
546 -- ongoing_reg <= '0';
566 -- ongoing_reg <= '0';
547 -- END IF;
567 -- END IF;
548 -- END IF;
568 -- END IF;
549 -- dma_send_reg <= dma_send;
569 -- dma_send_reg <= dma_send;
550 -- dma_address_reg <= dma_address;
570 -- dma_address_reg <= dma_address;
551 -- dma_data_reg <= dma_data;
571 -- dma_data_reg <= dma_data;
552 -- END IF;
572 -- END IF;
553 --END PROCESS;
573 --END PROCESS;
554
574
555 dma_data_2 <= dma_data;
575 dma_data_2 <= dma_data;
556 --PROCESS (clk, rstn)
576 --PROCESS (clk, rstn)
557 --BEGIN -- PROCESS
577 --BEGIN -- PROCESS
558 -- IF rstn = '0' THEN -- asynchronous reset (active low)
578 -- IF rstn = '0' THEN -- asynchronous reset (active low)
559 -- dma_data_2 <= (OTHERS => '0');
579 -- dma_data_2 <= (OTHERS => '0');
560 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
580 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
561 -- dma_data_2 <= dma_data;
581 -- dma_data_2 <= dma_data;
562
582
563 -- END IF;
583 -- END IF;
564 --END PROCESS;
584 --END PROCESS;
565
585
566
586
567 -----------------------------------------------------------------------------
587 -----------------------------------------------------------------------------
568 -- DMA
588 -- DMA
569 -----------------------------------------------------------------------------
589 -----------------------------------------------------------------------------
570 lpp_dma_singleOrBurst_1: lpp_dma_singleOrBurst
590 lpp_dma_singleOrBurst_1: lpp_dma_singleOrBurst
571 GENERIC MAP (
591 GENERIC MAP (
572 tech => inferred,
592 tech => inferred,
573 hindex => hindex)
593 hindex => hindex)
574 PORT MAP (
594 PORT MAP (
575 HCLK => clk,
595 HCLK => clk,
576 HRESETn => rstn,
596 HRESETn => rstn,
577 run => run,
597 run => run,
578 AHB_Master_In => ahbi,
598 AHB_Master_In => ahbi,
579 AHB_Master_Out => ahbo,
599 AHB_Master_Out => ahbo,
580
600
581 send => dma_send,--_reg,
601 send => dma_send,--_reg,
582 valid_burst => dma_valid_burst,--_reg,
602 valid_burst => dma_valid_burst,--_reg,
583 done => dma_done,
603 done => dma_done,
584 ren => dma_ren,
604 ren => dma_ren,
585 address => dma_address,--_reg,
605 address => dma_address,--_reg,
586 data => dma_data_2);--_reg);
606 data => dma_data_2);--_reg);
587
607
588 -----------------------------------------------------------------------------
608 -----------------------------------------------------------------------------
589 -- Matrix Spectral - TODO
609 -- Matrix Spectral - TODO
590 -----------------------------------------------------------------------------
610 -----------------------------------------------------------------------------
591 -----------------------------------------------------------------------------
611 -----------------------------------------------------------------------------
592 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
612 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
593 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
613 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
594 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
614 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
595 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
615 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
596 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
616 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
597 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
617 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
598
618
599 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
619 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
600 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
620 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
601 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
621 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
602 -------------------------------------------------------------------------------
622 -------------------------------------------------------------------------------
603 --lpp_lfr_ms_1: lpp_lfr_ms
623 --lpp_lfr_ms_1: lpp_lfr_ms
604 -- GENERIC MAP (
624 -- GENERIC MAP (
605 -- hindex => hindex_ms)
625 -- hindex => hindex_ms)
606 -- PORT MAP (
626 -- PORT MAP (
607 -- clk => clk,
627 -- clk => clk,
608 -- rstn => rstn,
628 -- rstn => rstn,
609 -- sample_f0_wen => sample_f0_wen,
629 -- sample_f0_wen => sample_f0_wen,
610 -- sample_f0_wdata => sample_f0_wdata,
630 -- sample_f0_wdata => sample_f0_wdata,
611 -- sample_f1_wen => sample_f1_wen,
631 -- sample_f1_wen => sample_f1_wen,
612 -- sample_f1_wdata => sample_f1_wdata,
632 -- sample_f1_wdata => sample_f1_wdata,
613 -- sample_f3_wen => sample_f3_wen,
633 -- sample_f3_wen => sample_f3_wen,
614 -- sample_f3_wdata => sample_f3_wdata,
634 -- sample_f3_wdata => sample_f3_wdata,
615 -- AHB_Master_In => ahbi_ms,
635 -- AHB_Master_In => ahbi_ms,
616 -- AHB_Master_Out => ahbo_ms,
636 -- AHB_Master_Out => ahbo_ms,
617
637
618 -- ready_matrix_f0_0 => ready_matrix_f0_0,
638 -- ready_matrix_f0_0 => ready_matrix_f0_0,
619 -- ready_matrix_f0_1 => ready_matrix_f0_1,
639 -- ready_matrix_f0_1 => ready_matrix_f0_1,
620 -- ready_matrix_f1 => ready_matrix_f1,
640 -- ready_matrix_f1 => ready_matrix_f1,
621 -- ready_matrix_f2 => ready_matrix_f2,
641 -- ready_matrix_f2 => ready_matrix_f2,
622 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
642 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
623 -- error_bad_component_error => error_bad_component_error,
643 -- error_bad_component_error => error_bad_component_error,
624 -- debug_reg => debug_reg,
644 -- debug_reg => debug_reg,
625 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
645 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
626 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
646 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
627 -- status_ready_matrix_f1 => status_ready_matrix_f1,
647 -- status_ready_matrix_f1 => status_ready_matrix_f1,
628 -- status_ready_matrix_f2 => status_ready_matrix_f2,
648 -- status_ready_matrix_f2 => status_ready_matrix_f2,
629 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
649 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
630 -- status_error_bad_component_error => status_error_bad_component_error,
650 -- status_error_bad_component_error => status_error_bad_component_error,
631 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
651 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
632 -- config_active_interruption_onError => config_active_interruption_onError,
652 -- config_active_interruption_onError => config_active_interruption_onError,
633 -- addr_matrix_f0_0 => addr_matrix_f0_0,
653 -- addr_matrix_f0_0 => addr_matrix_f0_0,
634 -- addr_matrix_f0_1 => addr_matrix_f0_1,
654 -- addr_matrix_f0_1 => addr_matrix_f0_1,
635 -- addr_matrix_f1 => addr_matrix_f1,
655 -- addr_matrix_f1 => addr_matrix_f1,
636 -- addr_matrix_f2 => addr_matrix_f2);
656 -- addr_matrix_f2 => addr_matrix_f2);
637
657
638 END beh;
658 END beh;
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@@ -1,472 +1,475
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_data_by_buffer_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
42 delta_vector_size : INTEGER := 20;
42 delta_vector_size : INTEGER := 20;
43 delta_vector_size_f0_2 : INTEGER := 3;
43 delta_vector_size_f0_2 : INTEGER := 3;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1;
49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
51 PORT (
51 PORT (
52 -- AMBA AHB system signals
52 -- AMBA AHB system signals
53 HCLK : IN STD_ULOGIC;
53 HCLK : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
55
55
56 -- AMBA APB Slave Interface
56 -- AMBA APB Slave Interface
57 apbi : IN apb_slv_in_type;
57 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
58 apbo : OUT apb_slv_out_type;
59
59
60 ---------------------------------------------------------------------------
60 ---------------------------------------------------------------------------
61 -- Spectral Matrix Reg
61 -- Spectral Matrix Reg
62 -- IN
62 -- IN
63 ready_matrix_f0_0 : IN STD_LOGIC;
63 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70
70
71 -- OUT
71 -- OUT
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
78
78
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
87 -- WaveForm picker Reg
87 -- WaveForm picker Reg
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92
92
93 -- OUT
93 -- OUT
94 data_shaping_BW : OUT STD_LOGIC;
94 data_shaping_BW : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
99
99
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
108
108
109 enable_f0 : OUT STD_LOGIC;
109 enable_f0 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
113
113
114 burst_f0 : OUT STD_LOGIC;
114 burst_f0 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
117
117
118 run : OUT STD_LOGIC;
118 run : OUT STD_LOGIC;
119
119
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
125
125
126 ---------------------------------------------------------------------------
126 ---------------------------------------------------------------------------
127 );
127 );
128
128
129 END lpp_lfr_apbreg;
129 END lpp_lfr_apbreg;
130
130
131 ARCHITECTURE beh OF lpp_lfr_apbreg IS
131 ARCHITECTURE beh OF lpp_lfr_apbreg IS
132
132
133 CONSTANT REVISION : INTEGER := 1;
133 CONSTANT REVISION : INTEGER := 1;
134
134
135 CONSTANT pconfig : apb_config_type := (
135 CONSTANT pconfig : apb_config_type := (
136 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
136 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
137 1 => apb_iobar(paddr, pmask));
137 1 => apb_iobar(paddr, pmask));
138
138
139 TYPE lpp_SpectralMatrix_regs IS RECORD
139 TYPE lpp_SpectralMatrix_regs IS RECORD
140 config_active_interruption_onNewMatrix : STD_LOGIC;
140 config_active_interruption_onNewMatrix : STD_LOGIC;
141 config_active_interruption_onError : STD_LOGIC;
141 config_active_interruption_onError : STD_LOGIC;
142 status_ready_matrix_f0_0 : STD_LOGIC;
142 status_ready_matrix_f0_0 : STD_LOGIC;
143 status_ready_matrix_f0_1 : STD_LOGIC;
143 status_ready_matrix_f0_1 : STD_LOGIC;
144 status_ready_matrix_f1 : STD_LOGIC;
144 status_ready_matrix_f1 : STD_LOGIC;
145 status_ready_matrix_f2 : STD_LOGIC;
145 status_ready_matrix_f2 : STD_LOGIC;
146 status_error_anticipating_empty_fifo : STD_LOGIC;
146 status_error_anticipating_empty_fifo : STD_LOGIC;
147 status_error_bad_component_error : STD_LOGIC;
147 status_error_bad_component_error : STD_LOGIC;
148 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 END RECORD;
152 END RECORD;
153 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
153 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
154
154
155 TYPE lpp_WaveformPicker_regs IS RECORD
155 TYPE lpp_WaveformPicker_regs IS RECORD
156 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 data_shaping_BW : STD_LOGIC;
159 data_shaping_BW : STD_LOGIC;
160 data_shaping_SP0 : STD_LOGIC;
160 data_shaping_SP0 : STD_LOGIC;
161 data_shaping_SP1 : STD_LOGIC;
161 data_shaping_SP1 : STD_LOGIC;
162 data_shaping_R0 : STD_LOGIC;
162 data_shaping_R0 : STD_LOGIC;
163 data_shaping_R1 : STD_LOGIC;
163 data_shaping_R1 : STD_LOGIC;
164 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
166 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
167 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
167 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
169 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
170 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
170 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
171 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
171 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
172 enable_f0 : STD_LOGIC;
172 enable_f0 : STD_LOGIC;
173 enable_f1 : STD_LOGIC;
173 enable_f1 : STD_LOGIC;
174 enable_f2 : STD_LOGIC;
174 enable_f2 : STD_LOGIC;
175 enable_f3 : STD_LOGIC;
175 enable_f3 : STD_LOGIC;
176 burst_f0 : STD_LOGIC;
176 burst_f0 : STD_LOGIC;
177 burst_f1 : STD_LOGIC;
177 burst_f1 : STD_LOGIC;
178 burst_f2 : STD_LOGIC;
178 burst_f2 : STD_LOGIC;
179 run : STD_LOGIC;
179 run : STD_LOGIC;
180 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
185 END RECORD;
185 END RECORD;
186 SIGNAL reg_wp : lpp_WaveformPicker_regs;
186 SIGNAL reg_wp : lpp_WaveformPicker_regs;
187
187
188 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
189
189
190 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
191 -- IRQ
191 -- IRQ
192 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
193 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
193 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
194 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
194 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
195 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
195 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
196 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
196 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
197 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
197 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
198 SIGNAL ored_irq_wfp : STD_LOGIC;
198 SIGNAL ored_irq_wfp : STD_LOGIC;
199
199
200 BEGIN -- beh
200 BEGIN -- beh
201
201
202 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
202 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
203 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
203 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
204 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
204 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
205 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
205 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
206 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
206 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
207 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
207 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
208
208
209 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
209 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
210 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
210 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
211 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
211 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
212 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
212 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
213 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
213 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
214 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
214 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
215
215
216
216
217 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
217 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
218 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
218 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
219 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
219 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
220 data_shaping_R0 <= reg_wp.data_shaping_R0;
220 data_shaping_R0 <= reg_wp.data_shaping_R0;
221 data_shaping_R1 <= reg_wp.data_shaping_R1;
221 data_shaping_R1 <= reg_wp.data_shaping_R1;
222
222
223 delta_snapshot <= reg_wp.delta_snapshot;
223 delta_snapshot <= reg_wp.delta_snapshot;
224 delta_f0 <= reg_wp.delta_f0;
224 delta_f0 <= reg_wp.delta_f0;
225 delta_f0_2 <= reg_wp.delta_f0_2;
225 delta_f0_2 <= reg_wp.delta_f0_2;
226 delta_f1 <= reg_wp.delta_f1;
226 delta_f1 <= reg_wp.delta_f1;
227 delta_f2 <= reg_wp.delta_f2;
227 delta_f2 <= reg_wp.delta_f2;
228 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
228 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
229 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
229 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
230 nb_snapshot_param <= reg_wp.nb_snapshot_param;
230 nb_snapshot_param <= reg_wp.nb_snapshot_param;
231
231
232 enable_f0 <= reg_wp.enable_f0;
232 enable_f0 <= reg_wp.enable_f0;
233 enable_f1 <= reg_wp.enable_f1;
233 enable_f1 <= reg_wp.enable_f1;
234 enable_f2 <= reg_wp.enable_f2;
234 enable_f2 <= reg_wp.enable_f2;
235 enable_f3 <= reg_wp.enable_f3;
235 enable_f3 <= reg_wp.enable_f3;
236
236
237 burst_f0 <= reg_wp.burst_f0;
237 burst_f0 <= reg_wp.burst_f0;
238 burst_f1 <= reg_wp.burst_f1;
238 burst_f1 <= reg_wp.burst_f1;
239 burst_f2 <= reg_wp.burst_f2;
239 burst_f2 <= reg_wp.burst_f2;
240
240
241 run <= reg_wp.run;
241 run <= reg_wp.run;
242
242
243 addr_data_f0 <= reg_wp.addr_data_f0;
243 addr_data_f0 <= reg_wp.addr_data_f0;
244 addr_data_f1 <= reg_wp.addr_data_f1;
244 addr_data_f1 <= reg_wp.addr_data_f1;
245 addr_data_f2 <= reg_wp.addr_data_f2;
245 addr_data_f2 <= reg_wp.addr_data_f2;
246 addr_data_f3 <= reg_wp.addr_data_f3;
246 addr_data_f3 <= reg_wp.addr_data_f3;
247
247
248 start_date <= reg_wp.start_date;
248 start_date <= reg_wp.start_date;
249
249
250 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
250 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
251 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
251 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
252 BEGIN -- PROCESS lpp_dma_top
252 BEGIN -- PROCESS lpp_dma_top
253 IF HRESETn = '0' THEN -- asynchronous reset (active low)
253 IF HRESETn = '0' THEN -- asynchronous reset (active low)
254 reg_sp.config_active_interruption_onNewMatrix <= '0';
254 reg_sp.config_active_interruption_onNewMatrix <= '0';
255 reg_sp.config_active_interruption_onError <= '0';
255 reg_sp.config_active_interruption_onError <= '0';
256 reg_sp.status_ready_matrix_f0_0 <= '0';
256 reg_sp.status_ready_matrix_f0_0 <= '0';
257 reg_sp.status_ready_matrix_f0_1 <= '0';
257 reg_sp.status_ready_matrix_f0_1 <= '0';
258 reg_sp.status_ready_matrix_f1 <= '0';
258 reg_sp.status_ready_matrix_f1 <= '0';
259 reg_sp.status_ready_matrix_f2 <= '0';
259 reg_sp.status_ready_matrix_f2 <= '0';
260 reg_sp.status_error_anticipating_empty_fifo <= '0';
260 reg_sp.status_error_anticipating_empty_fifo <= '0';
261 reg_sp.status_error_bad_component_error <= '0';
261 reg_sp.status_error_bad_component_error <= '0';
262 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
262 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
263 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
263 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
264 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
264 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
265 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
265 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
266 prdata <= (OTHERS => '0');
266 prdata <= (OTHERS => '0');
267
267
268 apbo.pirq <= (OTHERS => '0');
268 apbo.pirq <= (OTHERS => '0');
269
269
270 status_full_ack <= (OTHERS => '0');
270 status_full_ack <= (OTHERS => '0');
271
271
272 reg_wp.data_shaping_BW <= '0';
272 reg_wp.data_shaping_BW <= '0';
273 reg_wp.data_shaping_SP0 <= '0';
273 reg_wp.data_shaping_SP0 <= '0';
274 reg_wp.data_shaping_SP1 <= '0';
274 reg_wp.data_shaping_SP1 <= '0';
275 reg_wp.data_shaping_R0 <= '0';
275 reg_wp.data_shaping_R0 <= '0';
276 reg_wp.data_shaping_R1 <= '0';
276 reg_wp.data_shaping_R1 <= '0';
277 reg_wp.enable_f0 <= '0';
277 reg_wp.enable_f0 <= '0';
278 reg_wp.enable_f1 <= '0';
278 reg_wp.enable_f1 <= '0';
279 reg_wp.enable_f2 <= '0';
279 reg_wp.enable_f2 <= '0';
280 reg_wp.enable_f3 <= '0';
280 reg_wp.enable_f3 <= '0';
281 reg_wp.burst_f0 <= '0';
281 reg_wp.burst_f0 <= '0';
282 reg_wp.burst_f1 <= '0';
282 reg_wp.burst_f1 <= '0';
283 reg_wp.burst_f2 <= '0';
283 reg_wp.burst_f2 <= '0';
284 reg_wp.run <= '0';
284 reg_wp.run <= '0';
285 reg_wp.addr_data_f0 <= (OTHERS => '0');
285 reg_wp.addr_data_f0 <= (OTHERS => '0');
286 reg_wp.addr_data_f1 <= (OTHERS => '0');
286 reg_wp.addr_data_f1 <= (OTHERS => '0');
287 reg_wp.addr_data_f2 <= (OTHERS => '0');
287 reg_wp.addr_data_f2 <= (OTHERS => '0');
288 reg_wp.addr_data_f3 <= (OTHERS => '0');
288 reg_wp.addr_data_f3 <= (OTHERS => '0');
289 reg_wp.status_full <= (OTHERS => '0');
289 reg_wp.status_full <= (OTHERS => '0');
290 reg_wp.status_full_err <= (OTHERS => '0');
290 reg_wp.status_full_err <= (OTHERS => '0');
291 reg_wp.status_new_err <= (OTHERS => '0');
291 reg_wp.status_new_err <= (OTHERS => '0');
292 reg_wp.delta_snapshot <= (OTHERS => '0');
292 reg_wp.delta_snapshot <= (OTHERS => '0');
293 reg_wp.delta_f0 <= (OTHERS => '0');
293 reg_wp.delta_f0 <= (OTHERS => '0');
294 reg_wp.delta_f0_2 <= (OTHERS => '0');
294 reg_wp.delta_f0_2 <= (OTHERS => '0');
295 reg_wp.delta_f1 <= (OTHERS => '0');
295 reg_wp.delta_f1 <= (OTHERS => '0');
296 reg_wp.delta_f2 <= (OTHERS => '0');
296 reg_wp.delta_f2 <= (OTHERS => '0');
297 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
297 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
298 reg_wp.nb_snapshot_param <= (OTHERS => '0');
298 reg_wp.nb_snapshot_param <= (OTHERS => '0');
299 reg_wp.start_date <= (OTHERS => '0');
299 reg_wp.start_date <= (OTHERS => '0');
300
300
301 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
301 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
302 status_full_ack <= (OTHERS => '0');
302 status_full_ack <= (OTHERS => '0');
303
303
304 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
304 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
305 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
305 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
306 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
306 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
307 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
307 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
308
308
309 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
309 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
310 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
310 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
311 all_status: FOR I IN 3 DOWNTO 0 LOOP
311 all_status: FOR I IN 3 DOWNTO 0 LOOP
312 reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
312 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
313 reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
313 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
314 reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
314 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
315 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
316 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
317 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
315 END LOOP all_status;
318 END LOOP all_status;
316
319
317 paddr := "000000";
320 paddr := "000000";
318 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
321 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
319 prdata <= (OTHERS => '0');
322 prdata <= (OTHERS => '0');
320 IF apbi.psel(pindex) = '1' THEN
323 IF apbi.psel(pindex) = '1' THEN
321 -- APB DMA READ --
324 -- APB DMA READ --
322 CASE paddr(7 DOWNTO 2) IS
325 CASE paddr(7 DOWNTO 2) IS
323 --
326 --
324 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
327 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
325 prdata(1) <= reg_sp.config_active_interruption_onError;
328 prdata(1) <= reg_sp.config_active_interruption_onError;
326 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
329 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
327 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
330 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
328 prdata(2) <= reg_sp.status_ready_matrix_f1;
331 prdata(2) <= reg_sp.status_ready_matrix_f1;
329 prdata(3) <= reg_sp.status_ready_matrix_f2;
332 prdata(3) <= reg_sp.status_ready_matrix_f2;
330 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
333 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
331 prdata(5) <= reg_sp.status_error_bad_component_error;
334 prdata(5) <= reg_sp.status_error_bad_component_error;
332 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
335 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
333 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
336 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
334 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
337 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
335 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
338 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
336 WHEN "000110" => prdata <= debug_reg;
339 WHEN "000110" => prdata <= debug_reg;
337 --
340 --
338 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
341 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
339 prdata(1) <= reg_wp.data_shaping_SP0;
342 prdata(1) <= reg_wp.data_shaping_SP0;
340 prdata(2) <= reg_wp.data_shaping_SP1;
343 prdata(2) <= reg_wp.data_shaping_SP1;
341 prdata(3) <= reg_wp.data_shaping_R0;
344 prdata(3) <= reg_wp.data_shaping_R0;
342 prdata(4) <= reg_wp.data_shaping_R1;
345 prdata(4) <= reg_wp.data_shaping_R1;
343 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
346 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
344 prdata(1) <= reg_wp.enable_f1;
347 prdata(1) <= reg_wp.enable_f1;
345 prdata(2) <= reg_wp.enable_f2;
348 prdata(2) <= reg_wp.enable_f2;
346 prdata(3) <= reg_wp.enable_f3;
349 prdata(3) <= reg_wp.enable_f3;
347 prdata(4) <= reg_wp.burst_f0;
350 prdata(4) <= reg_wp.burst_f0;
348 prdata(5) <= reg_wp.burst_f1;
351 prdata(5) <= reg_wp.burst_f1;
349 prdata(6) <= reg_wp.burst_f2;
352 prdata(6) <= reg_wp.burst_f2;
350 prdata(7) <= reg_wp.run;
353 prdata(7) <= reg_wp.run;
351 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
354 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
352 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
355 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
353 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
356 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
354 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
357 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
355 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
358 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
356 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
359 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
357 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
360 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
358 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
361 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
359 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
362 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
360 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
363 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
361 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
364 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
362 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
365 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
363 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
366 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
364 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
367 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
365 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
368 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
366 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
369 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
367 ----------------------------------------------------
370 ----------------------------------------------------
368 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
371 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
369 WHEN OTHERS => NULL;
372 WHEN OTHERS => NULL;
370 END CASE;
373 END CASE;
371 IF (apbi.pwrite AND apbi.penable) = '1' THEN
374 IF (apbi.pwrite AND apbi.penable) = '1' THEN
372 -- APB DMA WRITE --
375 -- APB DMA WRITE --
373 CASE paddr(7 DOWNTO 2) IS
376 CASE paddr(7 DOWNTO 2) IS
374 --
377 --
375 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
378 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
376 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
379 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
377 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
380 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
378 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
381 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
379 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
382 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
380 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
383 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
381 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
384 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
382 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
385 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
383 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
386 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
384 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
387 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
385 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
388 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
386 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
389 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
387 --
390 --
388 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
391 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
389 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
392 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
390 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
393 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
391 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
394 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
392 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
395 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
393 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
396 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
394 reg_wp.enable_f1 <= apbi.pwdata(1);
397 reg_wp.enable_f1 <= apbi.pwdata(1);
395 reg_wp.enable_f2 <= apbi.pwdata(2);
398 reg_wp.enable_f2 <= apbi.pwdata(2);
396 reg_wp.enable_f3 <= apbi.pwdata(3);
399 reg_wp.enable_f3 <= apbi.pwdata(3);
397 reg_wp.burst_f0 <= apbi.pwdata(4);
400 reg_wp.burst_f0 <= apbi.pwdata(4);
398 reg_wp.burst_f1 <= apbi.pwdata(5);
401 reg_wp.burst_f1 <= apbi.pwdata(5);
399 reg_wp.burst_f2 <= apbi.pwdata(6);
402 reg_wp.burst_f2 <= apbi.pwdata(6);
400 reg_wp.run <= apbi.pwdata(7);
403 reg_wp.run <= apbi.pwdata(7);
401 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
404 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
402 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
405 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
403 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
406 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
404 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
407 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
405 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
408 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
406 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
409 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
407 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
410 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
408 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
411 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
409 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
412 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
410 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
413 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
411 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
414 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
412 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
415 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
413 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
416 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
414 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
417 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
415 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
418 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
416 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
419 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
417 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
420 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
418 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
421 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
419 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
422 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
420 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
423 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
421 --
424 --
422 WHEN OTHERS => NULL;
425 WHEN OTHERS => NULL;
423 END CASE;
426 END CASE;
424 END IF;
427 END IF;
425 END IF;
428 END IF;
426
429
427 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
430 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
428 ready_matrix_f0_1 OR
431 ready_matrix_f0_1 OR
429 ready_matrix_f1 OR
432 ready_matrix_f1 OR
430 ready_matrix_f2)
433 ready_matrix_f2)
431 )
434 )
432 OR
435 OR
433 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
436 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
434 error_bad_component_error)
437 error_bad_component_error)
435 ));
438 ));
436
439
437 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
440 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
438 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
441 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
439 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
442 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
440 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
443 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
441 -- );
444 -- );
442 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
445 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
443
446
444 END IF;
447 END IF;
445 END PROCESS lpp_lfr_apbreg;
448 END PROCESS lpp_lfr_apbreg;
446
449
447 apbo.pindex <= pindex;
450 apbo.pindex <= pindex;
448 apbo.pconfig <= pconfig;
451 apbo.pconfig <= pconfig;
449 apbo.prdata <= prdata;
452 apbo.prdata <= prdata;
450
453
451 -----------------------------------------------------------------------------
454 -----------------------------------------------------------------------------
452 -- IRQ
455 -- IRQ
453 -----------------------------------------------------------------------------
456 -----------------------------------------------------------------------------
454 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
457 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
455
458
456 PROCESS (HCLK, HRESETn)
459 PROCESS (HCLK, HRESETn)
457 BEGIN -- PROCESS
460 BEGIN -- PROCESS
458 IF HRESETn = '0' THEN -- asynchronous reset (active low)
461 IF HRESETn = '0' THEN -- asynchronous reset (active low)
459 irq_wfp_reg <= (OTHERS => '0');
462 irq_wfp_reg <= (OTHERS => '0');
460 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
463 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
461 irq_wfp_reg <= irq_wfp_reg_s;
464 irq_wfp_reg <= irq_wfp_reg_s;
462 END IF;
465 END IF;
463 END PROCESS;
466 END PROCESS;
464
467
465 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
468 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
466 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
469 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
467 END GENERATE all_irq_wfp;
470 END GENERATE all_irq_wfp;
468
471
469 irq_wfp_ZERO <= (OTHERS => '0');
472 irq_wfp_ZERO <= (OTHERS => '0');
470 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
473 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
471
474
472 END beh;
475 END beh;
Show file before | Show file after | Hide comments
@@ -1,202 +1,212
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 hindex : INTEGER);
19 hindex : INTEGER);
20 PORT (
20 PORT (
21 clk : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 AHB_Master_In : IN AHB_Mst_In_Type;
29 AHB_Master_In : IN AHB_Mst_In_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 END COMPONENT;
50 END COMPONENT;
51
51
52 COMPONENT lpp_lfr_filter
52 COMPONENT lpp_lfr_filter
53 GENERIC (
53 GENERIC (
54 Mem_use : INTEGER);
54 Mem_use : INTEGER);
55 PORT (
55 PORT (
56 sample : IN Samples(7 DOWNTO 0);
56 sample : IN Samples(7 DOWNTO 0);
57 sample_val : IN STD_LOGIC;
57 sample_val : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 END COMPONENT;
72 END COMPONENT;
73
73
74 COMPONENT lpp_lfr
74 COMPONENT lpp_lfr
75 GENERIC (
75 GENERIC (
76 Mem_use : INTEGER;
76 Mem_use : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
80 delta_vector_size : INTEGER;
80 delta_vector_size : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
82 pindex : INTEGER;
82 pindex : INTEGER;
83 paddr : INTEGER;
83 paddr : INTEGER;
84 pmask : INTEGER;
84 pmask : INTEGER;
85 pirq_ms : INTEGER;
85 pirq_ms : INTEGER;
86 pirq_wfp : INTEGER;
86 pirq_wfp : INTEGER;
87 hindex : INTEGER;
87 hindex : INTEGER;
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
89 );
89 );
90 PORT (
90 PORT (
91 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
93 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_B : IN Samples14v(2 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
95 sample_val : IN STD_LOGIC;
95 sample_val : IN STD_LOGIC;
96 apbi : IN apb_slv_in_type;
96 apbi : IN apb_slv_in_type;
97 apbo : OUT apb_slv_out_type;
97 apbo : OUT apb_slv_out_type;
98 ahbi : IN AHB_Mst_In_Type;
98 ahbi : IN AHB_Mst_In_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 data_shaping_BW : OUT STD_LOGIC);
102 data_shaping_BW : OUT STD_LOGIC;
103
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC );
103 END COMPONENT;
113 END COMPONENT;
104
114
105 COMPONENT lpp_lfr_apbreg
115 COMPONENT lpp_lfr_apbreg
106 GENERIC (
116 GENERIC (
107 nb_data_by_buffer_size : INTEGER;
117 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
118 nb_word_by_buffer_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
119 nb_snapshot_param_size : INTEGER;
110 delta_vector_size : INTEGER;
120 delta_vector_size : INTEGER;
111 delta_vector_size_f0_2 : INTEGER;
121 delta_vector_size_f0_2 : INTEGER;
112 pindex : INTEGER;
122 pindex : INTEGER;
113 paddr : INTEGER;
123 paddr : INTEGER;
114 pmask : INTEGER;
124 pmask : INTEGER;
115 pirq_ms : INTEGER;
125 pirq_ms : INTEGER;
116 pirq_wfp : INTEGER;
126 pirq_wfp : INTEGER;
117 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
127 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
118 PORT (
128 PORT (
119 HCLK : IN STD_ULOGIC;
129 HCLK : IN STD_ULOGIC;
120 HRESETn : IN STD_ULOGIC;
130 HRESETn : IN STD_ULOGIC;
121 apbi : IN apb_slv_in_type;
131 apbi : IN apb_slv_in_type;
122 apbo : OUT apb_slv_out_type;
132 apbo : OUT apb_slv_out_type;
123 ready_matrix_f0_0 : IN STD_LOGIC;
133 ready_matrix_f0_0 : IN STD_LOGIC;
124 ready_matrix_f0_1 : IN STD_LOGIC;
134 ready_matrix_f0_1 : IN STD_LOGIC;
125 ready_matrix_f1 : IN STD_LOGIC;
135 ready_matrix_f1 : IN STD_LOGIC;
126 ready_matrix_f2 : IN STD_LOGIC;
136 ready_matrix_f2 : IN STD_LOGIC;
127 error_anticipating_empty_fifo : IN STD_LOGIC;
137 error_anticipating_empty_fifo : IN STD_LOGIC;
128 error_bad_component_error : IN STD_LOGIC;
138 error_bad_component_error : IN STD_LOGIC;
129 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 status_ready_matrix_f0_0 : OUT STD_LOGIC;
140 status_ready_matrix_f0_0 : OUT STD_LOGIC;
131 status_ready_matrix_f0_1 : OUT STD_LOGIC;
141 status_ready_matrix_f0_1 : OUT STD_LOGIC;
132 status_ready_matrix_f1 : OUT STD_LOGIC;
142 status_ready_matrix_f1 : OUT STD_LOGIC;
133 status_ready_matrix_f2 : OUT STD_LOGIC;
143 status_ready_matrix_f2 : OUT STD_LOGIC;
134 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
144 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
135 status_error_bad_component_error : OUT STD_LOGIC;
145 status_error_bad_component_error : OUT STD_LOGIC;
136 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
146 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
137 config_active_interruption_onError : OUT STD_LOGIC;
147 config_active_interruption_onError : OUT STD_LOGIC;
138 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
152 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
143 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
153 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
144 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
154 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
145 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
155 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
146 data_shaping_BW : OUT STD_LOGIC;
156 data_shaping_BW : OUT STD_LOGIC;
147 data_shaping_SP0 : OUT STD_LOGIC;
157 data_shaping_SP0 : OUT STD_LOGIC;
148 data_shaping_SP1 : OUT STD_LOGIC;
158 data_shaping_SP1 : OUT STD_LOGIC;
149 data_shaping_R0 : OUT STD_LOGIC;
159 data_shaping_R0 : OUT STD_LOGIC;
150 data_shaping_R1 : OUT STD_LOGIC;
160 data_shaping_R1 : OUT STD_LOGIC;
151 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
152 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
153 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
154 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
155 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
156 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
166 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
157 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
167 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
158 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
168 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
159 enable_f0 : OUT STD_LOGIC;
169 enable_f0 : OUT STD_LOGIC;
160 enable_f1 : OUT STD_LOGIC;
170 enable_f1 : OUT STD_LOGIC;
161 enable_f2 : OUT STD_LOGIC;
171 enable_f2 : OUT STD_LOGIC;
162 enable_f3 : OUT STD_LOGIC;
172 enable_f3 : OUT STD_LOGIC;
163 burst_f0 : OUT STD_LOGIC;
173 burst_f0 : OUT STD_LOGIC;
164 burst_f1 : OUT STD_LOGIC;
174 burst_f1 : OUT STD_LOGIC;
165 burst_f2 : OUT STD_LOGIC;
175 burst_f2 : OUT STD_LOGIC;
166 run : OUT STD_LOGIC;
176 run : OUT STD_LOGIC;
167 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
177 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
171 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0));
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0));
172 END COMPONENT;
182 END COMPONENT;
173
183
174 COMPONENT lpp_top_ms
184 COMPONENT lpp_top_ms
175 GENERIC (
185 GENERIC (
176 Mem_use : INTEGER;
186 Mem_use : INTEGER;
177 nb_burst_available_size : INTEGER;
187 nb_burst_available_size : INTEGER;
178 nb_snapshot_param_size : INTEGER;
188 nb_snapshot_param_size : INTEGER;
179 delta_snapshot_size : INTEGER;
189 delta_snapshot_size : INTEGER;
180 delta_f2_f0_size : INTEGER;
190 delta_f2_f0_size : INTEGER;
181 delta_f2_f1_size : INTEGER;
191 delta_f2_f1_size : INTEGER;
182 pindex : INTEGER;
192 pindex : INTEGER;
183 paddr : INTEGER;
193 paddr : INTEGER;
184 pmask : INTEGER;
194 pmask : INTEGER;
185 pirq_ms : INTEGER;
195 pirq_ms : INTEGER;
186 pirq_wfp : INTEGER;
196 pirq_wfp : INTEGER;
187 hindex_wfp : INTEGER;
197 hindex_wfp : INTEGER;
188 hindex_ms : INTEGER);
198 hindex_ms : INTEGER);
189 PORT (
199 PORT (
190 clk : IN STD_LOGIC;
200 clk : IN STD_LOGIC;
191 rstn : IN STD_LOGIC;
201 rstn : IN STD_LOGIC;
192 sample_B : IN Samples14v(2 DOWNTO 0);
202 sample_B : IN Samples14v(2 DOWNTO 0);
193 sample_E : IN Samples14v(4 DOWNTO 0);
203 sample_E : IN Samples14v(4 DOWNTO 0);
194 sample_val : IN STD_LOGIC;
204 sample_val : IN STD_LOGIC;
195 apbi : IN apb_slv_in_type;
205 apbi : IN apb_slv_in_type;
196 apbo : OUT apb_slv_out_type;
206 apbo : OUT apb_slv_out_type;
197 ahbi_ms : IN AHB_Mst_In_Type;
207 ahbi_ms : IN AHB_Mst_In_Type;
198 ahbo_ms : OUT AHB_Mst_Out_Type;
208 ahbo_ms : OUT AHB_Mst_Out_Type;
199 data_shaping_BW : OUT STD_LOGIC);
209 data_shaping_BW : OUT STD_LOGIC);
200 END COMPONENT;
210 END COMPONENT;
201
211
202 END lpp_lfr_pkg;
212 END lpp_lfr_pkg;
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@@ -1,436 +1,457
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35
35
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 ENTITY lpp_waveform IS
39 ENTITY lpp_waveform IS
40
40
41 GENERIC (
41 GENERIC (
42 tech : INTEGER := inferred;
42 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
43 data_size : INTEGER := 96; --16*6
44 nb_data_by_buffer_size : INTEGER := 11;
44 nb_data_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
47 delta_vector_size : INTEGER := 20;
47 delta_vector_size : INTEGER := 20;
48 delta_vector_size_f0_2 : INTEGER := 3);
48 delta_vector_size_f0_2 : INTEGER := 3);
49
49
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53
53
54 ---- AMBA AHB Master Interface
54 ---- AMBA AHB Master Interface
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57
57
58 --config
58 --config
59 reg_run : IN STD_LOGIC;
59 reg_run : IN STD_LOGIC;
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66
66
67 enable_f0 : IN STD_LOGIC;
67 enable_f0 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
71
71
72 burst_f0 : IN STD_LOGIC;
72 burst_f0 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
75
75
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
84 -- INPUT
84 -- INPUT
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87
87
88 --f0
88 --f0
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 data_f0_in_valid : IN STD_LOGIC;
90 data_f0_in_valid : IN STD_LOGIC;
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 --f1
92 --f1
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data_f1_in_valid : IN STD_LOGIC;
94 data_f1_in_valid : IN STD_LOGIC;
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 --f2
96 --f2
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data_f2_in_valid : IN STD_LOGIC;
98 data_f2_in_valid : IN STD_LOGIC;
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 --f3
100 --f3
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 data_f3_in_valid : IN STD_LOGIC;
102 data_f3_in_valid : IN STD_LOGIC;
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104
104
105 ---------------------------------------------------------------------------
105 ---------------------------------------------------------------------------
106 -- OUTPUT
106 -- OUTPUT
107 --f0
107 --f0
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_valid : OUT STD_LOGIC;
110 data_f0_data_out_valid : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
113 --f1
113 --f1
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out_valid : OUT STD_LOGIC;
116 data_f1_data_out_valid : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
119 --f2
119 --f2
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out_valid : OUT STD_LOGIC;
122 data_f2_data_out_valid : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
125 --f3
125 --f3
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out_valid : OUT STD_LOGIC;
128 data_f3_data_out_valid : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC
130 data_f3_data_out_ren : IN STD_LOGIC;
131
131
132
132 --debug
133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 debug_f0_data_valid : OUT STD_LOGIC;
135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 debug_f1_data_valid : OUT STD_LOGIC;
137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 debug_f2_data_valid : OUT STD_LOGIC;
139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 debug_f3_data_valid : OUT STD_LOGIC
133 );
141 );
134
142
135 END lpp_waveform;
143 END lpp_waveform;
136
144
137 ARCHITECTURE beh OF lpp_waveform IS
145 ARCHITECTURE beh OF lpp_waveform IS
138 SIGNAL start_snapshot_f0 : STD_LOGIC;
146 SIGNAL start_snapshot_f0 : STD_LOGIC;
139 SIGNAL start_snapshot_f1 : STD_LOGIC;
147 SIGNAL start_snapshot_f1 : STD_LOGIC;
140 SIGNAL start_snapshot_f2 : STD_LOGIC;
148 SIGNAL start_snapshot_f2 : STD_LOGIC;
141
149
142 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
151 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
145 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146
154
147 SIGNAL data_f0_out_valid : STD_LOGIC;
155 SIGNAL data_f0_out_valid : STD_LOGIC;
148 SIGNAL data_f1_out_valid : STD_LOGIC;
156 SIGNAL data_f1_out_valid : STD_LOGIC;
149 SIGNAL data_f2_out_valid : STD_LOGIC;
157 SIGNAL data_f2_out_valid : STD_LOGIC;
150 SIGNAL data_f3_out_valid : STD_LOGIC;
158 SIGNAL data_f3_out_valid : STD_LOGIC;
151 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
159 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
152 --
160 --
153 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 --
174 --
167 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 --
179 --
172 SIGNAL run : STD_LOGIC;
180 SIGNAL run : STD_LOGIC;
173 --
181 --
174 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
182 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
175 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
176 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
177 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
178 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
186 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180
188
181 BEGIN -- beh
189 BEGIN -- beh
182
190
183 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
191 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
184 GENERIC MAP (
192 GENERIC MAP (
185 delta_vector_size => delta_vector_size,
193 delta_vector_size => delta_vector_size,
186 delta_vector_size_f0_2 => delta_vector_size_f0_2
194 delta_vector_size_f0_2 => delta_vector_size_f0_2
187 )
195 )
188 PORT MAP (
196 PORT MAP (
189 clk => clk,
197 clk => clk,
190 rstn => rstn,
198 rstn => rstn,
191 reg_run => reg_run,
199 reg_run => reg_run,
192 reg_start_date => reg_start_date,
200 reg_start_date => reg_start_date,
193 reg_delta_snapshot => reg_delta_snapshot,
201 reg_delta_snapshot => reg_delta_snapshot,
194 reg_delta_f0 => reg_delta_f0,
202 reg_delta_f0 => reg_delta_f0,
195 reg_delta_f0_2 => reg_delta_f0_2,
203 reg_delta_f0_2 => reg_delta_f0_2,
196 reg_delta_f1 => reg_delta_f1,
204 reg_delta_f1 => reg_delta_f1,
197 reg_delta_f2 => reg_delta_f2,
205 reg_delta_f2 => reg_delta_f2,
198 coarse_time => coarse_time(30 DOWNTO 0),
206 coarse_time => coarse_time(30 DOWNTO 0),
199 data_f0_valid => data_f0_in_valid,
207 data_f0_valid => data_f0_in_valid,
200 data_f2_valid => data_f2_in_valid,
208 data_f2_valid => data_f2_in_valid,
201 start_snapshot_f0 => start_snapshot_f0,
209 start_snapshot_f0 => start_snapshot_f0,
202 start_snapshot_f1 => start_snapshot_f1,
210 start_snapshot_f1 => start_snapshot_f1,
203 start_snapshot_f2 => start_snapshot_f2,
211 start_snapshot_f2 => start_snapshot_f2,
204 wfp_on => run);
212 wfp_on => run);
205
213
206 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
214 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
207 GENERIC MAP (
215 GENERIC MAP (
208 data_size => data_size,
216 data_size => data_size,
209 nb_snapshot_param_size => nb_snapshot_param_size)
217 nb_snapshot_param_size => nb_snapshot_param_size)
210 PORT MAP (
218 PORT MAP (
211 clk => clk,
219 clk => clk,
212 rstn => rstn,
220 rstn => rstn,
213 run => run,
221 run => run,
214 enable => enable_f0,
222 enable => enable_f0,
215 burst_enable => burst_f0,
223 burst_enable => burst_f0,
216 nb_snapshot_param => nb_snapshot_param,
224 nb_snapshot_param => nb_snapshot_param,
217 start_snapshot => start_snapshot_f0,
225 start_snapshot => start_snapshot_f0,
218 data_in => data_f0_in,
226 data_in => data_f0_in,
219 data_in_valid => data_f0_in_valid,
227 data_in_valid => data_f0_in_valid,
220 data_out => data_f0_out,
228 data_out => data_f0_out,
221 data_out_valid => data_f0_out_valid);
229 data_out_valid => data_f0_out_valid);
222
230
223 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
231 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
224
232
225 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
233 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
226 GENERIC MAP (
234 GENERIC MAP (
227 data_size => data_size,
235 data_size => data_size,
228 nb_snapshot_param_size => nb_snapshot_param_size+1)
236 nb_snapshot_param_size => nb_snapshot_param_size+1)
229 PORT MAP (
237 PORT MAP (
230 clk => clk,
238 clk => clk,
231 rstn => rstn,
239 rstn => rstn,
232 run => run,
240 run => run,
233 enable => enable_f1,
241 enable => enable_f1,
234 burst_enable => burst_f1,
242 burst_enable => burst_f1,
235 nb_snapshot_param => nb_snapshot_param_more_one,
243 nb_snapshot_param => nb_snapshot_param_more_one,
236 start_snapshot => start_snapshot_f1,
244 start_snapshot => start_snapshot_f1,
237 data_in => data_f1_in,
245 data_in => data_f1_in,
238 data_in_valid => data_f1_in_valid,
246 data_in_valid => data_f1_in_valid,
239 data_out => data_f1_out,
247 data_out => data_f1_out,
240 data_out_valid => data_f1_out_valid);
248 data_out_valid => data_f1_out_valid);
241
249
242 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
250 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
243 GENERIC MAP (
251 GENERIC MAP (
244 data_size => data_size,
252 data_size => data_size,
245 nb_snapshot_param_size => nb_snapshot_param_size+1)
253 nb_snapshot_param_size => nb_snapshot_param_size+1)
246 PORT MAP (
254 PORT MAP (
247 clk => clk,
255 clk => clk,
248 rstn => rstn,
256 rstn => rstn,
249 run => run,
257 run => run,
250 enable => enable_f2,
258 enable => enable_f2,
251 burst_enable => burst_f2,
259 burst_enable => burst_f2,
252 nb_snapshot_param => nb_snapshot_param_more_one,
260 nb_snapshot_param => nb_snapshot_param_more_one,
253 start_snapshot => start_snapshot_f2,
261 start_snapshot => start_snapshot_f2,
254 data_in => data_f2_in,
262 data_in => data_f2_in,
255 data_in_valid => data_f2_in_valid,
263 data_in_valid => data_f2_in_valid,
256 data_out => data_f2_out,
264 data_out => data_f2_out,
257 data_out_valid => data_f2_out_valid);
265 data_out_valid => data_f2_out_valid);
258
266
259 lpp_waveform_burst_f3 : lpp_waveform_burst
267 lpp_waveform_burst_f3 : lpp_waveform_burst
260 GENERIC MAP (
268 GENERIC MAP (
261 data_size => data_size)
269 data_size => data_size)
262 PORT MAP (
270 PORT MAP (
263 clk => clk,
271 clk => clk,
264 rstn => rstn,
272 rstn => rstn,
265 run => run,
273 run => run,
266 enable => enable_f3,
274 enable => enable_f3,
267 data_in => data_f3_in,
275 data_in => data_f3_in,
268 data_in_valid => data_f3_in_valid,
276 data_in_valid => data_f3_in_valid,
269 data_out => data_f3_out,
277 data_out => data_f3_out,
270 data_out_valid => data_f3_out_valid);
278 data_out_valid => data_f3_out_valid);
271
279
280 -----------------------------------------------------------------------------
281 -- DEBUG
282 debug_f0_data_valid <= data_f0_out_valid;
283 debug_f0_data <= data_f0_out;
284 debug_f1_data_valid <= data_f1_out_valid;
285 debug_f1_data <= data_f1_out;
286 debug_f2_data_valid <= data_f2_out_valid;
287 debug_f2_data <= data_f2_out;
288 debug_f3_data_valid <= data_f3_out_valid;
289 debug_f3_data <= data_f3_out;
290 -----------------------------------------------------------------------------
291
272 PROCESS (clk, rstn)
292 PROCESS (clk, rstn)
273 BEGIN -- PROCESS
293 BEGIN -- PROCESS
274 IF rstn = '0' THEN -- asynchronous reset (active low)
294 IF rstn = '0' THEN -- asynchronous reset (active low)
275 time_reg1 <= (OTHERS => '0');
295 time_reg1 <= (OTHERS => '0');
276 time_reg2 <= (OTHERS => '0');
296 time_reg2 <= (OTHERS => '0');
277 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
297 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
278 time_reg1 <= fine_time & coarse_time;
298 time_reg1 <= fine_time & coarse_time;
279 time_reg2 <= time_reg1;
299 time_reg2 <= time_reg1;
280 END IF;
300 END IF;
281 END PROCESS;
301 END PROCESS;
282
302
283 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
303 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
284 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
304 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
285 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
305 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
286 PORT MAP (
306 PORT MAP (
287 HCLK => clk,
307 HCLK => clk,
288 HRESETn => rstn,
308 HRESETn => rstn,
289 run => run,
309 run => run,
290 valid_in => valid_in(I),
310 valid_in => valid_in(I),
291 ack_in => valid_ack(I),
311 ack_in => valid_ack(I),
292 time_in => time_reg2, -- Todo
312 time_in => time_reg2, -- Todo
293 valid_out => valid_out(I),
313 valid_out => valid_out(I),
294 time_out => time_out(I), -- Todo
314 time_out => time_out(I), -- Todo
295 error => status_new_err(I));
315 error => status_new_err(I));
296 END GENERATE all_input_valid;
316 END GENERATE all_input_valid;
297
317
298 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
318 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
299 data_out(0,I) <= data_f0_out(I);
319 data_out(0,I) <= data_f0_out(I);
300 data_out(1,I) <= data_f1_out(I);
320 data_out(1,I) <= data_f1_out(I);
301 data_out(2,I) <= data_f2_out(I);
321 data_out(2,I) <= data_f2_out(I);
302 data_out(3,I) <= data_f3_out(I);
322 data_out(3,I) <= data_f3_out(I);
303 END GENERATE all_bit_of_data_out;
323 END GENERATE all_bit_of_data_out;
304
324
305 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
325 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
306 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
326 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
307 time_out_2(J,I) <= time_out(J)(I);
327 time_out_2(J,I) <= time_out(J)(I);
308 END GENERATE all_sample_of_time_out;
328 END GENERATE all_sample_of_time_out;
309 END GENERATE all_bit_of_time_out;
329 END GENERATE all_bit_of_time_out;
310
330
311 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
331 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
312 GENERIC MAP (tech => tech,
332 GENERIC MAP (tech => tech,
313 nb_data_by_buffer_size =>nb_data_by_buffer_size)
333 nb_data_by_buffer_size =>nb_data_by_buffer_size)
314 PORT MAP (
334 PORT MAP (
315 clk => clk,
335 clk => clk,
316 rstn => rstn,
336 rstn => rstn,
317 run => run,
337 run => run,
318 nb_data_by_buffer => nb_data_by_buffer,
338 nb_data_by_buffer => nb_data_by_buffer,
319 data_in_valid => valid_out,
339 data_in_valid => valid_out,
320 data_in_ack => valid_ack,
340 data_in_ack => valid_ack,
321 data_in => data_out,
341 data_in => data_out,
322 time_in => time_out_2,
342 time_in => time_out_2,
323
343
324 data_out => wdata,
344 data_out => wdata,
325 data_out_wen => data_wen,
345 data_out_wen => data_wen,
346 full_almost => full_almost,
326 full => full);
347 full => full);
327
348
328 lpp_waveform_fifo_1 : lpp_waveform_fifo
349 lpp_waveform_fifo_1 : lpp_waveform_fifo
329 GENERIC MAP (tech => tech)
350 GENERIC MAP (tech => tech)
330 PORT MAP (
351 PORT MAP (
331 clk => clk,
352 clk => clk,
332 rstn => rstn,
353 rstn => rstn,
333 run => run,
354 run => run,
334
355
335 empty => empty,
356 empty => empty,
336 empty_almost => empty_almost,
357 empty_almost => empty_almost,
337
358
338 data_ren => data_ren,
359 data_ren => data_ren,
339 rdata => rdata,
360 rdata => rdata,
340
361
341
362
342 full_almost => full_almost,
363 full_almost => full_almost,
343 full => full,
364 full => full,
344 data_wen => data_wen,
365 data_wen => data_wen,
345 wdata => wdata);
366 wdata => wdata);
346
367
347 data_f0_data_out <= rdata;
368 data_f0_data_out <= rdata;
348 data_f1_data_out <= rdata;
369 data_f1_data_out <= rdata;
349 data_f2_data_out <= rdata;
370 data_f2_data_out <= rdata;
350 data_f3_data_out <= rdata;
371 data_f3_data_out <= rdata;
351
372
352 --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency
373 --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency
353 -- GENERIC MAP (
374 -- GENERIC MAP (
354 -- tech => tech)
375 -- tech => tech)
355 -- PORT MAP (
376 -- PORT MAP (
356 -- clk => clk,
377 -- clk => clk,
357 -- rstn => rstn,
378 -- rstn => rstn,
358 -- run => run,
379 -- run => run,
359
380
360 -- empty_almost => empty_almost,
381 -- empty_almost => empty_almost,
361 -- empty => empty,
382 -- empty => empty,
362 -- data_ren => data_ren,
383 -- data_ren => data_ren,
363
384
364 -- rdata_0 => data_f0_data_out,
385 -- rdata_0 => data_f0_data_out,
365 -- rdata_1 => data_f1_data_out,
386 -- rdata_1 => data_f1_data_out,
366 -- rdata_2 => data_f2_data_out,
387 -- rdata_2 => data_f2_data_out,
367 -- rdata_3 => data_f3_data_out,
388 -- rdata_3 => data_f3_data_out,
368
389
369 -- full_almost => full_almost,
390 -- full_almost => full_almost,
370 -- full => full,
391 -- full => full,
371 -- data_wen => data_wen,
392 -- data_wen => data_wen,
372 -- wdata => wdata);
393 -- wdata => wdata);
373
394
374
395
375
396
376
397
377 data_ren <= data_f3_data_out_ren &
398 data_ren <= data_f3_data_out_ren &
378 data_f2_data_out_ren &
399 data_f2_data_out_ren &
379 data_f1_data_out_ren &
400 data_f1_data_out_ren &
380 data_f0_data_out_ren;
401 data_f0_data_out_ren;
381
402
382 -----------------------------------------------------------------------------
403 -----------------------------------------------------------------------------
383 -- TODO : set the alterance : time, data, data, .....
404 -- TODO : set the alterance : time, data, data, .....
384 -----------------------------------------------------------------------------
405 -----------------------------------------------------------------------------
385 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
406 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
386 GENERIC MAP (
407 GENERIC MAP (
387 nb_data_by_buffer_size => nb_word_by_buffer_size)
408 nb_data_by_buffer_size => nb_word_by_buffer_size)
388 PORT MAP (
409 PORT MAP (
389 clk => clk,
410 clk => clk,
390 rstn => rstn,
411 rstn => rstn,
391 run => run,
412 run => run,
392
413
393 -------------------------------------------------------------------------
414 -------------------------------------------------------------------------
394 -- CONFIG
415 -- CONFIG
395 -------------------------------------------------------------------------
416 -------------------------------------------------------------------------
396 nb_data_by_buffer => nb_word_by_buffer,
417 nb_data_by_buffer => nb_word_by_buffer,
397
418
398 addr_data_f0 => addr_data_f0,
419 addr_data_f0 => addr_data_f0,
399 addr_data_f1 => addr_data_f1,
420 addr_data_f1 => addr_data_f1,
400 addr_data_f2 => addr_data_f2,
421 addr_data_f2 => addr_data_f2,
401 addr_data_f3 => addr_data_f3,
422 addr_data_f3 => addr_data_f3,
402 -------------------------------------------------------------------------
423 -------------------------------------------------------------------------
403 -- CTRL
424 -- CTRL
404 -------------------------------------------------------------------------
425 -------------------------------------------------------------------------
405 -- IN
426 -- IN
406 empty => empty,
427 empty => empty,
407 empty_almost => empty_almost,
428 empty_almost => empty_almost,
408 data_ren => data_ren,
429 data_ren => data_ren,
409
430
410 -------------------------------------------------------------------------
431 -------------------------------------------------------------------------
411 -- STATUS
432 -- STATUS
412 -------------------------------------------------------------------------
433 -------------------------------------------------------------------------
413 status_full => status_full,
434 status_full => status_full,
414 status_full_ack => status_full_ack,
435 status_full_ack => status_full_ack,
415 status_full_err => status_full_err,
436 status_full_err => status_full_err,
416
437
417 -------------------------------------------------------------------------
438 -------------------------------------------------------------------------
418 -- ADDR DATA OUT
439 -- ADDR DATA OUT
419 -------------------------------------------------------------------------
440 -------------------------------------------------------------------------
420 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
441 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
421 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
442 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
422 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
443 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
423 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
444 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
424
445
425 data_f0_data_out_valid => data_f0_data_out_valid,
446 data_f0_data_out_valid => data_f0_data_out_valid,
426 data_f1_data_out_valid => data_f1_data_out_valid,
447 data_f1_data_out_valid => data_f1_data_out_valid,
427 data_f2_data_out_valid => data_f2_data_out_valid,
448 data_f2_data_out_valid => data_f2_data_out_valid,
428 data_f3_data_out_valid => data_f3_data_out_valid,
449 data_f3_data_out_valid => data_f3_data_out_valid,
429
450
430 data_f0_addr_out => data_f0_addr_out,
451 data_f0_addr_out => data_f0_addr_out,
431 data_f1_addr_out => data_f1_addr_out,
452 data_f1_addr_out => data_f1_addr_out,
432 data_f2_addr_out => data_f2_addr_out,
453 data_f2_addr_out => data_f2_addr_out,
433 data_f3_addr_out => data_f3_addr_out
454 data_f3_addr_out => data_f3_addr_out
434 );
455 );
435
456
436 END beh;
457 END beh;
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@@ -1,297 +1,394
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25
25
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY lpp_waveform_fifo_arbiter IS
30 ENTITY lpp_waveform_fifo_arbiter IS
31 GENERIC(
31 GENERIC(
32 tech : INTEGER := 0;
32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER
33 nb_data_by_buffer_size : INTEGER
34 );
34 );
35 PORT(
35 PORT(
36 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- SNAPSHOT INTERFACE (INPUT)
42 -- SNAPSHOT INTERFACE (INPUT)
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48
48
49 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
50 -- FIFO INTERFACE (OUTPUT)
50 -- FIFO INTERFACE (OUTPUT)
51 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
54 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
55 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
55
56
56 );
57 );
57 END ENTITY;
58 END ENTITY;
58
59
59
60
60 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
61 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
62 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
63 SIGNAL state : state_type_fifo_arbiter;
64
61 -----------------------------------------------------------------------------
65 -----------------------------------------------------------------------------
62 -- DATA MUX
66 -- DATA MUX
63 -----------------------------------------------------------------------------
67 -----------------------------------------------------------------------------
64 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
68 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
65 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
69 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
66 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
67 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
68 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
72 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
69 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
73 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
70 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
74 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
71 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
75 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
72 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
73 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
77 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
74
78
75 -----------------------------------------------------------------------------
79 -----------------------------------------------------------------------------
76 -- RR and SELECTION
80 -- RR and SELECTION
77 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
78 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
82 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
79 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
83 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 SIGNAL sel_reg : STD_LOGIC;
86 SIGNAL sel_ack : STD_LOGIC;
80 SIGNAL no_sel : STD_LOGIC;
87 SIGNAL no_sel : STD_LOGIC;
81
88
82 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
83 -- REG
90 -- REG
84 -----------------------------------------------------------------------------
91 -----------------------------------------------------------------------------
85 SIGNAL count_enable : STD_LOGIC;
92 SIGNAL count_enable : STD_LOGIC;
86 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
93 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
87 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
94 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
88
95
89 SIGNAL shift_data_enable : STD_LOGIC;
96 --SIGNAL shift_data_enable : STD_LOGIC;
90 SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
97 --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
92
99
93 SIGNAL shift_time_enable : STD_LOGIC;
100 --SIGNAL shift_time_enable : STD_LOGIC;
94 SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
101 --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
95 SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
96
103
97 BEGIN
104 BEGIN
98
105
99 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
100 -- CONTROL
107 -- CONTROL
101 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
102 PROCESS (clk, rstn)
109 PROCESS (clk, rstn)
103 BEGIN -- PROCESS
110 BEGIN -- PROCESS
104 IF rstn = '0' THEN -- asynchronous reset (active low)
111 IF rstn = '0' THEN -- asynchronous reset (active low)
105 count_enable <= '0';
112 count_enable <= '0';
106 shift_time_enable <= '0';
107 shift_data_enable <= '0';
108 data_in_ack <= (OTHERS => '0');
113 data_in_ack <= (OTHERS => '0');
109 data_out_wen <= (OTHERS => '1');
114 data_out_wen <= (OTHERS => '1');
115 sel_ack <= '0';
116 state <= IDLE;
110 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
111 IF run = '0' OR no_sel = '1' THEN
112 count_enable <= '0';
118 count_enable <= '0';
113 shift_time_enable <= '0';
114 shift_data_enable <= '0';
115 data_in_ack <= (OTHERS => '0');
119 data_in_ack <= (OTHERS => '0');
116 data_out_wen <= (OTHERS => '1');
120 data_out_wen <= (OTHERS => '1');
121 sel_ack <= '0';
122 IF run = '0' THEN
123 state <= IDLE;
117 ELSE
124 ELSE
118 --COUNT
125 CASE state IS
119 IF shift_data_s = "10" THEN
126 WHEN IDLE =>
127 IF no_sel = '0' THEN
128 state <= TIME1;
129 END IF;
130 WHEN TIME1 =>
120 count_enable <= '1';
131 count_enable <= '1';
132 IF UNSIGNED(count) = 0 THEN
133 state <= TIME2;
134 data_out_wen <= NOT sel;
135 data_out <= data_sel(0);
121 ELSE
136 ELSE
122 count_enable <= '0';
137 state <= DATA1;
123 END IF;
138 END IF;
124 --DATA
139 WHEN TIME2 =>
125 IF shift_time_s = "10" THEN
140 data_out_wen <= NOT sel;
126 shift_data_enable <= '1';
141 data_out <= data_sel(1) ;
127 ELSE
142 state <= DATA1;
128 shift_data_enable <= '0';
143 WHEN DATA1 =>
129 END IF;
144 data_out_wen <= NOT sel;
145 data_out <= data_sel(2);
146 state <= DATA2;
147 WHEN DATA2 =>
148 data_out_wen <= NOT sel;
149 data_out <= data_sel(3);
150 state <= DATA3;
151 WHEN DATA3 =>
152 data_out_wen <= NOT sel;
153 data_out <= data_sel(4);
154 state <= LAST;
155 data_in_ack <= sel;
156 WHEN LAST =>
157 state <= IDLE;
158 sel_ack <= '1';
130
159
131 --TIME
160 WHEN OTHERS => NULL;
132 IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
161 END CASE;
133 shift_time_s = "00" OR
134 shift_time_s = "01"
135 THEN
136 shift_time_enable <= '1';
137 ELSE
138 shift_time_enable <= '0';
139 END IF;
140
141 --ACK
142 IF shift_data_s = "10" THEN
143 data_in_ack <= sel;
144 ELSE
145 data_in_ack <= (OTHERS => '0');
146 END IF;
147
148 --VALID OUT
149 all_wen: FOR I IN 3 DOWNTO 0 LOOP
150 IF sel(I) = '1' AND count_enable = '0' THEN
151 data_out_wen(I) <= '0';
152 ELSE
153 data_out_wen(I) <= '1';
154 END IF;
155 END LOOP all_wen;
156
157 END IF;
162 END IF;
158 END IF;
163 END IF;
159 END PROCESS;
164 END PROCESS;
165 -----------------------------------------------------------------------------
166
167
168 --PROCESS (clk, rstn)
169 --BEGIN -- PROCESS
170 -- IF rstn = '0' THEN -- asynchronous reset (active low)
171 -- count_enable <= '0';
172 -- shift_time_enable <= '0';
173 -- shift_data_enable <= '0';
174 -- data_in_ack <= (OTHERS => '0');
175 -- data_out_wen <= (OTHERS => '1');
176 -- sel_ack <= '0';
177 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
178 -- IF run = '0' OR no_sel = '1' THEN
179 -- count_enable <= '0';
180 -- shift_time_enable <= '0';
181 -- shift_data_enable <= '0';
182 -- data_in_ack <= (OTHERS => '0');
183 -- data_out_wen <= (OTHERS => '1');
184 -- sel_ack <= '0';
185 -- ELSE
186 -- --COUNT
187 -- IF shift_data_s = "10" THEN
188 -- count_enable <= '1';
189 -- ELSE
190 -- count_enable <= '0';
191 -- END IF;
192 -- --DATA
193 -- IF shift_time_s = "10" THEN
194 -- shift_data_enable <= '1';
195 -- ELSE
196 -- shift_data_enable <= '0';
197 -- END IF;
198
199 -- --TIME
200 -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
201 -- shift_time_s = "00" OR
202 -- shift_time_s = "01"
203 -- THEN
204 -- shift_time_enable <= '1';
205 -- ELSE
206 -- shift_time_enable <= '0';
207 -- END IF;
208
209 -- --ACK
210 -- IF shift_data_s = "10" THEN
211 -- data_in_ack <= sel;
212 -- sel_ack <= '1';
213 -- ELSE
214 -- data_in_ack <= (OTHERS => '0');
215 -- sel_ack <= '0';
216 -- END IF;
217
218 -- --VALID OUT
219 -- all_wen: FOR I IN 3 DOWNTO 0 LOOP
220 -- IF sel(I) = '1' AND count_enable = '0' THEN
221 -- data_out_wen(I) <= '0';
222 -- ELSE
223 -- data_out_wen(I) <= '1';
224 -- END IF;
225 -- END LOOP all_wen;
226
227 -- END IF;
228 -- END IF;
229 --END PROCESS;
160
230
161 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
162 -- DATA MUX
232 -- DATA MUX
163 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
164 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
234 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
165 I_time_in: IF I < 48 GENERATE
235 I_time_in: IF I < 48 GENERATE
166 data_0_v(I) <= time_in(0,I);
236 data_0_v(I) <= time_in(0,I);
167 data_1_v(I) <= time_in(1,I);
237 data_1_v(I) <= time_in(1,I);
168 data_2_v(I) <= time_in(2,I);
238 data_2_v(I) <= time_in(2,I);
169 data_3_v(I) <= time_in(3,I);
239 data_3_v(I) <= time_in(3,I);
170 END GENERATE I_time_in;
240 END GENERATE I_time_in;
171 I_null: IF (I > 47) AND (I < 32*2) GENERATE
241 I_null: IF (I > 47) AND (I < 32*2) GENERATE
172 data_0_v(I) <= '0';
242 data_0_v(I) <= '0';
173 data_1_v(I) <= '0';
243 data_1_v(I) <= '0';
174 data_2_v(I) <= '0';
244 data_2_v(I) <= '0';
175 data_3_v(I) <= '0';
245 data_3_v(I) <= '0';
176 END GENERATE I_null;
246 END GENERATE I_null;
177 I_data_in: IF I > 32*2-1 GENERATE
247 I_data_in: IF I > 32*2-1 GENERATE
178 data_0_v(I) <= data_in(0,I-32*2);
248 data_0_v(I) <= data_in(0,I-32*2);
179 data_1_v(I) <= data_in(1,I-32*2);
249 data_1_v(I) <= data_in(1,I-32*2);
180 data_2_v(I) <= data_in(2,I-32*2);
250 data_2_v(I) <= data_in(2,I-32*2);
181 data_3_v(I) <= data_in(3,I-32*2);
251 data_3_v(I) <= data_in(3,I-32*2);
182 END GENERATE I_data_in;
252 END GENERATE I_data_in;
183 END GENERATE all_bit_data_in;
253 END GENERATE all_bit_data_in;
184
254
185 all_word: FOR J IN 4 DOWNTO 0 GENERATE
255 all_word: FOR J IN 4 DOWNTO 0 GENERATE
186 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
256 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
187 data_0(J)(I) <= data_0_v(J*32+I);
257 data_0(J)(I) <= data_0_v(J*32+I);
188 data_1(J)(I) <= data_1_v(J*32+I);
258 data_1(J)(I) <= data_1_v(J*32+I);
189 data_2(J)(I) <= data_2_v(J*32+I);
259 data_2(J)(I) <= data_2_v(J*32+I);
190 data_3(J)(I) <= data_3_v(J*32+I);
260 data_3(J)(I) <= data_3_v(J*32+I);
191 END GENERATE all_data_bit;
261 END GENERATE all_data_bit;
192 END GENERATE all_word;
262 END GENERATE all_word;
193
263
194 data_sel <= data_0 WHEN sel(0) = '1' ELSE
264 data_sel <= data_0 WHEN sel(0) = '1' ELSE
195 data_1 WHEN sel(1) = '1' ELSE
265 data_1 WHEN sel(1) = '1' ELSE
196 data_2 WHEN sel(2) = '1' ELSE
266 data_2 WHEN sel(2) = '1' ELSE
197 data_3;
267 data_3;
198
268
199 data_out <= data_sel(0) WHEN shift_time = "00" ELSE
269 --data_out <= data_sel(0) WHEN shift_time = "00" ELSE
200 data_sel(1) WHEN shift_time = "01" ELSE
270 -- data_sel(1) WHEN shift_time = "01" ELSE
201 data_sel(2) WHEN shift_data = "00" ELSE
271 -- data_sel(2) WHEN shift_data = "00" ELSE
202 data_sel(3) WHEN shift_data = "01" ELSE
272 -- data_sel(3) WHEN shift_data = "01" ELSE
203 data_sel(4);
273 -- data_sel(4);
204
274
205
275
206 -----------------------------------------------------------------------------
276 -----------------------------------------------------------------------------
207 -- RR and SELECTION
277 -- RR and SELECTION
208 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
209 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
279 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
210 valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
280 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
281 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
211 END GENERATE all_input_rr;
282 END GENERATE all_input_rr;
212
283
213 RR_Arbiter_4_1 : RR_Arbiter_4
284 RR_Arbiter_4_1 : RR_Arbiter_4
214 PORT MAP (
285 PORT MAP (
215 clk => clk,
286 clk => clk,
216 rstn => rstn,
287 rstn => rstn,
217 in_valid => valid_in_rr,
288 in_valid => valid_in_rr,
218 out_grant => sel);
289 out_grant => sel_s); --sel_s);
290
291 -- sel <= sel_s;
292
293 PROCESS (clk, rstn)
294 BEGIN -- PROCESS
295 IF rstn = '0' THEN -- asynchronous reset (active low)
296 sel <= "0000";
297 sel_reg <= '0';
298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
299 -- sel_reg
300 -- sel_ack
301 -- sel_s
302 -- sel = "0000 "
303 --sel <= sel_s;
304 IF sel_reg = '0' OR sel_ack = '1'
305 --OR shift_data_s = "10"
306 THEN
307 sel <= sel_s;
308 IF sel_s = "0000" THEN
309 sel_reg <= '0';
310 ELSE
311 sel_reg <= '1';
312 END IF;
313 END IF;
314 END IF;
315 END PROCESS;
219
316
220 no_sel <= '1' WHEN sel = "0000" ELSE '0';
317 no_sel <= '1' WHEN sel = "0000" ELSE '0';
221
318
222 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
223 -- REG
320 -- REG
224 -----------------------------------------------------------------------------
321 -----------------------------------------------------------------------------
225 reg_count_i: lpp_waveform_fifo_arbiter_reg
322 reg_count_i: lpp_waveform_fifo_arbiter_reg
226 GENERIC MAP (
323 GENERIC MAP (
227 data_size => nb_data_by_buffer_size,
324 data_size => nb_data_by_buffer_size,
228 data_nb => 4)
325 data_nb => 4)
229 PORT MAP (
326 PORT MAP (
230 clk => clk,
327 clk => clk,
231 rstn => rstn,
328 rstn => rstn,
232 run => run,
329 run => run,
233 max_count => nb_data_by_buffer,
330 max_count => nb_data_by_buffer,
234 enable => count_enable,
331 enable => count_enable,
235 sel => sel,
332 sel => sel,
236 data => count,
333 data => count,
237 data_s => count_s);
334 data_s => count_s);
238
335
239 reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
336 --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
240 GENERIC MAP (
337 -- GENERIC MAP (
241 data_size => 2,
338 -- data_size => 2,
242 data_nb => 4)
339 -- data_nb => 4)
243 PORT MAP (
340 -- PORT MAP (
244 clk => clk,
341 -- clk => clk,
245 rstn => rstn,
342 -- rstn => rstn,
246 run => run,
343 -- run => run,
247 max_count => "10", -- 2
344 -- max_count => "10", -- 2
248 enable => shift_data_enable,
345 -- enable => shift_data_enable,
249 sel => sel,
346 -- sel => sel,
250 data => shift_data,
347 -- data => shift_data,
251 data_s => shift_data_s);
348 -- data_s => shift_data_s);
252
349
253
350
254 reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
351 --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
255 GENERIC MAP (
352 -- GENERIC MAP (
256 data_size => 2,
353 -- data_size => 2,
257 data_nb => 4)
354 -- data_nb => 4)
258 PORT MAP (
355 -- PORT MAP (
259 clk => clk,
356 -- clk => clk,
260 rstn => rstn,
357 -- rstn => rstn,
261 run => run,
358 -- run => run,
262 max_count => "10", -- 2
359 -- max_count => "10", -- 2
263 enable => shift_time_enable,
360 -- enable => shift_time_enable,
264 sel => sel,
361 -- sel => sel,
265 data => shift_time,
362 -- data => shift_time,
266 data_s => shift_time_s);
363 -- data_s => shift_time_s);
267
364
268
365
269
366
270
367
271 END ARCHITECTURE;
368 END ARCHITECTURE;
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Show file before | Show file after | Hide comments
@@ -1,333 +1,344
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25
25
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
31
31
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34
34
35 PACKAGE lpp_waveform_pkg IS
35 PACKAGE lpp_waveform_pkg IS
36
36
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38
38
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>,NATURAL RANGE <>) OF STD_LOGIC;
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40
40
41 -----------------------------------------------------------------------------
41 -----------------------------------------------------------------------------
42 -- SNAPSHOT
42 -- SNAPSHOT
43 -----------------------------------------------------------------------------
43 -----------------------------------------------------------------------------
44
44
45 COMPONENT lpp_waveform_snapshot
45 COMPONENT lpp_waveform_snapshot
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER;
47 data_size : INTEGER;
48 nb_snapshot_param_size : INTEGER);
48 nb_snapshot_param_size : INTEGER);
49 PORT (
49 PORT (
50 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
52 run : IN STD_LOGIC;
52 run : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 start_snapshot : IN STD_LOGIC;
56 start_snapshot : IN STD_LOGIC;
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 data_in_valid : IN STD_LOGIC;
58 data_in_valid : IN STD_LOGIC;
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 data_out_valid : OUT STD_LOGIC);
60 data_out_valid : OUT STD_LOGIC);
61 END COMPONENT;
61 END COMPONENT;
62
62
63 COMPONENT lpp_waveform_burst
63 COMPONENT lpp_waveform_burst
64 GENERIC (
64 GENERIC (
65 data_size : INTEGER);
65 data_size : INTEGER);
66 PORT (
66 PORT (
67 clk : IN STD_LOGIC;
67 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 run : IN STD_LOGIC;
69 run : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 data_in_valid : IN STD_LOGIC;
72 data_in_valid : IN STD_LOGIC;
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 data_out_valid : OUT STD_LOGIC);
74 data_out_valid : OUT STD_LOGIC);
75 END COMPONENT;
75 END COMPONENT;
76
76
77 COMPONENT lpp_waveform_snapshot_controler
77 COMPONENT lpp_waveform_snapshot_controler
78 GENERIC (
78 GENERIC (
79 delta_vector_size : INTEGER;
79 delta_vector_size : INTEGER;
80 delta_vector_size_f0_2 : INTEGER);
80 delta_vector_size_f0_2 : INTEGER);
81 PORT (
81 PORT (
82 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 data_f0_valid : IN STD_LOGIC;
92 data_f0_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
97 wfp_on : OUT STD_LOGIC);
97 wfp_on : OUT STD_LOGIC);
98 END COMPONENT;
98 END COMPONENT;
99
99
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 --
101 --
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 COMPONENT lpp_waveform
103 COMPONENT lpp_waveform
104 GENERIC (
104 GENERIC (
105 tech : INTEGER;
105 tech : INTEGER;
106 data_size : INTEGER;
106 data_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
110 delta_vector_size : INTEGER;
110 delta_vector_size : INTEGER;
111 delta_vector_size_f0_2 : INTEGER);
111 delta_vector_size_f0_2 : INTEGER);
112 PORT (
112 PORT (
113 clk : IN STD_LOGIC;
113 clk : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
115 reg_run : IN STD_LOGIC;
115 reg_run : IN STD_LOGIC;
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 enable_f0 : IN STD_LOGIC;
122 enable_f0 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
128 burst_f2 : IN STD_LOGIC;
128 burst_f2 : IN STD_LOGIC;
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 data_f0_in_valid : IN STD_LOGIC;
139 data_f0_in_valid : IN STD_LOGIC;
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
142 data_f1_in_valid : IN STD_LOGIC;
142 data_f1_in_valid : IN STD_LOGIC;
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 data_f2_in_valid : IN STD_LOGIC;
145 data_f2_in_valid : IN STD_LOGIC;
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 data_f3_in_valid : IN STD_LOGIC;
148 data_f3_in_valid : IN STD_LOGIC;
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 data_f0_data_out_valid : OUT STD_LOGIC;
152 data_f0_data_out_valid : OUT STD_LOGIC;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
154 data_f0_data_out_ren : IN STD_LOGIC;
154 data_f0_data_out_ren : IN STD_LOGIC;
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 data_f1_data_out_valid : OUT STD_LOGIC;
157 data_f1_data_out_valid : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 data_f2_data_out_valid : OUT STD_LOGIC;
162 data_f2_data_out_valid : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_f3_data_out_valid : OUT STD_LOGIC;
167 data_f3_data_out_valid : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC);
169 data_f3_data_out_ren : IN STD_LOGIC;
170
171 --debug
172 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 debug_f0_data_valid : OUT STD_LOGIC;
174 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 debug_f1_data_valid : OUT STD_LOGIC;
176 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
177 debug_f2_data_valid : OUT STD_LOGIC;
178 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 debug_f3_data_valid : OUT STD_LOGIC);
170 END COMPONENT;
180 END COMPONENT;
171
181
172 COMPONENT lpp_waveform_dma_genvalid
182 COMPONENT lpp_waveform_dma_genvalid
173 PORT (
183 PORT (
174 HCLK : IN STD_LOGIC;
184 HCLK : IN STD_LOGIC;
175 HRESETn : IN STD_LOGIC;
185 HRESETn : IN STD_LOGIC;
176 run : IN STD_LOGIC;
186 run : IN STD_LOGIC;
177 valid_in : IN STD_LOGIC;
187 valid_in : IN STD_LOGIC;
178 ack_in : IN STD_LOGIC;
188 ack_in : IN STD_LOGIC;
179 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
189 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
180 valid_out : OUT STD_LOGIC;
190 valid_out : OUT STD_LOGIC;
181 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
191 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
182 error : OUT STD_LOGIC);
192 error : OUT STD_LOGIC);
183 END COMPONENT;
193 END COMPONENT;
184
194
185 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
186 -- FIFO
196 -- FIFO
187 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
188 COMPONENT lpp_waveform_fifo_ctrl
198 COMPONENT lpp_waveform_fifo_ctrl
189 GENERIC (
199 GENERIC (
190 offset : INTEGER;
200 offset : INTEGER;
191 length : INTEGER);
201 length : INTEGER);
192 PORT (
202 PORT (
193 clk : IN STD_LOGIC;
203 clk : IN STD_LOGIC;
194 rstn : IN STD_LOGIC;
204 rstn : IN STD_LOGIC;
195 run : IN STD_LOGIC;
205 run : IN STD_LOGIC;
196 ren : IN STD_LOGIC;
206 ren : IN STD_LOGIC;
197 wen : IN STD_LOGIC;
207 wen : IN STD_LOGIC;
198 mem_re : OUT STD_LOGIC;
208 mem_re : OUT STD_LOGIC;
199 mem_we : OUT STD_LOGIC;
209 mem_we : OUT STD_LOGIC;
200 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
210 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
201 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
211 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
202 empty_almost : OUT STD_LOGIC;
212 empty_almost : OUT STD_LOGIC;
203 empty : OUT STD_LOGIC;
213 empty : OUT STD_LOGIC;
204 full_almost : OUT STD_LOGIC;
214 full_almost : OUT STD_LOGIC;
205 full : OUT STD_LOGIC);
215 full : OUT STD_LOGIC);
206 END COMPONENT;
216 END COMPONENT;
207
217
208 COMPONENT lpp_waveform_fifo_arbiter
218 COMPONENT lpp_waveform_fifo_arbiter
209 GENERIC (
219 GENERIC (
210 tech : INTEGER;
220 tech : INTEGER;
211 nb_data_by_buffer_size : INTEGER);
221 nb_data_by_buffer_size : INTEGER);
212 PORT (
222 PORT (
213 clk : IN STD_LOGIC;
223 clk : IN STD_LOGIC;
214 rstn : IN STD_LOGIC;
224 rstn : IN STD_LOGIC;
215 run : IN STD_LOGIC;
225 run : IN STD_LOGIC;
216 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
226 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
217 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
227 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
218 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
228 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
219 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
229 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
220 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
230 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
221 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
231 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
222 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
232 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
233 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
223 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
234 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
224 END COMPONENT;
235 END COMPONENT;
225
236
226 COMPONENT lpp_waveform_fifo
237 COMPONENT lpp_waveform_fifo
227 GENERIC (
238 GENERIC (
228 tech : INTEGER);
239 tech : INTEGER);
229 PORT (
240 PORT (
230 clk : IN STD_LOGIC;
241 clk : IN STD_LOGIC;
231 rstn : IN STD_LOGIC;
242 rstn : IN STD_LOGIC;
232 run : IN STD_LOGIC;
243 run : IN STD_LOGIC;
233 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
244 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
234 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
235 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
246 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
236 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
247 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
237 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
248 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
238 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
249 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
239 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
250 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
240 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
251 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
241 END COMPONENT;
252 END COMPONENT;
242
253
243 COMPONENT lpp_waveform_fifo_latencyCorrection
254 COMPONENT lpp_waveform_fifo_latencyCorrection
244 GENERIC (
255 GENERIC (
245 tech : INTEGER);
256 tech : INTEGER);
246 PORT (
257 PORT (
247 clk : IN STD_LOGIC;
258 clk : IN STD_LOGIC;
248 rstn : IN STD_LOGIC;
259 rstn : IN STD_LOGIC;
249 run : IN STD_LOGIC;
260 run : IN STD_LOGIC;
250 empty_almost : OUT STD_LOGIC;
261 empty_almost : OUT STD_LOGIC;
251 empty : OUT STD_LOGIC;
262 empty : OUT STD_LOGIC;
252 data_ren : IN STD_LOGIC;
263 data_ren : IN STD_LOGIC;
253 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
264 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
254 empty_almost_fifo : IN STD_LOGIC;
265 empty_almost_fifo : IN STD_LOGIC;
255 empty_fifo : IN STD_LOGIC;
266 empty_fifo : IN STD_LOGIC;
256 data_ren_fifo : OUT STD_LOGIC;
267 data_ren_fifo : OUT STD_LOGIC;
257 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
268 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
258 END COMPONENT;
269 END COMPONENT;
259
270
260 COMPONENT lpp_waveform_fifo_withoutLatency
271 COMPONENT lpp_waveform_fifo_withoutLatency
261 GENERIC (
272 GENERIC (
262 tech : INTEGER);
273 tech : INTEGER);
263 PORT (
274 PORT (
264 clk : IN STD_LOGIC;
275 clk : IN STD_LOGIC;
265 rstn : IN STD_LOGIC;
276 rstn : IN STD_LOGIC;
266 run : IN STD_LOGIC;
277 run : IN STD_LOGIC;
267 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
278 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
268 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
279 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
269 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
280 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
270 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
281 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
271 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
272 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
273 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
274 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
285 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
275 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
286 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
276 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
287 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
277 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
288 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
278 END COMPONENT;
289 END COMPONENT;
279
290
280 -----------------------------------------------------------------------------
291 -----------------------------------------------------------------------------
281 -- GEN ADDRESS
292 -- GEN ADDRESS
282 -----------------------------------------------------------------------------
293 -----------------------------------------------------------------------------
283 COMPONENT lpp_waveform_genaddress
294 COMPONENT lpp_waveform_genaddress
284 GENERIC (
295 GENERIC (
285 nb_data_by_buffer_size : INTEGER);
296 nb_data_by_buffer_size : INTEGER);
286 PORT (
297 PORT (
287 clk : IN STD_LOGIC;
298 clk : IN STD_LOGIC;
288 rstn : IN STD_LOGIC;
299 rstn : IN STD_LOGIC;
289 run : IN STD_LOGIC;
300 run : IN STD_LOGIC;
290 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
301 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
291 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
302 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
292 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
303 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
293 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
304 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
294 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
305 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
295 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
306 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
296 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
307 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
297 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
308 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
298 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
309 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
299 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
310 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
300 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
311 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
301 data_f0_data_out_valid_burst : OUT STD_LOGIC;
312 data_f0_data_out_valid_burst : OUT STD_LOGIC;
302 data_f1_data_out_valid_burst : OUT STD_LOGIC;
313 data_f1_data_out_valid_burst : OUT STD_LOGIC;
303 data_f2_data_out_valid_burst : OUT STD_LOGIC;
314 data_f2_data_out_valid_burst : OUT STD_LOGIC;
304 data_f3_data_out_valid_burst : OUT STD_LOGIC;
315 data_f3_data_out_valid_burst : OUT STD_LOGIC;
305 data_f0_data_out_valid : OUT STD_LOGIC;
316 data_f0_data_out_valid : OUT STD_LOGIC;
306 data_f1_data_out_valid : OUT STD_LOGIC;
317 data_f1_data_out_valid : OUT STD_LOGIC;
307 data_f2_data_out_valid : OUT STD_LOGIC;
318 data_f2_data_out_valid : OUT STD_LOGIC;
308 data_f3_data_out_valid : OUT STD_LOGIC;
319 data_f3_data_out_valid : OUT STD_LOGIC;
309 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
310 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
311 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
312 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
323 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
313 END COMPONENT;
324 END COMPONENT;
314
325
315 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
316 -- lpp_waveform_fifo_arbiter_reg
327 -- lpp_waveform_fifo_arbiter_reg
317 -----------------------------------------------------------------------------
328 -----------------------------------------------------------------------------
318 COMPONENT lpp_waveform_fifo_arbiter_reg
329 COMPONENT lpp_waveform_fifo_arbiter_reg
319 GENERIC (
330 GENERIC (
320 data_size : INTEGER;
331 data_size : INTEGER;
321 data_nb : INTEGER);
332 data_nb : INTEGER);
322 PORT (
333 PORT (
323 clk : IN STD_LOGIC;
334 clk : IN STD_LOGIC;
324 rstn : IN STD_LOGIC;
335 rstn : IN STD_LOGIC;
325 run : IN STD_LOGIC;
336 run : IN STD_LOGIC;
326 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
337 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
327 enable : IN STD_LOGIC;
338 enable : IN STD_LOGIC;
328 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
339 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
329 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
340 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
330 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
341 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
331 END COMPONENT;
342 END COMPONENT;
332
343
333 END lpp_waveform_pkg;
344 END lpp_waveform_pkg;
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