@@ -1,112 +1,117 | |||
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1 | 1 | set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout |
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2 | 2 | set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout |
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3 | 3 | set_io reset -pinname N18 -fixed yes -DIRECTION Inout |
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4 | 4 | |
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5 | 5 | set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout |
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6 | 6 | set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout |
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7 | 7 | set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout |
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8 | 8 | set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout |
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9 | 9 | set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout |
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10 | 10 | set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout |
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11 | 11 | set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout |
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12 | 12 | set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout |
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13 | 13 | set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout |
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14 | 14 | set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout |
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15 | 15 | set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout |
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16 | 16 | set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout |
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17 | 17 | set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout |
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18 | 18 | set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout |
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19 | 19 | set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout |
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20 | 20 | set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout |
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21 | 21 | set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout |
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22 | 22 | set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout |
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23 | 23 | set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout |
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24 | 24 | set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout |
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25 | 25 | |
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26 | 26 | set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout |
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27 | 27 | set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout |
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28 | 28 | set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout |
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29 | 29 | set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout |
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30 | 30 | set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout |
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31 | 31 | set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout |
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32 | 32 | set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout |
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33 | 33 | set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout |
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34 | 34 | set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout |
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35 | 35 | set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout |
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36 | 36 | set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout |
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37 | 37 | set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout |
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38 | 38 | set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout |
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39 | 39 | set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout |
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40 | 40 | set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout |
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41 | 41 | set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout |
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42 | 42 | set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout |
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43 | 43 | set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout |
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44 | 44 | set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout |
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45 | 45 | set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout |
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46 | 46 | set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout |
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47 | 47 | set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout |
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48 | 48 | set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout |
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49 | 49 | set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout |
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50 | 50 | set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout |
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51 | 51 | set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout |
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52 | 52 | set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout |
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53 | 53 | set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout |
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54 | 54 | set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout |
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55 | 55 | set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout |
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56 | 56 | set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout |
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57 | 57 | set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout |
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58 | 58 | |
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59 | 59 | set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout |
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60 | 60 | set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout |
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61 | 61 | set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout |
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62 | 62 | set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout |
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63 | 63 | set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout |
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64 | 64 | set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout |
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65 | 65 | set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout |
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66 | 66 | |
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67 | 67 | set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout |
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68 | 68 | set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout |
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69 | 69 | set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout |
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70 | 70 | set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout |
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71 | 71 | |
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72 | set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout | |
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73 | set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout | |
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74 | set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout | |
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75 | set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout | |
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76 | ||
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72 | 77 | set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout |
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73 | 78 | set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout |
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74 | 79 | set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout |
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75 | 80 | |
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76 | 81 | set_io ahbtxd -pinname J12 -fixed yes -DIRECTION Inout |
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77 | 82 | #set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout |
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78 | 83 | set_io ahbrxd -pinname L16 -fixed yes -DIRECTION Inout |
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79 | 84 | #set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout |
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80 | 85 | set_io urxd1 -pinname M16 -fixed yes -DIRECTION Inout |
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81 | 86 | set_io utxd1 -pinname L13 -fixed yes -DIRECTION Inout |
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82 | 87 | set_io errorn -pinname P6 -fixed yes -DIRECTION Inout |
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83 | 88 | #set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout |
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84 | 89 | #set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout |
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85 | 90 | |
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86 | 91 | set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout |
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87 | 92 | |
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88 | 93 | set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout |
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89 | 94 | set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout |
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90 | 95 | set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout |
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91 | 96 | set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout |
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92 | 97 | set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout |
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93 | 98 | set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout |
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94 | 99 | set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout |
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95 | 100 | set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout |
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96 | 101 | |
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97 | 102 | set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout |
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98 | 103 | |
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99 | 104 | set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout |
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100 | 105 | set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout |
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101 | 106 | set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout |
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102 | 107 | set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout |
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103 | 108 | set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout |
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104 | 109 | set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout |
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105 | 110 | set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout |
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106 | 111 | set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout |
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107 | 112 | set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout |
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108 | 113 | set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout |
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109 | 114 | set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout |
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110 | 115 | set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout |
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111 | 116 | set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout |
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112 | 117 | set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout |
@@ -1,278 +1,279 | |||
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1 | 1 | LIBRARY ieee; |
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2 | 2 | USE ieee.std_logic_1164.ALL; |
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3 | 3 | |
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4 | 4 | LIBRARY grlib; |
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5 | 5 | USE grlib.amba.ALL; |
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6 | 6 | |
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7 | 7 | LIBRARY lpp; |
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8 | 8 | USE lpp.lpp_ad_conv.ALL; |
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9 | 9 | USE lpp.iir_filter.ALL; |
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10 | 10 | USE lpp.FILTERcfg.ALL; |
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11 | 11 | USE lpp.lpp_memory.ALL; |
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12 | 12 | LIBRARY techmap; |
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13 | 13 | USE techmap.gencomp.ALL; |
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14 | 14 | |
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15 | 15 | PACKAGE lpp_top_lfr_pkg IS |
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16 | 16 | |
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17 | 17 | COMPONENT lpp_top_acq |
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18 | 18 | GENERIC( |
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19 | 19 | tech : INTEGER := 0 |
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20 | 20 | ); |
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21 | 21 | PORT ( |
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22 | 22 | -- ADS7886 |
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23 | 23 | cnv_run : IN STD_LOGIC; |
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24 | 24 | cnv : OUT STD_LOGIC; |
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25 | 25 | sck : OUT STD_LOGIC; |
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26 | 26 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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27 | 27 | -- |
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28 | 28 | cnv_clk : IN STD_LOGIC; -- 49 MHz |
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29 | 29 | cnv_rstn : IN STD_LOGIC; |
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30 | 30 | -- |
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31 | 31 | clk : IN STD_LOGIC; -- 25 MHz |
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32 | 32 | rstn : IN STD_LOGIC; |
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33 | 33 | -- |
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34 | 34 | sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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35 | 35 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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36 | 36 | -- |
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37 | 37 | sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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38 | 38 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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39 | 39 | -- |
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40 | 40 | sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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41 | 41 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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42 | 42 | -- |
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43 | 43 | sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
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44 | 44 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0) |
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45 | 45 | ); |
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46 | 46 | END COMPONENT; |
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47 | 47 | |
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48 | 48 | COMPONENT lpp_top_apbreg |
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49 | 49 | GENERIC ( |
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50 | 50 | nb_burst_available_size : INTEGER; |
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51 | 51 | nb_snapshot_param_size : INTEGER; |
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52 | 52 | delta_snapshot_size : INTEGER; |
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53 | 53 | delta_f2_f0_size : INTEGER; |
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54 | 54 | delta_f2_f1_size : INTEGER; |
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55 | 55 | pindex : INTEGER; |
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56 | 56 | paddr : INTEGER; |
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57 | 57 | pmask : INTEGER; |
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58 | 58 | pirq : INTEGER); |
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59 | 59 | PORT ( |
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60 | 60 | HCLK : IN STD_ULOGIC; |
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61 | 61 | HRESETn : IN STD_ULOGIC; |
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62 | 62 | apbi : IN apb_slv_in_type; |
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63 | 63 | apbo : OUT apb_slv_out_type; |
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64 | 64 | ready_matrix_f0_0 : IN STD_LOGIC; |
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65 | 65 | ready_matrix_f0_1 : IN STD_LOGIC; |
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66 | 66 | ready_matrix_f1 : IN STD_LOGIC; |
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67 | 67 | ready_matrix_f2 : IN STD_LOGIC; |
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68 | 68 | error_anticipating_empty_fifo : IN STD_LOGIC; |
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69 | 69 | error_bad_component_error : IN STD_LOGIC; |
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70 | 70 | debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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71 | 71 | status_ready_matrix_f0_0 : OUT STD_LOGIC; |
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72 | 72 | status_ready_matrix_f0_1 : OUT STD_LOGIC; |
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73 | 73 | status_ready_matrix_f1 : OUT STD_LOGIC; |
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74 | 74 | status_ready_matrix_f2 : OUT STD_LOGIC; |
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75 | 75 | status_error_anticipating_empty_fifo : OUT STD_LOGIC; |
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76 | 76 | status_error_bad_component_error : OUT STD_LOGIC; |
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77 | 77 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
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78 | 78 | config_active_interruption_onError : OUT STD_LOGIC; |
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79 | 79 | addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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80 | 80 | addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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81 | 81 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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82 | 82 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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83 | 83 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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84 | 84 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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85 | 85 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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86 | 86 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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87 | 87 | data_shaping_BW : OUT STD_LOGIC; |
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88 | 88 | data_shaping_SP0 : OUT STD_LOGIC; |
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89 | 89 | data_shaping_SP1 : OUT STD_LOGIC; |
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90 | 90 | data_shaping_R0 : OUT STD_LOGIC; |
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91 | 91 | data_shaping_R1 : OUT STD_LOGIC; |
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92 | 92 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
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93 | 93 | delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
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94 | 94 | delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
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95 | 95 | nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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96 | 96 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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97 | 97 | enable_f0 : OUT STD_LOGIC; |
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98 | 98 | enable_f1 : OUT STD_LOGIC; |
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99 | 99 | enable_f2 : OUT STD_LOGIC; |
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100 | 100 | enable_f3 : OUT STD_LOGIC; |
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101 | 101 | burst_f0 : OUT STD_LOGIC; |
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102 | 102 | burst_f1 : OUT STD_LOGIC; |
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103 | 103 | burst_f2 : OUT STD_LOGIC; |
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104 | 104 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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105 | 105 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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106 | 106 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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107 | 107 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
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108 | 108 | END COMPONENT; |
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109 | 109 | |
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110 | 110 | COMPONENT lpp_top_lfr_wf_picker |
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111 | 111 | GENERIC ( |
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112 | 112 | hindex : INTEGER; |
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113 | 113 | pindex : INTEGER; |
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114 | 114 | paddr : INTEGER; |
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115 | 115 | pmask : INTEGER; |
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116 | 116 | pirq : INTEGER; |
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117 | 117 | tech : INTEGER; |
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118 | 118 | nb_burst_available_size : INTEGER; |
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119 | 119 | nb_snapshot_param_size : INTEGER; |
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120 | 120 | delta_snapshot_size : INTEGER; |
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121 | 121 | delta_f2_f0_size : INTEGER; |
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122 | 122 | delta_f2_f1_size : INTEGER; |
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123 | 123 | ENABLE_FILTER : STD_LOGIC); |
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124 | 124 | PORT ( |
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125 | 125 | cnv_run : IN STD_LOGIC; |
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126 | 126 | cnv : OUT STD_LOGIC; |
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127 | 127 | sck : OUT STD_LOGIC; |
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128 | 128 | sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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129 | 129 | cnv_clk : IN STD_LOGIC; |
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130 | 130 | cnv_rstn : IN STD_LOGIC; |
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131 | 131 | HCLK : IN STD_ULOGIC; |
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132 | 132 | HRESETn : IN STD_ULOGIC; |
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133 | 133 | apbi : IN apb_slv_in_type; |
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134 | 134 | apbo : OUT apb_slv_out_type; |
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135 | 135 | AHB_Master_In : IN AHB_Mst_In_Type; |
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136 | 136 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
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137 | 137 | coarse_time_0 : IN STD_LOGIC; |
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138 | 138 | data_shaping_BW : OUT STD_LOGIC); |
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139 | 139 | END COMPONENT; |
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140 | 140 | |
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141 | 141 | |
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142 | 142 | COMPONENT lpp_top_lfr_wf_picker_ip |
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143 | 143 | GENERIC ( |
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144 | 144 | hindex : INTEGER; |
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145 | 145 | nb_burst_available_size : INTEGER; |
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146 | 146 | nb_snapshot_param_size : INTEGER; |
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147 | 147 | delta_snapshot_size : INTEGER; |
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148 | 148 | delta_f2_f0_size : INTEGER; |
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149 | 149 | delta_f2_f1_size : INTEGER; |
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150 | 150 | tech : INTEGER; |
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151 | 151 | Mem_use : INTEGER); |
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152 | 152 | PORT ( |
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153 | 153 | sample : IN Samples(7 DOWNTO 0); |
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154 | 154 | sample_val : IN STD_LOGIC; |
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155 | 155 | cnv_clk : IN STD_LOGIC; |
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156 | 156 | cnv_rstn : IN STD_LOGIC; |
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157 | 157 | clk : IN STD_LOGIC; |
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158 | 158 | rstn : IN STD_LOGIC; |
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159 | 159 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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160 | 160 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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161 | 161 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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162 | 162 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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163 | 163 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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164 | 164 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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165 | 165 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
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166 | 166 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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167 | 167 | AHB_Master_In : IN AHB_Mst_In_Type; |
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168 | 168 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
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169 | 169 | coarse_time_0 : IN STD_LOGIC; |
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170 | 170 | data_shaping_SP0 : IN STD_LOGIC; |
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171 | 171 | data_shaping_SP1 : IN STD_LOGIC; |
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172 | 172 | data_shaping_R0 : IN STD_LOGIC; |
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173 | 173 | data_shaping_R1 : IN STD_LOGIC; |
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174 | 174 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
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175 | 175 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
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176 | 176 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
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177 | 177 | enable_f0 : IN STD_LOGIC; |
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178 | 178 | enable_f1 : IN STD_LOGIC; |
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179 | 179 | enable_f2 : IN STD_LOGIC; |
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180 | 180 | enable_f3 : IN STD_LOGIC; |
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181 | 181 | burst_f0 : IN STD_LOGIC; |
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182 | 182 | burst_f1 : IN STD_LOGIC; |
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183 | 183 | burst_f2 : IN STD_LOGIC; |
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184 | 184 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
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185 | 185 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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186 | 186 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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187 | 187 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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188 | 188 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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189 | 189 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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190 | 190 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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191 | 191 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
192 | 192 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | 193 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
194 | 194 | END COMPONENT; |
|
195 | 195 | |
|
196 | 196 | COMPONENT lpp_top_lfr_wf_picker_ip_whitout_filter |
|
197 | 197 | GENERIC ( |
|
198 | 198 | hindex : INTEGER; |
|
199 | 199 | nb_burst_available_size : INTEGER; |
|
200 | 200 | nb_snapshot_param_size : INTEGER; |
|
201 | 201 | delta_snapshot_size : INTEGER; |
|
202 | 202 | delta_f2_f0_size : INTEGER; |
|
203 | 203 | delta_f2_f1_size : INTEGER; |
|
204 | 204 | tech : INTEGER); |
|
205 | 205 | PORT ( |
|
206 | 206 | sample : IN Samples(7 DOWNTO 0); |
|
207 | 207 | sample_val : IN STD_LOGIC; |
|
208 | 208 | cnv_clk : IN STD_LOGIC; |
|
209 | 209 | cnv_rstn : IN STD_LOGIC; |
|
210 | 210 | clk : IN STD_LOGIC; |
|
211 | 211 | rstn : IN STD_LOGIC; |
|
212 | 212 | sample_f0_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
213 | 213 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
214 | 214 | sample_f1_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
215 | 215 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
216 | 216 | sample_f2_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
217 | 217 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
218 | 218 | sample_f3_wen : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
219 | 219 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
220 | 220 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
221 | 221 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
222 | 222 | coarse_time_0 : IN STD_LOGIC; |
|
223 | 223 | data_shaping_SP0 : IN STD_LOGIC; |
|
224 | 224 | data_shaping_SP1 : IN STD_LOGIC; |
|
225 | 225 | data_shaping_R0 : IN STD_LOGIC; |
|
226 | 226 | data_shaping_R1 : IN STD_LOGIC; |
|
227 | 227 | delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
228 | 228 | delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
229 | 229 | delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
230 | 230 | enable_f0 : IN STD_LOGIC; |
|
231 | 231 | enable_f1 : IN STD_LOGIC; |
|
232 | 232 | enable_f2 : IN STD_LOGIC; |
|
233 | 233 | enable_f3 : IN STD_LOGIC; |
|
234 | 234 | burst_f0 : IN STD_LOGIC; |
|
235 | 235 | burst_f1 : IN STD_LOGIC; |
|
236 | 236 | burst_f2 : IN STD_LOGIC; |
|
237 | 237 | nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
238 | 238 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
239 | 239 | status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
240 | 240 | status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
241 | 241 | status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
242 | 242 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
243 | 243 | addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
244 | 244 | addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
245 | 245 | addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
246 | 246 | addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
247 | 247 | END COMPONENT; |
|
248 | 248 | |
|
249 | 249 | COMPONENT top_wf_picker |
|
250 | 250 | GENERIC ( |
|
251 | 251 | hindex : INTEGER; |
|
252 | 252 | pindex : INTEGER; |
|
253 | 253 | paddr : INTEGER; |
|
254 | 254 | pmask : INTEGER; |
|
255 | 255 | pirq : INTEGER; |
|
256 | 256 | tech : INTEGER; |
|
257 | 257 | nb_burst_available_size : INTEGER; |
|
258 | 258 | nb_snapshot_param_size : INTEGER; |
|
259 | 259 | delta_snapshot_size : INTEGER; |
|
260 | 260 | delta_f2_f0_size : INTEGER; |
|
261 | 261 | delta_f2_f1_size : INTEGER; |
|
262 | 262 | ENABLE_FILTER : STD_LOGIC); |
|
263 | 263 | PORT ( |
|
264 | 264 | cnv_clk : IN STD_LOGIC; |
|
265 | 265 | cnv_rstn : IN STD_LOGIC; |
|
266 |
sample : IN Samples14v( |
|
|
266 | sample_B : IN Samples14v(2 DOWNTO 0); | |
|
267 | sample_E : IN Samples14v(4 DOWNTO 0); | |
|
267 | 268 | sample_val : IN STD_LOGIC; |
|
268 | 269 | HCLK : IN STD_ULOGIC; |
|
269 | 270 | HRESETn : IN STD_ULOGIC; |
|
270 | 271 | apbi : IN apb_slv_in_type; |
|
271 | 272 | apbo : OUT apb_slv_out_type; |
|
272 | 273 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
273 | 274 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
274 | 275 | coarse_time_0 : IN STD_LOGIC; |
|
275 | 276 | data_shaping_BW : OUT STD_LOGIC); |
|
276 | 277 | END COMPONENT; |
|
277 | 278 | |
|
278 | END lpp_top_lfr_pkg; No newline at end of file | |
|
279 | END lpp_top_lfr_pkg; |
@@ -1,343 +1,349 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | USE ieee.numeric_std.ALL; |
|
4 | 4 | |
|
5 | 5 | LIBRARY lpp; |
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
8 | 8 | USE lpp.FILTERcfg.ALL; |
|
9 | 9 | USE lpp.lpp_memory.ALL; |
|
10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
11 | 11 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
12 | 12 | |
|
13 | 13 | LIBRARY techmap; |
|
14 | 14 | USE techmap.gencomp.ALL; |
|
15 | 15 | |
|
16 | 16 | LIBRARY grlib; |
|
17 | 17 | USE grlib.amba.ALL; |
|
18 | 18 | USE grlib.stdlib.ALL; |
|
19 | 19 | USE grlib.devices.ALL; |
|
20 | 20 | USE GRLIB.DMA2AHB_Package.ALL; |
|
21 | 21 | |
|
22 | 22 | ENTITY top_wf_picker IS |
|
23 | 23 | GENERIC ( |
|
24 | 24 | hindex : INTEGER := 2; |
|
25 | 25 | pindex : INTEGER := 15; |
|
26 | 26 | paddr : INTEGER := 15; |
|
27 | 27 | pmask : INTEGER := 16#fff#; |
|
28 | 28 | pirq : INTEGER := 15; |
|
29 | 29 | tech : INTEGER := 0; |
|
30 | 30 | nb_burst_available_size : INTEGER := 11; |
|
31 | 31 | nb_snapshot_param_size : INTEGER := 11; |
|
32 | 32 | delta_snapshot_size : INTEGER := 16; |
|
33 | 33 | delta_f2_f0_size : INTEGER := 10; |
|
34 | 34 | delta_f2_f1_size : INTEGER := 10; |
|
35 | 35 | ENABLE_FILTER : STD_LOGIC := '1' |
|
36 | 36 | ); |
|
37 | 37 | PORT ( |
|
38 | 38 | cnv_clk : IN STD_LOGIC; |
|
39 | 39 | cnv_rstn : IN STD_LOGIC; |
|
40 | 40 | -- |
|
41 |
sample |
|
|
41 | sample_B : IN Samples14v(2 DOWNTO 0); | |
|
42 | sample_E : IN Samples14v(4 DOWNTO 0); | |
|
42 | 43 | sample_val : IN STD_LOGIC; |
|
43 | 44 | |
|
44 | 45 | -- AMBA AHB system signals |
|
45 | 46 | HCLK : IN STD_ULOGIC; |
|
46 | 47 | HRESETn : IN STD_ULOGIC; |
|
47 | 48 | |
|
48 | 49 | -- AMBA APB Slave Interface |
|
49 | 50 | apbi : IN apb_slv_in_type; |
|
50 | 51 | apbo : OUT apb_slv_out_type; |
|
51 | 52 | |
|
52 | 53 | -- AMBA AHB Master Interface |
|
53 | 54 | AHB_Master_In : IN AHB_Mst_In_Type; |
|
54 | 55 | AHB_Master_Out : OUT AHB_Mst_Out_Type; |
|
55 | 56 | |
|
56 | 57 | -- |
|
57 | 58 | coarse_time_0 : IN STD_LOGIC; |
|
58 | 59 | |
|
59 | 60 | -- |
|
60 | 61 | data_shaping_BW : OUT STD_LOGIC |
|
61 | 62 | ); |
|
62 | 63 | END top_wf_picker; |
|
63 | 64 | |
|
64 | 65 | ARCHITECTURE tb OF top_wf_picker IS |
|
65 | 66 | |
|
66 | 67 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
|
67 | 68 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
68 | 69 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
69 | 70 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
70 | 71 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
71 | 72 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
72 | 73 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
73 | 74 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
|
74 | 75 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
75 | 76 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
76 | 77 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
77 | 78 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
78 | 79 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
79 | 80 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
80 | 81 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
81 | 82 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
82 | 83 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
83 | 84 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 85 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | 86 | |
|
86 | 87 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
87 | 88 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
88 | 89 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
89 | 90 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
90 | 91 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
|
91 | 92 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
|
92 | 93 | SIGNAL data_shaping_R0 : STD_LOGIC; |
|
93 | 94 | SIGNAL data_shaping_R1 : STD_LOGIC; |
|
94 | 95 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); |
|
95 | 96 | SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); |
|
96 | 97 | SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); |
|
97 | 98 | SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); |
|
98 | 99 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
99 | 100 | SIGNAL enable_f0 : STD_LOGIC; |
|
100 | 101 | SIGNAL enable_f1 : STD_LOGIC; |
|
101 | 102 | SIGNAL enable_f2 : STD_LOGIC; |
|
102 | 103 | SIGNAL enable_f3 : STD_LOGIC; |
|
103 | 104 | SIGNAL burst_f0 : STD_LOGIC; |
|
104 | 105 | SIGNAL burst_f1 : STD_LOGIC; |
|
105 | 106 | SIGNAL burst_f2 : STD_LOGIC; |
|
106 | 107 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | 108 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | 109 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
109 | 110 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
110 | 111 | |
|
111 | 112 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
112 | 113 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
113 | 114 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
114 | 115 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
115 | 116 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
116 | 117 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
117 | 118 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
118 | 119 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
119 | 120 | |
|
120 | 121 | CONSTANT ChanelCount : INTEGER := 8; |
|
121 | 122 | CONSTANT ncycle_cnv_high : INTEGER := 40; |
|
122 | 123 | CONSTANT ncycle_cnv : INTEGER := 250; |
|
123 | 124 | |
|
124 |
SIGNAL |
|
|
125 | SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0); | |
|
126 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
|
125 | 127 | |
|
126 | 128 | BEGIN |
|
127 | 129 | |
|
130 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); | |
|
131 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); | |
|
132 | ||
|
133 | ||
|
128 | 134 |
|
|
129 | 135 | ready_matrix_f0_1 <= '0'; |
|
130 | 136 | ready_matrix_f1 <= '0'; |
|
131 | 137 | ready_matrix_f2 <= '0'; |
|
132 | 138 | error_anticipating_empty_fifo <= '0'; |
|
133 | 139 | error_bad_component_error <= '0'; |
|
134 | 140 | debug_reg <= (OTHERS => '0'); |
|
135 | 141 | |
|
136 | 142 | lpp_top_apbreg_1 : lpp_top_apbreg |
|
137 | 143 | GENERIC MAP ( |
|
138 | 144 | nb_burst_available_size => nb_burst_available_size, |
|
139 | 145 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
140 | 146 | delta_snapshot_size => delta_snapshot_size, |
|
141 | 147 | delta_f2_f0_size => delta_f2_f0_size, |
|
142 | 148 | delta_f2_f1_size => delta_f2_f1_size, |
|
143 | 149 | pindex => pindex, |
|
144 | 150 | paddr => paddr, |
|
145 | 151 | pmask => pmask, |
|
146 | 152 | pirq => pirq) |
|
147 | 153 | PORT MAP ( |
|
148 | 154 | HCLK => HCLK, |
|
149 | 155 | HRESETn => HRESETn, |
|
150 | 156 | apbi => apbi, |
|
151 | 157 | apbo => apbo, |
|
152 | 158 | |
|
153 | 159 | ready_matrix_f0_0 => ready_matrix_f0_0, |
|
154 | 160 | ready_matrix_f0_1 => ready_matrix_f0_1, |
|
155 | 161 | ready_matrix_f1 => ready_matrix_f1, |
|
156 | 162 | ready_matrix_f2 => ready_matrix_f2, |
|
157 | 163 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
158 | 164 | error_bad_component_error => error_bad_component_error, |
|
159 | 165 | debug_reg => debug_reg, |
|
160 | 166 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
|
161 | 167 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
162 | 168 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
163 | 169 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
164 | 170 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
165 | 171 | status_error_bad_component_error => status_error_bad_component_error, |
|
166 | 172 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
167 | 173 | config_active_interruption_onError => config_active_interruption_onError, |
|
168 | 174 | addr_matrix_f0_0 => addr_matrix_f0_0, |
|
169 | 175 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
170 | 176 | addr_matrix_f1 => addr_matrix_f1, |
|
171 | 177 | addr_matrix_f2 => addr_matrix_f2, |
|
172 | 178 | |
|
173 | 179 | status_full => status_full, |
|
174 | 180 | status_full_ack => status_full_ack, |
|
175 | 181 | status_full_err => status_full_err, |
|
176 | 182 | status_new_err => status_new_err, |
|
177 | 183 | data_shaping_BW => data_shaping_BW, |
|
178 | 184 | data_shaping_SP0 => data_shaping_SP0, |
|
179 | 185 | data_shaping_SP1 => data_shaping_SP1, |
|
180 | 186 | data_shaping_R0 => data_shaping_R0, |
|
181 | 187 | data_shaping_R1 => data_shaping_R1, |
|
182 | 188 | delta_snapshot => delta_snapshot, |
|
183 | 189 | delta_f2_f1 => delta_f2_f1, |
|
184 | 190 | delta_f2_f0 => delta_f2_f0, |
|
185 | 191 | nb_burst_available => nb_burst_available, |
|
186 | 192 | nb_snapshot_param => nb_snapshot_param, |
|
187 | 193 | enable_f0 => enable_f0, |
|
188 | 194 | enable_f1 => enable_f1, |
|
189 | 195 | enable_f2 => enable_f2, |
|
190 | 196 | enable_f3 => enable_f3, |
|
191 | 197 | burst_f0 => burst_f0, |
|
192 | 198 | burst_f1 => burst_f1, |
|
193 | 199 | burst_f2 => burst_f2, |
|
194 | 200 | addr_data_f0 => addr_data_f0, |
|
195 | 201 | addr_data_f1 => addr_data_f1, |
|
196 | 202 | addr_data_f2 => addr_data_f2, |
|
197 | 203 | addr_data_f3 => addr_data_f3); |
|
198 | 204 | |
|
199 | 205 | |
|
200 | 206 | |
|
201 | 207 | |
|
202 | 208 | --DIGITAL_acquisition : AD7688_drvr_sync |
|
203 | 209 | -- GENERIC MAP ( |
|
204 | 210 | -- ChanelCount => ChanelCount, |
|
205 | 211 | -- ncycle_cnv_high => ncycle_cnv_high, |
|
206 | 212 | -- ncycle_cnv => ncycle_cnv) |
|
207 | 213 | -- PORT MAP ( |
|
208 | 214 | -- cnv_clk => cnv_clk, -- |
|
209 | 215 | -- cnv_rstn => cnv_rstn, -- |
|
210 | 216 | -- cnv_run => cnv_run, -- |
|
211 | 217 | -- cnv => cnv, -- |
|
212 | 218 | -- sck => sck, -- |
|
213 | 219 | -- sdo => sdo(ChanelCount-1 DOWNTO 0), -- |
|
214 | 220 | -- sample => sample, |
|
215 | 221 | -- sample_val => sample_val); |
|
216 | 222 | |
|
217 | 223 | all_channel: FOR i IN 7 DOWNTO 0 GENERATE |
|
218 | 224 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
|
219 | 225 | END GENERATE all_channel; |
|
220 | 226 | |
|
221 | 227 | |
|
222 | 228 | wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE |
|
223 | 229 | |
|
224 | 230 | lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip |
|
225 | 231 | GENERIC MAP ( |
|
226 | 232 | hindex => hindex, |
|
227 | 233 | nb_burst_available_size => nb_burst_available_size, |
|
228 | 234 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
229 | 235 | delta_snapshot_size => delta_snapshot_size, |
|
230 | 236 | delta_f2_f0_size => delta_f2_f0_size, |
|
231 | 237 | delta_f2_f1_size => delta_f2_f1_size, |
|
232 | 238 | tech => tech, |
|
233 | 239 | Mem_use => use_RAM |
|
234 | 240 | ) |
|
235 | 241 | PORT MAP ( |
|
236 | 242 | sample => sample_s, |
|
237 | 243 | sample_val => sample_val, |
|
238 | 244 | |
|
239 | 245 | cnv_clk => HCLK,--cnv_clk, |
|
240 | 246 | cnv_rstn => HRESETn,--cnv_rstn, |
|
241 | 247 | |
|
242 | 248 | clk => HCLK, |
|
243 | 249 | rstn => HRESETn, |
|
244 | 250 | |
|
245 | 251 | sample_f0_wen => sample_f0_wen, |
|
246 | 252 | sample_f0_wdata => sample_f0_wdata, |
|
247 | 253 | sample_f1_wen => sample_f1_wen, |
|
248 | 254 | sample_f1_wdata => sample_f1_wdata, |
|
249 | 255 | sample_f2_wen => sample_f2_wen, |
|
250 | 256 | sample_f2_wdata => sample_f2_wdata, |
|
251 | 257 | sample_f3_wen => sample_f3_wen, |
|
252 | 258 | sample_f3_wdata => sample_f3_wdata, |
|
253 | 259 | AHB_Master_In => AHB_Master_In, |
|
254 | 260 | AHB_Master_Out => AHB_Master_Out, |
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255 | 261 | coarse_time_0 => coarse_time_0, |
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256 | 262 | data_shaping_SP0 => data_shaping_SP0, |
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257 | 263 | data_shaping_SP1 => data_shaping_SP1, |
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258 | 264 | data_shaping_R0 => data_shaping_R0, |
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259 | 265 | data_shaping_R1 => data_shaping_R1, |
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260 | 266 | delta_snapshot => delta_snapshot, |
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261 | 267 | delta_f2_f1 => delta_f2_f1, |
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262 | 268 | delta_f2_f0 => delta_f2_f0, |
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263 | 269 | enable_f0 => enable_f0, |
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264 | 270 | enable_f1 => enable_f1, |
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265 | 271 | enable_f2 => enable_f2, |
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266 | 272 | enable_f3 => enable_f3, |
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267 | 273 | burst_f0 => burst_f0, |
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268 | 274 | burst_f1 => burst_f1, |
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269 | 275 | burst_f2 => burst_f2, |
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270 | 276 | nb_burst_available => nb_burst_available, |
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271 | 277 | nb_snapshot_param => nb_snapshot_param, |
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272 | 278 | status_full => status_full, |
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273 | 279 | status_full_ack => status_full_ack, |
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274 | 280 | status_full_err => status_full_err, |
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275 | 281 | status_new_err => status_new_err, |
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276 | 282 | addr_data_f0 => addr_data_f0, |
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277 | 283 | addr_data_f1 => addr_data_f1, |
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278 | 284 | addr_data_f2 => addr_data_f2, |
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279 | 285 | addr_data_f3 => addr_data_f3); |
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280 | 286 | |
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281 | 287 | END GENERATE wf_picker_with_filter; |
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282 | 288 | |
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283 | 289 | |
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284 | 290 | wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE |
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285 | 291 | |
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286 | 292 | lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter |
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287 | 293 | GENERIC MAP ( |
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288 | 294 | hindex => hindex, |
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289 | 295 | nb_burst_available_size => nb_burst_available_size, |
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290 | 296 | nb_snapshot_param_size => nb_snapshot_param_size, |
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291 | 297 | delta_snapshot_size => delta_snapshot_size, |
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292 | 298 | delta_f2_f0_size => delta_f2_f0_size, |
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293 | 299 | delta_f2_f1_size => delta_f2_f1_size, |
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294 | 300 | tech => tech |
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295 | 301 | ) |
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296 | 302 | PORT MAP ( |
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297 | 303 | sample => sample_s, |
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298 | 304 | sample_val => sample_val, |
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299 | 305 | |
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300 | 306 | cnv_clk => cnv_clk, |
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301 | 307 | cnv_rstn => cnv_rstn, |
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302 | 308 | |
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303 | 309 | clk => HCLK, |
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304 | 310 | rstn => HRESETn, |
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305 | 311 | |
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306 | 312 | sample_f0_wen => sample_f0_wen, |
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307 | 313 | sample_f0_wdata => sample_f0_wdata, |
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308 | 314 | sample_f1_wen => sample_f1_wen, |
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309 | 315 | sample_f1_wdata => sample_f1_wdata, |
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310 | 316 | sample_f2_wen => sample_f2_wen, |
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311 | 317 | sample_f2_wdata => sample_f2_wdata, |
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312 | 318 | sample_f3_wen => sample_f3_wen, |
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313 | 319 | sample_f3_wdata => sample_f3_wdata, |
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314 | 320 | AHB_Master_In => AHB_Master_In, |
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315 | 321 | AHB_Master_Out => AHB_Master_Out, |
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316 | 322 | coarse_time_0 => coarse_time_0, |
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317 | 323 | data_shaping_SP0 => data_shaping_SP0, |
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318 | 324 | data_shaping_SP1 => data_shaping_SP1, |
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319 | 325 | data_shaping_R0 => data_shaping_R0, |
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320 | 326 | data_shaping_R1 => data_shaping_R1, |
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321 | 327 | delta_snapshot => delta_snapshot, |
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322 | 328 | delta_f2_f1 => delta_f2_f1, |
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323 | 329 | delta_f2_f0 => delta_f2_f0, |
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324 | 330 | enable_f0 => enable_f0, |
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325 | 331 | enable_f1 => enable_f1, |
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326 | 332 | enable_f2 => enable_f2, |
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327 | 333 | enable_f3 => enable_f3, |
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328 | 334 | burst_f0 => burst_f0, |
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329 | 335 | burst_f1 => burst_f1, |
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330 | 336 | burst_f2 => burst_f2, |
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331 | 337 | nb_burst_available => nb_burst_available, |
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332 | 338 | nb_snapshot_param => nb_snapshot_param, |
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333 | 339 | status_full => status_full, |
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334 | 340 | status_full_ack => status_full_ack, |
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335 | 341 | status_full_err => status_full_err, |
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336 | 342 | status_new_err => status_new_err, |
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337 | 343 | addr_data_f0 => addr_data_f0, |
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338 | 344 | addr_data_f1 => addr_data_f1, |
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339 | 345 | addr_data_f2 => addr_data_f2, |
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340 | 346 | addr_data_f3 => addr_data_f3); |
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341 | 347 | |
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342 | 348 | END GENERATE wf_picker_without_filter; |
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343 | 349 | END tb; |
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