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- Update files to simulate with questasim...
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 -- HK ---------------------------------------------------------------------
86 HK_smpclk : OUT STD_LOGIC;
87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
85 ---------------------------------------------------------------------------
89 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
90 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
92 );
89
93
90 END LFR_em;
94 END LFR_em;
91
95
92
96
93 ARCHITECTURE beh OF LFR_em IS
97 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
98 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
99 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
100 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
101 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
104
101 -- CONSTANTS
105 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
106 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
110
107 SIGNAL apbi_ext : apb_slv_in_type;
111 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
117
114 -- Spacewire signals
118 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
122 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
123 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
124 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
125 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
126 SIGNAL swno : grspw_out_type;
123
127
124 --GPIO
128 --GPIO
125 SIGNAL gpioi : gpio_in_type;
129 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
130 SIGNAL gpioo : gpio_out_type;
127
131
128 -- AD Converter ADS7886
132 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
133 SIGNAL sample : Samples14v(8 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
134 SIGNAL sample_s : Samples(8 DOWNTO 0);
131 SIGNAL sample_val : STD_LOGIC;
135 SIGNAL sample_val : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135
137
136 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138
140
139 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
140 SIGNAL rstn : STD_LOGIC;
142 SIGNAL rstn : STD_LOGIC;
141
143
142 SIGNAL LFR_soft_rstn : STD_LOGIC;
144 SIGNAL LFR_soft_rstn : STD_LOGIC;
143 SIGNAL LFR_rstn : STD_LOGIC;
145 SIGNAL LFR_rstn : STD_LOGIC;
144
146
145 SIGNAL ADC_smpclk_s : STD_LOGIC;
147 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 -----------------------------------------------------------------------------
149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
146
150
147 BEGIN -- beh
151 BEGIN -- beh
148
152
149 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
150 -- CLK
154 -- CLK
151 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
152 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
153
157
154 PROCESS(clk100MHz)
158 PROCESS(clk100MHz)
155 BEGIN
159 BEGIN
156 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
157 clk_50_s <= NOT clk_50_s;
161 clk_50_s <= NOT clk_50_s;
158 END IF;
162 END IF;
159 END PROCESS;
163 END PROCESS;
160
164
161 PROCESS(clk_50_s)
165 PROCESS(clk_50_s)
162 BEGIN
166 BEGIN
163 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
164 clk_25 <= NOT clk_25;
168 clk_25 <= NOT clk_25;
165 END IF;
169 END IF;
166 END PROCESS;
170 END PROCESS;
167
171
168 PROCESS(clk49_152MHz)
172 PROCESS(clk49_152MHz)
169 BEGIN
173 BEGIN
170 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
171 clk_24 <= NOT clk_24;
175 clk_24 <= NOT clk_24;
172 END IF;
176 END IF;
173 END PROCESS;
177 END PROCESS;
174
178
175 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
176
180
177 PROCESS (clk_25, rstn)
181 PROCESS (clk_25, rstn)
178 BEGIN -- PROCESS
182 BEGIN -- PROCESS
179 IF rstn = '0' THEN -- asynchronous reset (active low)
183 IF rstn = '0' THEN -- asynchronous reset (active low)
180 led(0) <= '0';
184 led(0) <= '0';
181 led(1) <= '0';
185 led(1) <= '0';
182 led(2) <= '0';
186 led(2) <= '0';
183 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
184 led(0) <= '0';
188 led(0) <= '0';
185 led(1) <= '1';
189 led(1) <= '1';
186 led(2) <= '1';
190 led(2) <= '1';
187 END IF;
191 END IF;
188 END PROCESS;
192 END PROCESS;
189
193
190 --
194 --
191 leon3_soc_1 : leon3_soc
195 leon3_soc_1 : leon3_soc
192 GENERIC MAP (
196 GENERIC MAP (
193 fabtech => apa3e,
197 fabtech => apa3e,
194 memtech => apa3e,
198 memtech => apa3e,
195 padtech => inferred,
199 padtech => inferred,
196 clktech => inferred,
200 clktech => inferred,
197 disas => 0,
201 disas => 0,
198 dbguart => 0,
202 dbguart => 0,
199 pclow => 2,
203 pclow => 2,
200 clk_freq => 25000,
204 clk_freq => 25000,
201 NB_CPU => 1,
205 NB_CPU => 1,
202 ENABLE_FPU => 1,
206 ENABLE_FPU => 1,
203 FPU_NETLIST => 0,
207 FPU_NETLIST => 0,
204 ENABLE_DSU => 1,
208 ENABLE_DSU => 1,
205 ENABLE_AHB_UART => 1,
209 ENABLE_AHB_UART => 1,
206 ENABLE_APB_UART => 1,
210 ENABLE_APB_UART => 1,
207 ENABLE_IRQMP => 1,
211 ENABLE_IRQMP => 1,
208 ENABLE_GPT => 1,
212 ENABLE_GPT => 1,
209 NB_AHB_MASTER => NB_AHB_MASTER,
213 NB_AHB_MASTER => NB_AHB_MASTER,
210 NB_AHB_SLAVE => NB_AHB_SLAVE,
214 NB_AHB_SLAVE => NB_AHB_SLAVE,
211 NB_APB_SLAVE => NB_APB_SLAVE)
215 NB_APB_SLAVE => NB_APB_SLAVE,
216 ADDRESS_SIZE => 20,
217 USES_IAP_MEMCTRLR => 0)
212 PORT MAP (
218 PORT MAP (
213 clk => clk_25,
219 clk => clk_25,
214 reset => rstn,
220 reset => rstn,
215 errorn => OPEN,
221 errorn => OPEN,
216
222
217 ahbrxd => TAG1,
223 ahbrxd => TAG1,
218 ahbtxd => TAG3,
224 ahbtxd => TAG3,
219 urxd1 => TAG2,
225 urxd1 => TAG2,
220 utxd1 => TAG4,
226 utxd1 => TAG4,
221
227
222 address => address,
228 address => address,
223 data => data,
229 data => data,
224 nSRAM_BE0 => nSRAM_BE0,
230 nSRAM_BE0 => nSRAM_BE0,
225 nSRAM_BE1 => nSRAM_BE1,
231 nSRAM_BE1 => nSRAM_BE1,
226 nSRAM_BE2 => nSRAM_BE2,
232 nSRAM_BE2 => nSRAM_BE2,
227 nSRAM_BE3 => nSRAM_BE3,
233 nSRAM_BE3 => nSRAM_BE3,
228 nSRAM_WE => nSRAM_WE,
234 nSRAM_WE => nSRAM_WE,
229 nSRAM_CE => nSRAM_CE,
235 nSRAM_CE => nSRAM_CE_s,
230 nSRAM_OE => nSRAM_OE,
236 nSRAM_OE => nSRAM_OE,
237 nSRAM_READY => '0',
238 SRAM_MBE => OPEN,
231
239
232 apbi_ext => apbi_ext,
240 apbi_ext => apbi_ext,
233 apbo_ext => apbo_ext,
241 apbo_ext => apbo_ext,
234 ahbi_s_ext => ahbi_s_ext,
242 ahbi_s_ext => ahbi_s_ext,
235 ahbo_s_ext => ahbo_s_ext,
243 ahbo_s_ext => ahbo_s_ext,
236 ahbi_m_ext => ahbi_m_ext,
244 ahbi_m_ext => ahbi_m_ext,
237 ahbo_m_ext => ahbo_m_ext);
245 ahbo_m_ext => ahbo_m_ext);
238
246
239
247
248 nSRAM_CE <= nSRAM_CE_s(0);
249
240 -------------------------------------------------------------------------------
250 -------------------------------------------------------------------------------
241 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
242 -------------------------------------------------------------------------------
252 -------------------------------------------------------------------------------
243 apb_lfr_time_management_1 : apb_lfr_time_management
253 apb_lfr_time_management_1 : apb_lfr_time_management
244 GENERIC MAP (
254 GENERIC MAP (
245 pindex => 6,
255 pindex => 6,
246 paddr => 6,
256 paddr => 6,
247 pmask => 16#fff#,
257 pmask => 16#fff#,
248 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
249 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
250 PORT MAP (
260 PORT MAP (
251 clk25MHz => clk_25,
261 clk25MHz => clk_25,
252 clk24_576MHz => clk_24, -- 49.152MHz/2
262 clk24_576MHz => clk_24, -- 49.152MHz/2
253 resetn => rstn,
263 resetn => rstn,
254 grspw_tick => swno.tickout,
264 grspw_tick => swno.tickout,
255 apbi => apbi_ext,
265 apbi => apbi_ext,
256 apbo => apbo_ext(6),
266 apbo => apbo_ext(6),
257 coarse_time => coarse_time,
267 coarse_time => coarse_time,
258 fine_time => fine_time,
268 fine_time => fine_time,
259 LFR_soft_rstn => LFR_soft_rstn
269 LFR_soft_rstn => LFR_soft_rstn
260 );
270 );
261
271
262 -----------------------------------------------------------------------
272 -----------------------------------------------------------------------
263 --- SpaceWire --------------------------------------------------------
273 --- SpaceWire --------------------------------------------------------
264 -----------------------------------------------------------------------
274 -----------------------------------------------------------------------
265
275
266 -- SPW_EN <= '1';
276 -- SPW_EN <= '1';
267
277
268 spw_clk <= clk_50_s;
278 spw_clk <= clk_50_s;
269 spw_rxtxclk <= spw_clk;
279 spw_rxtxclk <= spw_clk;
270 spw_rxclkn <= NOT spw_rxtxclk;
280 spw_rxclkn <= NOT spw_rxtxclk;
271
281
272 -- PADS for SPW1
282 -- PADS for SPW1
273 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
283 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
274 PORT MAP (spw1_din, dtmp(0));
284 PORT MAP (spw1_din, dtmp(0));
275 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
285 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
276 PORT MAP (spw1_sin, stmp(0));
286 PORT MAP (spw1_sin, stmp(0));
277 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
287 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
278 PORT MAP (spw1_dout, swno.d(0));
288 PORT MAP (spw1_dout, swno.d(0));
279 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
289 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
280 PORT MAP (spw1_sout, swno.s(0));
290 PORT MAP (spw1_sout, swno.s(0));
281 -- PADS FOR SPW2
291 -- PADS FOR SPW2
282 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
292 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
283 PORT MAP (spw2_din, dtmp(1));
293 PORT MAP (spw2_din, dtmp(1));
284 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
294 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
285 PORT MAP (spw2_sin, stmp(1));
295 PORT MAP (spw2_sin, stmp(1));
286 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
296 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
287 PORT MAP (spw2_dout, swno.d(1));
297 PORT MAP (spw2_dout, swno.d(1));
288 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
298 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
289 PORT MAP (spw2_sout, swno.s(1));
299 PORT MAP (spw2_sout, swno.s(1));
290
300
291 -- GRSPW PHY
301 -- GRSPW PHY
292 --spw1_input: if CFG_SPW_GRSPW = 1 generate
302 --spw1_input: if CFG_SPW_GRSPW = 1 generate
293 spw_inputloop : FOR j IN 0 TO 1 GENERATE
303 spw_inputloop : FOR j IN 0 TO 1 GENERATE
294 spw_phy0 : grspw_phy
304 spw_phy0 : grspw_phy
295 GENERIC MAP(
305 GENERIC MAP(
296 tech => apa3e,
306 tech => apa3e,
297 rxclkbuftype => 1,
307 rxclkbuftype => 1,
298 scantest => 0)
308 scantest => 0)
299 PORT MAP(
309 PORT MAP(
300 rxrst => swno.rxrst,
310 rxrst => swno.rxrst,
301 di => dtmp(j),
311 di => dtmp(j),
302 si => stmp(j),
312 si => stmp(j),
303 rxclko => spw_rxclk(j),
313 rxclko => spw_rxclk(j),
304 do => swni.d(j),
314 do => swni.d(j),
305 ndo => swni.nd(j*5+4 DOWNTO j*5),
315 ndo => swni.nd(j*5+4 DOWNTO j*5),
306 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
316 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
307 END GENERATE spw_inputloop;
317 END GENERATE spw_inputloop;
308
318
309 -- SPW core
319 -- SPW core
310 sw0 : grspwm GENERIC MAP(
320 sw0 : grspwm GENERIC MAP(
311 tech => apa3e,
321 tech => apa3e,
312 hindex => 1,
322 hindex => 1,
313 pindex => 5,
323 pindex => 5,
314 paddr => 5,
324 paddr => 5,
315 pirq => 11,
325 pirq => 11,
316 sysfreq => 25000, -- CPU_FREQ
326 sysfreq => 25000, -- CPU_FREQ
317 rmap => 1,
327 rmap => 1,
318 rmapcrc => 1,
328 rmapcrc => 1,
319 fifosize1 => 16,
329 fifosize1 => 16,
320 fifosize2 => 16,
330 fifosize2 => 16,
321 rxclkbuftype => 1,
331 rxclkbuftype => 1,
322 rxunaligned => 0,
332 rxunaligned => 0,
323 rmapbufs => 4,
333 rmapbufs => 4,
324 ft => 0,
334 ft => 0,
325 netlist => 0,
335 netlist => 0,
326 ports => 2,
336 ports => 2,
327 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
337 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
328 memtech => apa3e,
338 memtech => apa3e,
329 destkey => 2,
339 destkey => 2,
330 spwcore => 1
340 spwcore => 1
331 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
341 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
332 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
342 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
333 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
343 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
334 )
344 )
335 PORT MAP(rstn, clk_25, spw_rxclk(0),
345 PORT MAP(rstn, clk_25, spw_rxclk(0),
336 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
346 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
337 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
347 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
338 swni, swno);
348 swni, swno);
339
349
340 swni.tickin <= '0';
350 swni.tickin <= '0';
341 swni.rmapen <= '1';
351 swni.rmapen <= '1';
342 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
352 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
343 swni.tickinraw <= '0';
353 swni.tickinraw <= '0';
344 swni.timein <= (OTHERS => '0');
354 swni.timein <= (OTHERS => '0');
345 swni.dcrstval <= (OTHERS => '0');
355 swni.dcrstval <= (OTHERS => '0');
346 swni.timerrstval <= (OTHERS => '0');
356 swni.timerrstval <= (OTHERS => '0');
347
357
348 -------------------------------------------------------------------------------
358 -------------------------------------------------------------------------------
349 -- LFR ------------------------------------------------------------------------
359 -- LFR ------------------------------------------------------------------------
350 -------------------------------------------------------------------------------
360 -------------------------------------------------------------------------------
351 LFR_rstn <= LFR_soft_rstn AND rstn;
361 LFR_rstn <= LFR_soft_rstn AND rstn;
352
362
353 lpp_lfr_1 : lpp_lfr
363 lpp_lfr_1 : lpp_lfr
354 GENERIC MAP (
364 GENERIC MAP (
355 Mem_use => use_RAM,
365 Mem_use => use_RAM,
356 nb_data_by_buffer_size => 32,
366 nb_data_by_buffer_size => 32,
357 --nb_word_by_buffer_size => 30,
367 --nb_word_by_buffer_size => 30,
358 nb_snapshot_param_size => 32,
368 nb_snapshot_param_size => 32,
359 delta_vector_size => 32,
369 delta_vector_size => 32,
360 delta_vector_size_f0_2 => 7, -- log2(96)
370 delta_vector_size_f0_2 => 7, -- log2(96)
361 pindex => 15,
371 pindex => 15,
362 paddr => 15,
372 paddr => 15,
363 pmask => 16#fff#,
373 pmask => 16#fff#,
364 pirq_ms => 6,
374 pirq_ms => 6,
365 pirq_wfp => 14,
375 pirq_wfp => 14,
366 hindex => 2,
376 hindex => 2,
367 top_lfr_version => X"010123") -- aa.bb.cc version
377 top_lfr_version => X"01012D") -- aa.bb.cc version
368 -- AA : BOARD NUMBER
378 -- AA : BOARD NUMBER
369 -- 0 => MINI_LFR
379 -- 0 => MINI_LFR
370 -- 1 => EM
380 -- 1 => EM
371 PORT MAP (
381 PORT MAP (
372 clk => clk_25,
382 clk => clk_25,
373 rstn => LFR_rstn,
383 rstn => LFR_rstn,
374 sample_B => sample_s(2 DOWNTO 0),
384 sample_B => sample_s(2 DOWNTO 0),
375 sample_E => sample_s(7 DOWNTO 3),
385 sample_E => sample_s(7 DOWNTO 3),
376 sample_val => sample_val,
386 sample_val => sample_val,
377 apbi => apbi_ext,
387 apbi => apbi_ext,
378 apbo => apbo_ext(15),
388 apbo => apbo_ext(15),
379 ahbi => ahbi_m_ext,
389 ahbi => ahbi_m_ext,
380 ahbo => ahbo_m_ext(2),
390 ahbo => ahbo_m_ext(2),
381 coarse_time => coarse_time,
391 coarse_time => coarse_time,
382 fine_time => fine_time,
392 fine_time => fine_time,
383 data_shaping_BW => bias_fail_sw);--,
393 data_shaping_BW => bias_fail_sw,
394 debug_vector => OPEN,
395 debug_vector_ms => OPEN); --,
384 --observation_vector_0 => OPEN,
396 --observation_vector_0 => OPEN,
385 --observation_vector_1 => OPEN,
397 --observation_vector_1 => OPEN,
386 --observation_reg => observation_reg);
398 --observation_reg => observation_reg);
387
399
388
400
389 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
401 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
390 sample_s(I) <= sample(I) & '0' & '0';
402 sample_s(I) <= sample(I) & '0' & '0';
391 END GENERATE all_sample;
403 END GENERATE all_sample;
392
404 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
405
393 -----------------------------------------------------------------------------
406 -----------------------------------------------------------------------------
394 --
407 --
395 -----------------------------------------------------------------------------
408 -----------------------------------------------------------------------------
396 top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
409 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
397 GENERIC MAP (
410 GENERIC MAP (
398 ChanelCount => 8,
411 ChanelCount => 9,
399 ncycle_cnv_high => 13,
412 ncycle_cnv_high => 13,
400 ncycle_cnv => 25)
413 ncycle_cnv => 25,
414 FILTER_ENABLED => 16#FF#)
401 PORT MAP (
415 PORT MAP (
402 cnv_clk => clk_24,
416 cnv_clk => clk_24,
403 cnv_rstn => rstn,
417 cnv_rstn => rstn,
404 cnv => ADC_smpclk_s,
418 cnv => ADC_smpclk_s,
405 clk => clk_25,
419 clk => clk_25,
406 rstn => rstn,
420 rstn => rstn,
407 ADC_data => ADC_data,
421 ADC_data => ADC_data,
408 ADC_nOE => ADC_OEB_bar_CH,
422 ADC_nOE => ADC_OEB_bar_CH_s,
409 sample => sample,
423 sample => sample,
410 sample_val => sample_val);
424 sample_val => sample_val);
411
425
412
426 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
413
414
415 --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
416 -- GENERIC MAP (
417 -- ChanelCount => 8,
418 -- ncycle_cnv_high => 40, -- TODO : 79
419 -- ncycle_cnv => 250) -- TODO : 500
420 -- PORT MAP (
421 -- cnv_clk => clk_24, -- TODO : 49.152
422 -- cnv_rstn => rstn, -- ok
423 -- cnv => ADC_smpclk_s, -- ok
424 -- clk => clk_25, -- ok
425 -- rstn => rstn, -- ok
426 -- ADC_data => ADC_data, -- ok
427 -- ADC_nOE => ADC_OEB_bar_CH, -- ok
428 -- sample => sample, -- ok
429 -- sample_val => sample_val); -- ok
430
427
431 ADC_smpclk <= ADC_smpclk_s;
428 ADC_smpclk <= ADC_smpclk_s;
432
429 HK_smpclk <= ADC_smpclk_s;
430
433 TAG8 <= ADC_smpclk_s;
431 TAG8 <= ADC_smpclk_s;
434
432
433 -----------------------------------------------------------------------------
434 -- HK
435 -----------------------------------------------------------------------------
436 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
437
438 lpp_lfr_hk_1: lpp_lfr_hk
439 GENERIC MAP (
440 pindex => 7,
441 paddr => 7,
442 pmask => 16#fff#)
443 PORT MAP (
444 clk => clk_25,
445 rstn => rstn,
446
447 apbi => apbi_ext,
448 apbo => apbo_ext(7),
449
450 sample_val => sample_val,
451 sample => sample_s(8),
452 HK_SEL => HK_SEL);
453
435 END beh;
454 END beh;
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@@ -1,56 +1,59
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
5 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 #VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK.pdc
22
22
23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
25
25
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
27 CLEAN=soft-clean
27 CLEAN=soft-clean
28
28
29 TECHLIBS = proasic3e
29 TECHLIBS = proasic3e
30
30
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
31 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
32 tmtc openchip hynix ihp gleichmann micron usbhc
32 tmtc openchip hynix ihp gleichmann micron usbhc
33
33
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
34 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
35 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
36 ./amba_lcd_16x2_ctrlr \
36 ./amba_lcd_16x2_ctrlr \
37 ./general_purpose/lpp_AMR \
37 ./general_purpose/lpp_AMR \
38 ./general_purpose/lpp_balise \
38 ./general_purpose/lpp_balise \
39 ./general_purpose/lpp_delay \
39 ./general_purpose/lpp_delay \
40 ./lpp_bootloader \
40 ./lpp_bootloader \
41 ./lpp_cna \
41 ./lpp_cna \
42 ./dsp/lpp_fft_rtax \
42 ./dsp/lpp_fft_rtax \
43 ./lpp_uart \
43 ./lpp_uart \
44 ./lpp_usb \
44 ./lpp_usb \
45 ./lpp_sim/CY7C1061DV33 \
45
46
46 FILESKIP = i2cmst.vhd \
47 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
49 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
50 Top_MatrixSpec.vhd \
50 APB_FFT.vhd
51 APB_FFT.vhd\
52 CoreFFT_simu.vhd \
53 lpp_lfr_apbreg_simu.vhd
51
54
52 include $(GRLIB)/bin/Makefile
55 include $(GRLIB)/bin/Makefile
53 include $(GRLIB)/software/leon3/Makefile
56 include $(GRLIB)/software/leon3/Makefile
54
57
55 ################## project specific targets ##########################
58 ################## project specific targets ##########################
56
59
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@@ -1,720 +1,720
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 --
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
198
199 BEGIN -- beh
199 BEGIN -- beh
200
200
201 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
202 -- CLK
202 -- CLK
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204
204
205 --PROCESS(clk_50)
205 --PROCESS(clk_50)
206 --BEGIN
206 --BEGIN
207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
208 -- clk_50_s <= NOT clk_50_s;
208 -- clk_50_s <= NOT clk_50_s;
209 -- END IF;
209 -- END IF;
210 --END PROCESS;
210 --END PROCESS;
211
211
212 --PROCESS(clk_50_s)
212 --PROCESS(clk_50_s)
213 --BEGIN
213 --BEGIN
214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
215 -- clk_25 <= NOT clk_25;
215 -- clk_25 <= NOT clk_25;
216 -- END IF;
216 -- END IF;
217 --END PROCESS;
217 --END PROCESS;
218
218
219 --PROCESS(clk_49)
219 --PROCESS(clk_49)
220 --BEGIN
220 --BEGIN
221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
222 -- clk_24 <= NOT clk_24;
222 -- clk_24 <= NOT clk_24;
223 -- END IF;
223 -- END IF;
224 --END PROCESS;
224 --END PROCESS;
225
225
226 --PROCESS(clk_25)
226 --PROCESS(clk_25)
227 --BEGIN
227 --BEGIN
228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
229 -- rstn_25 <= reset;
229 -- rstn_25 <= reset;
230 -- END IF;
230 -- END IF;
231 --END PROCESS;
231 --END PROCESS;
232
232
233 PROCESS (clk_50, reset)
233 PROCESS (clk_50, reset)
234 BEGIN -- PROCESS
234 BEGIN -- PROCESS
235 IF reset = '0' THEN -- asynchronous reset (active low)
235 IF reset = '0' THEN -- asynchronous reset (active low)
236 clk_50_s <= '0';
236 clk_50_s <= '0';
237 rstn_50 <= '0';
237 rstn_50 <= '0';
238 rstn_50_d1 <= '0';
238 rstn_50_d1 <= '0';
239 rstn_50_d2 <= '0';
239 rstn_50_d2 <= '0';
240 rstn_50_d3 <= '0';
240 rstn_50_d3 <= '0';
241
241
242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
243 clk_50_s <= NOT clk_50_s;
243 clk_50_s <= NOT clk_50_s;
244 rstn_50_d1 <= '1';
244 rstn_50_d1 <= '1';
245 rstn_50_d2 <= rstn_50_d1;
245 rstn_50_d2 <= rstn_50_d1;
246 rstn_50_d3 <= rstn_50_d2;
246 rstn_50_d3 <= rstn_50_d2;
247 rstn_50 <= rstn_50_d3;
247 rstn_50 <= rstn_50_d3;
248 END IF;
248 END IF;
249 END PROCESS;
249 END PROCESS;
250
250
251 PROCESS (clk_50_s, rstn_50)
251 PROCESS (clk_50_s, rstn_50)
252 BEGIN -- PROCESS
252 BEGIN -- PROCESS
253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
254 clk_25 <= '0';
254 clk_25 <= '0';
255 rstn_25 <= '0';
255 rstn_25 <= '0';
256 rstn_25_d1 <= '0';
256 rstn_25_d1 <= '0';
257 rstn_25_d2 <= '0';
257 rstn_25_d2 <= '0';
258 rstn_25_d3 <= '0';
258 rstn_25_d3 <= '0';
259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
260 clk_25 <= NOT clk_25;
260 clk_25 <= NOT clk_25;
261 rstn_25_d1 <= '1';
261 rstn_25_d1 <= '1';
262 rstn_25_d2 <= rstn_25_d1;
262 rstn_25_d2 <= rstn_25_d1;
263 rstn_25_d3 <= rstn_25_d2;
263 rstn_25_d3 <= rstn_25_d2;
264 rstn_25 <= rstn_25_d3;
264 rstn_25 <= rstn_25_d3;
265 END IF;
265 END IF;
266 END PROCESS;
266 END PROCESS;
267
267
268 PROCESS (clk_49, reset)
268 PROCESS (clk_49, reset)
269 BEGIN -- PROCESS
269 BEGIN -- PROCESS
270 IF reset = '0' THEN -- asynchronous reset (active low)
270 IF reset = '0' THEN -- asynchronous reset (active low)
271 clk_24 <= '0';
271 clk_24 <= '0';
272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
273 clk_24 <= NOT clk_24;
273 clk_24 <= NOT clk_24;
274 END IF;
274 END IF;
275 END PROCESS;
275 END PROCESS;
276
276
277 -----------------------------------------------------------------------------
277 -----------------------------------------------------------------------------
278
278
279 PROCESS (clk_25, rstn_25)
279 PROCESS (clk_25, rstn_25)
280 BEGIN -- PROCESS
280 BEGIN -- PROCESS
281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
282 LED0 <= '0';
282 LED0 <= '0';
283 LED1 <= '0';
283 LED1 <= '0';
284 LED2 <= '0';
284 LED2 <= '0';
285 --IO1 <= '0';
285 --IO1 <= '0';
286 --IO2 <= '1';
286 --IO2 <= '1';
287 --IO3 <= '0';
287 --IO3 <= '0';
288 --IO4 <= '0';
288 --IO4 <= '0';
289 --IO5 <= '0';
289 --IO5 <= '0';
290 --IO6 <= '0';
290 --IO6 <= '0';
291 --IO7 <= '0';
291 --IO7 <= '0';
292 --IO8 <= '0';
292 --IO8 <= '0';
293 --IO9 <= '0';
293 --IO9 <= '0';
294 --IO10 <= '0';
294 --IO10 <= '0';
295 --IO11 <= '0';
295 --IO11 <= '0';
296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
297 LED0 <= '0';
297 LED0 <= '0';
298 LED1 <= '1';
298 LED1 <= '1';
299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
300 --IO1 <= '1';
300 --IO1 <= '1';
301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
302 --IO3 <= ADC_SDO(0);
302 --IO3 <= ADC_SDO(0);
303 --IO4 <= ADC_SDO(1);
303 --IO4 <= ADC_SDO(1);
304 --IO5 <= ADC_SDO(2);
304 --IO5 <= ADC_SDO(2);
305 --IO6 <= ADC_SDO(3);
305 --IO6 <= ADC_SDO(3);
306 --IO7 <= ADC_SDO(4);
306 --IO7 <= ADC_SDO(4);
307 --IO8 <= ADC_SDO(5);
307 --IO8 <= ADC_SDO(5);
308 --IO9 <= ADC_SDO(6);
308 --IO9 <= ADC_SDO(6);
309 --IO10 <= ADC_SDO(7);
309 --IO10 <= ADC_SDO(7);
310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
311 END IF;
311 END IF;
312 END PROCESS;
312 END PROCESS;
313
313
314 PROCESS (clk_24, rstn_25)
314 PROCESS (clk_24, rstn_25)
315 BEGIN -- PROCESS
315 BEGIN -- PROCESS
316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
317 I00_s <= '0';
317 I00_s <= '0';
318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
319 I00_s <= NOT I00_s;
319 I00_s <= NOT I00_s;
320 END IF;
320 END IF;
321 END PROCESS;
321 END PROCESS;
322 -- IO0 <= I00_s;
322 -- IO0 <= I00_s;
323
323
324 --UARTs
324 --UARTs
325 nCTS1 <= '1';
325 nCTS1 <= '1';
326 nCTS2 <= '1';
326 nCTS2 <= '1';
327 nDCD2 <= '1';
327 nDCD2 <= '1';
328
328
329 --EXT CONNECTOR
329 --EXT CONNECTOR
330
330
331 --SPACE WIRE
331 --SPACE WIRE
332
332
333 leon3_soc_1 : leon3_soc
333 leon3_soc_1 : leon3_soc
334 GENERIC MAP (
334 GENERIC MAP (
335 fabtech => apa3e,
335 fabtech => apa3e,
336 memtech => apa3e,
336 memtech => apa3e,
337 padtech => inferred,
337 padtech => inferred,
338 clktech => inferred,
338 clktech => inferred,
339 disas => 0,
339 disas => 0,
340 dbguart => 0,
340 dbguart => 0,
341 pclow => 2,
341 pclow => 2,
342 clk_freq => 25000,
342 clk_freq => 25000,
343 NB_CPU => 1,
343 NB_CPU => 1,
344 ENABLE_FPU => 1,
344 ENABLE_FPU => 1,
345 FPU_NETLIST => 0,
345 FPU_NETLIST => 0,
346 ENABLE_DSU => 1,
346 ENABLE_DSU => 1,
347 ENABLE_AHB_UART => 1,
347 ENABLE_AHB_UART => 1,
348 ENABLE_APB_UART => 1,
348 ENABLE_APB_UART => 1,
349 ENABLE_IRQMP => 1,
349 ENABLE_IRQMP => 1,
350 ENABLE_GPT => 1,
350 ENABLE_GPT => 1,
351 NB_AHB_MASTER => NB_AHB_MASTER,
351 NB_AHB_MASTER => NB_AHB_MASTER,
352 NB_AHB_SLAVE => NB_AHB_SLAVE,
352 NB_AHB_SLAVE => NB_AHB_SLAVE,
353 NB_APB_SLAVE => NB_APB_SLAVE,
353 NB_APB_SLAVE => NB_APB_SLAVE,
354 ADDRESS_SIZE => 20,
354 ADDRESS_SIZE => 20,
355 USES_IAP_MEMCTRLR => 0)
355 USES_IAP_MEMCTRLR => 0)
356 PORT MAP (
356 PORT MAP (
357 clk => clk_25,
357 clk => clk_25,
358 reset => rstn_25,
358 reset => rstn_25,
359 errorn => errorn,
359 errorn => errorn,
360 ahbrxd => TXD1,
360 ahbrxd => TXD1,
361 ahbtxd => RXD1,
361 ahbtxd => RXD1,
362 urxd1 => TXD2,
362 urxd1 => TXD2,
363 utxd1 => RXD2,
363 utxd1 => RXD2,
364 address => SRAM_A,
364 address => SRAM_A,
365 data => SRAM_DQ,
365 data => SRAM_DQ,
366 nSRAM_BE0 => SRAM_nBE(0),
366 nSRAM_BE0 => SRAM_nBE(0),
367 nSRAM_BE1 => SRAM_nBE(1),
367 nSRAM_BE1 => SRAM_nBE(1),
368 nSRAM_BE2 => SRAM_nBE(2),
368 nSRAM_BE2 => SRAM_nBE(2),
369 nSRAM_BE3 => SRAM_nBE(3),
369 nSRAM_BE3 => SRAM_nBE(3),
370 nSRAM_WE => SRAM_nWE,
370 nSRAM_WE => SRAM_nWE,
371 nSRAM_CE => SRAM_CE_s,
371 nSRAM_CE => SRAM_CE_s,
372 nSRAM_OE => SRAM_nOE,
372 nSRAM_OE => SRAM_nOE,
373 nSRAM_READY => '0',
373 nSRAM_READY => '0',
374 SRAM_MBE => OPEN,
374 SRAM_MBE => OPEN,
375 apbi_ext => apbi_ext,
375 apbi_ext => apbi_ext,
376 apbo_ext => apbo_ext,
376 apbo_ext => apbo_ext,
377 ahbi_s_ext => ahbi_s_ext,
377 ahbi_s_ext => ahbi_s_ext,
378 ahbo_s_ext => ahbo_s_ext,
378 ahbo_s_ext => ahbo_s_ext,
379 ahbi_m_ext => ahbi_m_ext,
379 ahbi_m_ext => ahbi_m_ext,
380 ahbo_m_ext => ahbo_m_ext);
380 ahbo_m_ext => ahbo_m_ext);
381
381
382 SRAM_CE <= SRAM_CE_s(0);
382 SRAM_CE <= SRAM_CE_s(0);
383 -------------------------------------------------------------------------------
383 -------------------------------------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
385 -------------------------------------------------------------------------------
385 -------------------------------------------------------------------------------
386 apb_lfr_time_management_1 : apb_lfr_time_management
386 apb_lfr_time_management_1 : apb_lfr_time_management
387 GENERIC MAP (
387 GENERIC MAP (
388 pindex => 6,
388 pindex => 6,
389 paddr => 6,
389 paddr => 6,
390 pmask => 16#fff#,
390 pmask => 16#fff#,
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
393 PORT MAP (
393 PORT MAP (
394 clk25MHz => clk_25,
394 clk25MHz => clk_25,
395 clk24_576MHz => clk_24, -- 49.152MHz/2
395 clk24_576MHz => clk_24, -- 49.152MHz/2
396 resetn => rstn_25,
396 resetn => rstn_25,
397 grspw_tick => swno.tickout,
397 grspw_tick => swno.tickout,
398 apbi => apbi_ext,
398 apbi => apbi_ext,
399 apbo => apbo_ext(6),
399 apbo => apbo_ext(6),
400 coarse_time => coarse_time,
400 coarse_time => coarse_time,
401 fine_time => fine_time,
401 fine_time => fine_time,
402 LFR_soft_rstn => LFR_soft_rstn
402 LFR_soft_rstn => LFR_soft_rstn
403 );
403 );
404
404
405 -----------------------------------------------------------------------
405 -----------------------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
407 -----------------------------------------------------------------------
407 -----------------------------------------------------------------------
408
408
409 SPW_EN <= '1';
409 SPW_EN <= '1';
410
410
411 spw_clk <= clk_50_s;
411 spw_clk <= clk_50_s;
412 spw_rxtxclk <= spw_clk;
412 spw_rxtxclk <= spw_clk;
413 spw_rxclkn <= NOT spw_rxtxclk;
413 spw_rxclkn <= NOT spw_rxtxclk;
414
414
415 -- PADS for SPW1
415 -- PADS for SPW1
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 PORT MAP (SPW_NOM_SIN, stmp(0));
419 PORT MAP (SPW_NOM_SIN, stmp(0));
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 -- PADS FOR SPW2
424 -- PADS FOR SPW2
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 PORT MAP (SPW_RED_SIN, dtmp(1));
426 PORT MAP (SPW_RED_SIN, dtmp(1));
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 PORT MAP (SPW_RED_DIN, stmp(1));
428 PORT MAP (SPW_RED_DIN, stmp(1));
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
433
433
434 -- GRSPW PHY
434 -- GRSPW PHY
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 spw_phy0 : grspw_phy
437 spw_phy0 : grspw_phy
438 GENERIC MAP(
438 GENERIC MAP(
439 tech => apa3e,
439 tech => apa3e,
440 rxclkbuftype => 1,
440 rxclkbuftype => 1,
441 scantest => 0)
441 scantest => 0)
442 PORT MAP(
442 PORT MAP(
443 rxrst => swno.rxrst,
443 rxrst => swno.rxrst,
444 di => dtmp(j),
444 di => dtmp(j),
445 si => stmp(j),
445 si => stmp(j),
446 rxclko => spw_rxclk(j),
446 rxclko => spw_rxclk(j),
447 do => swni.d(j),
447 do => swni.d(j),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 END GENERATE spw_inputloop;
450 END GENERATE spw_inputloop;
451
451
452 swni.rmapnodeaddr <= (OTHERS => '0');
452 swni.rmapnodeaddr <= (OTHERS => '0');
453
453
454 -- SPW core
454 -- SPW core
455 sw0 : grspwm GENERIC MAP(
455 sw0 : grspwm GENERIC MAP(
456 tech => apa3e,
456 tech => apa3e,
457 hindex => 1,
457 hindex => 1,
458 pindex => 5,
458 pindex => 5,
459 paddr => 5,
459 paddr => 5,
460 pirq => 11,
460 pirq => 11,
461 sysfreq => 25000, -- CPU_FREQ
461 sysfreq => 25000, -- CPU_FREQ
462 rmap => 1,
462 rmap => 1,
463 rmapcrc => 1,
463 rmapcrc => 1,
464 fifosize1 => 16,
464 fifosize1 => 16,
465 fifosize2 => 16,
465 fifosize2 => 16,
466 rxclkbuftype => 1,
466 rxclkbuftype => 1,
467 rxunaligned => 0,
467 rxunaligned => 0,
468 rmapbufs => 4,
468 rmapbufs => 4,
469 ft => 0,
469 ft => 0,
470 netlist => 0,
470 netlist => 0,
471 ports => 2,
471 ports => 2,
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 memtech => apa3e,
473 memtech => apa3e,
474 destkey => 2,
474 destkey => 2,
475 spwcore => 1
475 spwcore => 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 )
479 )
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 swni, swno);
483 swni, swno);
484
484
485 swni.tickin <= '0';
485 swni.tickin <= '0';
486 swni.rmapen <= '1';
486 swni.rmapen <= '1';
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 swni.tickinraw <= '0';
488 swni.tickinraw <= '0';
489 swni.timein <= (OTHERS => '0');
489 swni.timein <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
492
492
493 -------------------------------------------------------------------------------
493 -------------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
496
496
497
497
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 --LFR_rstn <= rstn_25;
499 --LFR_rstn <= rstn_25;
500
500
501 lpp_lfr_1 : lpp_lfr
501 lpp_lfr_1 : lpp_lfr
502 GENERIC MAP (
502 GENERIC MAP (
503 Mem_use => use_RAM,
503 Mem_use => use_RAM,
504 nb_data_by_buffer_size => 32,
504 nb_data_by_buffer_size => 32,
505 nb_snapshot_param_size => 32,
505 nb_snapshot_param_size => 32,
506 delta_vector_size => 32,
506 delta_vector_size => 32,
507 delta_vector_size_f0_2 => 7, -- log2(96)
507 delta_vector_size_f0_2 => 7, -- log2(96)
508 pindex => 15,
508 pindex => 15,
509 paddr => 15,
509 paddr => 15,
510 pmask => 16#fff#,
510 pmask => 16#fff#,
511 pirq_ms => 6,
511 pirq_ms => 6,
512 pirq_wfp => 14,
512 pirq_wfp => 14,
513 hindex => 2,
513 hindex => 2,
514 top_lfr_version => X"00012A") -- aa.bb.cc version
514 top_lfr_version => X"00012C") -- aa.bb.cc version
515 PORT MAP (
515 PORT MAP (
516 clk => clk_25,
516 clk => clk_25,
517 rstn => LFR_rstn,
517 rstn => LFR_rstn,
518 sample_B => sample_s(2 DOWNTO 0),
518 sample_B => sample_s(2 DOWNTO 0),
519 sample_E => sample_s(7 DOWNTO 3),
519 sample_E => sample_s(7 DOWNTO 3),
520 sample_val => sample_val,
520 sample_val => sample_val,
521 apbi => apbi_ext,
521 apbi => apbi_ext,
522 apbo => apbo_ext(15),
522 apbo => apbo_ext(15),
523 ahbi => ahbi_m_ext,
523 ahbi => ahbi_m_ext,
524 ahbo => ahbo_m_ext(2),
524 ahbo => ahbo_m_ext(2),
525 coarse_time => coarse_time,
525 coarse_time => coarse_time,
526 fine_time => fine_time,
526 fine_time => fine_time,
527 data_shaping_BW => bias_fail_sw_sig,
527 data_shaping_BW => bias_fail_sw_sig,
528 debug_vector => lfr_debug_vector,
528 debug_vector => lfr_debug_vector,
529 debug_vector_ms => lfr_debug_vector_ms
529 debug_vector_ms => lfr_debug_vector_ms
530 );
530 );
531
531
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 IO0 <= rstn_25;
536 IO0 <= rstn_25;
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544
544
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 END GENERATE all_sample;
547 END GENERATE all_sample;
548
548
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 GENERIC MAP(
550 GENERIC MAP(
551 ChannelCount => 8,
551 ChannelCount => 8,
552 SampleNbBits => 14,
552 SampleNbBits => 14,
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 PORT MAP (
555 PORT MAP (
556 -- CONV
556 -- CONV
557 cnv_clk => clk_24,
557 cnv_clk => clk_24,
558 cnv_rstn => rstn_25,
558 cnv_rstn => rstn_25,
559 cnv => ADC_nCS_sig,
559 cnv => ADC_nCS_sig,
560 -- DATA
560 -- DATA
561 clk => clk_25,
561 clk => clk_25,
562 rstn => rstn_25,
562 rstn => rstn_25,
563 sck => ADC_CLK_sig,
563 sck => ADC_CLK_sig,
564 sdo => ADC_SDO_sig,
564 sdo => ADC_SDO_sig,
565 -- SAMPLE
565 -- SAMPLE
566 sample => sample,
566 sample => sample,
567 sample_val => sample_val);
567 sample_val => sample_val);
568
568
569 --IO10 <= ADC_SDO_sig(5);
569 --IO10 <= ADC_SDO_sig(5);
570 --IO9 <= ADC_SDO_sig(4);
570 --IO9 <= ADC_SDO_sig(4);
571 --IO8 <= ADC_SDO_sig(3);
571 --IO8 <= ADC_SDO_sig(3);
572
572
573 ADC_nCS <= ADC_nCS_sig;
573 ADC_nCS <= ADC_nCS_sig;
574 ADC_CLK <= ADC_CLK_sig;
574 ADC_CLK <= ADC_CLK_sig;
575 ADC_SDO_sig <= ADC_SDO;
575 ADC_SDO_sig <= ADC_SDO;
576
576
577 ----------------------------------------------------------------------
577 ----------------------------------------------------------------------
578 --- GPIO -----------------------------------------------------------
578 --- GPIO -----------------------------------------------------------
579 ----------------------------------------------------------------------
579 ----------------------------------------------------------------------
580
580
581 grgpio0 : grgpio
581 grgpio0 : grgpio
582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
584
584
585 gpioi.sig_en <= (OTHERS => '0');
585 gpioi.sig_en <= (OTHERS => '0');
586 gpioi.sig_in <= (OTHERS => '0');
586 gpioi.sig_in <= (OTHERS => '0');
587 gpioi.din <= (OTHERS => '0');
587 gpioi.din <= (OTHERS => '0');
588 --pio_pad_0 : iopad
588 --pio_pad_0 : iopad
589 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- GENERIC MAP (tech => CFG_PADTECH)
590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
591 --pio_pad_1 : iopad
591 --pio_pad_1 : iopad
592 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- GENERIC MAP (tech => CFG_PADTECH)
593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
594 --pio_pad_2 : iopad
594 --pio_pad_2 : iopad
595 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- GENERIC MAP (tech => CFG_PADTECH)
596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
597 --pio_pad_3 : iopad
597 --pio_pad_3 : iopad
598 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- GENERIC MAP (tech => CFG_PADTECH)
599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
600 --pio_pad_4 : iopad
600 --pio_pad_4 : iopad
601 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- GENERIC MAP (tech => CFG_PADTECH)
602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
603 --pio_pad_5 : iopad
603 --pio_pad_5 : iopad
604 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- GENERIC MAP (tech => CFG_PADTECH)
605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
606 --pio_pad_6 : iopad
606 --pio_pad_6 : iopad
607 -- GENERIC MAP (tech => CFG_PADTECH)
607 -- GENERIC MAP (tech => CFG_PADTECH)
608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
609 --pio_pad_7 : iopad
609 --pio_pad_7 : iopad
610 -- GENERIC MAP (tech => CFG_PADTECH)
610 -- GENERIC MAP (tech => CFG_PADTECH)
611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
612
612
613 PROCESS (clk_25, rstn_25)
613 PROCESS (clk_25, rstn_25)
614 BEGIN -- PROCESS
614 BEGIN -- PROCESS
615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
616 -- --IO0 <= '0';
616 -- --IO0 <= '0';
617 -- IO1 <= '0';
617 -- IO1 <= '0';
618 -- IO2 <= '0';
618 -- IO2 <= '0';
619 -- IO3 <= '0';
619 -- IO3 <= '0';
620 -- IO4 <= '0';
620 -- IO4 <= '0';
621 -- IO5 <= '0';
621 -- IO5 <= '0';
622 -- IO6 <= '0';
622 -- IO6 <= '0';
623 -- IO7 <= '0';
623 -- IO7 <= '0';
624 IO8 <= '0';
624 IO8 <= '0';
625 IO9 <= '0';
625 IO9 <= '0';
626 IO10 <= '0';
626 IO10 <= '0';
627 IO11 <= '0';
627 IO11 <= '0';
628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
629 CASE gpioo.dout(2 DOWNTO 0) IS
629 CASE gpioo.dout(2 DOWNTO 0) IS
630 WHEN "011" =>
630 WHEN "011" =>
631 -- --IO0 <= observation_reg(0 );
631 -- --IO0 <= observation_reg(0 );
632 -- IO1 <= observation_reg(1 );
632 -- IO1 <= observation_reg(1 );
633 -- IO2 <= observation_reg(2 );
633 -- IO2 <= observation_reg(2 );
634 -- IO3 <= observation_reg(3 );
634 -- IO3 <= observation_reg(3 );
635 -- IO4 <= observation_reg(4 );
635 -- IO4 <= observation_reg(4 );
636 -- IO5 <= observation_reg(5 );
636 -- IO5 <= observation_reg(5 );
637 -- IO6 <= observation_reg(6 );
637 -- IO6 <= observation_reg(6 );
638 -- IO7 <= observation_reg(7 );
638 -- IO7 <= observation_reg(7 );
639 IO8 <= observation_reg(8);
639 IO8 <= observation_reg(8);
640 IO9 <= observation_reg(9);
640 IO9 <= observation_reg(9);
641 IO10 <= observation_reg(10);
641 IO10 <= observation_reg(10);
642 IO11 <= observation_reg(11);
642 IO11 <= observation_reg(11);
643 WHEN "001" =>
643 WHEN "001" =>
644 -- --IO0 <= observation_reg(0 + 12);
644 -- --IO0 <= observation_reg(0 + 12);
645 -- IO1 <= observation_reg(1 + 12);
645 -- IO1 <= observation_reg(1 + 12);
646 -- IO2 <= observation_reg(2 + 12);
646 -- IO2 <= observation_reg(2 + 12);
647 -- IO3 <= observation_reg(3 + 12);
647 -- IO3 <= observation_reg(3 + 12);
648 -- IO4 <= observation_reg(4 + 12);
648 -- IO4 <= observation_reg(4 + 12);
649 -- IO5 <= observation_reg(5 + 12);
649 -- IO5 <= observation_reg(5 + 12);
650 -- IO6 <= observation_reg(6 + 12);
650 -- IO6 <= observation_reg(6 + 12);
651 -- IO7 <= observation_reg(7 + 12);
651 -- IO7 <= observation_reg(7 + 12);
652 IO8 <= observation_reg(8 + 12);
652 IO8 <= observation_reg(8 + 12);
653 IO9 <= observation_reg(9 + 12);
653 IO9 <= observation_reg(9 + 12);
654 IO10 <= observation_reg(10 + 12);
654 IO10 <= observation_reg(10 + 12);
655 IO11 <= observation_reg(11 + 12);
655 IO11 <= observation_reg(11 + 12);
656 WHEN "010" =>
656 WHEN "010" =>
657 -- --IO0 <= observation_reg(0 + 12 + 12);
657 -- --IO0 <= observation_reg(0 + 12 + 12);
658 -- IO1 <= observation_reg(1 + 12 + 12);
658 -- IO1 <= observation_reg(1 + 12 + 12);
659 -- IO2 <= observation_reg(2 + 12 + 12);
659 -- IO2 <= observation_reg(2 + 12 + 12);
660 -- IO3 <= observation_reg(3 + 12 + 12);
660 -- IO3 <= observation_reg(3 + 12 + 12);
661 -- IO4 <= observation_reg(4 + 12 + 12);
661 -- IO4 <= observation_reg(4 + 12 + 12);
662 -- IO5 <= observation_reg(5 + 12 + 12);
662 -- IO5 <= observation_reg(5 + 12 + 12);
663 -- IO6 <= observation_reg(6 + 12 + 12);
663 -- IO6 <= observation_reg(6 + 12 + 12);
664 -- IO7 <= observation_reg(7 + 12 + 12);
664 -- IO7 <= observation_reg(7 + 12 + 12);
665 IO8 <= '0';
665 IO8 <= '0';
666 IO9 <= '0';
666 IO9 <= '0';
667 IO10 <= '0';
667 IO10 <= '0';
668 IO11 <= '0';
668 IO11 <= '0';
669 WHEN "000" =>
669 WHEN "000" =>
670 -- --IO0 <= observation_vector_0(0 );
670 -- --IO0 <= observation_vector_0(0 );
671 -- IO1 <= observation_vector_0(1 );
671 -- IO1 <= observation_vector_0(1 );
672 -- IO2 <= observation_vector_0(2 );
672 -- IO2 <= observation_vector_0(2 );
673 -- IO3 <= observation_vector_0(3 );
673 -- IO3 <= observation_vector_0(3 );
674 -- IO4 <= observation_vector_0(4 );
674 -- IO4 <= observation_vector_0(4 );
675 -- IO5 <= observation_vector_0(5 );
675 -- IO5 <= observation_vector_0(5 );
676 -- IO6 <= observation_vector_0(6 );
676 -- IO6 <= observation_vector_0(6 );
677 -- IO7 <= observation_vector_0(7 );
677 -- IO7 <= observation_vector_0(7 );
678 IO8 <= observation_vector_0(8);
678 IO8 <= observation_vector_0(8);
679 IO9 <= observation_vector_0(9);
679 IO9 <= observation_vector_0(9);
680 IO10 <= observation_vector_0(10);
680 IO10 <= observation_vector_0(10);
681 IO11 <= observation_vector_0(11);
681 IO11 <= observation_vector_0(11);
682 WHEN "100" =>
682 WHEN "100" =>
683 -- --IO0 <= observation_vector_1(0 );
683 -- --IO0 <= observation_vector_1(0 );
684 -- IO1 <= observation_vector_1(1 );
684 -- IO1 <= observation_vector_1(1 );
685 -- IO2 <= observation_vector_1(2 );
685 -- IO2 <= observation_vector_1(2 );
686 -- IO3 <= observation_vector_1(3 );
686 -- IO3 <= observation_vector_1(3 );
687 -- IO4 <= observation_vector_1(4 );
687 -- IO4 <= observation_vector_1(4 );
688 -- IO5 <= observation_vector_1(5 );
688 -- IO5 <= observation_vector_1(5 );
689 -- IO6 <= observation_vector_1(6 );
689 -- IO6 <= observation_vector_1(6 );
690 -- IO7 <= observation_vector_1(7 );
690 -- IO7 <= observation_vector_1(7 );
691 IO8 <= observation_vector_1(8);
691 IO8 <= observation_vector_1(8);
692 IO9 <= observation_vector_1(9);
692 IO9 <= observation_vector_1(9);
693 IO10 <= observation_vector_1(10);
693 IO10 <= observation_vector_1(10);
694 IO11 <= observation_vector_1(11);
694 IO11 <= observation_vector_1(11);
695 WHEN OTHERS => NULL;
695 WHEN OTHERS => NULL;
696 END CASE;
696 END CASE;
697
697
698 END IF;
698 END IF;
699 END PROCESS;
699 END PROCESS;
700 -----------------------------------------------------------------------------
700 -----------------------------------------------------------------------------
701 --
701 --
702 -----------------------------------------------------------------------------
702 -----------------------------------------------------------------------------
703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
705 apbo_ext(I) <= apb_none;
705 apbo_ext(I) <= apb_none;
706 END GENERATE apbo_ext_not_used;
706 END GENERATE apbo_ext_not_used;
707 END GENERATE all_apbo_ext;
707 END GENERATE all_apbo_ext;
708
708
709
709
710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
711 ahbo_s_ext(I) <= ahbs_none;
711 ahbo_s_ext(I) <= ahbs_none;
712 END GENERATE all_ahbo_ext;
712 END GENERATE all_ahbo_ext;
713
713
714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
716 ahbo_m_ext(I) <= ahbm_none;
716 ahbo_m_ext(I) <= ahbm_none;
717 END GENERATE ahbo_m_ext_not_used;
717 END GENERATE ahbo_m_ext_not_used;
718 END GENERATE all_ahbo_m_ext;
718 END GENERATE all_ahbo_m_ext;
719
719
720 END beh;
720 END beh;
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@@ -1,386 +1,384
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
26 USE ieee.numeric_std.all;
27
27
28 LIBRARY lpp;
28 LIBRARY lpp;
29 USE lpp.cic_pkg.ALL;
29 USE lpp.cic_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31 USE lpp.iir_filter.ALL;
31 USE lpp.iir_filter.ALL;
32
32
33 LIBRARY techmap;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
34 USE techmap.gencomp.ALL;
35
35
36 ENTITY cic_lfr IS
36 ENTITY cic_lfr IS
37 GENERIC(
37 GENERIC(
38 tech : INTEGER := 0;
38 tech : INTEGER := 0;
39 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
39 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
40 );
40 );
41 PORT (
41 PORT (
42 clk : IN STD_LOGIC;
42 clk : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
44 run : IN STD_LOGIC;
44 run : IN STD_LOGIC;
45
45
46 data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
46 data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
47 data_in_valid : IN STD_LOGIC;
47 data_in_valid : IN STD_LOGIC;
48
48
49 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
49 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
50 data_out_16_valid : OUT STD_LOGIC;
50 data_out_16_valid : OUT STD_LOGIC;
51 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
51 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
52 data_out_256_valid : OUT STD_LOGIC
52 data_out_256_valid : OUT STD_LOGIC
53 );
53 );
54
54
55 END cic_lfr;
55 END cic_lfr;
56
56
57 ARCHITECTURE beh OF cic_lfr IS
57 ARCHITECTURE beh OF cic_lfr IS
58 --
58 --
59 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
59 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
60 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
60 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
61 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
61 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
62 --
62 --
63 SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0);
63 SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0);
64 SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
64 SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
65 SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
65 SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
66 --
66 --
67 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
67 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
68 SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
68 SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
69 SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
69 SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
70 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 SIGNAL data_in_Carry : STD_LOGIC;
71 SIGNAL data_in_Carry : STD_LOGIC;
72 SIGNAL data_out_Carry : STD_LOGIC;
72 SIGNAL data_out_Carry : STD_LOGIC;
73 --
73 --
74 CONSTANT S_parameter : INTEGER := 3;
74 CONSTANT S_parameter : INTEGER := 3;
75 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
75 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
76 SIGNAL CARRY_PUSH : STD_LOGIC;
76 SIGNAL CARRY_PUSH : STD_LOGIC;
77 SIGNAL CARRY_POP : STD_LOGIC;
77 SIGNAL CARRY_POP : STD_LOGIC;
78 --
78 --
79
79
80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
81 SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
81 SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
82 SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
82 SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
83
83
84 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
85 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
85 TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
86 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
86 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
87 CONSTANT base_addr_delta : INTEGER := 40;
87 CONSTANT base_addr_delta : INTEGER := 40;
88 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
88 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
89 SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
89 SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
90 SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
90 SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
91 SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
91 SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
92 SIGNAL addr_write_mux: STD_LOGIC_VECTOR(7 DOWNTO 0);
92 SIGNAL addr_write_mux: STD_LOGIC_VECTOR(7 DOWNTO 0);
93 SIGNAL addr_write_s: STD_LOGIC_VECTOR(7 DOWNTO 0);
93 SIGNAL addr_write_s: STD_LOGIC_VECTOR(7 DOWNTO 0);
94 SIGNAL data_we: STD_LOGIC;
94 SIGNAL data_we: STD_LOGIC;
95 SIGNAL data_we_s: STD_LOGIC;
95 SIGNAL data_we_s: STD_LOGIC;
96 SIGNAL data_wen : STD_LOGIC;
96 SIGNAL data_wen : STD_LOGIC;
97 -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
97 -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 SIGNAL sample_out_reg16 : sample_vector(6*2-1 DOWNTO 0, 15 DOWNTO 0);
101 SIGNAL sample_out_reg16 : sample_vector(6*2-1 DOWNTO 0, 15 DOWNTO 0);
102 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
102 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
103 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6*2 DOWNTO 0);
103 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6*2 DOWNTO 0);
104 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
104 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
105 SIGNAL data_out_16_valid_s : STD_LOGIC;
105 SIGNAL data_out_16_valid_s : STD_LOGIC;
106 SIGNAL data_out_256_valid_s : STD_LOGIC;
106 SIGNAL data_out_256_valid_s : STD_LOGIC;
107 SIGNAL data_out_16_valid_s1 : STD_LOGIC;
107 SIGNAL data_out_16_valid_s1 : STD_LOGIC;
108 SIGNAL data_out_256_valid_s1 : STD_LOGIC;
108 SIGNAL data_out_256_valid_s1 : STD_LOGIC;
109 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
109 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
110 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
110 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
112 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
113 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
113 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115
115
116
116
117 BEGIN
117 BEGIN
118
118
119
119
120 PROCESS (clk, rstn)
120 PROCESS (clk, rstn)
121 BEGIN -- PROCESS
121 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 data_B_reg <= (OTHERS => '0');
123 data_B_reg <= (OTHERS => '0');
124 OPERATION_reg <= (OTHERS => '0');
124 OPERATION_reg <= (OTHERS => '0');
125 OPERATION_reg2 <= (OTHERS => '0');
125 OPERATION_reg2 <= (OTHERS => '0');
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
126 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 OPERATION_reg <= OPERATION;
127 OPERATION_reg <= OPERATION;
128 OPERATION_reg2 <= OPERATION_reg;
128 OPERATION_reg2 <= OPERATION_reg;
129 data_B_reg <= data_B;
129 data_B_reg <= data_B;
130 END IF;
130 END IF;
131 END PROCESS;
131 END PROCESS;
132
132
133
133
134 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
135 -- SEL_SAMPLE
135 -- SEL_SAMPLE
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 sel_sample <= OPERATION_reg(2 DOWNTO 0);
137 sel_sample <= OPERATION_reg(2 DOWNTO 0);
138
138
139 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
139 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
140 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
140 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
141 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
141 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
142 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
142 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
143
143
144 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
144 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
145 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE '0';
145 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE '0';
146
146
147 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
147 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
148 END GENERATE all_bit;
148 END GENERATE all_bit;
149
149
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 -- SEL_DATA_IN_A
151 -- SEL_DATA_IN_A
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 sel_A <= OPERATION_reg(4 DOWNTO 3);
153 sel_A <= OPERATION_reg(4 DOWNTO 3);
154
154
155 all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
155 all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
156 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
156 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
157 data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15);
157 data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15);
158 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
158 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
159 data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
159 data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
160 END GENERATE all_data_mux_A;
160 END GENERATE all_data_mux_A;
161
161
162
162
163
163
164 -----------------------------------------------------------------------------
164 -----------------------------------------------------------------------------
165 -- ALU
165 -- ALU
166 -----------------------------------------------------------------------------
166 -----------------------------------------------------------------------------
167 ALU_OP <= OPERATION_reg(6 DOWNTO 5);
167 ALU_OP <= OPERATION_reg(6 DOWNTO 5);
168
168
169 ALU: cic_lfr_add_sub
169 ALU: cic_lfr_add_sub
170 PORT MAP (
170 PORT MAP (
171 clk => clk,
171 clk => clk,
172 rstn => rstn,
172 rstn => rstn,
173 run => run,
173 run => run,
174
174
175 OP => ALU_OP,
175 OP => ALU_OP,
176
176
177 data_in_A => data_A,
177 data_in_A => data_A,
178 data_in_B => data_B,
178 data_in_B => data_B,
179 data_in_Carry => data_in_Carry,
179 data_in_Carry => data_in_Carry,
180
180
181 data_out => data_out,
181 data_out => data_out,
182 data_out_Carry => data_out_Carry);
182 data_out_Carry => data_out_Carry);
183
183
184 -----------------------------------------------------------------------------
184 -----------------------------------------------------------------------------
185 -- CARRY_MANAGER
185 -- CARRY_MANAGER
186 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
187 data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
187 data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
188
188
189 -- CARRY_PUSH <= OPERATION_reg(7);
189 -- CARRY_PUSH <= OPERATION_reg(7);
190 -- CARRY_POP <= OPERATION_reg(6);
190 -- CARRY_POP <= OPERATION_reg(6);
191
191
192 PROCESS (clk, rstn)
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 carry_reg <= (OTHERS => '0');
195 carry_reg <= (OTHERS => '0');
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
197 --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
197 --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
198 carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
198 carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
199 carry_reg(0) <= data_out_Carry;
199 carry_reg(0) <= data_out_Carry;
200 --END IF;
200 --END IF;
201 END IF;
201 END IF;
202 END PROCESS;
202 END PROCESS;
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205 -- MEMORY
205 -- MEMORY
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
207 all_channel: FOR I IN 5 DOWNTO 0 GENERATE
208 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
208 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
209 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
209 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
210 END GENERATE all_bit;
210 END GENERATE all_bit;
211 END GENERATE all_channel;
211 END GENERATE all_channel;
212 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
212 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
213
213
214 cic_lfr_address_gen_1: cic_lfr_address_gen
214 cic_lfr_address_gen_1: cic_lfr_address_gen
215 PORT MAP (
215 PORT MAP (
216 clk => clk,
216 clk => clk,
217 rstn => rstn,
217 rstn => rstn,
218 run => run,
218 run => run,
219
219
220 addr_base => addr_base_sel,
220 addr_base => addr_base_sel,
221 addr_init => OPERATION(8),
221 addr_init => OPERATION(8),
222 addr_add_1 => OPERATION(9),
222 addr_add_1 => OPERATION(9),
223 addr => addr_gen);
223 addr => addr_gen);
224
224
225
225
226 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
226 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
227 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
227 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
228 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
228 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
229 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
229 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
230 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8));
230 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,8));
231
231
232 PROCESS (clk, rstn)
232 PROCESS (clk, rstn)
233 BEGIN -- PROCESS
233 BEGIN -- PROCESS
234 IF rstn = '0' THEN -- asynchronous reset (active low)
234 IF rstn = '0' THEN -- asynchronous reset (active low)
235 addr_write <= (OTHERS => '0');
235 addr_write <= (OTHERS => '0');
236 data_we <= '0';
236 data_we <= '0';
237 addr_write_s <= (OTHERS => '0');
237 addr_write_s <= (OTHERS => '0');
238 data_we_s <= '0';
238 data_we_s <= '0';
239 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
239 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
240 addr_write_s <= addr_read;
240 addr_write_s <= addr_read;
241 data_we_s <= OPERATION(13);
241 data_we_s <= OPERATION(13);
242 IF OPERATION_reg(15) = '0' THEN
242 IF OPERATION_reg(15) = '0' THEN
243 addr_write <= addr_write_s;
243 addr_write <= addr_write_s;
244 ELSE
244 ELSE
245 addr_write <= addr_read;
245 addr_write <= addr_read;
246 END IF;
246 END IF;
247 data_we <= data_we_s;
247 data_we <= data_we_s;
248 END IF;
248 END IF;
249 END PROCESS;
249 END PROCESS;
250
250
251 memCEL : IF use_RAM_nCEL = 0 GENERATE
251 memCEL : IF use_RAM_nCEL = 0 GENERATE
252 data_wen <= NOT data_we;
252 data_wen <= NOT data_we;
253 RAMblk : RAM_CEL
253 RAMblk : RAM_CEL
254 GENERIC MAP(16, 8)
254 GENERIC MAP(16, 8)
255 PORT MAP(
255 PORT MAP(
256 WD => data_out,
256 WD => data_out,
257 RD => data_B,
257 RD => data_B,
258 WEN => data_wen,
258 WEN => data_wen,
259 REN => '0',
259 REN => '0',
260 WADDR => addr_write,
260 WADDR => addr_write,
261 RADDR => addr_read,
261 RADDR => addr_read,
262 RWCLK => clk,
262 RWCLK => clk,
263 RESET => rstn
263 RESET => rstn
264 ) ;
264 ) ;
265 END GENERATE;
265 END GENERATE;
266
266
267 memRAM : IF use_RAM_nCEL = 1 GENERATE
267 memRAM : IF use_RAM_nCEL = 1 GENERATE
268 SRAM : syncram_2p
268 SRAM : syncram_2p
269 GENERIC MAP(tech, 8, 16)
269 GENERIC MAP(tech, 8, 16)
270 PORT MAP(clk, '1', addr_read, data_B,
270 PORT MAP(clk, '1', addr_read, data_B,
271 clk, data_we, addr_write, data_out);
271 clk, data_we, addr_write, data_out);
272 END GENERATE;
272 END GENERATE;
273
273
274 -----------------------------------------------------------------------------
274 -----------------------------------------------------------------------------
275 -- CONTROL
275 -- CONTROL
276 -----------------------------------------------------------------------------
276 -----------------------------------------------------------------------------
277 cic_lfr_control_1: cic_lfr_control
277 cic_lfr_control_1: cic_lfr_control
278 PORT MAP (
278 PORT MAP (
279 clk => clk,
279 clk => clk,
280 rstn => rstn,
280 rstn => rstn,
281 run => run,
281 run => run,
282 data_in_valid => data_in_valid,
282 data_in_valid => data_in_valid,
283 data_out_16_valid => data_out_16_valid_s,
283 data_out_16_valid => data_out_16_valid_s,
284 data_out_256_valid => data_out_256_valid_s,
284 data_out_256_valid => data_out_256_valid_s,
285 OPERATION => OPERATION);
285 OPERATION => OPERATION);
286
286
287 -----------------------------------------------------------------------------
287 -----------------------------------------------------------------------------
288 PROCESS (clk, rstn)
288 PROCESS (clk, rstn)
289 BEGIN -- PROCESS
289 BEGIN -- PROCESS
290 IF rstn = '0' THEN -- asynchronous reset (active low)
290 IF rstn = '0' THEN -- asynchronous reset (active low)
291 data_out_16_valid_s1 <= '0';
291 data_out_16_valid_s1 <= '0';
292 data_out_256_valid_s1 <= '0';
292 data_out_256_valid_s1 <= '0';
293 data_out_16_valid_s2 <= '0';
293 data_out_16_valid_s2 <= '0';
294 data_out_256_valid_s2 <= '0';
294 data_out_256_valid_s2 <= '0';
295 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
295 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
296 data_out_16_valid_s1 <= data_out_16_valid_s;
296 data_out_16_valid_s1 <= data_out_16_valid_s;
297 data_out_256_valid_s1 <= data_out_256_valid_s;
297 data_out_256_valid_s1 <= data_out_256_valid_s;
298 data_out_16_valid_s2 <= data_out_16_valid_s1;
298 data_out_16_valid_s2 <= data_out_16_valid_s1;
299 data_out_256_valid_s2 <= data_out_256_valid_s1;
299 data_out_256_valid_s2 <= data_out_256_valid_s1;
300 END IF;
300 END IF;
301 END PROCESS;
301 END PROCESS;
302
302
303 PROCESS (clk, rstn)
303 PROCESS (clk, rstn)
304 BEGIN -- PROCESS
304 BEGIN -- PROCESS
305 IF rstn = '0' THEN -- asynchronous reset (active low)
305 IF rstn = '0' THEN -- asynchronous reset (active low)
306 sample_valid_reg16 <= '0' & "000000" & "000001";
306 sample_valid_reg16 <= '0' & "000000" & "000001";
307 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
307 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
308 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
308 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
309 IF run = '0' THEN
309 IF run = '0' THEN
310 sample_valid_reg16 <= '0' & "000000" & "000001";
310 sample_valid_reg16 <= '0' & "000000" & "000001";
311 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
311 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
312 ELSE
312 ELSE
313 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(6*2) = '1' THEN
313 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(6*2) = '1' THEN
314 sample_valid_reg16 <= sample_valid_reg16(6*2-1 DOWNTO 0) & sample_valid_reg16(6*2);
314 sample_valid_reg16 <= sample_valid_reg16(6*2-1 DOWNTO 0) & sample_valid_reg16(6*2);
315 END IF;
315 END IF;
316 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
316 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
317 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
317 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
318 END IF;
318 END IF;
319 END IF;
319 END IF;
320 END IF;
320 END IF;
321 END PROCESS;
321 END PROCESS;
322
322
323 data_out_16_valid <= sample_valid_reg16(6*2);
323 data_out_16_valid <= sample_valid_reg16(6*2);
324 data_out_256_valid <= sample_valid_reg256(6*3);
324 data_out_256_valid <= sample_valid_reg256(6*3);
325
325
326 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
327
327
328 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
328 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
329 all_channel_out16: FOR I IN 6*2-1 DOWNTO 0 GENERATE
329 all_channel_out16: FOR I IN 6*2-1 DOWNTO 0 GENERATE
330 PROCESS (clk, rstn)
330 PROCESS (clk, rstn)
331 BEGIN -- PROCESS
331 BEGIN -- PROCESS
332 IF rstn = '0' THEN -- asynchronous reset (active low)
332 IF rstn = '0' THEN -- asynchronous reset (active low)
333 sample_out_reg16(I,J) <= '0';
333 sample_out_reg16(I,J) <= '0';
334 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
334 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
335 IF run = '0' THEN
335 IF run = '0' THEN
336 sample_out_reg16(I,J) <= '0';
336 sample_out_reg16(I,J) <= '0';
337 ELSE
337 ELSE
338 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
338 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
339 sample_out_reg16(I,J) <= data_out(J);
339 sample_out_reg16(I,J) <= data_out(J);
340 END IF;
340 END IF;
341 END IF;
341 END IF;
342 END IF;
342 END IF;
343 END PROCESS;
343 END PROCESS;
344 END GENERATE all_channel_out16;
344 END GENERATE all_channel_out16;
345
345
346 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
346 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
347 PROCESS (clk, rstn)
347 PROCESS (clk, rstn)
348 BEGIN -- PROCESS
348 BEGIN -- PROCESS
349 IF rstn = '0' THEN -- asynchronous reset (active low)
349 IF rstn = '0' THEN -- asynchronous reset (active low)
350 sample_out_reg256(I,J) <= '0';
350 sample_out_reg256(I,J) <= '0';
351 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
351 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
352 IF run = '0' THEN
352 IF run = '0' THEN
353 sample_out_reg256(I,J) <= '0';
353 sample_out_reg256(I,J) <= '0';
354 ELSE
354 ELSE
355 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
355 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
356 sample_out_reg256(I,J) <= data_out(J);
356 sample_out_reg256(I,J) <= data_out(J);
357 END IF;
357 END IF;
358 END IF;
358 END IF;
359 END IF;
359 END IF;
360 END PROCESS;
360 END PROCESS;
361 END GENERATE all_channel_out256;
361 END GENERATE all_channel_out256;
362 END GENERATE all_bits;
362 END GENERATE all_bits;
363
363
364
364
365 all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
365 all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
366 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
366 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
367 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
367 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
368 sample_out_reg16_s(I,J+(K*16)) <= sample_out_reg16(2*I+K,J);
368 sample_out_reg16_s(I,J+(K*16)) <= sample_out_reg16(2*I+K,J);
369 END GENERATE all_reg_16;
369 END GENERATE all_reg_16;
370 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
370 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
371 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
371 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
372 END GENERATE all_reg_256;
372 END GENERATE all_reg_256;
373 END GENERATE all_bits;
373 END GENERATE all_bits;
374 END GENERATE all_channel_out;
374 END GENERATE all_channel_out;
375
375
376 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
376 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
377 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
377 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
378 data_out_256(I,J) <= sample_out_reg256_s(I,J);
378 data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-1);
379
379 data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -1);
380 END GENERATE all_bits;
380 END GENERATE all_bits;
381 END GENERATE all_channel_out_v;
381 END GENERATE all_channel_out_v;
382
383 -- data_out_16 <= sample_out_reg16;
384
382
385 END beh;
383 END beh;
386
384
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@@ -1,373 +1,389
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
28 USE grlib.devices.ALL;
29
29
30 PACKAGE lpp_ad_conv IS
30 PACKAGE lpp_ad_conv IS
31
31
32
32
33 --CONSTANT AD7688 : INTEGER := 0;
33 --CONSTANT AD7688 : INTEGER := 0;
34 --CONSTANT ADS7886 : INTEGER := 1;
34 --CONSTANT ADS7886 : INTEGER := 1;
35
35
36
36
37 --TYPE AD7688_out IS
37 --TYPE AD7688_out IS
38 --RECORD
38 --RECORD
39 -- CNV : STD_LOGIC;
39 -- CNV : STD_LOGIC;
40 -- SCK : STD_LOGIC;
40 -- SCK : STD_LOGIC;
41 --END RECORD;
41 --END RECORD;
42
42
43 --TYPE AD7688_in_element IS
43 --TYPE AD7688_in_element IS
44 --RECORD
44 --RECORD
45 -- SDI : STD_LOGIC;
45 -- SDI : STD_LOGIC;
46 --END RECORD;
46 --END RECORD;
47
47
48 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
48 --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
49
49
50 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
50 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0);
51 TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0);
52
52
53 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
53 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
54
54
55 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
55 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
56
56
57 SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0);
57 SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0);
58
58
59 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
59 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
60
60
61 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
61 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
62
62
63 SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
63 SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
64
64
65 SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
65 SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
66
66
67 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
67 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
68
68
69 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
69 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
70
70
71 TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15;
71 TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15;
72
72
73 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
73 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
74
74
75 TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
75 TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
76
76
77 TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
77 TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
78
78
79 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
79 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
80
80
81 COMPONENT AD7688_drvr
81 COMPONENT AD7688_drvr
82 GENERIC (
82 GENERIC (
83 ChanelCount : INTEGER;
83 ChanelCount : INTEGER;
84 ncycle_cnv_high : INTEGER := 79;
84 ncycle_cnv_high : INTEGER := 79;
85 ncycle_cnv : INTEGER := 500);
85 ncycle_cnv : INTEGER := 500);
86 PORT (
86 PORT (
87 cnv_clk : IN STD_LOGIC;
87 cnv_clk : IN STD_LOGIC;
88 cnv_rstn : IN STD_LOGIC;
88 cnv_rstn : IN STD_LOGIC;
89 cnv_run : IN STD_LOGIC;
89 cnv_run : IN STD_LOGIC;
90 cnv : OUT STD_LOGIC;
90 cnv : OUT STD_LOGIC;
91 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
93 sck : OUT STD_LOGIC;
93 sck : OUT STD_LOGIC;
94 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
94 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
95 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
95 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
96 sample_val : OUT STD_LOGIC);
96 sample_val : OUT STD_LOGIC);
97 END COMPONENT;
97 END COMPONENT;
98
98
99 COMPONENT RHF1401_drvr IS
99 COMPONENT RHF1401_drvr IS
100 GENERIC(
100 GENERIC(
101 ChanelCount : INTEGER := 8);
101 ChanelCount : INTEGER := 8);
102 PORT (
102 PORT (
103 cnv_clk : IN STD_LOGIC;
103 cnv_clk : IN STD_LOGIC;
104 clk : IN STD_LOGIC;
104 clk : IN STD_LOGIC;
105 rstn : IN STD_LOGIC;
105 rstn : IN STD_LOGIC;
106 ADC_data : IN Samples14;
106 ADC_data : IN Samples14;
107 --ADC_smpclk : OUT STD_LOGIC;
107 --ADC_smpclk : OUT STD_LOGIC;
108 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
108 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
109 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
109 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
110 sample_val : OUT STD_LOGIC
110 sample_val : OUT STD_LOGIC
111 );
111 );
112 END COMPONENT;
112 END COMPONENT;
113
113
114 COMPONENT top_ad_conv_RHF1401
114 COMPONENT top_ad_conv_RHF1401
115 GENERIC (
115 GENERIC (
116 ChanelCount : INTEGER;
116 ChanelCount : INTEGER;
117 ncycle_cnv_high : INTEGER := 79;
117 ncycle_cnv_high : INTEGER := 79;
118 ncycle_cnv : INTEGER := 500);
118 ncycle_cnv : INTEGER := 500);
119 PORT (
119 PORT (
120 cnv_clk : IN STD_LOGIC;
120 cnv_clk : IN STD_LOGIC;
121 cnv_rstn : IN STD_LOGIC;
121 cnv_rstn : IN STD_LOGIC;
122 cnv : OUT STD_LOGIC;
122 cnv : OUT STD_LOGIC;
123 clk : IN STD_LOGIC;
123 clk : IN STD_LOGIC;
124 rstn : IN STD_LOGIC;
124 rstn : IN STD_LOGIC;
125 ADC_data : IN Samples14;
125 ADC_data : IN Samples14;
126 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
126 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
127 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
127 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
128 sample_val : OUT STD_LOGIC);
128 sample_val : OUT STD_LOGIC);
129 END COMPONENT;
129 END COMPONENT;
130
130
131
131
132 COMPONENT AD7688_drvr_sync
132 COMPONENT AD7688_drvr_sync
133 GENERIC (
133 GENERIC (
134 ChanelCount : INTEGER;
134 ChanelCount : INTEGER;
135 ncycle_cnv_high : INTEGER;
135 ncycle_cnv_high : INTEGER;
136 ncycle_cnv : INTEGER);
136 ncycle_cnv : INTEGER);
137 PORT (
137 PORT (
138 cnv_clk : IN STD_LOGIC;
138 cnv_clk : IN STD_LOGIC;
139 cnv_rstn : IN STD_LOGIC;
139 cnv_rstn : IN STD_LOGIC;
140 cnv_run : IN STD_LOGIC;
140 cnv_run : IN STD_LOGIC;
141 cnv : OUT STD_LOGIC;
141 cnv : OUT STD_LOGIC;
142 sck : OUT STD_LOGIC;
142 sck : OUT STD_LOGIC;
143 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
143 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
144 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
144 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
145 sample_val : OUT STD_LOGIC);
145 sample_val : OUT STD_LOGIC);
146 END COMPONENT;
146 END COMPONENT;
147
147
148 COMPONENT TestModule_RHF1401
148 COMPONENT TestModule_RHF1401
149 GENERIC (
149 GENERIC (
150 freq : INTEGER;
150 freq : INTEGER;
151 amplitude : INTEGER;
151 amplitude : INTEGER;
152 impulsion : INTEGER);
152 impulsion : INTEGER);
153 PORT (
153 PORT (
154 ADC_smpclk : IN STD_LOGIC;
154 ADC_smpclk : IN STD_LOGIC;
155 ADC_OEB_bar : IN STD_LOGIC;
155 ADC_OEB_bar : IN STD_LOGIC;
156 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
156 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
157 END COMPONENT;
157 END COMPONENT;
158
158
159 --COMPONENT AD7688_drvr IS
159 --COMPONENT AD7688_drvr IS
160 -- GENERIC(ChanelCount : INTEGER;
160 -- GENERIC(ChanelCount : INTEGER;
161 -- clkkHz : INTEGER);
161 -- clkkHz : INTEGER);
162 -- PORT (clk : IN STD_LOGIC;
162 -- PORT (clk : IN STD_LOGIC;
163 -- rstn : IN STD_LOGIC;
163 -- rstn : IN STD_LOGIC;
164 -- enable : IN STD_LOGIC;
164 -- enable : IN STD_LOGIC;
165 -- smplClk : IN STD_LOGIC;
165 -- smplClk : IN STD_LOGIC;
166 -- DataReady : OUT STD_LOGIC;
166 -- DataReady : OUT STD_LOGIC;
167 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
167 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
168 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
168 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
169 -- AD_out : OUT AD7688_out);
169 -- AD_out : OUT AD7688_out);
170 --END COMPONENT;
170 --END COMPONENT;
171
171
172
172
173 --COMPONENT AD7688_spi_if IS
173 --COMPONENT AD7688_spi_if IS
174 -- GENERIC(ChanelCount : INTEGER);
174 -- GENERIC(ChanelCount : INTEGER);
175 -- PORT(clk : IN STD_LOGIC;
175 -- PORT(clk : IN STD_LOGIC;
176 -- reset : IN STD_LOGIC;
176 -- reset : IN STD_LOGIC;
177 -- cnv : IN STD_LOGIC;
177 -- cnv : IN STD_LOGIC;
178 -- DataReady : OUT STD_LOGIC;
178 -- DataReady : OUT STD_LOGIC;
179 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
179 -- sdi : IN AD7688_in(ChanelCount-1 DOWNTO 0);
180 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
180 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0)
181 -- );
181 -- );
182 --END COMPONENT;
182 --END COMPONENT;
183
183
184
184
185 --COMPONENT lpp_apb_ad_conv
185 --COMPONENT lpp_apb_ad_conv
186 -- GENERIC(
186 -- GENERIC(
187 -- pindex : INTEGER := 0;
187 -- pindex : INTEGER := 0;
188 -- paddr : INTEGER := 0;
188 -- paddr : INTEGER := 0;
189 -- pmask : INTEGER := 16#fff#;
189 -- pmask : INTEGER := 16#fff#;
190 -- pirq : INTEGER := 0;
190 -- pirq : INTEGER := 0;
191 -- abits : INTEGER := 8;
191 -- abits : INTEGER := 8;
192 -- ChanelCount : INTEGER := 1;
192 -- ChanelCount : INTEGER := 1;
193 -- clkkHz : INTEGER := 50000;
193 -- clkkHz : INTEGER := 50000;
194 -- smpClkHz : INTEGER := 100;
194 -- smpClkHz : INTEGER := 100;
195 -- ADCref : INTEGER := AD7688);
195 -- ADCref : INTEGER := AD7688);
196 -- PORT (
196 -- PORT (
197 -- clk : IN STD_LOGIC;
197 -- clk : IN STD_LOGIC;
198 -- reset : IN STD_LOGIC;
198 -- reset : IN STD_LOGIC;
199 -- apbi : IN apb_slv_in_type;
199 -- apbi : IN apb_slv_in_type;
200 -- apbo : OUT apb_slv_out_type;
200 -- apbo : OUT apb_slv_out_type;
201 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
201 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
202 -- AD_out : OUT AD7688_out);
202 -- AD_out : OUT AD7688_out);
203 --END COMPONENT;
203 --END COMPONENT;
204
204
205 --COMPONENT ADS7886_drvr IS
205 --COMPONENT ADS7886_drvr IS
206 -- GENERIC(ChanelCount : INTEGER;
206 -- GENERIC(ChanelCount : INTEGER;
207 -- clkkHz : INTEGER);
207 -- clkkHz : INTEGER);
208 -- PORT (
208 -- PORT (
209 -- clk : IN STD_LOGIC;
209 -- clk : IN STD_LOGIC;
210 -- reset : IN STD_LOGIC;
210 -- reset : IN STD_LOGIC;
211 -- smplClk : IN STD_LOGIC;
211 -- smplClk : IN STD_LOGIC;
212 -- DataReady : OUT STD_LOGIC;
212 -- DataReady : OUT STD_LOGIC;
213 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
213 -- smpout : OUT Samples_out(ChanelCount-1 DOWNTO 0);
214 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
214 -- AD_in : IN AD7688_in(ChanelCount-1 DOWNTO 0);
215 -- AD_out : OUT AD7688_out
215 -- AD_out : OUT AD7688_out
216 -- );
216 -- );
217 --END COMPONENT;
217 --END COMPONENT;
218
218
219 --COMPONENT WriteGen_ADC IS
219 --COMPONENT WriteGen_ADC IS
220 -- PORT(
220 -- PORT(
221 -- clk : IN STD_LOGIC;
221 -- clk : IN STD_LOGIC;
222 -- rstn : IN STD_LOGIC;
222 -- rstn : IN STD_LOGIC;
223 -- SmplCLK : IN STD_LOGIC;
223 -- SmplCLK : IN STD_LOGIC;
224 -- DataReady : IN STD_LOGIC;
224 -- DataReady : IN STD_LOGIC;
225 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
225 -- Full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
226 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
226 -- ReUse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
227 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
227 -- Write : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
228 -- );
228 -- );
229 --END COMPONENT;
229 --END COMPONENT;
230
230
231
231
232 --===========================================================|
232 --===========================================================|
233 --======================= ADS 127X =========================|
233 --======================= ADS 127X =========================|
234 --===========================================================|
234 --===========================================================|
235
235
236 TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC;
236 TYPE ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC;
237 CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
237 CONSTANT ADS127X_SPI_FORMAT : ADS127X_FORMAT_Type := "010";
238 CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
238 CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
239
239
240 TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC;
240 TYPE ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC;
241 CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
241 CONSTANT ADS127X_MODE_low_power : ADS127X_MODE_Type := "10";
242 CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
242 CONSTANT ADS127X_MODE_low_speed : ADS127X_MODE_Type := "11";
243 CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
243 CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
244
244
245 TYPE ADS127X_config IS
245 TYPE ADS127X_config IS
246 RECORD
246 RECORD
247 SYNC : STD_LOGIC;
247 SYNC : STD_LOGIC;
248 CLKDIV : STD_LOGIC;
248 CLKDIV : STD_LOGIC;
249 FORMAT : ADS127X_FORMAT_Type;
249 FORMAT : ADS127X_FORMAT_Type;
250 MODE : ADS127X_MODE_Type;
250 MODE : ADS127X_MODE_Type;
251 END RECORD;
251 END RECORD;
252
252
253 COMPONENT ADS1274_DRIVER IS
253 COMPONENT ADS1274_DRIVER IS
254 GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
254 GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
255 PORT(
255 PORT(
256 Clk : IN STD_LOGIC;
256 Clk : IN STD_LOGIC;
257 reset : IN STD_LOGIC;
257 reset : IN STD_LOGIC;
258 SpiClk : OUT STD_LOGIC;
258 SpiClk : OUT STD_LOGIC;
259 DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
259 DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
260 Ready : IN STD_LOGIC;
260 Ready : IN STD_LOGIC;
261 Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
261 Format : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
262 Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
262 Mode : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
263 ClkDiv : OUT STD_LOGIC;
263 ClkDiv : OUT STD_LOGIC;
264 PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
264 PWDOWN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
265 SmplClk : IN STD_LOGIC;
265 SmplClk : IN STD_LOGIC;
266 OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
266 OUT0 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
267 OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
267 OUT1 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
268 OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
268 OUT2 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
269 OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
269 OUT3 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
270 FSynch : OUT STD_LOGIC;
270 FSynch : OUT STD_LOGIC;
271 test : OUT STD_LOGIC
271 test : OUT STD_LOGIC
272 );
272 );
273 END COMPONENT;
273 END COMPONENT;
274
274
275 -- todo clean file
275 -- todo clean file
276 COMPONENT DUAL_ADS1278_DRIVER IS
276 COMPONENT DUAL_ADS1278_DRIVER IS
277 PORT(
277 PORT(
278 Clk : IN STD_LOGIC;
278 Clk : IN STD_LOGIC;
279 reset : IN STD_LOGIC;
279 reset : IN STD_LOGIC;
280 SpiClk : OUT STD_LOGIC;
280 SpiClk : OUT STD_LOGIC;
281 DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
281 DIN : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
282 SmplClk : IN STD_LOGIC;
282 SmplClk : IN STD_LOGIC;
283 OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
283 OUT00 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
284 OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
284 OUT01 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
285 OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
285 OUT02 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
286 OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
286 OUT03 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
287 OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
287 OUT04 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
288 OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
288 OUT05 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
289 OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
289 OUT06 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
290 OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
290 OUT07 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
291 OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
291 OUT10 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
292 OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
292 OUT11 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
293 OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
293 OUT12 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
294 OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
294 OUT13 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
295 OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
295 OUT14 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
296 OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
296 OUT15 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
297 OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
297 OUT16 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
298 OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
298 OUT17 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
299 FSynch : OUT STD_LOGIC
299 FSynch : OUT STD_LOGIC
300 );
300 );
301 END COMPONENT;
301 END COMPONENT;
302
302
303 --===========================================================|
303 --===========================================================|
304 -- DRIVER ADS7886
304 -- DRIVER ADS7886
305 --===========================================================|
305 --===========================================================|
306 COMPONENT top_ad_conv_ADS7886_v2 IS
306 COMPONENT top_ad_conv_ADS7886_v2 IS
307 GENERIC(
307 GENERIC(
308 ChannelCount : INTEGER := 8;
308 ChannelCount : INTEGER := 8;
309 SampleNbBits : INTEGER := 14;
309 SampleNbBits : INTEGER := 14;
310 ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles
310 ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles
311 ncycle_cnv : INTEGER := 500);
311 ncycle_cnv : INTEGER := 500);
312 PORT (
312 PORT (
313 -- CONV
313 -- CONV
314 cnv_clk : IN STD_LOGIC;
314 cnv_clk : IN STD_LOGIC;
315 cnv_rstn : IN STD_LOGIC;
315 cnv_rstn : IN STD_LOGIC;
316 cnv : OUT STD_LOGIC;
316 cnv : OUT STD_LOGIC;
317 -- DATA
317 -- DATA
318 clk : IN STD_LOGIC;
318 clk : IN STD_LOGIC;
319 rstn : IN STD_LOGIC;
319 rstn : IN STD_LOGIC;
320 sck : OUT STD_LOGIC;
320 sck : OUT STD_LOGIC;
321 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
321 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
322 -- SAMPLE
322 -- SAMPLE
323 sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);
323 sample : OUT Samples14v(ChannelCount-1 DOWNTO 0);
324 sample_val : OUT STD_LOGIC
324 sample_val : OUT STD_LOGIC
325 );
325 );
326 END COMPONENT;
326 END COMPONENT;
327
327
328 COMPONENT ADS7886_drvr_v2 IS
328 COMPONENT ADS7886_drvr_v2 IS
329 GENERIC(
329 GENERIC(
330 ChannelCount : INTEGER := 8;
330 ChannelCount : INTEGER := 8;
331 NbBitsSamples : INTEGER := 16);
331 NbBitsSamples : INTEGER := 16);
332 PORT (
332 PORT (
333 -- CONV --
333 -- CONV --
334 cnv_clk : IN STD_LOGIC;
334 cnv_clk : IN STD_LOGIC;
335 cnv_rstn : IN STD_LOGIC;
335 cnv_rstn : IN STD_LOGIC;
336 -- DATA --
336 -- DATA --
337 clk : IN STD_LOGIC;
337 clk : IN STD_LOGIC;
338 rstn : IN STD_LOGIC;
338 rstn : IN STD_LOGIC;
339 sck : OUT STD_LOGIC;
339 sck : OUT STD_LOGIC;
340 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
340 sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
341 -- SAMPLE --
341 -- SAMPLE --
342 sample : OUT Samples(ChannelCount-1 DOWNTO 0);
342 sample : OUT Samples(ChannelCount-1 DOWNTO 0);
343 sample_val : OUT STD_LOGIC
343 sample_val : OUT STD_LOGIC
344 );
344 );
345 END COMPONENT;
345 END COMPONENT;
346
346
347 COMPONENT top_ad_conv_RHF1401_withFilter
347 COMPONENT top_ad_conv_RHF1401_withFilter
348 GENERIC (
348 GENERIC (
349 ChanelCount : INTEGER;
349 ChanelCount : INTEGER;
350 ncycle_cnv_high : INTEGER;
350 ncycle_cnv_high : INTEGER;
351 ncycle_cnv : INTEGER);
351 ncycle_cnv : INTEGER;
352 FILTER_ENABLED : INTEGER := 16#FF#);
352 PORT (
353 PORT (
353 cnv_clk : IN STD_LOGIC;
354 cnv_clk : IN STD_LOGIC;
354 cnv_rstn : IN STD_LOGIC;
355 cnv_rstn : IN STD_LOGIC;
355 cnv : OUT STD_LOGIC;
356 cnv : OUT STD_LOGIC;
356 clk : IN STD_LOGIC;
357 clk : IN STD_LOGIC;
357 rstn : IN STD_LOGIC;
358 rstn : IN STD_LOGIC;
358 ADC_data : IN Samples14;
359 ADC_data : IN Samples14;
359 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
360 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
360 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
361 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
361 sample_val : OUT STD_LOGIC);
362 sample_val : OUT STD_LOGIC);
362 END COMPONENT;
363 END COMPONENT;
363
364
365 COMPONENT lpp_lfr_hk
366 GENERIC (
367 pindex : INTEGER;
368 paddr : INTEGER;
369 pmask : INTEGER);
370 PORT (
371 clk : IN STD_LOGIC;
372 rstn : IN STD_LOGIC;
373 apbi : IN apb_slv_in_type;
374 apbo : OUT apb_slv_out_type;
375 sample_val : IN STD_LOGIC;
376 sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
377 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
378 END COMPONENT;
379
364
380
365 END lpp_ad_conv;
381 END lpp_ad_conv;
366
382
367
383
368
384
369
385
370
386
371
387
372
388
373
389
Show file before | Show file after | Hide comments
@@ -1,221 +1,218
1
1
2 LIBRARY IEEE;
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 USE IEEE.numeric_std.ALL;
4 USE IEEE.numeric_std.ALL;
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.general_purpose.SYNC_FF;
7 USE lpp.general_purpose.SYNC_FF;
8
8
9 ENTITY top_ad_conv_RHF1401_withFilter IS
9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 GENERIC(
10 GENERIC(
11 ChanelCount : INTEGER := 8;
11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 13;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25);
13 ncycle_cnv : INTEGER := 25;
14 FILTER_ENABLED : INTEGER := 16#FF#
15 );
14 PORT (
16 PORT (
15 cnv_clk : IN STD_LOGIC; -- 24Mhz
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
16 cnv_rstn : IN STD_LOGIC;
18 cnv_rstn : IN STD_LOGIC;
17
19
18 cnv : OUT STD_LOGIC;
20 cnv : OUT STD_LOGIC;
19
21
20 clk : IN STD_LOGIC; -- 25MHz
22 clk : IN STD_LOGIC; -- 25MHz
21 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
22 ADC_data : IN Samples14;
24 ADC_data : IN Samples14;
23 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
24 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
25 sample_val : OUT STD_LOGIC
27 sample_val : OUT STD_LOGIC
26 );
28 );
27 END top_ad_conv_RHF1401_withFilter;
29 END top_ad_conv_RHF1401_withFilter;
28
30
29 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
30
32
31 SIGNAL cnv_cycle_counter : INTEGER;
33 SIGNAL cnv_cycle_counter : INTEGER;
32 SIGNAL cnv_s : STD_LOGIC;
34 SIGNAL cnv_s : STD_LOGIC;
33 SIGNAL cnv_sync : STD_LOGIC;
35 SIGNAL cnv_sync : STD_LOGIC;
34 SIGNAL cnv_sync_pre : STD_LOGIC;
36 SIGNAL cnv_sync_pre : STD_LOGIC;
35
37
36 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
38 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
37 SIGNAL enable_ADC : STD_LOGIC;
39 SIGNAL enable_ADC : STD_LOGIC;
38
40
39
41
40 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
42 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
41
43
42 SIGNAL channel_counter : INTEGER;
44 SIGNAL channel_counter : INTEGER;
43 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
45 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
44
46
45 SIGNAL ADC_data_selected : Samples14;
47 SIGNAL ADC_data_selected : Samples14;
46 SIGNAL ADC_data_result : Samples15;
48 SIGNAL ADC_data_result : Samples15;
47
49
48 SIGNAL sample_counter : INTEGER;
50 SIGNAL sample_counter : INTEGER;
51 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
52
53 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
49
54
50 BEGIN
55 BEGIN
51
56
52
57
53 -----------------------------------------------------------------------------
58 -----------------------------------------------------------------------------
54 -- CNV GEN
59 -- CNV GEN
55 -----------------------------------------------------------------------------
60 -----------------------------------------------------------------------------
56 PROCESS (cnv_clk, cnv_rstn)
61 PROCESS (cnv_clk, cnv_rstn)
57 BEGIN -- PROCESS
62 BEGIN -- PROCESS
58 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
63 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
59 cnv_cycle_counter <= 0;
64 cnv_cycle_counter <= 0;
60 cnv_s <= '0';
65 cnv_s <= '0';
61 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
66 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
62 IF cnv_cycle_counter < ncycle_cnv-1 THEN
67 IF cnv_cycle_counter < ncycle_cnv-1 THEN
63 cnv_cycle_counter <= cnv_cycle_counter + 1;
68 cnv_cycle_counter <= cnv_cycle_counter + 1;
64 IF cnv_cycle_counter < ncycle_cnv_high THEN
69 IF cnv_cycle_counter < ncycle_cnv_high THEN
65 cnv_s <= '1';
70 cnv_s <= '1';
66 ELSE
71 ELSE
67 cnv_s <= '0';
72 cnv_s <= '0';
68 END IF;
73 END IF;
69 ELSE
74 ELSE
70 cnv_s <= '1';
75 cnv_s <= '1';
71 cnv_cycle_counter <= 0;
76 cnv_cycle_counter <= 0;
72 END IF;
77 END IF;
73 END IF;
78 END IF;
74 END PROCESS;
79 END PROCESS;
75
80
76 cnv <= cnv_s;
81 cnv <= cnv_s;
77
82
78
83
79 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
80 -- SYNC CNV
85 -- SYNC CNV
81 -----------------------------------------------------------------------------
86 -----------------------------------------------------------------------------
82
87
83 SYNC_FF_cnv : SYNC_FF
88 SYNC_FF_cnv : SYNC_FF
84 GENERIC MAP (
89 GENERIC MAP (
85 NB_FF_OF_SYNC => 2)
90 NB_FF_OF_SYNC => 2)
86 PORT MAP (
91 PORT MAP (
87 clk => clk,
92 clk => clk,
88 rstn => rstn,
93 rstn => rstn,
89 A => cnv_s,
94 A => cnv_s,
90 A_sync => cnv_sync);
95 A_sync => cnv_sync);
91
96
92
97
93 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
94 -- DATA GEN Output Enable
99 -- DATA GEN Output Enable
95 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
96 PROCESS (clk, rstn)
101 PROCESS (clk, rstn)
97 BEGIN -- PROCESS
102 BEGIN -- PROCESS
98 IF rstn = '0' THEN -- asynchronous reset (active low)
103 IF rstn = '0' THEN -- asynchronous reset (active low)
99 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
104 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
100 cnv_sync_pre <= '0';
105 cnv_sync_pre <= '0';
101 enable_ADC <= '0';
106 enable_ADC <= '0';
102 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
107 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
103 cnv_sync_pre <= cnv_sync;
108 cnv_sync_pre <= cnv_sync;
104 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
109 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
105 enable_ADC <= '1';
110 enable_ADC <= '1';
106 ADC_nOE_reg(0) <= '0';
111 ADC_nOE_reg(0) <= '0';
107 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
112 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
108 ELSE
113 ELSE
109 enable_ADC <= NOT enable_ADC;
114 enable_ADC <= NOT enable_ADC;
110 IF enable_ADC = '0' THEN
115 IF enable_ADC = '0' THEN
111 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
116 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
112 END IF;
117 END IF;
113 END IF;
118 END IF;
114
119
115 END IF;
120 END IF;
116 END PROCESS;
121 END PROCESS;
117
122
118 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
123 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
119
124
120 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
121 -- ADC READ DATA
126 -- ADC READ DATA
122 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
123 PROCESS (clk, rstn)
128 PROCESS (clk, rstn)
124 BEGIN -- PROCESS
129 BEGIN -- PROCESS
125 IF rstn = '0' THEN -- asynchronous reset (active low)
130 IF rstn = '0' THEN -- asynchronous reset (active low)
126 channel_counter <= MAX_COUNTER;
131 channel_counter <= MAX_COUNTER;
127 sample_reg(0) <= (OTHERS => '0');
128 sample_reg(1) <= (OTHERS => '0');
129 sample_reg(2) <= (OTHERS => '0');
130 sample_reg(3) <= (OTHERS => '0');
131 sample_reg(4) <= (OTHERS => '0');
132 sample_reg(5) <= (OTHERS => '0');
133 sample_reg(6) <= (OTHERS => '0');
134 sample_reg(7) <= (OTHERS => '0');
135
132
133 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
134 sample_reg(I) <= (OTHERS => '0');
135 END LOOP all_sample_reg_init;
136
136 sample_val <= '0';
137 sample_val <= '0';
137 sample_counter <= 0;
138 sample_counter <= 0;
138 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
139 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
139 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
140 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
140 channel_counter <= 0;
141 channel_counter <= 0;
141 ELSE
142 ELSE
142 IF channel_counter < MAX_COUNTER THEN
143 IF channel_counter < MAX_COUNTER THEN
143 channel_counter <= channel_counter + 1;
144 channel_counter <= channel_counter + 1;
144 END IF;
145 END IF;
145 END IF;
146 END IF;
146 sample_val <= '0';
147 sample_val <= '0';
147
148
148 CASE channel_counter IS
149 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
149 WHEN 0*2 => sample_reg(0) <= ADC_data_result(14 DOWNTO 1);
150 IF channel_counter = I*2 THEN
150 WHEN 1*2 => sample_reg(1) <= ADC_data_result(14 DOWNTO 1);
151 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
151 WHEN 2*2 => sample_reg(2) <= ADC_data_result(14 DOWNTO 1);
152 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
152 WHEN 3*2 => sample_reg(3) <= ADC_data_result(14 DOWNTO 1);
153 WHEN 4*2 => sample_reg(4) <= ADC_data_result(14 DOWNTO 1);
154 WHEN 5*2 => sample_reg(5) <= ADC_data_result(14 DOWNTO 1);
155 WHEN 6*2 => sample_reg(6) <= ADC_data_result(14 DOWNTO 1);
156 WHEN 7*2 => sample_reg(7) <= ADC_data_result(14 DOWNTO 1);
157 IF sample_counter = 9 THEN
158 sample_counter <= 0 ;
159 sample_val <= '1';
160 ELSE
153 ELSE
161 sample_counter <= sample_counter +1;
154 sample_reg(I) <= ADC_data;
162 END IF;
155 END IF;
163
156 END IF;
164 WHEN OTHERS => NULL;
157 END LOOP all_sample_reg;
165 END CASE;
166
158
159 IF channel_counter = (ChanelCount-1)*2 THEN
160
161 IF sample_counter = MAX_SAMPLE_COUNTER THEN
162 sample_counter <= 0 ;
163 sample_val <= '1';
164 ELSE
165 sample_counter <= sample_counter +1;
166 END IF;
167
168 END IF;
167 END IF;
169 END IF;
168 END PROCESS;
170 END PROCESS;
169
171
172 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
173 -- BEGIN -- PROCESS mux_adc
174 -- CASE channel_counter IS
175 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
176 -- END CASE;
177 -- END PROCESS mux_adc;
178
179
180 -----------------------------------------------------------------------------
181 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
182 -----------------------------------------------------------------------------
170
183
171 WITH channel_counter SELECT
184 WITH channel_counter SELECT
172 ADC_data_selected <= sample_reg(0) WHEN 0*2,
185 ADC_data_selected <= sample_reg(0) WHEN 0*2,
173 sample_reg(1) WHEN 1*2,
186 sample_reg(1) WHEN 1*2,
174 sample_reg(2) WHEN 2*2,
187 sample_reg(2) WHEN 2*2,
175 sample_reg(3) WHEN 3*2,
188 sample_reg(3) WHEN 3*2,
176 sample_reg(4) WHEN 4*2,
189 sample_reg(4) WHEN 4*2,
177 sample_reg(5) WHEN 5*2,
190 sample_reg(5) WHEN 5*2,
178 sample_reg(6) WHEN 6*2,
191 sample_reg(6) WHEN 6*2,
179 sample_reg(7) WHEN OTHERS ;
192 sample_reg(7) WHEN 7*2,
193 sample_reg(8) WHEN OTHERS ;
180
194
195 -----------------------------------------------------------------------------
196 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
197 -----------------------------------------------------------------------------
181
198
182 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
199 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
183
200
184 sample <= sample_reg;
201 sample <= sample_reg;
185
186
187
188
189 --RHF1401_drvr_1: RHF1401_drvr
190 -- GENERIC MAP (
191 -- ChanelCount => ChanelCount)
192 -- PORT MAP (
193 -- cnv_clk => cnv_sync,
194 -- clk => clk,
195 -- rstn => rstn,
196 -- ADC_data => ADC_data,
197 -- --ADC_smpclk => OPEN,
198 -- ADC_nOE => ADC_nOE,
199 -- sample => sample,
200 -- sample_val => sample_val);
201
202
203
204
202
205 END ar_top_ad_conv_RHF1401;
203 END ar_top_ad_conv_RHF1401;
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@@ -1,7 +1,8
1 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
2 RHF1401.vhd
2 RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
4 top_ad_conv_RHF1401_withFilter.vhd
4 top_ad_conv_RHF1401_withFilter.vhd
5 TestModule_RHF1401.vhd
5 TestModule_RHF1401.vhd
6 top_ad_conv_ADS7886_v2.vhd
6 top_ad_conv_ADS7886_v2.vhd
7 ADS7886_drvr_v2.vhd
7 ADS7886_drvr_v2.vhd
8 lpp_lfr_hk.vhd
Show file before | Show file after | Hide comments
@@ -1,47 +1,48
1
1
2 --=================================================================================
2 --=================================================================================
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 --
4 --
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 --=================================================================================
6 --=================================================================================
7
7
8
8
9 LIBRARY ieee;
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.ALL;
10 USE ieee.std_logic_1164.ALL;
11 LIBRARY grlib;
11 LIBRARY grlib;
12 USE grlib.amba.ALL;
12 USE grlib.amba.ALL;
13 USE std.textio.ALL;
13 USE std.textio.ALL;
14
14
15
15
16 PACKAGE apb_devices_list IS
16 PACKAGE apb_devices_list IS
17
17
18
18
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20
20
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
40 CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#;
41 CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#;
41
42
42 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
43 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
43 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
44
45
45 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
46 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
46
47
47 END;
48 END;
Show file before | Show file after | Hide comments
@@ -1,491 +1,491
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
44 LIBRARY iap;
44 LIBRARY iap;
45 USE iap.memctrl.all;
45 USE iap.memctrl.all;
46
46
47
47
48 ENTITY leon3_soc IS
48 ENTITY leon3_soc IS
49 GENERIC (
49 GENERIC (
50 fabtech : INTEGER := apa3e;
50 fabtech : INTEGER := apa3e;
51 memtech : INTEGER := apa3e;
51 memtech : INTEGER := apa3e;
52 padtech : INTEGER := inferred;
52 padtech : INTEGER := inferred;
53 clktech : INTEGER := inferred;
53 clktech : INTEGER := inferred;
54 disas : INTEGER := 0; -- Enable disassembly to console
54 disas : INTEGER := 0; -- Enable disassembly to console
55 dbguart : INTEGER := 0; -- Print UART on console
55 dbguart : INTEGER := 0; -- Print UART on console
56 pclow : INTEGER := 2;
56 pclow : INTEGER := 2;
57 --
57 --
58 clk_freq : INTEGER := 25000; --kHz
58 clk_freq : INTEGER := 25000; --kHz
59 --
59 --
60 NB_CPU : INTEGER := 1;
60 NB_CPU : INTEGER := 1;
61 ENABLE_FPU : INTEGER := 1;
61 ENABLE_FPU : INTEGER := 1;
62 FPU_NETLIST : INTEGER := 1;
62 FPU_NETLIST : INTEGER := 1;
63 ENABLE_DSU : INTEGER := 1;
63 ENABLE_DSU : INTEGER := 1;
64 ENABLE_AHB_UART : INTEGER := 1;
64 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_APB_UART : INTEGER := 1;
65 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_IRQMP : INTEGER := 1;
66 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_GPT : INTEGER := 1;
67 ENABLE_GPT : INTEGER := 1;
68 --
68 --
69 NB_AHB_MASTER : INTEGER := 0;
69 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_SLAVE : INTEGER := 0;
70 NB_AHB_SLAVE : INTEGER := 1;
71 NB_APB_SLAVE : INTEGER := 0;
71 NB_APB_SLAVE : INTEGER := 1;
72 --
72 --
73 ADDRESS_SIZE : INTEGER := 20;
73 ADDRESS_SIZE : INTEGER := 20;
74 USES_IAP_MEMCTRLR : INTEGER := 0
74 USES_IAP_MEMCTRLR : INTEGER := 0
75
75
76 );
76 );
77 PORT (
77 PORT (
78 clk : IN STD_ULOGIC;
78 clk : IN STD_ULOGIC;
79 reset : IN STD_ULOGIC;
79 reset : IN STD_ULOGIC;
80
80
81 errorn : OUT STD_ULOGIC;
81 errorn : OUT STD_ULOGIC;
82
82
83 -- UART AHB ---------------------------------------------------------------
83 -- UART AHB ---------------------------------------------------------------
84 ahbrxd : IN STD_ULOGIC; -- DSU rx data
84 ahbrxd : IN STD_ULOGIC; -- DSU rx data
85 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
85 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
86
86
87 -- UART APB ---------------------------------------------------------------
87 -- UART APB ---------------------------------------------------------------
88 urxd1 : IN STD_ULOGIC; -- UART1 rx data
88 urxd1 : IN STD_ULOGIC; -- UART1 rx data
89 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
89 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
90
90
91 -- RAM --------------------------------------------------------------------
91 -- RAM --------------------------------------------------------------------
92 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
92 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
93 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 nSRAM_BE0 : OUT STD_LOGIC;
94 nSRAM_BE0 : OUT STD_LOGIC;
95 nSRAM_BE1 : OUT STD_LOGIC;
95 nSRAM_BE1 : OUT STD_LOGIC;
96 nSRAM_BE2 : OUT STD_LOGIC;
96 nSRAM_BE2 : OUT STD_LOGIC;
97 nSRAM_BE3 : OUT STD_LOGIC;
97 nSRAM_BE3 : OUT STD_LOGIC;
98 nSRAM_WE : OUT STD_LOGIC;
98 nSRAM_WE : OUT STD_LOGIC;
99 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
99 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 downto 0);
100 nSRAM_OE : OUT STD_LOGIC;
100 nSRAM_OE : OUT STD_LOGIC;
101 nSRAM_READY : IN STD_LOGIC;
101 nSRAM_READY : IN STD_LOGIC;
102 SRAM_MBE : INOUT STD_LOGIC;
102 SRAM_MBE : INOUT STD_LOGIC;
103 -- APB --------------------------------------------------------------------
103 -- APB --------------------------------------------------------------------
104 apbi_ext : OUT apb_slv_in_type;
104 apbi_ext : OUT apb_slv_in_type;
105 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
105 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
106 -- AHB_Slave --------------------------------------------------------------
106 -- AHB_Slave --------------------------------------------------------------
107 ahbi_s_ext : OUT ahb_slv_in_type;
107 ahbi_s_ext : OUT ahb_slv_in_type;
108 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
108 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
109 -- AHB_Master -------------------------------------------------------------
109 -- AHB_Master -------------------------------------------------------------
110 ahbi_m_ext : OUT AHB_Mst_In_Type;
110 ahbi_m_ext : OUT AHB_Mst_In_Type;
111 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
111 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
112
112
113 );
113 );
114 END;
114 END;
115
115
116 ARCHITECTURE Behavioral OF leon3_soc IS
116 ARCHITECTURE Behavioral OF leon3_soc IS
117
117
118 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
119 -- CONFIG -------------------------------------------------------------------
119 -- CONFIG -------------------------------------------------------------------
120 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
121
121
122 -- Clock generator
122 -- Clock generator
123 constant CFG_CLKMUL : integer := (1);
123 constant CFG_CLKMUL : integer := (1);
124 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
124 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
125 constant CFG_OCLKDIV : integer := (1);
125 constant CFG_OCLKDIV : integer := (1);
126 constant CFG_CLK_NOFB : integer := 0;
126 constant CFG_CLK_NOFB : integer := 0;
127 -- LEON3 processor core
127 -- LEON3 processor core
128 constant CFG_LEON3 : integer := 1;
128 constant CFG_LEON3 : integer := 1;
129 constant CFG_NCPU : integer := NB_CPU;
129 constant CFG_NCPU : integer := NB_CPU;
130 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
130 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
131 constant CFG_V8 : integer := 0;
131 constant CFG_V8 : integer := 0;
132 constant CFG_MAC : integer := 0;
132 constant CFG_MAC : integer := 0;
133 constant CFG_SVT : integer := 0;
133 constant CFG_SVT : integer := 0;
134 constant CFG_RSTADDR : integer := 16#00000#;
134 constant CFG_RSTADDR : integer := 16#00000#;
135 constant CFG_LDDEL : integer := (1);
135 constant CFG_LDDEL : integer := (1);
136 constant CFG_NWP : integer := (0);
136 constant CFG_NWP : integer := (0);
137 constant CFG_PWD : integer := 1*2;
137 constant CFG_PWD : integer := 1*2;
138 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
138 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
139 -- 1*(8 + 16 * 0) => grfpu-light
139 -- 1*(8 + 16 * 0) => grfpu-light
140 -- 1*(8 + 16 * 1) => netlist
140 -- 1*(8 + 16 * 1) => netlist
141 -- 0*(8 + 16 * 0) => No FPU
141 -- 0*(8 + 16 * 0) => No FPU
142 -- 0*(8 + 16 * 1) => No FPU;
142 -- 0*(8 + 16 * 1) => No FPU;
143 constant CFG_ICEN : integer := 1;
143 constant CFG_ICEN : integer := 1;
144 constant CFG_ISETS : integer := 1;
144 constant CFG_ISETS : integer := 1;
145 constant CFG_ISETSZ : integer := 4;
145 constant CFG_ISETSZ : integer := 4;
146 constant CFG_ILINE : integer := 4;
146 constant CFG_ILINE : integer := 4;
147 constant CFG_IREPL : integer := 0;
147 constant CFG_IREPL : integer := 0;
148 constant CFG_ILOCK : integer := 0;
148 constant CFG_ILOCK : integer := 0;
149 constant CFG_ILRAMEN : integer := 0;
149 constant CFG_ILRAMEN : integer := 0;
150 constant CFG_ILRAMADDR: integer := 16#8E#;
150 constant CFG_ILRAMADDR: integer := 16#8E#;
151 constant CFG_ILRAMSZ : integer := 1;
151 constant CFG_ILRAMSZ : integer := 1;
152 constant CFG_DCEN : integer := 1;
152 constant CFG_DCEN : integer := 1;
153 constant CFG_DSETS : integer := 1;
153 constant CFG_DSETS : integer := 1;
154 constant CFG_DSETSZ : integer := 4;
154 constant CFG_DSETSZ : integer := 4;
155 constant CFG_DLINE : integer := 4;
155 constant CFG_DLINE : integer := 4;
156 constant CFG_DREPL : integer := 0;
156 constant CFG_DREPL : integer := 0;
157 constant CFG_DLOCK : integer := 0;
157 constant CFG_DLOCK : integer := 0;
158 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
158 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
159 constant CFG_DLRAMEN : integer := 0;
159 constant CFG_DLRAMEN : integer := 0;
160 constant CFG_DLRAMADDR: integer := 16#8F#;
160 constant CFG_DLRAMADDR: integer := 16#8F#;
161 constant CFG_DLRAMSZ : integer := 1;
161 constant CFG_DLRAMSZ : integer := 1;
162 constant CFG_MMUEN : integer := 0;
162 constant CFG_MMUEN : integer := 0;
163 constant CFG_ITLBNUM : integer := 2;
163 constant CFG_ITLBNUM : integer := 2;
164 constant CFG_DTLBNUM : integer := 2;
164 constant CFG_DTLBNUM : integer := 2;
165 constant CFG_TLB_TYPE : integer := 1 + 0*2;
165 constant CFG_TLB_TYPE : integer := 1 + 0*2;
166 constant CFG_TLB_REP : integer := 1;
166 constant CFG_TLB_REP : integer := 1;
167
167
168 constant CFG_DSU : integer := ENABLE_DSU;
168 constant CFG_DSU : integer := ENABLE_DSU;
169 constant CFG_ITBSZ : integer := 0;
169 constant CFG_ITBSZ : integer := 0;
170 constant CFG_ATBSZ : integer := 0;
170 constant CFG_ATBSZ : integer := 0;
171
171
172 -- AMBA settings
172 -- AMBA settings
173 constant CFG_DEFMST : integer := (0);
173 constant CFG_DEFMST : integer := (0);
174 constant CFG_RROBIN : integer := 1;
174 constant CFG_RROBIN : integer := 1;
175 constant CFG_SPLIT : integer := 0;
175 constant CFG_SPLIT : integer := 0;
176 constant CFG_AHBIO : integer := 16#FFF#;
176 constant CFG_AHBIO : integer := 16#FFF#;
177 constant CFG_APBADDR : integer := 16#800#;
177 constant CFG_APBADDR : integer := 16#800#;
178
178
179 -- DSU UART
179 -- DSU UART
180 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
180 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
181
181
182 -- LEON2 memory controller
182 -- LEON2 memory controller
183 constant CFG_MCTRL_SDEN : integer := 0;
183 constant CFG_MCTRL_SDEN : integer := 0;
184
184
185 -- UART 1
185 -- UART 1
186 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
186 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
187 constant CFG_UART1_FIFO : integer := 1;
187 constant CFG_UART1_FIFO : integer := 1;
188
188
189 -- LEON3 interrupt controller
189 -- LEON3 interrupt controller
190 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
190 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
191
191
192 -- Modular timer
192 -- Modular timer
193 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
193 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
194 constant CFG_GPT_NTIM : integer := (2);
194 constant CFG_GPT_NTIM : integer := (2);
195 constant CFG_GPT_SW : integer := (8);
195 constant CFG_GPT_SW : integer := (8);
196 constant CFG_GPT_TW : integer := (32);
196 constant CFG_GPT_TW : integer := (32);
197 constant CFG_GPT_IRQ : integer := (8);
197 constant CFG_GPT_IRQ : integer := (8);
198 constant CFG_GPT_SEPIRQ : integer := 1;
198 constant CFG_GPT_SEPIRQ : integer := 1;
199 constant CFG_GPT_WDOGEN : integer := 0;
199 constant CFG_GPT_WDOGEN : integer := 0;
200 constant CFG_GPT_WDOG : integer := 16#0#;
200 constant CFG_GPT_WDOG : integer := 16#0#;
201 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
202
202
203 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
204 -- SIGNALs
204 -- SIGNALs
205 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
206 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
206 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
207 -- CLK & RST --
207 -- CLK & RST --
208 SIGNAL clk2x : STD_ULOGIC;
208 SIGNAL clk2x : STD_ULOGIC;
209 SIGNAL clkmn : STD_ULOGIC;
209 SIGNAL clkmn : STD_ULOGIC;
210 SIGNAL clkm : STD_ULOGIC;
210 SIGNAL clkm : STD_ULOGIC;
211 SIGNAL rstn : STD_ULOGIC;
211 SIGNAL rstn : STD_ULOGIC;
212 SIGNAL rstraw : STD_ULOGIC;
212 SIGNAL rstraw : STD_ULOGIC;
213 SIGNAL pciclk : STD_ULOGIC;
213 SIGNAL pciclk : STD_ULOGIC;
214 SIGNAL sdclkl : STD_ULOGIC;
214 SIGNAL sdclkl : STD_ULOGIC;
215 SIGNAL cgi : clkgen_in_type;
215 SIGNAL cgi : clkgen_in_type;
216 SIGNAL cgo : clkgen_out_type;
216 SIGNAL cgo : clkgen_out_type;
217 --- AHB / APB
217 --- AHB / APB
218 SIGNAL apbi : apb_slv_in_type;
218 SIGNAL apbi : apb_slv_in_type;
219 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
219 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
220 SIGNAL ahbsi : ahb_slv_in_type;
220 SIGNAL ahbsi : ahb_slv_in_type;
221 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
221 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
222 SIGNAL ahbmi : ahb_mst_in_type;
222 SIGNAL ahbmi : ahb_mst_in_type;
223 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
223 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
224 --UART
224 --UART
225 SIGNAL ahbuarti : uart_in_type;
225 SIGNAL ahbuarti : uart_in_type;
226 SIGNAL ahbuarto : uart_out_type;
226 SIGNAL ahbuarto : uart_out_type;
227 SIGNAL apbuarti : uart_in_type;
227 SIGNAL apbuarti : uart_in_type;
228 SIGNAL apbuarto : uart_out_type;
228 SIGNAL apbuarto : uart_out_type;
229 --MEM CTRLR
229 --MEM CTRLR
230 SIGNAL memi : memory_in_type;
230 SIGNAL memi : memory_in_type;
231 SIGNAL memo : memory_out_type;
231 SIGNAL memo : memory_out_type;
232 SIGNAL wpo : wprot_out_type;
232 SIGNAL wpo : wprot_out_type;
233 SIGNAL sdo : sdram_out_type;
233 SIGNAL sdo : sdram_out_type;
234 SIGNAl mbe : std_logic; -- enable memory programming
234 SIGNAl mbe : std_logic; -- enable memory programming
235 SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal
235 SIGNAL mbe_drive : std_logic; -- drive the MBE memory signal
236 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0);
236 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 downto 0);
237 SIGNAL nSRAM_OE_s : STD_LOGIC;
237 SIGNAL nSRAM_OE_s : STD_LOGIC;
238 --IRQ
238 --IRQ
239 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
239 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
240 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
240 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
241 --Timer
241 --Timer
242 SIGNAL gpti : gptimer_in_type;
242 SIGNAL gpti : gptimer_in_type;
243 SIGNAL gpto : gptimer_out_type;
243 SIGNAL gpto : gptimer_out_type;
244 --DSU
244 --DSU
245 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
245 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
246 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
246 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
247 SIGNAL dsui : dsu_in_type;
247 SIGNAL dsui : dsu_in_type;
248 SIGNAL dsuo : dsu_out_type;
248 SIGNAL dsuo : dsu_out_type;
249 -----------------------------------------------------------------------------
249 -----------------------------------------------------------------------------
250
250
251
251
252 BEGIN
252 BEGIN
253
253
254
254
255 ----------------------------------------------------------------------
255 ----------------------------------------------------------------------
256 --- Reset and Clock generation -------------------------------------
256 --- Reset and Clock generation -------------------------------------
257 ----------------------------------------------------------------------
257 ----------------------------------------------------------------------
258
258
259 cgi.pllctrl <= "00";
259 cgi.pllctrl <= "00";
260 cgi.pllrst <= rstraw;
260 cgi.pllrst <= rstraw;
261
261
262 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
262 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
263
263
264 clkgen0 : clkgen -- clock generator
264 clkgen0 : clkgen -- clock generator
265 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
265 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
266 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
266 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
267 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
267 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
268
268
269 ----------------------------------------------------------------------
269 ----------------------------------------------------------------------
270 --- LEON3 processor / DSU / IRQ ------------------------------------
270 --- LEON3 processor / DSU / IRQ ------------------------------------
271 ----------------------------------------------------------------------
271 ----------------------------------------------------------------------
272
272
273 l3 : IF CFG_LEON3 = 1 GENERATE
273 l3 : IF CFG_LEON3 = 1 GENERATE
274 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
274 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
275 u0 : leon3s -- LEON3 processor
275 u0 : leon3s -- LEON3 processor
276 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
276 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
277 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
277 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
278 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
278 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
279 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
279 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
280 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
280 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
281 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
281 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
282 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
282 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
283 irqi(i), irqo(i), dbgi(i), dbgo(i));
283 irqi(i), irqo(i), dbgi(i), dbgo(i));
284 END GENERATE;
284 END GENERATE;
285 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
285 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
286
286
287 dsugen : IF CFG_DSU = 1 GENERATE
287 dsugen : IF CFG_DSU = 1 GENERATE
288 dsu0 : dsu3 -- LEON3 Debug Support Unit
288 dsu0 : dsu3 -- LEON3 Debug Support Unit
289 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
289 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
290 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
290 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
291 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
291 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
292 dsui.enable <= '1';
292 dsui.enable <= '1';
293 dsui.break <= '0';
293 dsui.break <= '0';
294 END GENERATE;
294 END GENERATE;
295 END GENERATE;
295 END GENERATE;
296
296
297 nodsu : IF CFG_DSU = 0 GENERATE
297 nodsu : IF CFG_DSU = 0 GENERATE
298 ahbso(2) <= ahbs_none;
298 ahbso(2) <= ahbs_none;
299 dsuo.tstop <= '0';
299 dsuo.tstop <= '0';
300 dsuo.active <= '0';
300 dsuo.active <= '0';
301 END GENERATE;
301 END GENERATE;
302
302
303 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
303 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
304 irqctrl0 : irqmp -- interrupt controller
304 irqctrl0 : irqmp -- interrupt controller
305 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
305 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
306 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
306 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
307 END GENERATE;
307 END GENERATE;
308 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
308 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
309 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
309 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
310 irqi(i).irl <= "0000";
310 irqi(i).irl <= "0000";
311 END GENERATE;
311 END GENERATE;
312 apbo(2) <= apb_none;
312 apbo(2) <= apb_none;
313 END GENERATE;
313 END GENERATE;
314
314
315 ----------------------------------------------------------------------
315 ----------------------------------------------------------------------
316 --- Memory controllers ---------------------------------------------
316 --- Memory controllers ---------------------------------------------
317 ----------------------------------------------------------------------
317 ----------------------------------------------------------------------
318 ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
318 ESAMEMCT: IF USES_IAP_MEMCTRLR =0 GENERATE
319 memctrlr : mctrl GENERIC MAP (
319 memctrlr : mctrl GENERIC MAP (
320 hindex => 0,
320 hindex => 0,
321 pindex => 0,
321 pindex => 0,
322 paddr => 0,
322 paddr => 0,
323 srbanks => 1
323 srbanks => 1
324 )
324 )
325 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
325 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
326 memi.bexcn <= '1';
326 memi.bexcn <= '1';
327 memi.brdyn <= '1';
327 memi.brdyn <= '1';
328
328
329 nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0));
329 nSRAM_CE_s <= NOT (memo.ramsn(1 downto 0));
330 nSRAM_OE_s <= memo.ramoen(0);
330 nSRAM_OE_s <= memo.ramoen(0);
331 END GENERATE;
331 END GENERATE;
332
332
333 IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
333 IAPMEMCT: IF USES_IAP_MEMCTRLR =1 GENERATE
334 memctrlr : srctrle_0ws
334 memctrlr : srctrle_0ws
335 GENERIC MAP(
335 GENERIC MAP(
336 hindex => 0,
336 hindex => 0,
337 pindex => 0,
337 pindex => 0,
338 paddr => 0,
338 paddr => 0,
339 srbanks => 2,
339 srbanks => 2,
340 banksz => 8, --512k * 32
340 banksz => 8, --512k * 32
341 rmw => 1,
341 rmw => 1,
342 --Aeroflex memory generics:
342 --Aeroflex memory generics:
343 mprog => 1, -- program memory by default values after reset
343 mprog => 1, -- program memory by default values after reset
344 mpsrate => 12, -- default scrub rate period
344 mpsrate => 12, -- default scrub rate period
345 mpb2s => 4, -- default busy to scrub delay
345 mpb2s => 4, -- default busy to scrub delay
346 mpapb => 1, -- instantiate apb register
346 mpapb => 1, -- instantiate apb register
347 mchipcnt => 2,
347 mchipcnt => 2,
348 mpenall => 1 -- when 0 program only E1 chip, else program all dies
348 mpenall => 1 -- when 0 program only E1 chip, else program all dies
349 )
349 )
350 PORT MAP (
350 PORT MAP (
351 rst => rstn,
351 rst => rstn,
352 clk => clkm,
352 clk => clkm,
353 ahbsi => ahbsi,
353 ahbsi => ahbsi,
354 ahbso => ahbso(0),
354 ahbso => ahbso(0),
355 apbi => apbi,
355 apbi => apbi,
356 apbo => apbo(0),
356 apbo => apbo(0),
357 sri => memi,
357 sri => memi,
358 sro => memo,
358 sro => memo,
359 --Aeroflex memory signals:
359 --Aeroflex memory signals:
360 ucerr => open, -- uncorrectable error signal
360 ucerr => open, -- uncorrectable error signal
361 mbe => mbe, -- enable memory programming
361 mbe => mbe, -- enable memory programming
362 mbe_drive => mbe_drive -- drive the MBE memory signal
362 mbe_drive => mbe_drive -- drive the MBE memory signal
363 );
363 );
364
364
365 memi.brdyn <= nSRAM_READY;
365 memi.brdyn <= nSRAM_READY;
366
366
367 mbe_pad : iopad
367 mbe_pad : iopad
368 GENERIC MAP(tech => padtech)
368 GENERIC MAP(tech => padtech)
369 PORT MAP(pad => SRAM_MBE,
369 PORT MAP(pad => SRAM_MBE,
370 i => mbe,
370 i => mbe,
371 en => mbe_drive,
371 en => mbe_drive,
372 o => memi.bexcn );
372 o => memi.bexcn );
373
373
374 nSRAM_CE_s <= (memo.ramsn(1 downto 0));
374 nSRAM_CE_s <= (memo.ramsn(1 downto 0));
375 nSRAM_OE_s <= memo.oen;
375 nSRAM_OE_s <= memo.oen;
376
376
377 END GENERATE;
377 END GENERATE;
378
378
379
379
380 memi.writen <= '1';
380 memi.writen <= '1';
381 memi.wrn <= "1111";
381 memi.wrn <= "1111";
382 memi.bwidth <= "10";
382 memi.bwidth <= "10";
383
383
384 bdr : FOR i IN 0 TO 3 GENERATE
384 bdr : FOR i IN 0 TO 3 GENERATE
385 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
385 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8,oepol=> USES_IAP_MEMCTRLR)
386 PORT MAP (
386 PORT MAP (
387 data(31-i*8 DOWNTO 24-i*8),
387 data(31-i*8 DOWNTO 24-i*8),
388 memo.data(31-i*8 DOWNTO 24-i*8),
388 memo.data(31-i*8 DOWNTO 24-i*8),
389 memo.bdrive(i),
389 memo.bdrive(i),
390 memi.data(31-i*8 DOWNTO 24-i*8));
390 memi.data(31-i*8 DOWNTO 24-i*8));
391 END GENERATE;
391 END GENERATE;
392
392
393 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
393 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
394 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
394 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
395 rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
395 rams_pad : outpadv GENERIC MAP (tech => padtech,width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
396 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
396 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
397 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
397 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
398 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
398 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
399 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
399 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
400 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
400 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
401 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
401 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
402
402
403
403
404
404
405 ----------------------------------------------------------------------
405 ----------------------------------------------------------------------
406 --- AHB CONTROLLER -------------------------------------------------
406 --- AHB CONTROLLER -------------------------------------------------
407 ----------------------------------------------------------------------
407 ----------------------------------------------------------------------
408 ahb0 : ahbctrl -- AHB arbiter/multiplexer
408 ahb0 : ahbctrl -- AHB arbiter/multiplexer
409 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
409 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
410 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
410 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
411 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
411 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
412 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
412 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
413
413
414 ----------------------------------------------------------------------
414 ----------------------------------------------------------------------
415 --- AHB UART -------------------------------------------------------
415 --- AHB UART -------------------------------------------------------
416 ----------------------------------------------------------------------
416 ----------------------------------------------------------------------
417 dcomgen : IF CFG_AHB_UART = 1 GENERATE
417 dcomgen : IF CFG_AHB_UART = 1 GENERATE
418 dcom0 : ahbuart
418 dcom0 : ahbuart
419 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
419 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
420 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
420 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
421 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
421 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
422 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
422 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
423 END GENERATE;
423 END GENERATE;
424 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
424 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
425
425
426 ----------------------------------------------------------------------
426 ----------------------------------------------------------------------
427 --- APB Bridge -----------------------------------------------------
427 --- APB Bridge -----------------------------------------------------
428 ----------------------------------------------------------------------
428 ----------------------------------------------------------------------
429 apb0 : apbctrl -- AHB/APB bridge
429 apb0 : apbctrl -- AHB/APB bridge
430 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
430 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
431 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
431 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
432
432
433 ----------------------------------------------------------------------
433 ----------------------------------------------------------------------
434 --- GPT Timer ------------------------------------------------------
434 --- GPT Timer ------------------------------------------------------
435 ----------------------------------------------------------------------
435 ----------------------------------------------------------------------
436 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
436 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
437 timer0 : gptimer -- timer unit
437 timer0 : gptimer -- timer unit
438 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
438 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
439 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
439 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
440 nbits => CFG_GPT_TW)
440 nbits => CFG_GPT_TW)
441 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
441 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
442 gpti.dhalt <= dsuo.tstop;
442 gpti.dhalt <= dsuo.tstop;
443 gpti.extclk <= '0';
443 gpti.extclk <= '0';
444 END GENERATE;
444 END GENERATE;
445 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
445 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
446
446
447
447
448 ----------------------------------------------------------------------
448 ----------------------------------------------------------------------
449 --- APB UART -------------------------------------------------------
449 --- APB UART -------------------------------------------------------
450 ----------------------------------------------------------------------
450 ----------------------------------------------------------------------
451 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
451 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
452 uart1 : apbuart -- UART 1
452 uart1 : apbuart -- UART 1
453 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
453 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
454 fifosize => CFG_UART1_FIFO)
454 fifosize => CFG_UART1_FIFO)
455 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
455 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
456 apbuarti.rxd <= urxd1;
456 apbuarti.rxd <= urxd1;
457 apbuarti.extclk <= '0';
457 apbuarti.extclk <= '0';
458 utxd1 <= apbuarto.txd;
458 utxd1 <= apbuarto.txd;
459 apbuarti.ctsn <= '0';
459 apbuarti.ctsn <= '0';
460 END GENERATE;
460 END GENERATE;
461 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
461 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
462
462
463 -------------------------------------------------------------------------------
463 -------------------------------------------------------------------------------
464 -- AMBA BUS -------------------------------------------------------------------
464 -- AMBA BUS -------------------------------------------------------------------
465 -------------------------------------------------------------------------------
465 -------------------------------------------------------------------------------
466
466
467 -- APB --------------------------------------------------------------------
467 -- APB --------------------------------------------------------------------
468 apbi_ext <= apbi;
468 apbi_ext <= apbi;
469 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
469 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
470 max_16_apb: IF I + 5 < 16 GENERATE
470 max_16_apb: IF I + 5 < 16 GENERATE
471 apbo(I+5)<= apbo_ext(I+5);
471 apbo(I+5)<= apbo_ext(I+5);
472 END GENERATE max_16_apb;
472 END GENERATE max_16_apb;
473 END GENERATE all_apb;
473 END GENERATE all_apb;
474 -- AHB_Slave --------------------------------------------------------------
474 -- AHB_Slave --------------------------------------------------------------
475 ahbi_s_ext <= ahbsi;
475 ahbi_s_ext <= ahbsi;
476 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
476 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
477 max_16_ahbs: IF I + 3 < 16 GENERATE
477 max_16_ahbs: IF I + 3 < 16 GENERATE
478 ahbso(I+3) <= ahbo_s_ext(I+3);
478 ahbso(I+3) <= ahbo_s_ext(I+3);
479 END GENERATE max_16_ahbs;
479 END GENERATE max_16_ahbs;
480 END GENERATE all_ahbs;
480 END GENERATE all_ahbs;
481 -- AHB_Master -------------------------------------------------------------
481 -- AHB_Master -------------------------------------------------------------
482 ahbi_m_ext <= ahbmi;
482 ahbi_m_ext <= ahbmi;
483 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
483 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
484 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
484 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
485 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
485 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
486 END GENERATE max_16_ahbm;
486 END GENERATE max_16_ahbm;
487 END GENERATE all_ahbm;
487 END GENERATE all_ahbm;
488
488
489
489
490
490
491 END Behavioral;
491 END Behavioral; No newline at end of file
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@@ -1,419 +1,419
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.iir_filter.ALL;
29 USE lpp.iir_filter.ALL;
30 USE lpp.FILTERcfg.ALL;
30 USE lpp.FILTERcfg.ALL;
31 USE lpp.lpp_memory.ALL;
31 USE lpp.lpp_memory.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
33 USE lpp.cic_pkg.ALL;
34 USE data_type_pkg.ALL;
34 USE lpp.data_type_pkg.ALL;
35
35
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 LIBRARY grlib;
39 LIBRARY grlib;
40 USE grlib.amba.ALL;
40 USE grlib.amba.ALL;
41 USE grlib.stdlib.ALL;
41 USE grlib.stdlib.ALL;
42 USE grlib.devices.ALL;
42 USE grlib.devices.ALL;
43 USE GRLIB.DMA2AHB_Package.ALL;
43 USE GRLIB.DMA2AHB_Package.ALL;
44
44
45 ENTITY lpp_lfr_filter IS
45 ENTITY lpp_lfr_filter IS
46 GENERIC(
46 GENERIC(
47 Mem_use : INTEGER := use_RAM
47 Mem_use : INTEGER := use_RAM
48 );
48 );
49 PORT (
49 PORT (
50 sample : IN Samples(7 DOWNTO 0);
50 sample : IN Samples(7 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 --
52 --
53 clk : IN STD_LOGIC;
53 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
55 --
55 --
56 data_shaping_SP0 : IN STD_LOGIC;
56 data_shaping_SP0 : IN STD_LOGIC;
57 data_shaping_SP1 : IN STD_LOGIC;
57 data_shaping_SP1 : IN STD_LOGIC;
58 data_shaping_R0 : IN STD_LOGIC;
58 data_shaping_R0 : IN STD_LOGIC;
59 data_shaping_R1 : IN STD_LOGIC;
59 data_shaping_R1 : IN STD_LOGIC;
60 data_shaping_R2 : IN STD_LOGIC;
60 data_shaping_R2 : IN STD_LOGIC;
61 --
61 --
62 sample_f0_val : OUT STD_LOGIC;
62 sample_f0_val : OUT STD_LOGIC;
63 sample_f1_val : OUT STD_LOGIC;
63 sample_f1_val : OUT STD_LOGIC;
64 sample_f2_val : OUT STD_LOGIC;
64 sample_f2_val : OUT STD_LOGIC;
65 sample_f3_val : OUT STD_LOGIC;
65 sample_f3_val : OUT STD_LOGIC;
66 --
66 --
67 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
67 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
70 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)
71 );
71 );
72 END lpp_lfr_filter;
72 END lpp_lfr_filter;
73
73
74 ARCHITECTURE tb OF lpp_lfr_filter IS
74 ARCHITECTURE tb OF lpp_lfr_filter IS
75
75
76 COMPONENT Downsampling
76 COMPONENT Downsampling
77 GENERIC (
77 GENERIC (
78 ChanelCount : INTEGER;
78 ChanelCount : INTEGER;
79 SampleSize : INTEGER;
79 SampleSize : INTEGER;
80 DivideParam : INTEGER);
80 DivideParam : INTEGER);
81 PORT (
81 PORT (
82 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
84 sample_in_val : IN STD_LOGIC;
84 sample_in_val : IN STD_LOGIC;
85 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
85 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
86 sample_out_val : OUT STD_LOGIC;
86 sample_out_val : OUT STD_LOGIC;
87 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
87 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
88 END COMPONENT;
88 END COMPONENT;
89
89
90 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
91 CONSTANT ChanelCount : INTEGER := 8;
91 CONSTANT ChanelCount : INTEGER := 8;
92
92
93 -----------------------------------------------------------------------------
93 -----------------------------------------------------------------------------
94 SIGNAL sample_val_delay : STD_LOGIC;
94 SIGNAL sample_val_delay : STD_LOGIC;
95 -----------------------------------------------------------------------------
95 -----------------------------------------------------------------------------
96 CONSTANT Coef_SZ : INTEGER := 9;
96 CONSTANT Coef_SZ : INTEGER := 9;
97 CONSTANT CoefCntPerCel : INTEGER := 6;
97 CONSTANT CoefCntPerCel : INTEGER := 6;
98 CONSTANT CoefPerCel : INTEGER := 5;
98 CONSTANT CoefPerCel : INTEGER := 5;
99 CONSTANT Cels_count : INTEGER := 5;
99 CONSTANT Cels_count : INTEGER := 5;
100
100
101 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
101 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
102 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
102 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
103 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
103 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
104 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
104 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
105 --
105 --
106 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
106 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
107 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
107 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
109 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
110 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
110 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
111 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
111 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
112 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
112 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
113 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
113 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
114 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
114 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
115 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
115 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
117 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
118 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
118 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 -- SIGNAL sample_f0_val : STD_LOGIC;
120 -- SIGNAL sample_f0_val : STD_LOGIC;
121 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
121 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
122 SIGNAL sample_f0_s : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
122 SIGNAL sample_f0_s : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
123 --
123 --
124 -- SIGNAL sample_f1_val : STD_LOGIC;
124 -- SIGNAL sample_f1_val : STD_LOGIC;
125 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
125 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
126 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
126 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
127 --
127 --
128 -- SIGNAL sample_f2_val : STD_LOGIC;
128 -- SIGNAL sample_f2_val : STD_LOGIC;
129 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
129 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
130 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
130 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
131 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
131 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
132 SIGNAL sample_f2_cic_val : STD_LOGIC;
132 SIGNAL sample_f2_cic_val : STD_LOGIC;
133
133
134 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
134 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
135 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
135 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
136 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
136 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
137 SIGNAL sample_f3_cic_val : STD_LOGIC;
137 SIGNAL sample_f3_cic_val : STD_LOGIC;
138
138
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
140 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
141 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
141 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
142 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
142 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
143 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
143 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
144 -----------------------------------------------------------------------------
144 -----------------------------------------------------------------------------
145
145
146 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
146 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
147 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
147 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
148 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
148 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
149 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
149 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
150
150
151 SIGNAL sample_f0_val_s : STD_LOGIC;
151 SIGNAL sample_f0_val_s : STD_LOGIC;
152 SIGNAL sample_f1_val_s : STD_LOGIC;
152 SIGNAL sample_f1_val_s : STD_LOGIC;
153 BEGIN
153 BEGIN
154
154
155 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
156 PROCESS (clk, rstn)
156 PROCESS (clk, rstn)
157 BEGIN -- PROCESS
157 BEGIN -- PROCESS
158 IF rstn = '0' THEN -- asynchronous reset (active low)
158 IF rstn = '0' THEN -- asynchronous reset (active low)
159 sample_val_delay <= '0';
159 sample_val_delay <= '0';
160 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
160 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
161 sample_val_delay <= sample_val;
161 sample_val_delay <= sample_val;
162 END IF;
162 END IF;
163 END PROCESS;
163 END PROCESS;
164
164
165 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
166 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
166 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
167 SampleLoop : FOR j IN 0 TO 15 GENERATE
167 SampleLoop : FOR j IN 0 TO 15 GENERATE
168 sample_filter_in(i, j) <= sample(i)(j);
168 sample_filter_in(i, j) <= sample(i)(j);
169 END GENERATE;
169 END GENERATE;
170
170
171 sample_filter_in(i, 16) <= sample(i)(15);
171 sample_filter_in(i, 16) <= sample(i)(15);
172 sample_filter_in(i, 17) <= sample(i)(15);
172 sample_filter_in(i, 17) <= sample(i)(15);
173 END GENERATE;
173 END GENERATE;
174
174
175 coefs_v2 <= CoefsInitValCst_v2;
175 coefs_v2 <= CoefsInitValCst_v2;
176
176
177 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
177 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
178 GENERIC MAP (
178 GENERIC MAP (
179 tech => 0,
179 tech => 0,
180 Mem_use => Mem_use, -- use_RAM
180 Mem_use => Mem_use, -- use_RAM
181 Sample_SZ => 18,
181 Sample_SZ => 18,
182 Coef_SZ => Coef_SZ,
182 Coef_SZ => Coef_SZ,
183 Coef_Nb => 25,
183 Coef_Nb => 25,
184 Coef_sel_SZ => 5,
184 Coef_sel_SZ => 5,
185 Cels_count => Cels_count,
185 Cels_count => Cels_count,
186 ChanelsCount => ChanelCount)
186 ChanelsCount => ChanelCount)
187 PORT MAP (
187 PORT MAP (
188 rstn => rstn,
188 rstn => rstn,
189 clk => clk,
189 clk => clk,
190 virg_pos => 7,
190 virg_pos => 7,
191 coefs => coefs_v2,
191 coefs => coefs_v2,
192 sample_in_val => sample_val_delay,
192 sample_in_val => sample_val_delay,
193 sample_in => sample_filter_in,
193 sample_in => sample_filter_in,
194 sample_out_val => sample_filter_v2_out_val,
194 sample_out_val => sample_filter_v2_out_val,
195 sample_out => sample_filter_v2_out);
195 sample_out => sample_filter_v2_out);
196
196
197 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
198 -- DATA_SHAPING
198 -- DATA_SHAPING
199 -----------------------------------------------------------------------------
199 -----------------------------------------------------------------------------
200 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
200 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
201 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
201 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
202 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
202 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
203 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
203 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
204 END GENERATE all_data_shaping_in_loop;
204 END GENERATE all_data_shaping_in_loop;
205
205
206 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
206 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
207 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
207 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
208
208
209 PROCESS (clk, rstn)
209 PROCESS (clk, rstn)
210 BEGIN -- PROCESS
210 BEGIN -- PROCESS
211 IF rstn = '0' THEN -- asynchronous reset (active low)
211 IF rstn = '0' THEN -- asynchronous reset (active low)
212 sample_data_shaping_out_val <= '0';
212 sample_data_shaping_out_val <= '0';
213 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
213 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
214 sample_data_shaping_out_val <= sample_filter_v2_out_val;
214 sample_data_shaping_out_val <= sample_filter_v2_out_val;
215 END IF;
215 END IF;
216 END PROCESS;
216 END PROCESS;
217
217
218 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
218 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
219 PROCESS (clk, rstn)
219 PROCESS (clk, rstn)
220 BEGIN
220 BEGIN
221 IF rstn = '0' THEN
221 IF rstn = '0' THEN
222 sample_data_shaping_out(0, j) <= '0';
222 sample_data_shaping_out(0, j) <= '0';
223 sample_data_shaping_out(1, j) <= '0';
223 sample_data_shaping_out(1, j) <= '0';
224 sample_data_shaping_out(2, j) <= '0';
224 sample_data_shaping_out(2, j) <= '0';
225 sample_data_shaping_out(3, j) <= '0';
225 sample_data_shaping_out(3, j) <= '0';
226 sample_data_shaping_out(4, j) <= '0';
226 sample_data_shaping_out(4, j) <= '0';
227 sample_data_shaping_out(5, j) <= '0';
227 sample_data_shaping_out(5, j) <= '0';
228 sample_data_shaping_out(6, j) <= '0';
228 sample_data_shaping_out(6, j) <= '0';
229 sample_data_shaping_out(7, j) <= '0';
229 sample_data_shaping_out(7, j) <= '0';
230 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
230 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
231 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
231 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
232 IF data_shaping_SP0 = '1' THEN
232 IF data_shaping_SP0 = '1' THEN
233 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
233 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
234 ELSE
234 ELSE
235 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
235 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
236 END IF;
236 END IF;
237 IF data_shaping_SP1 = '1' THEN
237 IF data_shaping_SP1 = '1' THEN
238 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
238 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
239 ELSE
239 ELSE
240 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
240 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
241 END IF;
241 END IF;
242 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
242 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
243 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
243 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
244 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
244 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
245 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
245 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
246 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
246 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
247 END IF;
247 END IF;
248 END PROCESS;
248 END PROCESS;
249 END GENERATE;
249 END GENERATE;
250
250
251 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
251 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
252 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
252 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
253 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
253 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
254 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
254 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
255 END GENERATE;
255 END GENERATE;
256 END GENERATE;
256 END GENERATE;
257 -----------------------------------------------------------------------------
257 -----------------------------------------------------------------------------
258 -- F0 -- @24.576 kHz
258 -- F0 -- @24.576 kHz
259 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
260 Downsampling_f0 : Downsampling
260 Downsampling_f0 : Downsampling
261 GENERIC MAP (
261 GENERIC MAP (
262 ChanelCount => 8,
262 ChanelCount => 8,
263 SampleSize => 16,
263 SampleSize => 16,
264 DivideParam => 4)
264 DivideParam => 4)
265 PORT MAP (
265 PORT MAP (
266 clk => clk,
266 clk => clk,
267 rstn => rstn,
267 rstn => rstn,
268 sample_in_val => sample_filter_v2_out_val_s,
268 sample_in_val => sample_filter_v2_out_val_s,
269 sample_in => sample_filter_v2_out_s,
269 sample_in => sample_filter_v2_out_s,
270 sample_out_val => sample_f0_val_s,
270 sample_out_val => sample_f0_val_s,
271 sample_out => sample_f0);
271 sample_out => sample_f0);
272
272
273 sample_f0_val <= sample_f0_val_s;
273 sample_f0_val <= sample_f0_val_s;
274
274
275 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
275 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
276 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
276 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
277 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
277 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
278 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
278 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
279 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
279 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
280 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
280 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
281 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
281 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
282 END GENERATE all_bit_sample_f0;
282 END GENERATE all_bit_sample_f0;
283
283
284 --sample_f0_wen <= NOT(sample_f0_val) &
284 --sample_f0_wen <= NOT(sample_f0_val) &
285 -- NOT(sample_f0_val) &
285 -- NOT(sample_f0_val) &
286 -- NOT(sample_f0_val) &
286 -- NOT(sample_f0_val) &
287 -- NOT(sample_f0_val) &
287 -- NOT(sample_f0_val) &
288 -- NOT(sample_f0_val) &
288 -- NOT(sample_f0_val) &
289 -- NOT(sample_f0_val);
289 -- NOT(sample_f0_val);
290
290
291 -----------------------------------------------------------------------------
291 -----------------------------------------------------------------------------
292 -- F1 -- @4096 Hz
292 -- F1 -- @4096 Hz
293 -----------------------------------------------------------------------------
293 -----------------------------------------------------------------------------
294 Downsampling_f1 : Downsampling
294 Downsampling_f1 : Downsampling
295 GENERIC MAP (
295 GENERIC MAP (
296 ChanelCount => 8,
296 ChanelCount => 8,
297 SampleSize => 16,
297 SampleSize => 16,
298 DivideParam => 6)
298 DivideParam => 6)
299 PORT MAP (
299 PORT MAP (
300 clk => clk,
300 clk => clk,
301 rstn => rstn,
301 rstn => rstn,
302 sample_in_val => sample_f0_val_s ,
302 sample_in_val => sample_f0_val_s ,
303 sample_in => sample_f0,
303 sample_in => sample_f0,
304 sample_out_val => sample_f1_val_s,
304 sample_out_val => sample_f1_val_s,
305 sample_out => sample_f1);
305 sample_out => sample_f1);
306
306
307 sample_f1_val <= sample_f1_val_s;
307 sample_f1_val <= sample_f1_val_s;
308
308
309 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
309 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
310 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
310 sample_f1_wdata_s(I) <= sample_f1(0, I); -- V
311 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
311 sample_f1_wdata_s(16*1+I) <= sample_f1(1, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(3, I); -- E1
312 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
312 sample_f1_wdata_s(16*2+I) <= sample_f1(2, I) WHEN data_shaping_R1 = '1' ELSE sample_f1(4, I); -- E2
313 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
313 sample_f1_wdata_s(16*3+I) <= sample_f1(5, I); -- B1
314 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
314 sample_f1_wdata_s(16*4+I) <= sample_f1(6, I); -- B2
315 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
315 sample_f1_wdata_s(16*5+I) <= sample_f1(7, I); -- B3
316 END GENERATE all_bit_sample_f1;
316 END GENERATE all_bit_sample_f1;
317
317
318 --sample_f1_wen <= NOT(sample_f1_val) &
318 --sample_f1_wen <= NOT(sample_f1_val) &
319 -- NOT(sample_f1_val) &
319 -- NOT(sample_f1_val) &
320 -- NOT(sample_f1_val) &
320 -- NOT(sample_f1_val) &
321 -- NOT(sample_f1_val) &
321 -- NOT(sample_f1_val) &
322 -- NOT(sample_f1_val) &
322 -- NOT(sample_f1_val) &
323 -- NOT(sample_f1_val);
323 -- NOT(sample_f1_val);
324
324
325 -----------------------------------------------------------------------------
325 -----------------------------------------------------------------------------
326 -- F2 -- @256 Hz
326 -- F2 -- @256 Hz
327 -- F3 -- @16 Hz
327 -- F3 -- @16 Hz
328 -----------------------------------------------------------------------------
328 -----------------------------------------------------------------------------
329 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
329 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
330 sample_f0_s(0, I) <= sample_f0(0, I); -- V
330 sample_f0_s(0, I) <= sample_f0(0, I); -- V
331 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
331 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
332 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
332 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
333 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
333 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
334 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
334 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
335 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
335 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
336 END GENERATE all_bit_sample_f0_s;
336 END GENERATE all_bit_sample_f0_s;
337
337
338
338
339 cic_lfr_1: cic_lfr
339 cic_lfr_1: cic_lfr
340 GENERIC MAP (
340 GENERIC MAP (
341 tech => 0,
341 tech => 0,
342 use_RAM_nCEL => Mem_use)
342 use_RAM_nCEL => Mem_use)
343 PORT MAP (
343 PORT MAP (
344 clk => clk,
344 clk => clk,
345 rstn => rstn,
345 rstn => rstn,
346 run => '1',
346 run => '1',
347
347
348 data_in => sample_f0_s,
348 data_in => sample_f0_s,
349 data_in_valid => sample_f0_val_s,
349 data_in_valid => sample_f0_val_s,
350
350
351 data_out_16 => sample_f2_cic,
351 data_out_16 => sample_f2_cic,
352 data_out_16_valid => sample_f2_cic_val,
352 data_out_16_valid => sample_f2_cic_val,
353
353
354 data_out_256 => sample_f3_cic,
354 data_out_256 => sample_f3_cic,
355 data_out_256_valid => sample_f3_cic_val);
355 data_out_256_valid => sample_f3_cic_val);
356
356
357 -----------------------------------------------------------------------------
357 -----------------------------------------------------------------------------
358
358
359 all_bit_sample_f2_cic : FOR I IN 15 DOWNTO 0 GENERATE
359 all_bit_sample_f2_cic : FOR I IN 15 DOWNTO 0 GENERATE
360 all_channel_sample_f2_cic : FOR J IN 5 DOWNTO 0 GENERATE
360 all_channel_sample_f2_cic : FOR J IN 5 DOWNTO 0 GENERATE
361 sample_f2_cic_s(J,I) <= sample_f2_cic(J,I);
361 sample_f2_cic_s(J,I) <= sample_f2_cic(J,I);
362 END GENERATE all_channel_sample_f2_cic;
362 END GENERATE all_channel_sample_f2_cic;
363 END GENERATE all_bit_sample_f2_cic;
363 END GENERATE all_bit_sample_f2_cic;
364
364
365 Downsampling_f2 : Downsampling
365 Downsampling_f2 : Downsampling
366 GENERIC MAP (
366 GENERIC MAP (
367 ChanelCount => 6,
367 ChanelCount => 6,
368 SampleSize => 16,
368 SampleSize => 16,
369 DivideParam => 6)
369 DivideParam => 6)
370 PORT MAP (
370 PORT MAP (
371 clk => clk,
371 clk => clk,
372 rstn => rstn,
372 rstn => rstn,
373 sample_in_val => sample_f2_cic_val ,
373 sample_in_val => sample_f2_cic_val ,
374 sample_in => sample_f2_cic_s,
374 sample_in => sample_f2_cic_s,
375 sample_out_val => sample_f2_val,
375 sample_out_val => sample_f2_val,
376 sample_out => sample_f2);
376 sample_out => sample_f2);
377
377
378 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
378 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
379 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
379 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
380 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
380 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
381 END GENERATE all_channel_sample_f2;
381 END GENERATE all_channel_sample_f2;
382 END GENERATE all_bit_sample_f2;
382 END GENERATE all_bit_sample_f2;
383
383
384 -----------------------------------------------------------------------------
384 -----------------------------------------------------------------------------
385
385
386 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
386 all_bit_sample_f3_cic : FOR I IN 15 DOWNTO 0 GENERATE
387 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
387 all_channel_sample_f3_cic : FOR J IN 5 DOWNTO 0 GENERATE
388 sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
388 sample_f3_cic_s(J,I) <= sample_f3_cic(J,I);
389 END GENERATE all_channel_sample_f3;
389 END GENERATE all_channel_sample_f3_cic;
390 END GENERATE all_bit_sample_f3;
390 END GENERATE all_bit_sample_f3_cic;
391
391
392 Downsampling_f3 : Downsampling
392 Downsampling_f3 : Downsampling
393 GENERIC MAP (
393 GENERIC MAP (
394 ChanelCount => 6,
394 ChanelCount => 6,
395 SampleSize => 16,
395 SampleSize => 16,
396 DivideParam => 6)
396 DivideParam => 6)
397 PORT MAP (
397 PORT MAP (
398 clk => clk,
398 clk => clk,
399 rstn => rstn,
399 rstn => rstn,
400 sample_in_val => sample_f3_cic_val ,
400 sample_in_val => sample_f3_cic_val ,
401 sample_in => sample_f3_cic_s,
401 sample_in => sample_f3_cic_s,
402 sample_out_val => sample_f3_val,
402 sample_out_val => sample_f3_val,
403 sample_out => sample_f3);
403 sample_out => sample_f3);
404
404
405 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
405 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
406 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
406 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
407 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
407 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
408 END GENERATE all_channel_sample_f3;
408 END GENERATE all_channel_sample_f3;
409 END GENERATE all_bit_sample_f3;
409 END GENERATE all_bit_sample_f3;
410
410
411 -----------------------------------------------------------------------------
411 -----------------------------------------------------------------------------
412 --
412 --
413 -----------------------------------------------------------------------------
413 -----------------------------------------------------------------------------
414 sample_f0_wdata <= sample_f0_wdata_s;
414 sample_f0_wdata <= sample_f0_wdata_s;
415 sample_f1_wdata <= sample_f1_wdata_s;
415 sample_f1_wdata <= sample_f1_wdata_s;
416 sample_f2_wdata <= sample_f2_wdata_s;
416 sample_f2_wdata <= sample_f2_wdata_s;
417 sample_f3_wdata <= sample_f3_wdata_s;
417 sample_f3_wdata <= sample_f3_wdata_s;
418
418
419 END tb;
419 END tb;
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