HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r32:ab7e840accef

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LPP_drivers/libsrc/DAC/Makefile created 644 +25 0

@@ -0,0 +1,25
	1	#------------------------------------------------------------------------------
	2	#-- This file is a part of the LPP VHDL IP LIBRARY
	3	#-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	#--
	5	#-- This program is free software; you can redistribute it and/or modify
	6	#-- it under the terms of the GNU General Public License as published by
	7	#-- the Free Software Foundation; either version 3 of the License, or
	8	#-- (at your option) any later version.
	9	#--
	10	#-- This program is distributed in the hope that it will be useful,
	11	#-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	#-- GNU General Public License for more details.
	14	#--
	15	#-- You should have received a copy of the GNU General Public License
	16	#-- along with this program; if not, write to the Free Software
	17	#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	#------------------------------------------------------------------------------
	19	FILE = apb_dac_Driver
	20	LIB = liblpp_dac_Driver.a
	21
	22	include ../../rules.mk
	23
	24	all: $(FILE).a
	25	@echo $(FILE)".a created"

LPP_drivers/libsrc/DAC/apb_dac_Driver.c created 644 +68 0

@@ -0,0 +1,68
	1	#include "apb_dac_Driver.h"
	2	#include "lpp_apb_functions.h"
	3	#include <stdio.h>
	4
	5
	6	DAC_Device* DacOpen(int count)
	7	{
	8	DAC_Device* dac0;
	9	dac0 = (DAC_Device*) apbgetdevice(LPP_DAC_CTRLR,VENDOR_LPP,count);
	10	dac0->configReg = DAC_enable;
	11	return dac0;
	12	}
	13
	14	/*
	15	DAC_Device* DacClose(int count)
	16	{
	17	DAC_Device* dac1;
	18	dac1 = (DAC_Device*) apbgetdevice(LPP_DAC_CTRLR,VENDOR_LPP,count);
	19	dac1->configReg = DAC_disable;
	20	return dac1;
	21	}
	22	*/
	23
	24
	25	int DacTable()
	26	{
	27	int i;
	28	DAC_Device* dac2;
	29	int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
	30	0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
	31	0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
	32	0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
	33	0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
	34	0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
	35	0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
	36	dac2 = (DAC_Device*)0x80000800;
	37	dac2->configReg = DAC_enable;
	38	dac2->dataReg = tablo[0];
	39
	40	while(1)
	41	{
	42	for (i = 0 ; i < 251 ; i++)
	43	{
	44	while(!((dac2->configReg & DAC_ready) == DAC_ready));
	45	dac2->dataReg = tablo[i];
	46	while((dac2->configReg & DAC_ready) == DAC_ready);
	47	}
	48	}
	49	return 0;
	50	}
	51
	52
	53
	54	int DacConst()
	55	{
	56	DAC_Device* dac3;
	57	int Value = 0x1FFF;
	58	dac3 = (DAC_Device*)0x80000800;
	59	dac3->configReg = DAC_enable;
	60	while(1)
	61	{
	62	printf("\nEntrer une valeur entre 4096 et 8191 : ");
	63	scanf("%d",&Value);
	64	dac3->dataReg = Value;
	65	}
	66	return 0;
	67	}
	68

LPP_drivers/libsrc/DAC/apb_dac_Driver.h created 644 +35 0

@@ -0,0 +1,35
	1	#ifndef APB_CNA_DRIVER_H
	2	#define APB_CNA_DRIVER_H
	3
	4	#define DAC_ready 3
	5	#define DAC_enable 1
	6	#define DAC_disable 0
	7
	8
	9	/*===================================================
	10	T Y P E S D E F
	11	====================================================*/
	12
	13	struct DAC_Driver
	14	{
	15	int configReg;
	16	int dataReg;
	17	};
	18
	19	typedef struct DAC_Driver DAC_Device;
	20
	21	/*===================================================
	22	F U N C T I O N S
	23	====================================================*/
	24
	25	DAC_Device* DacOpen(int count);
	26
	27	//DAC_Device* DacClose(int count);
	28
	29	int DacTable();
	30
	31	int DacConst();
	32
	33
	34
	35	#endif

lib/lpp/lpp_cna/Systeme_Clock.vhd created 644 +40 0

@@ -0,0 +1,40
	1	-- Systeme_Clock.vhd
	2	library IEEE;
	3	use IEEE.std_logic_1164.all;
	4	use IEEE.numeric_std.all;
	5
	6	--! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)
	7
	8	entity Systeme_Clock is
	9	generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
	10	port(
	11	clk, raz : in std_logic; --! Horloge et Reset globale
	12	sclk : out std_logic --! Horloge Systeme g�n�r�e
	13	);
	14	end Systeme_Clock;
	15
	16	--! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
	17	architecture ar_Systeme_Clock of Systeme_Clock is
	18
	19	signal clockint : std_logic;
	20	signal countint : integer range 0 to N/2-1;
	21
	22	begin
	23	process (clk,raz)
	24	begin
	25	if(raz = '0') then
	26	countint <= 0;
	27	clockint <= '0';
	28	elsif (clk' event and clk='1') then
	29	if (countint = N/2-1) then
	30	countint <= 0;
	31	clockint <= not clockint;
	32	else
	33	countint <= countint+1;
	34	end if;
	35	end if;
	36	end process;
	37
	38	sclk <= clockint;
	39
	40	end ar_Systeme_Clock; No newline at end of file

.hgignore +1 0

             # use glob syntax.
             syntax: glob
             *.tex
             *.html
             *log*
             *.png
             *.dot
             *.css
             *.md5
             *.eps
             *.pdf
             *.toc
             *.map
             *.sty
             *.3
             *.js
             *.aux
             *.idx
             *doc*
             *Doc*
             *vhdlsyn.txt
+            *dirs.txt
             *.orig
             *.o
             *.a
             *~

LPP_drivers/libsrc/AMBA/lpp_apb_functions.h +3 -1

             /*------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------*/
             #ifndef LPP_APB_FUNCTIONS_H
             #define LPP_APB_FUNCTIONS_H
             #define APB_TBL_HEAD   0x800FF000
             #define APB_BASE_ADDRS 0x80000000
             #define APB_MAX_DEVICES 256
             #define VENDOR_LPP  0x19
             #define ROCKET_TM           0x001
             #define otherCore           0x002
             #define LPP_SIMPLE_DIODE    0x003
             #define LPP_MULTI_DIODE     0x004
             #define LPP_LCD_CTRLR       0x005
+            #define LPP_UART_CTRLR      0x006
+            #define LPP_DAC_CTRLR       0x007
             /** @todo implemente a descriptor structure for any APB device */
             /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */
             struct apbPnPreg
             {
               int idReg;    /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
               int bar;      /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
             };
             struct apbdevinfo
             {
                 int vendorID;
                 int productID;
                 int version;
                 int irq;
                 int address;
                 int mask;
             };
             /** This Function scans APB devices table and returns counth device according to VID and PID */
             int* apbgetdevice(int PID,int VID,int count);
             /** This Function scans APB devices table and returns counth device informations according VID and PID  */
             void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
             void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
             void apbprintdeviceinfo(struct apbdevinfo devinfo);
             void apbprintdeviceslist();
             #endif // LPP_APB_FUNCTIONS_H

LPP_drivers/libsrc/Makefile +33 0

+            #------------------------------------------------------------------------------
+            #--  This file is a part of the LPP VHDL IP LIBRARY
+            #--  Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
+            #--
+            #--  This program is free software; you can redistribute it and/or modify
+            #--  it under the terms of the GNU General Public License as published by
+            #--  the Free Software Foundation; either version 3 of the License, or
+            #--  (at your option) any later version.
+            #--
+            #--  This program is distributed in the hope that it will be useful,
+            #--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+            #--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+            #--  GNU General Public License for more details.
+            #--
+            #--  You should have received a copy of the GNU General Public License
+            #--  along with this program; if not, write to the Free Software
+            #--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+            #------------------------------------------------------------------------------
+            include ../rules.mk
+            all:
+            	make all -C AMBA
+            	make all -C LCD
+            	make all -C DAC
+            cleanall:
+            	make clean -C AMBA
+            	make clean -C LCD
+            	make clean -C DAC
             #------------------------------------------------------------------------------
             #--  This file is a part of the LPP VHDL IP LIBRARY
             #--  Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
             #--
             #--  This program is free software; you can redistribute it and/or modify
             #--  it under the terms of the GNU General Public License as published by
             #--  the Free Software Foundation; either version 3 of the License, or
             #--  (at your option) any later version.
             #--
             #--  This program is distributed in the hope that it will be useful,
             #--  but WITHOUT ANY WARRANTY; without even the implied warranty of
             #--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             #--  GNU General Public License for more details.
             #--
             #--  You should have received a copy of the GNU General Public License
             #--  along with this program; if not, write to the Free Software
             #--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             #------------------------------------------------------------------------------
             include ../rules.mk
             all:
             	make all -C AMBA
             	make all -C LCD
             cleanall:
             	make clean -C AMBA
             	make clean -C LCD

lib/lpp/amba_lcd_16x2_ctrlr/vhdlsyn.txt +2 -2

-            amba_lcd_16x2_ctrlr.vhd
-            apb_lcd_ctrlr.vhd
             FRAME_CLK.vhd
             LCD_16x2_CFG.vhd
             LCD_16x2_DRVR.vhd
             LCD_16x2_ENGINE.vhd
             LCD_2x16_DRIVER.vhd
             LCD_CLK_GENERATOR.vhd
             Top_LCD.vhd
+            amba_lcd_16x2_ctrlr.vhd
+            apb_lcd_ctrlr.vhd

lib/lpp/dsp/iir_filter/vhdlsyn.txt +4 -4

             APB_IIR_CEL.vhd
+            FILTER.vhd
+            FILTER_RAM_CTRLR.vhd
             FILTERcfg.vhd
             FilterCTRLR.vhd
-            FILTER_RAM_CTRLR.vhd
-            FILTER.vhd
             IIR_CEL_CTRLR.vhd
             IIR_CEL_FILTER.vhd
-            iir_filter.vhd
+            RAM.vhd
             RAM_CEL.vhd
             RAM_CTRLR2.vhd
-            RAM.vhd
             Top_Filtre_IIR.vhd
+            iir_filter.vhd

lib/lpp/general_purpose/vhdlsyn.txt +5 -5

-            Adder.vhd
             ADDRcntr.vhd
             ALU.vhd
+            Adder.vhd
             Clk_divider.vhd
-            general_purpose.vhd
+            MAC.vhd
             MAC_CONTROLER.vhd
-            MAC_MUX2.vhd
             MAC_MUX.vhd
+            MAC_MUX2.vhd
             MAC_REG.vhd
-            MAC.vhd
+            MUX2.vhd
             Multiplier.vhd
-            MUX2.vhd
             REG.vhd
             Shifter.vhd
+            general_purpose.vhd

lib/lpp/lpp_amba/APB_MULTI_DIODE.vhd +6 -5

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             --use ieee.numeric_std.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             entity APB_MULTI_DIODE is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 rst    : in  std_ulogic;
                 clk    : in  std_ulogic;
                 apbi   : in  apb_slv_in_type;
                 apbo   : out apb_slv_out_type;
                 LED    : out std_logic_vector(2 downto 0)
                 );
             end;
             architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             type LEDregs is record
               DATAin    :   std_logic_vector(31 downto 0);
               DATAout   :   std_logic_vector(31 downto 0);
             end record;
             signal r : LEDregs;
+            signal Rdata     : std_logic_vector(31 downto 0);
             begin
             r.DATAout   <=  r.DATAin xor X"FFFFFFFF";
             process(rst,clk)
             begin
                 if rst = '0' then
                     LED <=  "000";
                     r.DATAin <= (others => '0');
-                    apbo.prdata <= (others => '0');
                 elsif clk'event and clk = '1' then
                         LED <= r.DATAin(2 downto 0);
             --APB Write OP
                     if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                         case apbi.paddr(abits-1 downto 2) is
                             when "000000" =>
                                 r.DATAin <= apbi.pwdata;
                             when others =>
                                 null;
                         end case;
                     end if;
             --APB READ OP
-                    if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+                    if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                         case apbi.paddr(abits-1 downto 2) is
                             when "000000" =>
-                                apbo.prdata <= r.DATAin;
+                                Rdata <= r.DATAin;
                             when others =>
-                                apbo.prdata <= r.DATAout;
+                                Rdata <= r.DATAout;
                         end case;
                     end if;
                 end if;
                 apbo.pconfig <= pconfig;
             end process;
+            apbo.prdata     <=   Rdata when apbi.penable = '1';
             end ar_APB_MULTI_DIODE;

lib/lpp/lpp_amba/APB_SIMPLE_DIODE.vhd +6 -6

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             --use ieee.numeric_std.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             entity APB_SIMPLE_DIODE is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 rst    : in  std_ulogic;
                 clk    : in  std_ulogic;
                 apbi   : in  apb_slv_in_type;
                 apbo   : out apb_slv_out_type;
                 LED    : out std_ulogic
                 );
             end;
             architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             type LEDregs is record
               DATAin    :   std_logic_vector(31 downto 0);
               DATAout   :   std_logic_vector(31 downto 0);
             end record;
             signal r : LEDregs;
+            signal Rdata     : std_logic_vector(31 downto 0);
             begin
             r.DATAout   <=  r.DATAin xor X"FFFFFFFF";
             process(rst,clk)
             begin
                 if rst = '0' then
                     LED <=  '0';
                     r.DATAin <= (others => '0');
-                    apbo.prdata <= (others => '0');
                 elsif clk'event and clk = '1' then
                         LED <= r.DATAin(0);
             --APB Write OP
                     if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                         case apbi.paddr(abits-1 downto 2) is
                             when "000000" =>
                                 r.DATAin <= apbi.pwdata;
                             when others =>
                                 null;
                         end case;
                     end if;
             --APB READ OP
-                    if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+                    if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                         case apbi.paddr(abits-1 downto 2) is
                             when "000000" =>
-                                apbo.prdata <= r.DATAin;
+                                Rdata <= r.DATAin;
                             when others =>
-                                apbo.prdata <= r.DATAout;
+                                Rdata <= r.DATAout;
                         end case;
                     end if;
                 end if;
                 apbo.pconfig <= pconfig;
             end process;
+            apbo.prdata     <=   Rdata when apbi.penable = '1';
             -- pragma translate_off
             --    bootmsg : report_version
             --    generic map ("apbuart" & tost(pindex) &
             --	": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
             --	", irq " & tost(pirq));
             -- pragma translate_on
             end ar_APB_SIMPLE_DIODE;

lib/lpp/lpp_cna/CNA_TabloC.vhd +1 -1

             -- CNA_TabloC.vhd
             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
             use work.Convertisseur_config.all;
             entity CNA_TabloC is
                 port(
                     clock       : in std_logic;
                     rst         : in std_logic;
                     enable      : in std_logic;
                     --bp          : in std_logic;
                     Data_C      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
                     --Rz          : out std_logic;
                     flag_sd     : out std_logic;
                     Data        : out std_logic
                     );
             end CNA_TabloC;
             architecture ar_CNA_TabloC of CNA_TabloC is
             component CLKINT
             port( A : in    std_logic := 'U';
                   Y : out   std_logic);
             end component;
             signal clk      : std_logic;
             signal raz          : std_logic;
             signal s_SCLK      : std_logic;
             signal OKAI_send    : std_logic;
             --signal Data_int     : std_logic_vector(15 downto 0);
             begin
             CLKINT_0 : CLKINT
                 port map(A => clock, Y => clk);
             CLKINT_1 : CLKINT
                 port map(A => rst, Y => raz);
-            SystemCLK : entity work.Clock_Serie
+            SystemCLK : entity work.Systeme_Clock
                 generic map (nb_serial)
                 port map (clk,raz,s_SCLK);
             Signal_sync : entity work.Gene_SYNC
                 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
             Serial : entity work.serialize
                 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
             --Rz          <= raz;
             SCLK        <= s_SCLK;
             --with bp select
             --    Data_int <= X"9555" when '1',
             --                Data_C when others;
             end ar_CNA_TabloC;

lib/lpp/lpp_cna/lpp_cna.vhd +1 -1

             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             -- pragma translate_off
             use std.textio.all;
             -- pragma translate_on
             library lpp;
             use lpp.lpp_amba.all;
             package lpp_cna is
             component APB_CNA is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
                 SYNC    : out std_logic;
                 SCLK    : out std_logic;
                 DATA    : out std_logic
                 );
             end component;
             component CNA_TabloC is
                 port(
                     clock       : in std_logic;
                     rst         : in std_logic;
                     flag_nw     : in std_logic;
                     bp          : in std_logic;
                     Data_C      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
                     Rz          : out std_logic;
                     flag_sd     : out std_logic;
                     Data        : out std_logic
                     );
             end component;
-            component Clock_Serie is
+            component Systeme_Clock is
                 generic(N :integer := 695);
                 port(
                     clk, raz   : in std_logic ;
                     clock      : out std_logic);
             end component;
             component Gene_SYNC is
                 port(
                     clk,raz     : in std_logic;
                     send     : in std_logic;
                     Sysclk      : in std_logic;
                     OKAI_send   : out std_logic;
                     SYNC        : out std_logic);
             end component;
             component Serialize is
             port(
                 clk,raz : in std_logic;
                 sclk    : in std_logic;
                 vectin  : in std_logic_vector(15 downto 0);
                 send    : in std_logic;
                 sended  : out std_logic;
                 Data    : out std_logic);
             end component;
             end;

lib/lpp/lpp_uart/APB_UART.vhd +11 -8

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             library ieee;
             use ieee.std_logic_1164.all;
             library grlib;
             use grlib.amba.all;
             use grlib.stdlib.all;
             use grlib.devices.all;
             library lpp;
             use lpp.lpp_amba.all;
             use lpp.lpp_uart.all;
             entity APB_UART is
               generic (
                 pindex   : integer := 0;
                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
                 abits    : integer := 8;
                 Data_sz  : integer := 8);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
                 TXD    :   out std_logic;
                 RXD    :   in  std_logic
                 );
             end APB_UART;
             architecture ar_APB_UART of APB_UART is
             constant REVISION : integer := 1;
             constant pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
 => apb_iobar(paddr, pmask));
             signal NwData   : std_logic;
             signal ACK      : std_logic;
             signal Capture  : std_logic;
             signal Send     : std_logic;
             signal Sended   : std_logic;
             type UART_ctrlr_Reg is record
                  UART_Cfg  : std_logic_vector(4 downto 0);
                  UART_Wdata : std_logic_vector(7 downto 0);
                  UART_Rdata : std_logic_vector(7 downto 0);
                  UART_BTrig : std_logic_vector(11 downto 0);
             end record;
             signal Rec : UART_ctrlr_Reg;
+            signal Rdata     : std_logic_vector(31 downto 0);
             begin
             Capture <= Rec.UART_Cfg(0);
             ACK <= Rec.UART_Cfg(1);
             Send <= Rec.UART_Cfg(2);
             Rec.UART_Cfg(3) <= Sended;
             Rec.UART_Cfg(4) <= NwData;
                 COM0 : entity work.UART
                     generic map (Data_sz)
                     port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
                 process(rst,clk)
                 begin
                     if(rst='0')then
                         Rec.UART_Wdata <=  (others => '0');
-                        apbo.prdata <= (others => '0');
                     elsif(clk'event and clk='1')then
                 --APB Write OP
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
                                     Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
                                 when "000001" =>
                                     Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
                                 when others =>
                                     null;
                             end case;
                         end if;
                 --APB READ OP
-                        if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
+                        if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                    apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
+                                    Rdata(31 downto 27) <= Rec.UART_Cfg;
-                                    apbo.prdata(26 downto 12) <= (others => '0');
+                                    Rdata(26 downto 12) <= (others => '0');
-                                    apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
+                                    Rdata(11 downto 0) <= Rec.UART_BTrig;
                                 when "000001" =>
-                                    apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
+                                    Rdata(7 downto 0) <= Rec.UART_Wdata;
                                 when "000010" =>
-                                    apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
+                                    Rdata(7 downto 0) <= Rec.UART_Rdata;
                                 when others =>
-                                    apbo.prdata <= (others => '0');
+                                    Rdata <= (others => '0');
                             end case;
                         end if;
                     end if;
                     apbo.pconfig <= pconfig;
                 end process;
+                apbo.prdata     <=   Rdata when apbi.penable = '1';
             end ar_APB_UART;

lib/lpp/dirs.txt removed 0 -8

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