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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe PELLION | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ---------------------------------------------------------------------------- | |||
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22 | LIBRARY IEEE; | |||
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23 | USE IEEE.numeric_std.ALL; | |||
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24 | USE IEEE.std_logic_1164.ALL; | |||
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25 | ||||
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26 | ENTITY SYNC_FF IS | |||
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27 | ||||
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28 | GENERIC ( | |||
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29 | NB_FF_OF_SYNC : INTEGER := 2); | |||
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30 | ||||
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31 | PORT ( | |||
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32 | clk : IN STD_LOGIC; | |||
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33 | rstn : IN STD_LOGIC; | |||
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34 | A : IN STD_LOGIC; | |||
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35 | A_sync : OUT STD_LOGIC); | |||
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36 | ||||
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37 | END SYNC_FF; | |||
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38 | ||||
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39 | ARCHITECTURE beh OF SYNC_FF IS | |||
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40 | SIGNAL A_temp : STD_LOGIC_VECTOR(NB_FF_OF_SYNC DOWNTO 0); | |||
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41 | BEGIN -- beh | |||
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42 | ||||
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43 | sync_loop : FOR I IN 0 TO NB_FF_OF_SYNC-1 GENERATE | |||
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44 | PROCESS (clk, rstn) | |||
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45 | BEGIN -- PROCESS | |||
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46 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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47 | A_temp(I) <= '0'; | |||
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48 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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49 | A_temp(I) <= A_temp(I+1); | |||
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50 | END IF; | |||
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51 | END PROCESS; | |||
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52 | END GENERATE sync_loop; | |||
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53 | ||||
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54 | A_temp(NB_FF_OF_SYNC) <= A; | |||
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55 | A_sync <= A_temp(0); | |||
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56 | ||||
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57 | END beh; | |||
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