@@ -426,7 +426,7 BEGIN -- beh | |||||
426 | pirq_ms => 6, |
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426 | pirq_ms => 6, | |
427 | pirq_wfp => 14, |
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427 | pirq_wfp => 14, | |
428 | hindex => 2, |
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428 | hindex => 2, | |
429 |
top_lfr_version => X"00010 |
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429 | top_lfr_version => X"00010D") -- aa.bb.cc version | |
430 | PORT MAP ( |
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430 | PORT MAP ( | |
431 | clk => clk_25, |
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431 | clk => clk_25, | |
432 | rstn => reset, |
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432 | rstn => reset, |
@@ -185,7 +185,8 BEGIN | |||||
185 | ----------------------------------------------------------------------------- |
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185 | ----------------------------------------------------------------------------- | |
186 | -- SEND 16 word by DMA (in burst mode) |
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186 | -- SEND 16 word by DMA (in burst mode) | |
187 | ----------------------------------------------------------------------------- |
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187 | ----------------------------------------------------------------------------- | |
188 | data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16); |
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188 | --data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16); | |
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189 | data_2_halfword(31 DOWNTO 0) <= data(31 DOWNTO 0); | |||
189 |
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190 | |||
190 | lpp_dma_send_16word_1 : lpp_dma_send_16word |
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191 | lpp_dma_send_16word_1 : lpp_dma_send_16word | |
191 | PORT MAP ( |
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192 | PORT MAP ( |
@@ -178,8 +178,8 BEGIN | |||||
178 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
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178 | ELSIF HCLK'EVENT AND HCLK = '1' THEN | |
179 | -- |
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179 | -- | |
180 | debug_reg_s(3) <= status_ready_matrix_f0; |
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180 | debug_reg_s(3) <= status_ready_matrix_f0; | |
181 |
debug_reg_s(4) <= status_ready_matrix_f |
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181 | debug_reg_s(4) <= status_ready_matrix_f1; | |
182 |
debug_reg_s(5) <= status_ready_matrix_f |
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182 | debug_reg_s(5) <= status_ready_matrix_f2; | |
183 | debug_reg_s(6) <= '0'; |
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183 | debug_reg_s(6) <= '0'; | |
184 | debug_reg_s(7) <= '0'; |
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184 | debug_reg_s(7) <= '0'; | |
185 | debug_reg_s(8) <= '0'; |
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185 | debug_reg_s(8) <= '0'; |
@@ -168,6 +168,11 ARCHITECTURE beh OF lpp_waveform IS | |||||
168 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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168 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
169 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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169 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |
170 |
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170 | |||
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171 | SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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172 | SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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173 | SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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174 | SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); | |||
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175 | ||||
171 | SIGNAL data_f0_out_valid : STD_LOGIC; |
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176 | SIGNAL data_f0_out_valid : STD_LOGIC; | |
172 | SIGNAL data_f1_out_valid : STD_LOGIC; |
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177 | SIGNAL data_f1_out_valid : STD_LOGIC; | |
173 | SIGNAL data_f2_out_valid : STD_LOGIC; |
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178 | SIGNAL data_f2_out_valid : STD_LOGIC; | |
@@ -362,13 +367,41 BEGIN -- beh | |||||
362 | error => status_new_err(I)); |
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367 | error => status_new_err(I)); | |
363 | END GENERATE all_input_valid; |
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368 | END GENERATE all_input_valid; | |
364 |
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369 | |||
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370 | data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) & | |||
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371 | data_f0_out((16*6)-1 DOWNTO 16*5) & | |||
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372 | data_f0_out((16*3)-1 DOWNTO 16*2) & | |||
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373 | data_f0_out((16*4)-1 DOWNTO 16*3) & | |||
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374 | data_f0_out((16*1)-1 DOWNTO 16*0) & | |||
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375 | data_f0_out((16*2)-1 DOWNTO 16*1) ; | |||
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376 | ||||
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377 | data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) & | |||
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378 | data_f1_out((16*6)-1 DOWNTO 16*5) & | |||
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379 | data_f1_out((16*3)-1 DOWNTO 16*2) & | |||
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380 | data_f1_out((16*4)-1 DOWNTO 16*3) & | |||
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381 | data_f1_out((16*1)-1 DOWNTO 16*0) & | |||
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382 | data_f1_out((16*2)-1 DOWNTO 16*1) ; | |||
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383 | ||||
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384 | data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) & | |||
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385 | data_f2_out((16*6)-1 DOWNTO 16*5) & | |||
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386 | data_f2_out((16*3)-1 DOWNTO 16*2) & | |||
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387 | data_f2_out((16*4)-1 DOWNTO 16*3) & | |||
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388 | data_f2_out((16*1)-1 DOWNTO 16*0) & | |||
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389 | data_f2_out((16*2)-1 DOWNTO 16*1) ; | |||
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390 | ||||
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391 | data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) & | |||
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392 | data_f3_out((16*6)-1 DOWNTO 16*5) & | |||
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393 | data_f3_out((16*3)-1 DOWNTO 16*2) & | |||
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394 | data_f3_out((16*4)-1 DOWNTO 16*3) & | |||
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395 | data_f3_out((16*1)-1 DOWNTO 16*0) & | |||
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396 | data_f3_out((16*2)-1 DOWNTO 16*1) ; | |||
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397 | ||||
365 |
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398 | all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE | |
366 | data_out(0, I) <= data_f0_out(I); |
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399 | data_out(0, I) <= data_f0_out_swap(I); | |
367 | data_out(1, I) <= data_f1_out(I); |
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400 | data_out(1, I) <= data_f1_out_swap(I); | |
368 | data_out(2, I) <= data_f2_out(I); |
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401 | data_out(2, I) <= data_f2_out_swap(I); | |
369 | data_out(3, I) <= data_f3_out(I); |
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402 | data_out(3, I) <= data_f3_out_swap(I); | |
370 | END GENERATE all_bit_of_data_out; |
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403 | END GENERATE all_bit_of_data_out; | |
371 |
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404 | |||
372 |
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405 | ----------------------------------------------------------------------------- | |
373 | -- TODO : debug |
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406 | -- TODO : debug | |
374 | ----------------------------------------------------------------------------- |
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407 | ----------------------------------------------------------------------------- |
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