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Simu MINI-LFR_WFP_MS ...
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);-- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);-- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182 BEGIN -- beh
183 183
184 184 -----------------------------------------------------------------------------
185 185 -- CLK
186 186 -----------------------------------------------------------------------------
187 187
188 188 PROCESS(clk_50)
189 189 BEGIN
190 190 IF clk_50'EVENT AND clk_50 = '1' THEN
191 191 clk_50_s <= NOT clk_50_s;
192 192 END IF;
193 193 END PROCESS;
194 194
195 195 PROCESS(clk_50_s)
196 196 BEGIN
197 197 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
198 198 clk_25 <= NOT clk_25;
199 199 END IF;
200 200 END PROCESS;
201 201
202 202 PROCESS(clk_49)
203 203 BEGIN
204 204 IF clk_49'EVENT AND clk_49 = '1' THEN
205 205 clk_24 <= NOT clk_24;
206 206 END IF;
207 207 END PROCESS;
208 208
209 209 -----------------------------------------------------------------------------
210 210
211 211 PROCESS (clk_25, reset)
212 212 BEGIN -- PROCESS
213 213 IF reset = '0' THEN -- asynchronous reset (active low)
214 214 LED0 <= '0';
215 215 LED1 <= '0';
216 216 LED2 <= '0';
217 217 --IO1 <= '0';
218 218 --IO2 <= '1';
219 219 --IO3 <= '0';
220 220 --IO4 <= '0';
221 221 --IO5 <= '0';
222 222 --IO6 <= '0';
223 223 --IO7 <= '0';
224 224 --IO8 <= '0';
225 225 --IO9 <= '0';
226 226 --IO10 <= '0';
227 227 --IO11 <= '0';
228 228 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
229 229 LED0 <= '0';
230 230 LED1 <= '1';
231 231 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
232 232 --IO1 <= '1';
233 233 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
234 234 --IO3 <= ADC_SDO(0);
235 235 --IO4 <= ADC_SDO(1);
236 236 --IO5 <= ADC_SDO(2);
237 237 --IO6 <= ADC_SDO(3);
238 238 --IO7 <= ADC_SDO(4);
239 239 --IO8 <= ADC_SDO(5);
240 240 --IO9 <= ADC_SDO(6);
241 241 --IO10 <= ADC_SDO(7);
242 242 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
243 243 END IF;
244 244 END PROCESS;
245 245
246 246 PROCESS (clk_24, reset)
247 247 BEGIN -- PROCESS
248 248 IF reset = '0' THEN -- asynchronous reset (active low)
249 249 I00_s <= '0';
250 250 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
251 251 I00_s <= NOT I00_s ;
252 252 END IF;
253 253 END PROCESS;
254 254 -- IO0 <= I00_s;
255 255
256 256 --UARTs
257 257 nCTS1 <= '1';
258 258 nCTS2 <= '1';
259 259 nDCD2 <= '1';
260 260
261 261 --EXT CONNECTOR
262 262
263 263 --SPACE WIRE
264 264
265 265 leon3_soc_1 : leon3_soc
266 266 GENERIC MAP (
267 267 fabtech => apa3e,
268 268 memtech => apa3e,
269 269 padtech => inferred,
270 270 clktech => inferred,
271 271 disas => 0,
272 272 dbguart => 0,
273 273 pclow => 2,
274 274 clk_freq => 25000,
275 275 NB_CPU => 1,
276 276 ENABLE_FPU => 1,
277 277 FPU_NETLIST => 0,
278 278 ENABLE_DSU => 1,
279 279 ENABLE_AHB_UART => 1,
280 280 ENABLE_APB_UART => 1,
281 281 ENABLE_IRQMP => 1,
282 282 ENABLE_GPT => 1,
283 283 NB_AHB_MASTER => NB_AHB_MASTER,
284 284 NB_AHB_SLAVE => NB_AHB_SLAVE,
285 NB_APB_SLAVE => NB_APB_SLAVE)
285 NB_APB_SLAVE => NB_APB_SLAVE,
286 ADDRESS_SIZE => 20)
286 287 PORT MAP (
287 288 clk => clk_25,
288 289 reset => reset,
289 290 errorn => errorn,
290 291 ahbrxd => TXD1,
291 292 ahbtxd => RXD1,
292 293 urxd1 => TXD2,
293 294 utxd1 => RXD2,
294 295 address => SRAM_A,
295 296 data => SRAM_DQ,
296 297 nSRAM_BE0 => SRAM_nBE(0),
297 298 nSRAM_BE1 => SRAM_nBE(1),
298 299 nSRAM_BE2 => SRAM_nBE(2),
299 300 nSRAM_BE3 => SRAM_nBE(3),
300 301 nSRAM_WE => SRAM_nWE,
301 302 nSRAM_CE => SRAM_CE,
302 303 nSRAM_OE => SRAM_nOE,
303 304
304 305 apbi_ext => apbi_ext,
305 306 apbo_ext => apbo_ext,
306 307 ahbi_s_ext => ahbi_s_ext,
307 308 ahbo_s_ext => ahbo_s_ext,
308 309 ahbi_m_ext => ahbi_m_ext,
309 310 ahbo_m_ext => ahbo_m_ext);
310 311
311 312 -------------------------------------------------------------------------------
312 313 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
313 314 -------------------------------------------------------------------------------
314 315 apb_lfr_time_management_1 : apb_lfr_time_management
315 316 GENERIC MAP (
316 317 pindex => 6,
317 318 paddr => 6,
318 319 pmask => 16#fff#,
319 320 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
320 321 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
321 322 PORT MAP (
322 323 clk25MHz => clk_25,
323 324 clk24_576MHz => clk_24, -- 49.152MHz/2
324 325 resetn => reset,
325 326 grspw_tick => swno.tickout,
326 327 apbi => apbi_ext,
327 328 apbo => apbo_ext(6),
328 329 coarse_time => coarse_time,
329 330 fine_time => fine_time,
330 331 LFR_soft_rstn => LFR_soft_rstn
331 332 );
332 333
333 334 -----------------------------------------------------------------------
334 335 --- SpaceWire --------------------------------------------------------
335 336 -----------------------------------------------------------------------
336 337
337 338 SPW_EN <= '1';
338 339
339 340 spw_clk <= clk_50_s;
340 341 spw_rxtxclk <= spw_clk;
341 342 spw_rxclkn <= NOT spw_rxtxclk;
342 343
343 344 -- PADS for SPW1
344 345 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
345 346 PORT MAP (SPW_NOM_DIN, dtmp(0));
346 347 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
347 348 PORT MAP (SPW_NOM_SIN, stmp(0));
348 349 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
349 350 PORT MAP (SPW_NOM_DOUT, swno.d(0));
350 351 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
351 352 PORT MAP (SPW_NOM_SOUT, swno.s(0));
352 353 -- PADS FOR SPW2
353 354 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
354 355 PORT MAP (SPW_RED_SIN, dtmp(1));
355 356 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
356 357 PORT MAP (SPW_RED_DIN, stmp(1));
357 358 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
358 359 PORT MAP (SPW_RED_DOUT, swno.d(1));
359 360 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
360 361 PORT MAP (SPW_RED_SOUT, swno.s(1));
361 362
362 363 -- GRSPW PHY
363 364 --spw1_input: if CFG_SPW_GRSPW = 1 generate
364 365 spw_inputloop : FOR j IN 0 TO 1 GENERATE
365 366 spw_phy0 : grspw_phy
366 367 GENERIC MAP(
367 368 tech => apa3e,
368 369 rxclkbuftype => 1,
369 370 scantest => 0)
370 371 PORT MAP(
371 372 rxrst => swno.rxrst,
372 373 di => dtmp(j),
373 374 si => stmp(j),
374 375 rxclko => spw_rxclk(j),
375 376 do => swni.d(j),
376 377 ndo => swni.nd(j*5+4 DOWNTO j*5),
377 378 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
378 379 END GENERATE spw_inputloop;
379 380
380 381 -- SPW core
381 382 sw0 : grspwm GENERIC MAP(
382 383 tech => apa3e,
383 384 hindex => 1,
384 385 pindex => 5,
385 386 paddr => 5,
386 387 pirq => 11,
387 388 sysfreq => 25000, -- CPU_FREQ
388 389 rmap => 1,
389 390 rmapcrc => 1,
390 391 fifosize1 => 16,
391 392 fifosize2 => 16,
392 393 rxclkbuftype => 1,
393 394 rxunaligned => 0,
394 395 rmapbufs => 4,
395 396 ft => 0,
396 397 netlist => 0,
397 398 ports => 2,
398 399 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
399 400 memtech => apa3e,
400 401 destkey => 2,
401 402 spwcore => 1
402 403 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
403 404 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
404 405 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
405 406 )
406 407 PORT MAP(reset, clk_25, spw_rxclk(0),
407 408 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
408 409 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
409 410 swni, swno);
410 411
411 412 swni.tickin <= '0';
412 413 swni.rmapen <= '1';
413 414 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
414 415 swni.tickinraw <= '0';
415 416 swni.timein <= (OTHERS => '0');
416 417 swni.dcrstval <= (OTHERS => '0');
417 418 swni.timerrstval <= (OTHERS => '0');
418 419
419 420 -------------------------------------------------------------------------------
420 421 -- LFR ------------------------------------------------------------------------
421 422 -------------------------------------------------------------------------------
422 423
423 424
424 425 LFR_rstn <= LFR_soft_rstn AND reset;
425 426
426 427 lpp_lfr_1 : lpp_lfr
427 428 GENERIC MAP (
428 429 Mem_use => use_RAM,
429 430 nb_data_by_buffer_size => 32,
430 431 nb_snapshot_param_size => 32,
431 432 delta_vector_size => 32,
432 433 delta_vector_size_f0_2 => 7, -- log2(96)
433 434 pindex => 15,
434 435 paddr => 15,
435 436 pmask => 16#fff#,
436 437 pirq_ms => 6,
437 438 pirq_wfp => 14,
438 439 hindex => 2,
439 top_lfr_version => X"000120") -- aa.bb.cc version
440 top_lfr_version => X"000121") -- aa.bb.cc version
440 441 PORT MAP (
441 442 clk => clk_25,
442 443 rstn => LFR_rstn,
443 444 sample_B => sample_s(2 DOWNTO 0),
444 445 sample_E => sample_s(7 DOWNTO 3),
445 446 sample_val => sample_val,
446 447 apbi => apbi_ext,
447 448 apbo => apbo_ext(15),
448 449 ahbi => ahbi_m_ext,
449 450 ahbo => ahbo_m_ext(2),
450 451 coarse_time => coarse_time,
451 452 fine_time => fine_time,
452 453 data_shaping_BW => bias_fail_sw_sig);
453 454
454 455 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
455 456 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
456 457 END GENERATE all_sample;
457 458
458 459
459 460
460 461 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
461 462 GENERIC MAP(
462 463 ChannelCount => 8,
463 464 SampleNbBits => 14,
464 465 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
465 466 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
466 467 PORT MAP (
467 468 -- CONV
468 469 cnv_clk => clk_24,
469 470 cnv_rstn => reset,
470 471 cnv => ADC_nCS_sig,
471 472 -- DATA
472 473 clk => clk_25,
473 474 rstn => reset,
474 475 sck => ADC_CLK_sig,
475 476 sdo => ADC_SDO_sig,
476 477 -- SAMPLE
477 478 sample => sample,
478 479 sample_val => sample_val);
479 480
480 481 --IO10 <= ADC_SDO_sig(5);
481 482 --IO9 <= ADC_SDO_sig(4);
482 483 --IO8 <= ADC_SDO_sig(3);
483 484
484 485 ADC_nCS <= ADC_nCS_sig;
485 486 ADC_CLK <= ADC_CLK_sig;
486 487 ADC_SDO_sig <= ADC_SDO;
487 488
488 489 ----------------------------------------------------------------------
489 490 --- GPIO -----------------------------------------------------------
490 491 ----------------------------------------------------------------------
491 492
492 493 grgpio0 : grgpio
493 494 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
494 495 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
495 496
496 497 --pio_pad_0 : iopad
497 498 -- GENERIC MAP (tech => CFG_PADTECH)
498 499 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
499 500 --pio_pad_1 : iopad
500 501 -- GENERIC MAP (tech => CFG_PADTECH)
501 502 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
502 503 --pio_pad_2 : iopad
503 504 -- GENERIC MAP (tech => CFG_PADTECH)
504 505 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
505 506 --pio_pad_3 : iopad
506 507 -- GENERIC MAP (tech => CFG_PADTECH)
507 508 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
508 509 --pio_pad_4 : iopad
509 510 -- GENERIC MAP (tech => CFG_PADTECH)
510 511 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
511 512 --pio_pad_5 : iopad
512 513 -- GENERIC MAP (tech => CFG_PADTECH)
513 514 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
514 515 --pio_pad_6 : iopad
515 516 -- GENERIC MAP (tech => CFG_PADTECH)
516 517 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
517 518 --pio_pad_7 : iopad
518 519 -- GENERIC MAP (tech => CFG_PADTECH)
519 520 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
520 521
521 522 PROCESS (clk_25, reset)
522 523 BEGIN -- PROCESS
523 524 IF reset = '0' THEN -- asynchronous reset (active low)
524 525 IO0 <= '0';
525 526 IO1 <= '0';
526 527 IO2 <= '0';
527 528 IO3 <= '0';
528 529 IO4 <= '0';
529 530 IO5 <= '0';
530 531 IO6 <= '0';
531 532 IO7 <= '0';
532 533 IO8 <= '0';
533 534 IO9 <= '0';
534 535 IO10 <= '0';
535 536 IO11 <= '0';
536 537 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
537 538 CASE gpioo.dout(2 DOWNTO 0) IS
538 539 WHEN "011" =>
539 540 IO0 <= observation_reg(0 );
540 541 IO1 <= observation_reg(1 );
541 542 IO2 <= observation_reg(2 );
542 543 IO3 <= observation_reg(3 );
543 544 IO4 <= observation_reg(4 );
544 545 IO5 <= observation_reg(5 );
545 546 IO6 <= observation_reg(6 );
546 547 IO7 <= observation_reg(7 );
547 548 IO8 <= observation_reg(8 );
548 549 IO9 <= observation_reg(9 );
549 550 IO10 <= observation_reg(10);
550 551 IO11 <= observation_reg(11);
551 552 WHEN "001" =>
552 553 IO0 <= observation_reg(0 + 12);
553 554 IO1 <= observation_reg(1 + 12);
554 555 IO2 <= observation_reg(2 + 12);
555 556 IO3 <= observation_reg(3 + 12);
556 557 IO4 <= observation_reg(4 + 12);
557 558 IO5 <= observation_reg(5 + 12);
558 559 IO6 <= observation_reg(6 + 12);
559 560 IO7 <= observation_reg(7 + 12);
560 561 IO8 <= observation_reg(8 + 12);
561 562 IO9 <= observation_reg(9 + 12);
562 563 IO10 <= observation_reg(10 + 12);
563 564 IO11 <= observation_reg(11 + 12);
564 565 WHEN "010" =>
565 566 IO0 <= observation_reg(0 + 12 + 12);
566 567 IO1 <= observation_reg(1 + 12 + 12);
567 568 IO2 <= observation_reg(2 + 12 + 12);
568 569 IO3 <= observation_reg(3 + 12 + 12);
569 570 IO4 <= observation_reg(4 + 12 + 12);
570 571 IO5 <= observation_reg(5 + 12 + 12);
571 572 IO6 <= observation_reg(6 + 12 + 12);
572 573 IO7 <= observation_reg(7 + 12 + 12);
573 574 IO8 <= '0';
574 575 IO9 <= '0';
575 576 IO10 <= '0';
576 577 IO11 <= '0';
577 578 WHEN "000" =>
578 579 IO0 <= observation_vector_0(0 );
579 580 IO1 <= observation_vector_0(1 );
580 581 IO2 <= observation_vector_0(2 );
581 582 IO3 <= observation_vector_0(3 );
582 583 IO4 <= observation_vector_0(4 );
583 584 IO5 <= observation_vector_0(5 );
584 585 IO6 <= observation_vector_0(6 );
585 586 IO7 <= observation_vector_0(7 );
586 587 IO8 <= observation_vector_0(8 );
587 588 IO9 <= observation_vector_0(9 );
588 589 IO10 <= observation_vector_0(10);
589 590 IO11 <= observation_vector_0(11);
590 591 WHEN "100" =>
591 592 IO0 <= observation_vector_1(0 );
592 593 IO1 <= observation_vector_1(1 );
593 594 IO2 <= observation_vector_1(2 );
594 595 IO3 <= observation_vector_1(3 );
595 596 IO4 <= observation_vector_1(4 );
596 597 IO5 <= observation_vector_1(5 );
597 598 IO6 <= observation_vector_1(6 );
598 599 IO7 <= observation_vector_1(7 );
599 600 IO8 <= observation_vector_1(8 );
600 601 IO9 <= observation_vector_1(9 );
601 602 IO10 <= observation_vector_1(10);
602 603 IO11 <= observation_vector_1(11);
603 604 WHEN OTHERS => NULL;
604 605 END CASE;
605 606
606 607 END IF;
607 608 END PROCESS;
609 -----------------------------------------------------------------------------
610 --
611 -----------------------------------------------------------------------------
612 all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
613 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
614 apbo_ext(I) <= apb_none;
615 END GENERATE apbo_ext_not_used;
616 END GENERATE all_apbo_ext;
617
618
619 all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
620 ahbo_s_ext(I) <= ahbs_none;
621 END GENERATE all_ahbo_ext;
622
623 all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
624 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
625 ahbo_m_ext(I) <= ahbm_none;
626 END GENERATE ahbo_m_ext_not_used;
627 END GENERATE all_ahbo_m_ext;
608 628
609 629 END beh;
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@@ -1,50 +1,52
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
13 VHDLSYNFILES= MINI_LFR_top.vhd
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
15 16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
19 20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
20 21 CLEAN=soft-clean
21 22
22 23 TECHLIBS = proasic3e
23 24
24 25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
25 26 tmtc openchip hynix ihp gleichmann micron usbhc
26 27
27 28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
28 29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
29 30 ./amba_lcd_16x2_ctrlr \
30 31 ./general_purpose/lpp_AMR \
31 32 ./general_purpose/lpp_balise \
32 33 ./general_purpose/lpp_delay \
33 34 ./lpp_bootloader \
34 35 ./lpp_cna \
35 36 ./lpp_uart \
36 37 ./lpp_usb \
37 38 ./dsp/lpp_fft_rtax \
38 39 ./lpp_sim/CY7C1061DV33 \
39 40
40 41 FILESKIP =i2cmst.vhd \
41 42 APB_MULTI_DIODE.vhd \
42 43 APB_SIMPLE_DIODE.vhd \
43 44 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45 APB_FFT.vhd \
46 CoreFFT_simu.vhd
45 47
46 48 include $(GRLIB)/bin/Makefile
47 49 include $(GRLIB)/software/leon3/Makefile
48 50
49 51 ################## project specific targets ##########################
50 52
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@@ -1,30 +1,31
1 1 ./amba_lcd_16x2_ctrlr
2 2 ./general_purpose
3 3 ./general_purpose/lpp_AMR
4 4 ./general_purpose/lpp_balise
5 5 ./general_purpose/lpp_delay
6 6 ./lpp_amba
7 7 ./dsp/chirp
8 ./dsp/iir_filter
8 9 ./dsp/cic
9 ./dsp/iir_filter
10 10 ./dsp/lpp_downsampling
11 11 ./dsp/lpp_fft_rtax
12 12 ./lpp_memory
13 13 ./dsp/lpp_fft
14 14 ./lfr_time_management
15 15 ./lpp_ad_Conv
16 16 ./lpp_bootloader
17 17 ./lpp_cna
18 18 ./lpp_spectral_matrix
19 19 ./lpp_demux
20 20 ./lpp_Header
21 21 ./lpp_matrix
22 22 ./lpp_uart
23 23 ./lpp_usb
24 ./lpp_dma
24 25 ./lpp_waveform
25 ./lpp_dma
26 26 ./lpp_top_lfr
27 27 ./lpp_Header
28 28 ./lpp_leon3_soc
29 29 ./lpp_debug_lfr
30 30 ./lpp_sim/CY7C1061DV33
31 ./lpp_sim
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@@ -1,326 +1,329
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_time_management.ALL;
31 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
32
31 33
32 34 ENTITY apb_lfr_time_management IS
33 35
34 36 GENERIC(
35 37 pindex : INTEGER := 0; --! APB slave index
36 38 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 39 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 40 FIRST_DIVISION : INTEGER := 374;
39 41 NB_SECOND_DESYNC : INTEGER := 60
40 42 );
41 43
42 44 PORT (
43 45 clk25MHz : IN STD_LOGIC; --! Clock
44 46 clk24_576MHz : IN STD_LOGIC; --! secondary clock
45 47 resetn : IN STD_LOGIC; --! Reset
46 48
47 49 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 50
49 51 apbi : IN apb_slv_in_type; --! APB slave input signals
50 52 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 53
52 54 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
53 55 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
54 56 ---------------------------------------------------------------------------
55 57 LFR_soft_rstn : OUT STD_LOGIC
56 58 );
57 59
58 60 END apb_lfr_time_management;
59 61
60 62 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
61 63
62 64 CONSTANT REVISION : INTEGER := 1;
63 65 CONSTANT pconfig : apb_config_type := (
64 66 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
65 67 1 => apb_iobar(paddr, pmask)
66 68 );
67 69
68 70 TYPE apb_lfr_time_management_Reg IS RECORD
69 71 ctrl : STD_LOGIC;
70 72 soft_reset : STD_LOGIC;
71 73 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
72 74 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 75 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
74 76 LFR_soft_reset : STD_LOGIC;
75 77 END RECORD;
76 78 SIGNAL r : apb_lfr_time_management_Reg;
77 79
78 80 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 81 SIGNAL force_tick : STD_LOGIC;
80 82 SIGNAL previous_force_tick : STD_LOGIC;
81 83 SIGNAL soft_tick : STD_LOGIC;
82 84
83 85 SIGNAL coarsetime_reg_updated : STD_LOGIC;
84 86 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
85 87
86 88 --SIGNAL coarse_time_new : STD_LOGIC;
87 89 SIGNAL coarse_time_new_49 : STD_LOGIC;
88 90 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
89 91 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
90 92
91 93 --SIGNAL fine_time_new : STD_LOGIC;
92 94 --SIGNAL fine_time_new_temp : STD_LOGIC;
93 95 SIGNAL fine_time_new_49 : STD_LOGIC;
94 96 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
95 97 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
96 98 SIGNAL tick : STD_LOGIC;
97 99 SIGNAL new_timecode : STD_LOGIC;
98 100 SIGNAL new_coarsetime : STD_LOGIC;
99 101
100 102 SIGNAL time_new_49 : STD_LOGIC;
101 103 SIGNAL time_new : STD_LOGIC;
102 104
103 105 -----------------------------------------------------------------------------
104 106 SIGNAL force_reset : STD_LOGIC;
105 107 SIGNAL previous_force_reset : STD_LOGIC;
106 108 SIGNAL soft_reset : STD_LOGIC;
107 109 SIGNAL soft_reset_sync : STD_LOGIC;
108 110 -----------------------------------------------------------------------------
109 111
110 112 SIGNAL rstn_LFR_TM : STD_LOGIC;
111 113
112 114 BEGIN
113 115
114 116 LFR_soft_rstn <= NOT r.LFR_soft_reset;
115 117
116 118 PROCESS(resetn, clk25MHz)
117 119 BEGIN
118 120
119 121 IF resetn = '0' THEN
120 122 Rdata <= (OTHERS => '0');
121 123 r.coarse_time_load <= (OTHERS => '0');
122 124 r.soft_reset <= '0';
123 125 r.ctrl <= '0';
124 126 r.LFR_soft_reset <= '1';
125 127
126 128 force_tick <= '0';
127 129 previous_force_tick <= '0';
128 130 soft_tick <= '0';
129 131
130 132 coarsetime_reg_updated <= '0';
131 133
132 134 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
133 135 coarsetime_reg_updated <= '0';
134 136
135 137 force_tick <= r.ctrl;
136 138 previous_force_tick <= force_tick;
137 139 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
138 140 soft_tick <= '1';
139 141 ELSE
140 142 soft_tick <= '0';
141 143 END IF;
142 144
143 145 force_reset <= r.soft_reset;
144 146 previous_force_reset <= force_reset;
145 147 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
146 148 soft_reset <= '1';
147 149 ELSE
148 150 soft_reset <= '0';
149 151 END IF;
150 152
151 153 --APB Write OP
152 154 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
153 155 CASE apbi.paddr(7 DOWNTO 2) IS
154 WHEN "000000" =>
156 WHEN ADDR_LFR_TM_CONTROL =>
155 157 r.ctrl <= apbi.pwdata(0);
156 158 r.soft_reset <= apbi.pwdata(1);
157 159 r.LFR_soft_reset <= apbi.pwdata(2);
158 WHEN "000001" =>
160 WHEN ADDR_LFR_TM_TIME_LOAD =>
159 161 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
160 162 coarsetime_reg_updated <= '1';
161 163 WHEN OTHERS =>
162 164 NULL;
163 165 END CASE;
164 166 ELSE
165 167 IF r.ctrl = '1' THEN
166 168 r.ctrl <= '0';
167 169 END if;
168 170 IF r.soft_reset = '1' THEN
169 171 r.soft_reset <= '0';
170 172 END if;
171 173 END IF;
172 174
173 175 --APB READ OP
174 176 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
175 177 CASE apbi.paddr(7 DOWNTO 2) IS
176 WHEN "000000" =>
178 WHEN ADDR_LFR_TM_CONTROL =>
177 179 Rdata(0) <= r.ctrl;
178 180 Rdata(1) <= r.soft_reset;
179 181 Rdata(2) <= r.LFR_soft_reset;
180 182 Rdata(31 DOWNTO 3) <= (others => '0');
181 WHEN "000001" =>
183 WHEN ADDR_LFR_TM_TIME_LOAD =>
182 184 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
183 WHEN "000010" =>
185 WHEN ADDR_LFR_TM_TIME_COARSE =>
184 186 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
185 WHEN "000011" =>
187 WHEN ADDR_LFR_TM_TIME_FINE =>
186 188 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
187 189 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
188 190 WHEN OTHERS =>
189 191 Rdata(31 DOWNTO 0) <= (others => '0');
190 192 END CASE;
191 193 END IF;
192 194
193 195 END IF;
194 196 END PROCESS;
195 197
198 apbo.pirq <= (OTHERS => '0');
196 199 apbo.prdata <= Rdata;
197 200 apbo.pconfig <= pconfig;
198 201 apbo.pindex <= pindex;
199 202
200 203 -----------------------------------------------------------------------------
201 204 -- IN
202 205 coarse_time <= r.coarse_time;
203 206 fine_time <= r.fine_time;
204 207 coarsetime_reg <= r.coarse_time_load;
205 208 -----------------------------------------------------------------------------
206 209
207 210 -----------------------------------------------------------------------------
208 211 -- OUT
209 212 r.coarse_time <= coarse_time_s;
210 213 r.fine_time <= fine_time_s;
211 214 -----------------------------------------------------------------------------
212 215
213 216 -----------------------------------------------------------------------------
214 217 tick <= grspw_tick OR soft_tick;
215 218
216 219 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
217 220 GENERIC MAP (
218 221 NB_FF_OF_SYNC => 2)
219 222 PORT MAP (
220 223 clk_in => clk25MHz,
221 224 clk_out => clk24_576MHz,
222 225 rstn => resetn,
223 226 sin => tick,
224 227 sout => new_timecode);
225 228
226 229 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
227 230 GENERIC MAP (
228 231 NB_FF_OF_SYNC => 2)
229 232 PORT MAP (
230 233 clk_in => clk25MHz,
231 234 clk_out => clk24_576MHz,
232 235 rstn => resetn,
233 236 sin => coarsetime_reg_updated,
234 237 sout => new_coarsetime);
235 238
236 239 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
237 240 GENERIC MAP (
238 241 NB_FF_OF_SYNC => 2)
239 242 PORT MAP (
240 243 clk_in => clk25MHz,
241 244 clk_out => clk24_576MHz,
242 245 rstn => resetn,
243 246 sin => soft_reset,
244 247 sout => soft_reset_sync);
245 248
246 249 -----------------------------------------------------------------------------
247 250 --SYNC_FF_1 : SYNC_FF
248 251 -- GENERIC MAP (
249 252 -- NB_FF_OF_SYNC => 2)
250 253 -- PORT MAP (
251 254 -- clk => clk25MHz,
252 255 -- rstn => resetn,
253 256 -- A => fine_time_new_49,
254 257 -- A_sync => fine_time_new_temp);
255 258
256 259 --lpp_front_detection_1 : lpp_front_detection
257 260 -- PORT MAP (
258 261 -- clk => clk25MHz,
259 262 -- rstn => resetn,
260 263 -- sin => fine_time_new_temp,
261 264 -- sout => fine_time_new);
262 265
263 266 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
264 267 -- GENERIC MAP (
265 268 -- NB_FF_OF_SYNC => 2)
266 269 -- PORT MAP (
267 270 -- clk_in => clk24_576MHz,
268 271 -- clk_out => clk25MHz,
269 272 -- rstn => resetn,
270 273 -- sin => coarse_time_new_49,
271 274 -- sout => coarse_time_new);
272 275
273 276 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
274 277
275 278 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
276 279 GENERIC MAP (
277 280 NB_FF_OF_SYNC => 2)
278 281 PORT MAP (
279 282 clk_in => clk24_576MHz,
280 283 clk_out => clk25MHz,
281 284 rstn => resetn,
282 285 sin => time_new_49,
283 286 sout => time_new);
284 287
285 288
286 289
287 290 PROCESS (clk25MHz, resetn)
288 291 BEGIN -- PROCESS
289 292 IF resetn = '0' THEN -- asynchronous reset (active low)
290 293 fine_time_s <= (OTHERS => '0');
291 294 coarse_time_s <= (OTHERS => '0');
292 295 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
293 296 IF time_new = '1' THEN
294 297 fine_time_s <= fine_time_49;
295 298 coarse_time_s <= coarse_time_49;
296 299 END IF;
297 300 END IF;
298 301 END PROCESS;
299 302
300 303
301 304 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
302 305 '0' WHEN soft_reset_sync = '1' ELSE
303 306 '1';
304 307
305 308
306 309 -----------------------------------------------------------------------------
307 310 -- LFR_TIME_MANAGMENT
308 311 -----------------------------------------------------------------------------
309 312 lfr_time_management_1 : lfr_time_management
310 313 GENERIC MAP (
311 314 FIRST_DIVISION => FIRST_DIVISION,
312 315 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
313 316 PORT MAP (
314 317 clk => clk24_576MHz,
315 318 rstn => rstn_LFR_TM,
316 319
317 320 tick => new_timecode,
318 321 new_coarsetime => new_coarsetime,
319 322 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
320 323
321 324 fine_time => fine_time_49,
322 325 fine_time_new => fine_time_new_49,
323 326 coarse_time => coarse_time_49,
324 327 coarse_time_new => coarse_time_new_49);
325 328
326 329 END Behavioral;
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@@ -1,5 +1,6
1 1 lpp_lfr_time_management.vhd
2 lpp_lfr_time_management_apbreg_pkg.vhd
2 3 apb_lfr_time_management.vhd
3 4 lfr_time_management.vhd
4 5 fine_time_counter.vhd
5 6 coarse_time_counter.vhd
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@@ -1,428 +1,428
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_lfr_time_management.ALL;
43 43 USE lpp.lpp_leon3_soc_pkg.ALL;
44 44
45 45 ENTITY leon3_soc IS
46 46 GENERIC (
47 47 fabtech : INTEGER := apa3e;
48 48 memtech : INTEGER := apa3e;
49 49 padtech : INTEGER := inferred;
50 50 clktech : INTEGER := inferred;
51 51 disas : INTEGER := 0; -- Enable disassembly to console
52 52 dbguart : INTEGER := 0; -- Print UART on console
53 53 pclow : INTEGER := 2;
54 54 --
55 55 clk_freq : INTEGER := 25000; --kHz
56 56 --
57 57 NB_CPU : INTEGER := 1;
58 58 ENABLE_FPU : INTEGER := 1;
59 59 FPU_NETLIST : INTEGER := 1;
60 60 ENABLE_DSU : INTEGER := 1;
61 61 ENABLE_AHB_UART : INTEGER := 1;
62 62 ENABLE_APB_UART : INTEGER := 1;
63 63 ENABLE_IRQMP : INTEGER := 1;
64 64 ENABLE_GPT : INTEGER := 1;
65 65 --
66 66 NB_AHB_MASTER : INTEGER := 0;
67 67 NB_AHB_SLAVE : INTEGER := 0;
68 68 NB_APB_SLAVE : INTEGER := 0;
69 69 --
70 70 ADDRESS_SIZE : INTEGER := 20
71 71 );
72 72 PORT (
73 73 clk : IN STD_ULOGIC;
74 74 reset : IN STD_ULOGIC;
75 75
76 76 errorn : OUT STD_ULOGIC;
77 77
78 78 -- UART AHB ---------------------------------------------------------------
79 79 ahbrxd : IN STD_ULOGIC; -- DSU rx data
80 80 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
81 81
82 82 -- UART APB ---------------------------------------------------------------
83 83 urxd1 : IN STD_ULOGIC; -- UART1 rx data
84 84 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
85 85
86 86 -- RAM --------------------------------------------------------------------
87 87 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
88 88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 nSRAM_BE0 : OUT STD_LOGIC;
90 90 nSRAM_BE1 : OUT STD_LOGIC;
91 91 nSRAM_BE2 : OUT STD_LOGIC;
92 92 nSRAM_BE3 : OUT STD_LOGIC;
93 93 nSRAM_WE : OUT STD_LOGIC;
94 94 nSRAM_CE : OUT STD_LOGIC;
95 95 nSRAM_OE : OUT STD_LOGIC;
96 96
97 97 -- APB --------------------------------------------------------------------
98 98 apbi_ext : OUT apb_slv_in_type;
99 99 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
100 100 -- AHB_Slave --------------------------------------------------------------
101 101 ahbi_s_ext : OUT ahb_slv_in_type;
102 102 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
103 103 -- AHB_Master -------------------------------------------------------------
104 104 ahbi_m_ext : OUT AHB_Mst_In_Type;
105 105 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
106 106
107 107 );
108 108 END;
109 109
110 110 ARCHITECTURE Behavioral OF leon3_soc IS
111 111
112 112 -----------------------------------------------------------------------------
113 113 -- CONFIG -------------------------------------------------------------------
114 114 -----------------------------------------------------------------------------
115 115
116 116 -- Clock generator
117 117 constant CFG_CLKMUL : integer := (1);
118 118 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
119 119 constant CFG_OCLKDIV : integer := (1);
120 120 constant CFG_CLK_NOFB : integer := 0;
121 121 -- LEON3 processor core
122 122 constant CFG_LEON3 : integer := 1;
123 123 constant CFG_NCPU : integer := NB_CPU;
124 124 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
125 125 constant CFG_V8 : integer := 0;
126 126 constant CFG_MAC : integer := 0;
127 127 constant CFG_SVT : integer := 0;
128 128 constant CFG_RSTADDR : integer := 16#00000#;
129 129 constant CFG_LDDEL : integer := (1);
130 130 constant CFG_NWP : integer := (0);
131 131 constant CFG_PWD : integer := 1*2;
132 132 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
133 133 -- 1*(8 + 16 * 0) => grfpu-light
134 134 -- 1*(8 + 16 * 1) => netlist
135 135 -- 0*(8 + 16 * 0) => No FPU
136 136 -- 0*(8 + 16 * 1) => No FPU;
137 137 constant CFG_ICEN : integer := 1;
138 138 constant CFG_ISETS : integer := 1;
139 139 constant CFG_ISETSZ : integer := 4;
140 140 constant CFG_ILINE : integer := 4;
141 141 constant CFG_IREPL : integer := 0;
142 142 constant CFG_ILOCK : integer := 0;
143 143 constant CFG_ILRAMEN : integer := 0;
144 144 constant CFG_ILRAMADDR: integer := 16#8E#;
145 145 constant CFG_ILRAMSZ : integer := 1;
146 146 constant CFG_DCEN : integer := 1;
147 147 constant CFG_DSETS : integer := 1;
148 148 constant CFG_DSETSZ : integer := 4;
149 149 constant CFG_DLINE : integer := 4;
150 150 constant CFG_DREPL : integer := 0;
151 151 constant CFG_DLOCK : integer := 0;
152 152 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
153 153 constant CFG_DLRAMEN : integer := 0;
154 154 constant CFG_DLRAMADDR: integer := 16#8F#;
155 155 constant CFG_DLRAMSZ : integer := 1;
156 156 constant CFG_MMUEN : integer := 0;
157 157 constant CFG_ITLBNUM : integer := 2;
158 158 constant CFG_DTLBNUM : integer := 2;
159 159 constant CFG_TLB_TYPE : integer := 1 + 0*2;
160 160 constant CFG_TLB_REP : integer := 1;
161 161
162 162 constant CFG_DSU : integer := ENABLE_DSU;
163 163 constant CFG_ITBSZ : integer := 0;
164 164 constant CFG_ATBSZ : integer := 0;
165 165
166 166 -- AMBA settings
167 167 constant CFG_DEFMST : integer := (0);
168 168 constant CFG_RROBIN : integer := 1;
169 169 constant CFG_SPLIT : integer := 0;
170 170 constant CFG_AHBIO : integer := 16#FFF#;
171 171 constant CFG_APBADDR : integer := 16#800#;
172 172
173 173 -- DSU UART
174 174 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
175 175
176 176 -- LEON2 memory controller
177 177 constant CFG_MCTRL_SDEN : integer := 0;
178 178
179 179 -- UART 1
180 180 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
181 181 constant CFG_UART1_FIFO : integer := 1;
182 182
183 183 -- LEON3 interrupt controller
184 184 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
185 185
186 186 -- Modular timer
187 187 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
188 188 constant CFG_GPT_NTIM : integer := (2);
189 189 constant CFG_GPT_SW : integer := (8);
190 190 constant CFG_GPT_TW : integer := (32);
191 191 constant CFG_GPT_IRQ : integer := (8);
192 192 constant CFG_GPT_SEPIRQ : integer := 1;
193 193 constant CFG_GPT_WDOGEN : integer := 0;
194 194 constant CFG_GPT_WDOG : integer := 16#0#;
195 195 -----------------------------------------------------------------------------
196 196
197 197 -----------------------------------------------------------------------------
198 198 -- SIGNALs
199 199 -----------------------------------------------------------------------------
200 200 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
201 201 -- CLK & RST --
202 202 SIGNAL clk2x : STD_ULOGIC;
203 203 SIGNAL clkmn : STD_ULOGIC;
204 204 SIGNAL clkm : STD_ULOGIC;
205 205 SIGNAL rstn : STD_ULOGIC;
206 206 SIGNAL rstraw : STD_ULOGIC;
207 207 SIGNAL pciclk : STD_ULOGIC;
208 208 SIGNAL sdclkl : STD_ULOGIC;
209 209 SIGNAL cgi : clkgen_in_type;
210 210 SIGNAL cgo : clkgen_out_type;
211 211 --- AHB / APB
212 212 SIGNAL apbi : apb_slv_in_type;
213 213 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
214 214 SIGNAL ahbsi : ahb_slv_in_type;
215 215 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
216 216 SIGNAL ahbmi : ahb_mst_in_type;
217 217 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
218 218 --UART
219 219 SIGNAL ahbuarti : uart_in_type;
220 220 SIGNAL ahbuarto : uart_out_type;
221 221 SIGNAL apbuarti : uart_in_type;
222 222 SIGNAL apbuarto : uart_out_type;
223 223 --MEM CTRLR
224 224 SIGNAL memi : memory_in_type;
225 225 SIGNAL memo : memory_out_type;
226 226 SIGNAL wpo : wprot_out_type;
227 227 SIGNAL sdo : sdram_out_type;
228 228 --IRQ
229 229 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
230 230 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
231 231 --Timer
232 232 SIGNAL gpti : gptimer_in_type;
233 233 SIGNAL gpto : gptimer_out_type;
234 234 --DSU
235 235 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
236 236 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
237 237 SIGNAL dsui : dsu_in_type;
238 238 SIGNAL dsuo : dsu_out_type;
239 239 -----------------------------------------------------------------------------
240 240
241 241 SIGNAL nSRAM_CE_s : STD_LOGIC;
242 242 BEGIN
243 243
244 244
245 245 ----------------------------------------------------------------------
246 246 --- Reset and Clock generation -------------------------------------
247 247 ----------------------------------------------------------------------
248 248
249 249 cgi.pllctrl <= "00";
250 250 cgi.pllrst <= rstraw;
251 251
252 252 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
253 253
254 254 clkgen0 : clkgen -- clock generator
255 255 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
256 256 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
257 257 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
258 258
259 259 ----------------------------------------------------------------------
260 260 --- LEON3 processor / DSU / IRQ ------------------------------------
261 261 ----------------------------------------------------------------------
262 262
263 263 l3 : IF CFG_LEON3 = 1 GENERATE
264 264 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
265 265 u0 : leon3s -- LEON3 processor
266 266 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
267 267 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
268 268 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
269 269 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
270 270 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
271 271 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
272 272 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
273 273 irqi(i), irqo(i), dbgi(i), dbgo(i));
274 274 END GENERATE;
275 275 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
276 276
277 277 dsugen : IF CFG_DSU = 1 GENERATE
278 278 dsu0 : dsu3 -- LEON3 Debug Support Unit
279 279 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
280 280 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
281 281 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
282 282 dsui.enable <= '1';
283 283 dsui.break <= '0';
284 284 END GENERATE;
285 285 END GENERATE;
286 286
287 287 nodsu : IF CFG_DSU = 0 GENERATE
288 288 ahbso(2) <= ahbs_none;
289 289 dsuo.tstop <= '0';
290 290 dsuo.active <= '0';
291 291 END GENERATE;
292 292
293 293 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
294 294 irqctrl0 : irqmp -- interrupt controller
295 295 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
296 296 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
297 297 END GENERATE;
298 298 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
299 299 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
300 300 irqi(i).irl <= "0000";
301 301 END GENERATE;
302 302 apbo(2) <= apb_none;
303 303 END GENERATE;
304 304
305 305 ----------------------------------------------------------------------
306 306 --- Memory controllers ---------------------------------------------
307 307 ----------------------------------------------------------------------
308 308 memctrlr : mctrl GENERIC MAP (
309 309 hindex => 0,
310 310 pindex => 0,
311 311 paddr => 0,
312 312 srbanks => 1
313 313 )
314 314 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
315 315
316 316 memi.brdyn <= '1';
317 317 memi.bexcn <= '1';
318 318 memi.writen <= '1';
319 319 memi.wrn <= "1111";
320 320 memi.bwidth <= "10";
321 321
322 322 bdr : FOR i IN 0 TO 3 GENERATE
323 323 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
324 324 PORT MAP (
325 325 data(31-i*8 DOWNTO 24-i*8),
326 326 memo.data(31-i*8 DOWNTO 24-i*8),
327 327 memo.bdrive(i),
328 328 memi.data(31-i*8 DOWNTO 24-i*8));
329 329 END GENERATE;
330 330
331 331 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
332 332 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
333 333 nSRAM_CE_s <= NOT(memo.ramsn(0));
334 334 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
335 335 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
336 336 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
337 337 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
338 338 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
339 339 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
340 340 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
341 341
342 342 ----------------------------------------------------------------------
343 343 --- AHB CONTROLLER -------------------------------------------------
344 344 ----------------------------------------------------------------------
345 345 ahb0 : ahbctrl -- AHB arbiter/multiplexer
346 346 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
347 347 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
348 348 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
349 349 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
350 350
351 351 ----------------------------------------------------------------------
352 352 --- AHB UART -------------------------------------------------------
353 353 ----------------------------------------------------------------------
354 354 dcomgen : IF CFG_AHB_UART = 1 GENERATE
355 355 dcom0 : ahbuart
356 356 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
357 357 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
358 358 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
359 359 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
360 360 END GENERATE;
361 361 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
362 362
363 363 ----------------------------------------------------------------------
364 364 --- APB Bridge -----------------------------------------------------
365 365 ----------------------------------------------------------------------
366 366 apb0 : apbctrl -- AHB/APB bridge
367 367 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
368 368 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
369 369
370 370 ----------------------------------------------------------------------
371 371 --- GPT Timer ------------------------------------------------------
372 372 ----------------------------------------------------------------------
373 373 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
374 374 timer0 : gptimer -- timer unit
375 375 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
376 376 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
377 377 nbits => CFG_GPT_TW)
378 378 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
379 379 gpti.dhalt <= dsuo.tstop;
380 380 gpti.extclk <= '0';
381 381 END GENERATE;
382 382 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
383 383
384 384
385 385 ----------------------------------------------------------------------
386 386 --- APB UART -------------------------------------------------------
387 387 ----------------------------------------------------------------------
388 388 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
389 389 uart1 : apbuart -- UART 1
390 390 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
391 391 fifosize => CFG_UART1_FIFO)
392 392 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
393 393 apbuarti.rxd <= urxd1;
394 394 apbuarti.extclk <= '0';
395 395 utxd1 <= apbuarto.txd;
396 396 apbuarti.ctsn <= '0';
397 397 END GENERATE;
398 398 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
399 399
400 400 -------------------------------------------------------------------------------
401 401 -- AMBA BUS -------------------------------------------------------------------
402 402 -------------------------------------------------------------------------------
403 403
404 404 -- APB --------------------------------------------------------------------
405 405 apbi_ext <= apbi;
406 406 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
407 407 max_16_apb: IF I + 5 < 16 GENERATE
408 408 apbo(I+5)<= apbo_ext(I+5);
409 409 END GENERATE max_16_apb;
410 410 END GENERATE all_apb;
411 411 -- AHB_Slave --------------------------------------------------------------
412 412 ahbi_s_ext <= ahbsi;
413 413 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
414 414 max_16_ahbs: IF I + 3 < 16 GENERATE
415 415 ahbso(I+3) <= ahbo_s_ext(I+3);
416 416 END GENERATE max_16_ahbs;
417 417 END GENERATE all_ahbs;
418 418 -- AHB_Master -------------------------------------------------------------
419 419 ahbi_m_ext <= ahbmi;
420 420 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
421 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
421 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
422 422 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
423 423 END GENERATE max_16_ahbm;
424 424 END GENERATE all_ahbm;
425 425
426 426
427 427
428 428 END Behavioral;
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@@ -1,784 +1,781
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26
26 27 LIBRARY grlib;
27 28 USE grlib.amba.ALL;
28 29 USE grlib.stdlib.ALL;
29 30 USE grlib.devices.ALL;
31
30 32 LIBRARY lpp;
31 33 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
33 34 USE lpp.apb_devices_list.ALL;
34 35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37
35 38 LIBRARY techmap;
36 39 USE techmap.gencomp.ALL;
37 40
38 41 ENTITY lpp_lfr_apbreg IS
39 42 GENERIC (
40 43 nb_data_by_buffer_size : INTEGER := 11;
41 -- nb_word_by_buffer_size : INTEGER := 11;
42 44 nb_snapshot_param_size : INTEGER := 11;
43 45 delta_vector_size : INTEGER := 20;
44 46 delta_vector_size_f0_2 : INTEGER := 3;
45 47
46 48 pindex : INTEGER := 4;
47 49 paddr : INTEGER := 4;
48 50 pmask : INTEGER := 16#fff#;
49 51 pirq_ms : INTEGER := 0;
50 52 pirq_wfp : INTEGER := 1;
51 53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 54 PORT (
53 55 -- AMBA AHB system signals
54 56 HCLK : IN STD_ULOGIC;
55 57 HRESETn : IN STD_ULOGIC;
56 58
57 59 -- AMBA APB Slave Interface
58 60 apbi : IN apb_slv_in_type;
59 61 apbo : OUT apb_slv_out_type;
60 62
61 63 ---------------------------------------------------------------------------
62 64 -- Spectral Matrix Reg
63 65 run_ms : OUT STD_LOGIC;
64 66 -- IN
65 67 ready_matrix_f0 : IN STD_LOGIC;
66 68 ready_matrix_f1 : IN STD_LOGIC;
67 69 ready_matrix_f2 : IN STD_LOGIC;
68 70
69 71 -- error_bad_component_error : IN STD_LOGIC;
70 72 error_buffer_full : IN STD_LOGIC; -- TODO
71 73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72 74
73 75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 76
75 77 -- OUT
76 78 status_ready_matrix_f0 : OUT STD_LOGIC;
77 79 status_ready_matrix_f1 : OUT STD_LOGIC;
78 80 status_ready_matrix_f2 : OUT STD_LOGIC;
79 81
80 82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 83 --config_active_interruption_onError : OUT STD_LOGIC;
82 84
83 85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 88
87 89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
88 90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 92
91 93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92 94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 96
95 97 ---------------------------------------------------------------------------
96 98 ---------------------------------------------------------------------------
97 99 -- WaveForm picker Reg
98 100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
99 101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
100 102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102 104
103 105 -- OUT
104 106 data_shaping_BW : OUT STD_LOGIC;
105 107 data_shaping_SP0 : OUT STD_LOGIC;
106 108 data_shaping_SP1 : OUT STD_LOGIC;
107 109 data_shaping_R0 : OUT STD_LOGIC;
108 110 data_shaping_R1 : OUT STD_LOGIC;
109 111 data_shaping_R2 : OUT STD_LOGIC;
110 112
111 113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
112 114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
114 116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
117 119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
118 120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
119 121
120 122 enable_f0 : OUT STD_LOGIC;
121 123 enable_f1 : OUT STD_LOGIC;
122 124 enable_f2 : OUT STD_LOGIC;
123 125 enable_f3 : OUT STD_LOGIC;
124 126
125 127 burst_f0 : OUT STD_LOGIC;
126 128 burst_f1 : OUT STD_LOGIC;
127 129 burst_f2 : OUT STD_LOGIC;
128 130
129 131 run : OUT STD_LOGIC;
130 132
131 133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
132 134
133 135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
135 137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
136 138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
137 139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
138 140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
139 141
140 142 );
141 143
142 144 END lpp_lfr_apbreg;
143 145
144 146 ARCHITECTURE beh OF lpp_lfr_apbreg IS
145 147
146 148 CONSTANT REVISION : INTEGER := 1;
147 149
148 150 CONSTANT pconfig : apb_config_type := (
149 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
151 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
150 152 1 => apb_iobar(paddr, pmask));
151 153
154 --CONSTANT pconfig : apb_config_type := (
155 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
156 -- 1 => apb_iobar(paddr, pmask));
157
152 158 TYPE lpp_SpectralMatrix_regs IS RECORD
153 159 config_active_interruption_onNewMatrix : STD_LOGIC;
154 160 config_active_interruption_onError : STD_LOGIC;
155 161 config_ms_run : STD_LOGIC;
156 162 status_ready_matrix_f0_0 : STD_LOGIC;
157 163 status_ready_matrix_f1_0 : STD_LOGIC;
158 164 status_ready_matrix_f2_0 : STD_LOGIC;
159 165 status_ready_matrix_f0_1 : STD_LOGIC;
160 166 status_ready_matrix_f1_1 : STD_LOGIC;
161 167 status_ready_matrix_f2_1 : STD_LOGIC;
162 168 -- status_error_bad_component_error : STD_LOGIC;
163 169 status_error_buffer_full : STD_LOGIC;
164 170 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
165 171
166 172 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 173 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 174 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 175 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 176 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 177 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 178
173 179 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
174 180
175 181 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 182 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 183 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
178 184 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
179 185 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
180 186 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
181 187 END RECORD;
182 188 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
183 189
184 190 TYPE lpp_WaveformPicker_regs IS RECORD
185 191 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 192 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 193 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 194 data_shaping_BW : STD_LOGIC;
189 195 data_shaping_SP0 : STD_LOGIC;
190 196 data_shaping_SP1 : STD_LOGIC;
191 197 data_shaping_R0 : STD_LOGIC;
192 198 data_shaping_R1 : STD_LOGIC;
193 199 data_shaping_R2 : STD_LOGIC;
194 200 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 201 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 202 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
197 203 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
198 204 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
199 205 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
200 206 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
201 207 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
202 208 enable_f0 : STD_LOGIC;
203 209 enable_f1 : STD_LOGIC;
204 210 enable_f2 : STD_LOGIC;
205 211 enable_f3 : STD_LOGIC;
206 212 burst_f0 : STD_LOGIC;
207 213 burst_f1 : STD_LOGIC;
208 214 burst_f2 : STD_LOGIC;
209 215 run : STD_LOGIC;
210 216 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
211 217 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
212 218 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
213 219 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
214 220 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 221 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
216 222 END RECORD;
217 223 SIGNAL reg_wp : lpp_WaveformPicker_regs;
218 224
219 225 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 226
221 227 -----------------------------------------------------------------------------
222 228 -- IRQ
223 229 -----------------------------------------------------------------------------
224 230 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
225 231 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
226 232 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
227 233 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
228 234 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
229 235 SIGNAL ored_irq_wfp : STD_LOGIC;
230 236
231 237 -----------------------------------------------------------------------------
232 238 --
233 239 -----------------------------------------------------------------------------
234 240 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
235 241 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 242 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237 243
238 244 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
239 245 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 246 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241 247
242 248 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
243 249 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 250 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
245 251
246 252 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
247 253 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 254 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 255
250 256 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
251 257 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 258 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253 259
254 260 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
255 261 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 262 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 263 SIGNAL apbo_irq_ms : STD_LOGIC;
258 264 SIGNAL apbo_irq_wfp : STD_LOGIC;
259 265 -----------------------------------------------------------------------------
260 266 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
267
268 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 269
262 270 BEGIN -- beh
263 271
264 272 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
265 273 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
266 274 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
267 275
268 276 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
269 277 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
270 278
271 279
272 280 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
273 281 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
274 282 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
275 283
276 284
277 285 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
278 286 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
279 287 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
280 288 data_shaping_R0 <= reg_wp.data_shaping_R0;
281 289 data_shaping_R1 <= reg_wp.data_shaping_R1;
282 290 data_shaping_R2 <= reg_wp.data_shaping_R2;
283 291
284 292 delta_snapshot <= reg_wp.delta_snapshot;
285 293 delta_f0 <= reg_wp.delta_f0;
286 294 delta_f0_2 <= reg_wp.delta_f0_2;
287 295 delta_f1 <= reg_wp.delta_f1;
288 296 delta_f2 <= reg_wp.delta_f2;
289 297 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
290 298 nb_snapshot_param <= reg_wp.nb_snapshot_param;
291 299
292 300 enable_f0 <= reg_wp.enable_f0;
293 301 enable_f1 <= reg_wp.enable_f1;
294 302 enable_f2 <= reg_wp.enable_f2;
295 303 enable_f3 <= reg_wp.enable_f3;
296 304
297 305 burst_f0 <= reg_wp.burst_f0;
298 306 burst_f1 <= reg_wp.burst_f1;
299 307 burst_f2 <= reg_wp.burst_f2;
300 308
301 309 run <= reg_wp.run;
302 310
303 311 --addr_data_f0 <= reg_wp.addr_data_f0;
304 312 --addr_data_f1 <= reg_wp.addr_data_f1;
305 313 --addr_data_f2 <= reg_wp.addr_data_f2;
306 314 --addr_data_f3 <= reg_wp.addr_data_f3;
307 315
308 316 start_date <= reg_wp.start_date;
309 317
310 318 length_matrix_f0 <= reg_sp.length_matrix;
311 319 length_matrix_f1 <= reg_sp.length_matrix;
312 320 length_matrix_f2 <= reg_sp.length_matrix;
313 321 wfp_length_buffer <= reg_wp.length_buffer;
314 322
315 323
316 324 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
317 325 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
318 326 BEGIN -- PROCESS lpp_dma_top
319 327 IF HRESETn = '0' THEN -- asynchronous reset (active low)
320 328 reg_sp.config_active_interruption_onNewMatrix <= '0';
321 329 reg_sp.config_active_interruption_onError <= '0';
322 330 reg_sp.config_ms_run <= '0';
323 331 reg_sp.status_ready_matrix_f0_0 <= '0';
324 332 reg_sp.status_ready_matrix_f1_0 <= '0';
325 333 reg_sp.status_ready_matrix_f2_0 <= '0';
326 334 reg_sp.status_ready_matrix_f0_1 <= '0';
327 335 reg_sp.status_ready_matrix_f1_1 <= '0';
328 336 reg_sp.status_ready_matrix_f2_1 <= '0';
329 337 reg_sp.status_error_buffer_full <= '0';
330 338 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
331 339
332 340 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
333 341 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
334 342 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
335 343
336 344 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
337 345 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
338 346 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
339 347
340 348 reg_sp.length_matrix <= (OTHERS => '0');
341 349
342 350 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
343 351 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
344 352 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
345 353
346 354 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
347 355 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
348 356 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
349 357
350 358 prdata <= (OTHERS => '0');
351 359
352 360
353 361 apbo_irq_ms <= '0';
354 362 apbo_irq_wfp <= '0';
355 363
356 364
357 365 -- status_full_ack <= (OTHERS => '0');
358 366
359 367 reg_wp.data_shaping_BW <= '0';
360 368 reg_wp.data_shaping_SP0 <= '0';
361 369 reg_wp.data_shaping_SP1 <= '0';
362 370 reg_wp.data_shaping_R0 <= '0';
363 371 reg_wp.data_shaping_R1 <= '0';
364 372 reg_wp.data_shaping_R2 <= '0';
365 373 reg_wp.enable_f0 <= '0';
366 374 reg_wp.enable_f1 <= '0';
367 375 reg_wp.enable_f2 <= '0';
368 376 reg_wp.enable_f3 <= '0';
369 377 reg_wp.burst_f0 <= '0';
370 378 reg_wp.burst_f1 <= '0';
371 379 reg_wp.burst_f2 <= '0';
372 380 reg_wp.run <= '0';
373 381 -- reg_wp.status_full <= (OTHERS => '0');
374 382 -- reg_wp.status_full_err <= (OTHERS => '0');
375 383 reg_wp.status_new_err <= (OTHERS => '0');
376 384 reg_wp.error_buffer_full <= (OTHERS => '0');
377 385 reg_wp.delta_snapshot <= (OTHERS => '0');
378 386 reg_wp.delta_f0 <= (OTHERS => '0');
379 387 reg_wp.delta_f0_2 <= (OTHERS => '0');
380 388 reg_wp.delta_f1 <= (OTHERS => '0');
381 389 reg_wp.delta_f2 <= (OTHERS => '0');
382 390 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
383 391 reg_wp.nb_snapshot_param <= (OTHERS => '0');
384 392 reg_wp.start_date <= (OTHERS => '1');
385 393
386 394 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
387 395 reg_wp.length_buffer <= (OTHERS => '0');
396
397 pirq_temp <= (OTHERS => '0');
398
399 reg_wp.addr_buffer_f <= (OTHERS => '0');
400
388 401 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
389 402
390 403 -- status_full_ack <= (OTHERS => '0');
391 404
392 405 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
393 406 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
394 407 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
395 408
396 409 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
397 410 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
398 411 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
399 412
400 413 all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
401 414 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
402 415 END LOOP all_status_ready_buffer_bit;
403 416
404 417
405 418 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
406 419 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
407 420 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
408 421 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
409 422
410 423
411 424
412 425 all_status : FOR I IN 3 DOWNTO 0 LOOP
413 426 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
414 427 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
415 428 END LOOP all_status;
416 429
417 430 paddr := "000000";
418 431 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
419 432 prdata <= (OTHERS => '0');
420 433 IF apbi.psel(pindex) = '1' THEN
421 434 -- APB DMA READ --
422 435 CASE paddr(7 DOWNTO 2) IS
423 --0
424 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
425 prdata(1) <= reg_sp.config_active_interruption_onError;
426 prdata(2) <= reg_sp.config_ms_run;
427 --1
428 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
429 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
430 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
431 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
432 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
433 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
434 -- prdata(6) <= reg_sp.status_error_bad_component_error;
435 prdata(7) <= reg_sp.status_error_buffer_full;
436 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
437 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
438 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
439 --2
440 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
441 --3
442 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
443 --4
444 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
445 --5
446 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
447 --6
448 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
449 --7
450 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
451 --8
452 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
453 --9
454 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
455 --10
456 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
457 --11
458 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
459 --12
460 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
461 --13
462 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
463 --14
464 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
465 --15
466 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
467 --16
468 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
469 --17
470 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 --18
472 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
473 --19
474 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
475 --20
476 WHEN "010100" => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
477 ---------------------------------------------------------------------
478 --20
479 WHEN "010101" => prdata(0) <= reg_wp.data_shaping_BW;
480 prdata(1) <= reg_wp.data_shaping_SP0;
481 prdata(2) <= reg_wp.data_shaping_SP1;
482 prdata(3) <= reg_wp.data_shaping_R0;
483 prdata(4) <= reg_wp.data_shaping_R1;
484 prdata(5) <= reg_wp.data_shaping_R2;
485 --21
486 WHEN "010110" => prdata(0) <= reg_wp.enable_f0;
487 prdata(1) <= reg_wp.enable_f1;
488 prdata(2) <= reg_wp.enable_f2;
489 prdata(3) <= reg_wp.enable_f3;
490 prdata(4) <= reg_wp.burst_f0;
491 prdata(5) <= reg_wp.burst_f1;
492 prdata(6) <= reg_wp.burst_f2;
493 prdata(7) <= reg_wp.run;
494 --22
495 --ON GOING \/
496 WHEN "010111" => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
497 WHEN "011000" => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
498 WHEN "011001" => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
499 WHEN "011010" => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
500 WHEN "011011" => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
501 WHEN "011100" => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
502 WHEN "011101" => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
503 WHEN "011110" => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
504 --ON GOING /\
505 WHEN "011111" => prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
506 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
507 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
508 --prdata(3 DOWNTO 0) <= reg_wp.status_full;
509 -- prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
510 --27
511 WHEN "100000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
512 --28
513 WHEN "100001" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
514 --29
515 WHEN "100010" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
516 --30
517 WHEN "100011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
518 --31
519 WHEN "100100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
520 --32
521 WHEN "100101" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
522 --33
523 WHEN "100110" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
524 --34
525 WHEN "100111" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
526 --35
527 WHEN "101000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); --reg_wp.time_buffer_f(48*0+15 DOWNTO 48*0);
528 WHEN "101001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); --reg_wp.time_buffer_f(48*0+47 DOWNTO 48*0+16);
529 WHEN "101010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
530 WHEN "101011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
436
437 WHEN ADDR_LFR_SM_CONFIG =>
438 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
439 prdata(1) <= reg_sp.config_active_interruption_onError;
440 prdata(2) <= reg_sp.config_ms_run;
441
442 WHEN ADDR_LFR_SM_STATUS =>
443 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
444 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
445 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
446 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
447 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
448 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
449 -- prdata(6) <= reg_sp.status_error_bad_component_error;
450 prdata(7) <= reg_sp.status_error_buffer_full;
451 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
452 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
453 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
454
455 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
456 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
457 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
458 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
459 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
460 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
461 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
462 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
463 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
464 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
465 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
466 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
467 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
468 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
469 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
470 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
471 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
472 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
473 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
474 ---------------------------------------------------------------------
475 WHEN ADDR_LFR_WP_DATASHAPING =>
476 prdata(0) <= reg_wp.data_shaping_BW;
477 prdata(1) <= reg_wp.data_shaping_SP0;
478 prdata(2) <= reg_wp.data_shaping_SP1;
479 prdata(3) <= reg_wp.data_shaping_R0;
480 prdata(4) <= reg_wp.data_shaping_R1;
481 prdata(5) <= reg_wp.data_shaping_R2;
482 WHEN ADDR_LFR_WP_CONTROL =>
483 prdata(0) <= reg_wp.enable_f0;
484 prdata(1) <= reg_wp.enable_f1;
485 prdata(2) <= reg_wp.enable_f2;
486 prdata(3) <= reg_wp.enable_f3;
487 prdata(4) <= reg_wp.burst_f0;
488 prdata(5) <= reg_wp.burst_f1;
489 prdata(6) <= reg_wp.burst_f2;
490 prdata(7) <= reg_wp.run;
491 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
492 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
493 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
494 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
495 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
496 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
497 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
498 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
499
500 WHEN ADDR_LFR_WP_STATUS =>
501 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
502 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
503 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
504
505 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
506 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
507 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
508 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
509 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
510 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
511 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
512 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
513
514 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
515 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
516 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
517 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
531 518
532 WHEN "101100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
533 WHEN "101101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
534 WHEN "101110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
535 WHEN "101111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
536
537 WHEN "110000" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
538 WHEN "110001" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
539 WHEN "110010" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
540 WHEN "110011" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
519 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
520 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
521 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
522 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
541 523
542 WHEN "110100" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
543 WHEN "110101" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
544 WHEN "110110" => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
545 WHEN "110111" => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
524 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
525 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
526 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
527 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
528
529 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
530 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
531 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
532 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
546 533
547 WHEN "111000" => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
548
549 -- WHEN "100100" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
550 ----------------------------------------------------
551 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
534 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
535 ---------------------------------------------------------------------
536 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
552 537 WHEN OTHERS => NULL;
553 538
554 539 END CASE;
555 540 IF (apbi.pwrite AND apbi.penable) = '1' THEN
556 541 -- APB DMA WRITE --
557 542 CASE paddr(7 DOWNTO 2) IS
558 543 --
559 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
560 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
561 reg_sp.config_ms_run <= apbi.pwdata(2);
544 WHEN ADDR_LFR_SM_CONFIG =>
545 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
546 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
547 reg_sp.config_ms_run <= apbi.pwdata(2);
562 548
563 WHEN "000001" =>
549 WHEN ADDR_LFR_SM_STATUS =>
564 550 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
565 551 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
566 552 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
567 553 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
568 554 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
569 555 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
570 556 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
571 557 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
572 558 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
573 559 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
574 --2
575 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
576 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
577 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
578 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
579 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
580 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
581 --8 to 19
582 --20
583 WHEN "010100" => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
584 --20
585 WHEN "010101" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
586 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
587 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
588 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
589 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
590 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
591 WHEN "010110" => reg_wp.enable_f0 <= apbi.pwdata(0);
592 reg_wp.enable_f1 <= apbi.pwdata(1);
593 reg_wp.enable_f2 <= apbi.pwdata(2);
594 reg_wp.enable_f3 <= apbi.pwdata(3);
595 reg_wp.burst_f0 <= apbi.pwdata(4);
596 reg_wp.burst_f1 <= apbi.pwdata(5);
597 reg_wp.burst_f2 <= apbi.pwdata(6);
598 reg_wp.run <= apbi.pwdata(7);
599 --22
600 WHEN "010111" => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
601 WHEN "011000" => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
602 WHEN "011001" => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
603 WHEN "011010" => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
604 WHEN "011011" => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
605 WHEN "011100" => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
606 WHEN "011101" => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
607 WHEN "011110" => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
608 --26
609 WHEN "011111" =>
560 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
561 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
562 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
563 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
564 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
565 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
566
567 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
568 ---------------------------------------------------------------------
569 WHEN ADDR_LFR_WP_DATASHAPING =>
570 reg_wp.data_shaping_BW <= apbi.pwdata(0);
571 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
572 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
573 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
574 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
575 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
576 WHEN ADDR_LFR_WP_CONTROL =>
577 reg_wp.enable_f0 <= apbi.pwdata(0);
578 reg_wp.enable_f1 <= apbi.pwdata(1);
579 reg_wp.enable_f2 <= apbi.pwdata(2);
580 reg_wp.enable_f3 <= apbi.pwdata(3);
581 reg_wp.burst_f0 <= apbi.pwdata(4);
582 reg_wp.burst_f1 <= apbi.pwdata(5);
583 reg_wp.burst_f2 <= apbi.pwdata(6);
584 reg_wp.run <= apbi.pwdata(7);
585 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
586 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
587 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
588 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
589 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
590 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
591 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
592 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
593 WHEN ADDR_LFR_WP_STATUS =>
610 594 all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
611 595 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) ) AND reg_wp.status_ready_buffer_f(I*2) ) OR reg_ready_buffer_f(I*2);
612 596 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
613 597 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) ) AND reg_wp.error_buffer_full(I) ) OR wfp_error_buffer_full(I);
614 598 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I) ) OR status_new_err(I);
615 599 END LOOP all_reg_wp_status_bit;
616 600
617 WHEN "100000" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
618 WHEN "100001" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
619 WHEN "100010" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
620 WHEN "100011" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
621 WHEN "100100" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
622 WHEN "100101" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
623 WHEN "100110" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
624 WHEN "100111" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
601 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
602 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
603 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
604 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
605 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
606 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
607 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
608 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
625 609
626 WHEN "111000" => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
627
628
610 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
629 611
630
631
632 -- WHEN "100100" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
633 --
634 612 WHEN OTHERS => NULL;
635 613 END CASE;
636 614 END IF;
637 615 END IF;
638 616 --apbo.pirq(pirq_ms) <=
617 pirq_temp( pirq_ms) <= apbo_irq_ms;
618 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
639 619 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
640 620 ready_matrix_f1 OR
641 621 ready_matrix_f2)
642 622 )
643 623 OR
644 624 (reg_sp.config_active_interruption_onError AND (
645 625 -- error_bad_component_error OR
646 626 error_buffer_full
647 627 OR error_input_fifo_write(0)
648 628 OR error_input_fifo_write(1)
649 629 OR error_input_fifo_write(2))
650 630 ));
651 631 -- apbo.pirq(pirq_wfp)
652 632 apbo_irq_wfp<= ored_irq_wfp;
653 633
654 634 END IF;
655 635 END PROCESS lpp_lfr_apbreg;
636
637 apbo.pirq <= pirq_temp;
638
656 639
657 apbo.pirq(pirq_ms) <= apbo_irq_ms;
658 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
640 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
641 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
642 -- apbo.pirq(I) <= apbo_irq_ms;
643 -- END GENERATE IRQ_is_PIRQ_MS;
644 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
645 -- apbo.pirq(I) <= apbo_irq_wfp;
646 -- END GENERATE IRQ_is_PIRQ_WFP;
647 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
648 -- apbo.pirq(I) <= '0';
649 -- END GENERATE IRQ_OTHERS;
650
651 --END GENERATE all_irq;
652
653
659 654
660 655 apbo.pindex <= pindex;
661 656 apbo.pconfig <= pconfig;
662 657 apbo.prdata <= prdata;
663 658
664 659 -----------------------------------------------------------------------------
665 660 -- IRQ
666 661 -----------------------------------------------------------------------------
667 662 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
668 663
669 664 PROCESS (HCLK, HRESETn)
670 665 BEGIN -- PROCESS
671 666 IF HRESETn = '0' THEN -- asynchronous reset (active low)
672 667 irq_wfp_reg <= (OTHERS => '0');
673 668 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
674 669 irq_wfp_reg <= irq_wfp_reg_s;
675 670 END IF;
676 671 END PROCESS;
677 672
678 673 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
679 674 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
680 675 END GENERATE all_irq_wfp;
681 676
682 677 irq_wfp_ZERO <= (OTHERS => '0');
683 678 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
684 679
685 680 run_ms <= reg_sp.config_ms_run;
686 681
687 682 -----------------------------------------------------------------------------
688 683 --
689 684 -----------------------------------------------------------------------------
690 685 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
691 686 PORT MAP (
692 687 clk => HCLK,
693 688 rstn => HRESETn,
694 689
695 690 run => '1',--reg_sp.config_ms_run,
696 691
697 692 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
698 693 reg0_ready_matrix => reg0_ready_matrix_f0,
699 694 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
700 695 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
701 696
702 697 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
703 698 reg1_ready_matrix => reg1_ready_matrix_f0,
704 699 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
705 700 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
706 701
707 702 ready_matrix => ready_matrix_f0,
708 703 status_ready_matrix => status_ready_matrix_f0,
709 704 addr_matrix => addr_matrix_f0,
710 705 matrix_time => matrix_time_f0);
711 706
712 707 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
713 708 PORT MAP (
714 709 clk => HCLK,
715 710 rstn => HRESETn,
716 711
717 712 run => '1',--reg_sp.config_ms_run,
718 713
719 714 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
720 715 reg0_ready_matrix => reg0_ready_matrix_f1,
721 716 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
722 717 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
723 718
724 719 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
725 720 reg1_ready_matrix => reg1_ready_matrix_f1,
726 721 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
727 722 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
728 723
729 724 ready_matrix => ready_matrix_f1,
730 725 status_ready_matrix => status_ready_matrix_f1,
731 726 addr_matrix => addr_matrix_f1,
732 727 matrix_time => matrix_time_f1);
733 728
734 729 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
735 730 PORT MAP (
736 731 clk => HCLK,
737 732 rstn => HRESETn,
738 733
739 734 run => '1',--reg_sp.config_ms_run,
740 735
741 736 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
742 737 reg0_ready_matrix => reg0_ready_matrix_f2,
743 738 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
744 739 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
745 740
746 741 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
747 742 reg1_ready_matrix => reg1_ready_matrix_f2,
748 743 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
749 744 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
750 745
751 746 ready_matrix => ready_matrix_f2,
752 747 status_ready_matrix => status_ready_matrix_f2,
753 748 addr_matrix => addr_matrix_f2,
754 749 matrix_time => matrix_time_f2);
755 750
756 751 -----------------------------------------------------------------------------
757 752 all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
758 753 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
759 754 PORT MAP (
760 755 clk => HCLK,
761 756 rstn => HRESETn,
762 757
763 758 run => '1',--reg_wp.run,
764 759
765 760 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
766 761 reg0_ready_matrix => reg_ready_buffer_f(2*I),
767 762 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
768 763 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
769 764
770 765 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
771 766 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
772 767 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
773 768 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
774 769
775 770 ready_matrix => wfp_ready_buffer(I),
776 771 status_ready_matrix => wfp_status_buffer_ready(I),
777 772 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
778 773 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
779 774 );
780 775
781 776 END GENERATE all_wfp_pointer;
782 777 -----------------------------------------------------------------------------
783 778
784 779 END beh;
780
781 -------------------------------------------------------------------------------
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@@ -1,10 +1,11
1 1 lpp_top_lfr_pkg.vhd
2 2 lpp_lfr_pkg.vhd
3 lpp_lfr_apbreg_pkg.vhd
3 4 lpp_lfr_filter.vhd
4 5 lpp_lfr_apbreg.vhd
5 6 lpp_lfr_apbreg_ms_pointer.vhd
6 7 lpp_lfr_ms_fsmdma.vhd
7 8 lpp_lfr_ms_FFT.vhd
8 9 lpp_lfr_ms.vhd
9 10 lpp_lfr_ms_reg_head.vhd
10 11 lpp_lfr.vhd
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