##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Changed design MINI-LFR_WFP_MS to SOLO_LFR_MINI-LFR....
Alexis Jeandet -
r656:a69a331fccb2 SOLO_LFR_01-5A (MINI-LFR) default draft
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,10
1 SOLO\_LFR\_MINI-LFR is the implementation of Solar Orbiter LFR analyser for the board MINI-LFR.
2
3 You can find information about :
4
5 - MINI-LFR board in the redmine here :
6 [Mini_LFR](https://hephaistos.lpp.polytechnique.fr/redmine/projects/mini-lfr/wiki)
7 - the bistream Generation :
8 [Bitstream_Generation](https://hephaistos.lpp.polytechnique.fr/redmine/projects/vhdlib/wiki/Mini_LFR_-_Bitstream_Generation)
9
10
Show file before | Show file after | Hide comments
1 NO CONTENT: file renamed from boards/MINI-LFR/MINI-LFR.sdc to boards/MINI-LFR/MINI-LFR_PlaceAndRoute.sdc
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (1264 lines changed) Show them Hide them
@@ -1,632 +1,632
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk100MHz : IN STD_LOGIC;
52 clk49_152MHz : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
125
126 SIGNAL clk_50_s : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
129 -----------------------------------------------------------------------------
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 --
133 SIGNAL errorn : STD_LOGIC;
134 --
135 SIGNAL I00_s : STD_LOGIC;
136
137 -- CONSTANTS
138 CONSTANT CFG_PADTECH : INTEGER := inferred;
139 --
140 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
141 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
142 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
143
144 SIGNAL apbi_ext : apb_slv_in_type;
145 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
146 SIGNAL ahbi_s_ext : ahb_slv_in_type;
147 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
148 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
149 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
150
151 -- Spacewire signals
152 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
155 SIGNAL spw_rxtxclk : STD_ULOGIC;
156 SIGNAL spw_rxclkn : STD_ULOGIC;
157 SIGNAL spw_clk : STD_LOGIC;
158 SIGNAL swni : grspw_in_type;
159 SIGNAL swno : grspw_out_type;
160
161 --GPIO
162 SIGNAL gpioi : gpio_in_type;
163 SIGNAL gpioo : gpio_out_type;
164
165 -- AD Converter ADS7886
166 SIGNAL sample : Samples14v(7 DOWNTO 0);
167 SIGNAL sample_s : Samples(7 DOWNTO 0);
168 SIGNAL sample_val : STD_LOGIC;
169 SIGNAL ADC_nCS_sig : STD_LOGIC;
170 SIGNAL ADC_CLK_sig : STD_LOGIC;
171 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
172
173 SIGNAL bias_fail_sw_sig : STD_LOGIC;
174
175 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
178 -----------------------------------------------------------------------------
179
180 SIGNAL LFR_soft_rstn : STD_LOGIC;
181 SIGNAL LFR_rstn : STD_LOGIC;
182
183
184 SIGNAL rstn_25 : STD_LOGIC;
185 SIGNAL rstn_25_d1 : STD_LOGIC;
186 SIGNAL rstn_25_d2 : STD_LOGIC;
187 SIGNAL rstn_25_d3 : STD_LOGIC;
188
189 SIGNAL rstn_24 : STD_LOGIC;
190 SIGNAL rstn_24_d1 : STD_LOGIC;
191 SIGNAL rstn_24_d2 : STD_LOGIC;
192 SIGNAL rstn_24_d3 : STD_LOGIC;
193
194 SIGNAL rstn_50 : STD_LOGIC;
195 SIGNAL rstn_50_d1 : STD_LOGIC;
196 SIGNAL rstn_50_d2 : STD_LOGIC;
197 SIGNAL rstn_50_d3 : STD_LOGIC;
198
199 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
200 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
201
202 --
203 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
204
205 --
206 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
207 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
208
209 SIGNAL nSRAM_READY : STD_LOGIC;
210
211 BEGIN -- beh
212
213 -----------------------------------------------------------------------------
214 PROCESS (clk100MHz, reset)
215 BEGIN -- PROCESS
216 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
217 clk_50_s <= NOT clk_50_s;
218 END IF;
219 END PROCESS;
220 -----------------------------------------------------------------------------
221
222 PROCESS (clk_50_s, reset)
223 BEGIN -- PROCESS
224 IF reset = '0' THEN -- asynchronous reset (active low)
225 clk_25 <= '0';
226 rstn_25 <= '0';
227 rstn_25_d1 <= '0';
228 rstn_25_d2 <= '0';
229 rstn_25_d3 <= '0';
230 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
231 clk_25 <= NOT clk_25;
232 rstn_25_d1 <= '1';
233 rstn_25_d2 <= rstn_25_d1;
234 rstn_25_d3 <= rstn_25_d2;
235 rstn_25 <= rstn_25_d3;
236 END IF;
237 END PROCESS;
238
239 PROCESS (clk49_152MHz, reset)
240 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 clk_24 <= '0';
243 rstn_24_d1 <= '0';
244 rstn_24_d2 <= '0';
245 rstn_24_d3 <= '0';
246 rstn_24 <= '0';
247 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
248 clk_24 <= NOT clk_24;
249 rstn_24_d1 <= '1';
250 rstn_24_d2 <= rstn_24_d1;
251 rstn_24_d3 <= rstn_24_d2;
252 rstn_24 <= rstn_24_d3;
253 END IF;
254 END PROCESS;
255
256 -----------------------------------------------------------------------------
257
258 PROCESS (clk_25, rstn_25)
259 BEGIN -- PROCESS
260 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
261 LED0 <= '0';
262 LED1 <= '0';
263 LED2 <= '0';
264 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
265 LED0 <= '0';
266 LED1 <= '1';
267 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
268 END IF;
269 END PROCESS;
270
271 PROCESS (clk49_152MHz, rstn_24)
272 BEGIN -- PROCESS
273 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
274 I00_s <= '0';
275 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
276 I00_s <= NOT I00_s;
277 END IF;
278 END PROCESS;
279
280 --UARTs
281 nCTS1 <= '1';
282 nCTS2 <= '1';
283 nDCD2 <= '1';
284 -- No AHB UART
285 RXD1 <= TXD1;
286
287 --
288
289 leon3_soc_1 : leon3_soc
290 GENERIC MAP (
291 fabtech => apa3e,
292 memtech => apa3e,
293 padtech => inferred,
294 clktech => inferred,
295 disas => 0,
296 dbguart => 0,
297 pclow => 2,
298 clk_freq => 25000,
299 IS_RADHARD => 0,
300 NB_CPU => 1,
301 ENABLE_FPU => 1,
302 FPU_NETLIST => 0,
303 ENABLE_DSU => 1,
304 ENABLE_AHB_UART => 0,
305 ENABLE_APB_UART => 1,
306 ENABLE_IRQMP => 1,
307 ENABLE_GPT => 1,
308 NB_AHB_MASTER => NB_AHB_MASTER,
309 NB_AHB_SLAVE => NB_AHB_SLAVE,
310 NB_APB_SLAVE => NB_APB_SLAVE,
311 ADDRESS_SIZE => 20,
312 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
313 BYPASS_EDAC_MEMCTRLR => '0',
314 SRBANKSZ => 9)
315 PORT MAP (
316 clk => clk_25,
317 reset => rstn_25,
318 errorn => errorn,
319 ahbrxd => OPEN,--TXD1,
320 ahbtxd => OPEN,--RXD1,
321 urxd1 => TXD2,
322 utxd1 => RXD2,
323 address => SRAM_A,
324 data => SRAM_DQ,
325 nSRAM_BE0 => SRAM_nBE(0),
326 nSRAM_BE1 => SRAM_nBE(1),
327 nSRAM_BE2 => SRAM_nBE(2),
328 nSRAM_BE3 => SRAM_nBE(3),
329 nSRAM_WE => SRAM_nWE,
330 nSRAM_CE => SRAM_CE_s,
331 nSRAM_OE => SRAM_nOE,
332 nSRAM_READY => nSRAM_READY,
333 SRAM_MBE => OPEN,
334 apbi_ext => apbi_ext,
335 apbo_ext => apbo_ext,
336 ahbi_s_ext => ahbi_s_ext,
337 ahbo_s_ext => ahbo_s_ext,
338 ahbi_m_ext => ahbi_m_ext,
339 ahbo_m_ext => ahbo_m_ext);
340
341 PROCESS (clk_25, rstn_25)
342 BEGIN -- PROCESS
343 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
344 nSRAM_READY <= '1';
345 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
346 nSRAM_READY <= '1';
347 IF IO0 = '1' THEN
348 nSRAM_READY <= '0';
349 END IF;
350 END IF;
351 END PROCESS;
352
353
354
355 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
356 SRAM_CE <= not SRAM_CE_s(0);
357 END GENERATE;
358
359 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
360 SRAM_CE <= SRAM_CE_s(0);
361 END GENERATE;
362 -------------------------------------------------------------------------------
363 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
364 -------------------------------------------------------------------------------
365 apb_lfr_management_1 : apb_lfr_management
366 GENERIC MAP (
367 tech => apa3e,
368 pindex => 6,
369 paddr => 6,
370 pmask => 16#fff#,
371 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
372 PORT MAP (
373 clk25MHz => clk_25,
374 resetn_25MHz => rstn_25,
375 grspw_tick => swno.tickout,
376 apbi => apbi_ext,
377 apbo => apbo_ext(6),
378 HK_sample => sample_hk,
379 HK_val => sample_val,
380 HK_sel => HK_SEL,
381 DAC_SDO => OPEN,
382 DAC_SCK => OPEN,
383 DAC_SYNC => OPEN,
384 DAC_CAL_EN => OPEN,
385 coarse_time => coarse_time,
386 fine_time => fine_time,
387 LFR_soft_rstn => LFR_soft_rstn
388 );
389
390 -----------------------------------------------------------------------
391 --- SpaceWire --------------------------------------------------------
392 -----------------------------------------------------------------------
393
394 SPW_EN <= '1';
395
396 spw_clk <= clk_50_s;
397 spw_rxtxclk <= spw_clk;
398 spw_rxclkn <= NOT spw_rxtxclk;
399
400 -- PADS for SPW1
401 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
402 PORT MAP (SPW_NOM_DIN, dtmp(0));
403 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
404 PORT MAP (SPW_NOM_SIN, stmp(0));
405 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
406 PORT MAP (SPW_NOM_DOUT, swno.d(0));
407 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
408 PORT MAP (SPW_NOM_SOUT, swno.s(0));
409 -- PADS FOR SPW2
410 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
411 PORT MAP (SPW_RED_SIN, dtmp(1));
412 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
413 PORT MAP (SPW_RED_DIN, stmp(1));
414 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_RED_DOUT, swno.d(1));
416 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_RED_SOUT, swno.s(1));
418
419 -- GRSPW PHY
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
422 GENERIC MAP(
423 tech => apa3e,
424 rxclkbuftype => 1,
425 scantest => 0)
426 PORT MAP(
427 rxrst => swno.rxrst,
428 di => dtmp(j),
429 si => stmp(j),
430 rxclko => spw_rxclk(j),
431 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
435
436 swni.rmapnodeaddr <= (OTHERS => '0');
437
438 -- SPW core
439 sw0 : grspwm GENERIC MAP(
440 tech => apa3e,
441 hindex => 1,
442 pindex => 5,
443 paddr => 5,
444 pirq => 11,
445 sysfreq => 25000, -- CPU_FREQ
446 rmap => 1,
447 rmapcrc => 1,
448 fifosize1 => 16,
449 fifosize2 => 16,
450 rxclkbuftype => 1,
451 rxunaligned => 0,
452 rmapbufs => 4,
453 ft => 0,
454 netlist => 0,
455 ports => 2,
456 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
457 memtech => apa3e,
458 destkey => 2,
459 spwcore => 1
460 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
461 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
462 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
463 )
464 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
465 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
466 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
467 swni, swno);
468
469 swni.tickin <= '0';
470 swni.rmapen <= '1';
471 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
472 swni.tickinraw <= '0';
473 swni.timein <= (OTHERS => '0');
474 swni.dcrstval <= (OTHERS => '0');
475 swni.timerrstval <= (OTHERS => '0');
476
477 -------------------------------------------------------------------------------
478 -- LFR ------------------------------------------------------------------------
479 -------------------------------------------------------------------------------
480
481
482 LFR_rstn <= LFR_soft_rstn AND rstn_25;
483
484 lpp_lfr_1 : lpp_lfr
485 GENERIC MAP (
486 Mem_use => use_RAM,
487 nb_data_by_buffer_size => 32,
488 nb_snapshot_param_size => 32,
489 delta_vector_size => 32,
490 delta_vector_size_f0_2 => 7, -- log2(96)
491 pindex => 15,
492 paddr => 15,
493 pmask => 16#fff#,
494 pirq_ms => 6,
495 pirq_wfp => 14,
496 hindex => 2,
497 top_lfr_version => X"000159") -- aa.bb.cc version
498 PORT MAP (
499 clk => clk_25,
500 rstn => LFR_rstn,
501 sample_B => sample_s(2 DOWNTO 0),
502 sample_E => sample_s(7 DOWNTO 3),
503 sample_val => sample_val,
504 apbi => apbi_ext,
505 apbo => apbo_ext(15),
506 ahbi => ahbi_m_ext,
507 ahbo => ahbo_m_ext(2),
508 coarse_time => coarse_time,
509 fine_time => fine_time,
510 data_shaping_BW => bias_fail_sw_sig,
511 debug_vector => lfr_debug_vector,
512 debug_vector_ms => lfr_debug_vector_ms
513 );
514
515 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
516 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
517 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
518 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
519
520 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
521 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
522 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
523 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
524 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
525 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
526 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
527
528 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
529 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
530 END GENERATE all_sample;
531
532 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
533 GENERIC MAP(
534 ChannelCount => 8,
535 SampleNbBits => 14,
536 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
537 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
538 PORT MAP (
539 -- CONV
540 cnv_clk => clk_24,
541 cnv_rstn => rstn_24,
542 cnv => ADC_nCS_sig,
543 -- DATA
544 clk => clk_25,
545 rstn => rstn_25,
546 sck => ADC_CLK_sig,
547 sdo => ADC_SDO_sig,
548 -- SAMPLE
549 sample => sample,
550 sample_val => sample_val);
551
552 ADC_nCS <= ADC_nCS_sig;
553 ADC_CLK <= ADC_CLK_sig;
554 ADC_SDO_sig <= ADC_SDO;
555
556 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
557 "0010001000100010" WHEN HK_SEL = "01" ELSE
558 "0100010001000100" WHEN HK_SEL = "10" ELSE
559 (OTHERS => '0');
560
561
562 ----------------------------------------------------------------------
563 --- GPIO -----------------------------------------------------------
564 ----------------------------------------------------------------------
565
566 grgpio0 : grgpio
567 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
568 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
569
570 gpioi.sig_en <= (OTHERS => '0');
571 gpioi.sig_in <= (OTHERS => '0');
572 gpioi.din <= (OTHERS => '0');
573 PROCESS (clk_25, rstn_25)
574 BEGIN -- PROCESS
575 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
576 IO8 <= '0';
577 IO9 <= '0';
578 IO10 <= '0';
579 IO11 <= '0';
580 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
581 CASE gpioo.dout(2 DOWNTO 0) IS
582 WHEN "011" =>
583 IO8 <= observation_reg(8);
584 IO9 <= observation_reg(9);
585 IO10 <= observation_reg(10);
586 IO11 <= observation_reg(11);
587 WHEN "001" =>
588 IO8 <= observation_reg(8 + 12);
589 IO9 <= observation_reg(9 + 12);
590 IO10 <= observation_reg(10 + 12);
591 IO11 <= observation_reg(11 + 12);
592 WHEN "010" =>
593 IO8 <= '0';
594 IO9 <= '0';
595 IO10 <= '0';
596 IO11 <= '0';
597 WHEN "000" =>
598 IO8 <= observation_vector_0(8);
599 IO9 <= observation_vector_0(9);
600 IO10 <= observation_vector_0(10);
601 IO11 <= observation_vector_0(11);
602 WHEN "100" =>
603 IO8 <= observation_vector_1(8);
604 IO9 <= observation_vector_1(9);
605 IO10 <= observation_vector_1(10);
606 IO11 <= observation_vector_1(11);
607 WHEN OTHERS => NULL;
608 END CASE;
609
610 END IF;
611 END PROCESS;
612 -----------------------------------------------------------------------------
613 --
614 -----------------------------------------------------------------------------
615 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
616 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
617 apbo_ext(I) <= apb_none;
618 END GENERATE apbo_ext_not_used;
619 END GENERATE all_apbo_ext;
620
621
622 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
623 ahbo_s_ext(I) <= ahbs_none;
624 END GENERATE all_ahbo_ext;
625
626 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
627 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
628 ahbo_m_ext(I) <= ahbm_none;
629 END GENERATE ahbo_m_ext_not_used;
630 END GENERATE all_ahbo_m_ext;
631
632 END beh;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY MINI_LFR_top IS
49
50 PORT (
51 clk100MHz : IN STD_LOGIC;
52 clk49_152MHz : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
111
112 END MINI_LFR_top;
113
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
125
126 SIGNAL clk_50_s : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
129 -----------------------------------------------------------------------------
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 --
133 SIGNAL errorn : STD_LOGIC;
134 --
135 SIGNAL I00_s : STD_LOGIC;
136
137 -- CONSTANTS
138 CONSTANT CFG_PADTECH : INTEGER := inferred;
139 --
140 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
141 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
142 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
143
144 SIGNAL apbi_ext : apb_slv_in_type;
145 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
146 SIGNAL ahbi_s_ext : ahb_slv_in_type;
147 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
148 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
149 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
150
151 -- Spacewire signals
152 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
155 SIGNAL spw_rxtxclk : STD_ULOGIC;
156 SIGNAL spw_rxclkn : STD_ULOGIC;
157 SIGNAL spw_clk : STD_LOGIC;
158 SIGNAL swni : grspw_in_type;
159 SIGNAL swno : grspw_out_type;
160
161 --GPIO
162 SIGNAL gpioi : gpio_in_type;
163 SIGNAL gpioo : gpio_out_type;
164
165 -- AD Converter ADS7886
166 SIGNAL sample : Samples14v(7 DOWNTO 0);
167 SIGNAL sample_s : Samples(7 DOWNTO 0);
168 SIGNAL sample_val : STD_LOGIC;
169 SIGNAL ADC_nCS_sig : STD_LOGIC;
170 SIGNAL ADC_CLK_sig : STD_LOGIC;
171 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
172
173 SIGNAL bias_fail_sw_sig : STD_LOGIC;
174
175 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
178 -----------------------------------------------------------------------------
179
180 SIGNAL LFR_soft_rstn : STD_LOGIC;
181 SIGNAL LFR_rstn : STD_LOGIC;
182
183
184 SIGNAL rstn_25 : STD_LOGIC;
185 SIGNAL rstn_25_d1 : STD_LOGIC;
186 SIGNAL rstn_25_d2 : STD_LOGIC;
187 SIGNAL rstn_25_d3 : STD_LOGIC;
188
189 SIGNAL rstn_24 : STD_LOGIC;
190 SIGNAL rstn_24_d1 : STD_LOGIC;
191 SIGNAL rstn_24_d2 : STD_LOGIC;
192 SIGNAL rstn_24_d3 : STD_LOGIC;
193
194 SIGNAL rstn_50 : STD_LOGIC;
195 SIGNAL rstn_50_d1 : STD_LOGIC;
196 SIGNAL rstn_50_d2 : STD_LOGIC;
197 SIGNAL rstn_50_d3 : STD_LOGIC;
198
199 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
200 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
201
202 --
203 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
204
205 --
206 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
207 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
208
209 SIGNAL nSRAM_READY : STD_LOGIC;
210
211 BEGIN -- beh
212
213 -----------------------------------------------------------------------------
214 PROCESS (clk100MHz, reset)
215 BEGIN -- PROCESS
216 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
217 clk_50_s <= NOT clk_50_s;
218 END IF;
219 END PROCESS;
220 -----------------------------------------------------------------------------
221
222 PROCESS (clk_50_s, reset)
223 BEGIN -- PROCESS
224 IF reset = '0' THEN -- asynchronous reset (active low)
225 clk_25 <= '0';
226 rstn_25 <= '0';
227 rstn_25_d1 <= '0';
228 rstn_25_d2 <= '0';
229 rstn_25_d3 <= '0';
230 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
231 clk_25 <= NOT clk_25;
232 rstn_25_d1 <= '1';
233 rstn_25_d2 <= rstn_25_d1;
234 rstn_25_d3 <= rstn_25_d2;
235 rstn_25 <= rstn_25_d3;
236 END IF;
237 END PROCESS;
238
239 PROCESS (clk49_152MHz, reset)
240 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 clk_24 <= '0';
243 rstn_24_d1 <= '0';
244 rstn_24_d2 <= '0';
245 rstn_24_d3 <= '0';
246 rstn_24 <= '0';
247 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
248 clk_24 <= NOT clk_24;
249 rstn_24_d1 <= '1';
250 rstn_24_d2 <= rstn_24_d1;
251 rstn_24_d3 <= rstn_24_d2;
252 rstn_24 <= rstn_24_d3;
253 END IF;
254 END PROCESS;
255
256 -----------------------------------------------------------------------------
257
258 PROCESS (clk_25, rstn_25)
259 BEGIN -- PROCESS
260 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
261 LED0 <= '0';
262 LED1 <= '0';
263 LED2 <= '0';
264 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
265 LED0 <= '0';
266 LED1 <= '1';
267 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
268 END IF;
269 END PROCESS;
270
271 PROCESS (clk49_152MHz, rstn_24)
272 BEGIN -- PROCESS
273 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
274 I00_s <= '0';
275 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
276 I00_s <= NOT I00_s;
277 END IF;
278 END PROCESS;
279
280 --UARTs
281 nCTS1 <= '1';
282 nCTS2 <= '1';
283 nDCD2 <= '1';
284 -- No AHB UART
285 RXD1 <= TXD1;
286
287 --
288
289 leon3_soc_1 : leon3_soc
290 GENERIC MAP (
291 fabtech => apa3e,
292 memtech => apa3e,
293 padtech => inferred,
294 clktech => inferred,
295 disas => 0,
296 dbguart => 0,
297 pclow => 2,
298 clk_freq => 25000,
299 IS_RADHARD => 0,
300 NB_CPU => 1,
301 ENABLE_FPU => 1,
302 FPU_NETLIST => 0,
303 ENABLE_DSU => 1,
304 ENABLE_AHB_UART => 0,
305 ENABLE_APB_UART => 1,
306 ENABLE_IRQMP => 1,
307 ENABLE_GPT => 1,
308 NB_AHB_MASTER => NB_AHB_MASTER,
309 NB_AHB_SLAVE => NB_AHB_SLAVE,
310 NB_APB_SLAVE => NB_APB_SLAVE,
311 ADDRESS_SIZE => 20,
312 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
313 BYPASS_EDAC_MEMCTRLR => '0',
314 SRBANKSZ => 9)
315 PORT MAP (
316 clk => clk_25,
317 reset => rstn_25,
318 errorn => errorn,
319 ahbrxd => OPEN,--TXD1,
320 ahbtxd => OPEN,--RXD1,
321 urxd1 => TXD2,
322 utxd1 => RXD2,
323 address => SRAM_A,
324 data => SRAM_DQ,
325 nSRAM_BE0 => SRAM_nBE(0),
326 nSRAM_BE1 => SRAM_nBE(1),
327 nSRAM_BE2 => SRAM_nBE(2),
328 nSRAM_BE3 => SRAM_nBE(3),
329 nSRAM_WE => SRAM_nWE,
330 nSRAM_CE => SRAM_CE_s,
331 nSRAM_OE => SRAM_nOE,
332 nSRAM_READY => nSRAM_READY,
333 SRAM_MBE => OPEN,
334 apbi_ext => apbi_ext,
335 apbo_ext => apbo_ext,
336 ahbi_s_ext => ahbi_s_ext,
337 ahbo_s_ext => ahbo_s_ext,
338 ahbi_m_ext => ahbi_m_ext,
339 ahbo_m_ext => ahbo_m_ext);
340
341 PROCESS (clk_25, rstn_25)
342 BEGIN -- PROCESS
343 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
344 nSRAM_READY <= '1';
345 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
346 nSRAM_READY <= '1';
347 IF IO0 = '1' THEN
348 nSRAM_READY <= '0';
349 END IF;
350 END IF;
351 END PROCESS;
352
353
354
355 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
356 SRAM_CE <= not SRAM_CE_s(0);
357 END GENERATE;
358
359 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
360 SRAM_CE <= SRAM_CE_s(0);
361 END GENERATE;
362 -------------------------------------------------------------------------------
363 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
364 -------------------------------------------------------------------------------
365 apb_lfr_management_1 : apb_lfr_management
366 GENERIC MAP (
367 tech => apa3e,
368 pindex => 6,
369 paddr => 6,
370 pmask => 16#fff#,
371 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
372 PORT MAP (
373 clk25MHz => clk_25,
374 resetn_25MHz => rstn_25,
375 grspw_tick => swno.tickout,
376 apbi => apbi_ext,
377 apbo => apbo_ext(6),
378 HK_sample => sample_hk,
379 HK_val => sample_val,
380 HK_sel => HK_SEL,
381 DAC_SDO => OPEN,
382 DAC_SCK => OPEN,
383 DAC_SYNC => OPEN,
384 DAC_CAL_EN => OPEN,
385 coarse_time => coarse_time,
386 fine_time => fine_time,
387 LFR_soft_rstn => LFR_soft_rstn
388 );
389
390 -----------------------------------------------------------------------
391 --- SpaceWire --------------------------------------------------------
392 -----------------------------------------------------------------------
393
394 SPW_EN <= '1';
395
396 spw_clk <= clk_50_s;
397 spw_rxtxclk <= spw_clk;
398 spw_rxclkn <= NOT spw_rxtxclk;
399
400 -- PADS for SPW1
401 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
402 PORT MAP (SPW_NOM_DIN, dtmp(0));
403 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
404 PORT MAP (SPW_NOM_SIN, stmp(0));
405 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
406 PORT MAP (SPW_NOM_DOUT, swno.d(0));
407 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
408 PORT MAP (SPW_NOM_SOUT, swno.s(0));
409 -- PADS FOR SPW2
410 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
411 PORT MAP (SPW_RED_SIN, dtmp(1));
412 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
413 PORT MAP (SPW_RED_DIN, stmp(1));
414 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_RED_DOUT, swno.d(1));
416 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_RED_SOUT, swno.s(1));
418
419 -- GRSPW PHY
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
422 GENERIC MAP(
423 tech => apa3e,
424 rxclkbuftype => 1,
425 scantest => 0)
426 PORT MAP(
427 rxrst => swno.rxrst,
428 di => dtmp(j),
429 si => stmp(j),
430 rxclko => spw_rxclk(j),
431 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
435
436 swni.rmapnodeaddr <= (OTHERS => '0');
437
438 -- SPW core
439 sw0 : grspwm GENERIC MAP(
440 tech => apa3e,
441 hindex => 1,
442 pindex => 5,
443 paddr => 5,
444 pirq => 11,
445 sysfreq => 25000, -- CPU_FREQ
446 rmap => 1,
447 rmapcrc => 1,
448 fifosize1 => 16,
449 fifosize2 => 16,
450 rxclkbuftype => 1,
451 rxunaligned => 0,
452 rmapbufs => 4,
453 ft => 0,
454 netlist => 0,
455 ports => 2,
456 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
457 memtech => apa3e,
458 destkey => 2,
459 spwcore => 1
460 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
461 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
462 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
463 )
464 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
465 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
466 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
467 swni, swno);
468
469 swni.tickin <= '0';
470 swni.rmapen <= '1';
471 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
472 swni.tickinraw <= '0';
473 swni.timein <= (OTHERS => '0');
474 swni.dcrstval <= (OTHERS => '0');
475 swni.timerrstval <= (OTHERS => '0');
476
477 -------------------------------------------------------------------------------
478 -- LFR ------------------------------------------------------------------------
479 -------------------------------------------------------------------------------
480
481
482 LFR_rstn <= LFR_soft_rstn AND rstn_25;
483
484 lpp_lfr_1 : lpp_lfr
485 GENERIC MAP (
486 Mem_use => use_RAM,
487 nb_data_by_buffer_size => 32,
488 nb_snapshot_param_size => 32,
489 delta_vector_size => 32,
490 delta_vector_size_f0_2 => 7, -- log2(96)
491 pindex => 15,
492 paddr => 15,
493 pmask => 16#fff#,
494 pirq_ms => 6,
495 pirq_wfp => 14,
496 hindex => 2,
497 top_lfr_version => LPP_LFR_BOARD_MINI_LFR & X"015A") -- aa.bb.cc version
498 PORT MAP (
499 clk => clk_25,
500 rstn => LFR_rstn,
501 sample_B => sample_s(2 DOWNTO 0),
502 sample_E => sample_s(7 DOWNTO 3),
503 sample_val => sample_val,
504 apbi => apbi_ext,
505 apbo => apbo_ext(15),
506 ahbi => ahbi_m_ext,
507 ahbo => ahbo_m_ext(2),
508 coarse_time => coarse_time,
509 fine_time => fine_time,
510 data_shaping_BW => bias_fail_sw_sig,
511 debug_vector => lfr_debug_vector,
512 debug_vector_ms => lfr_debug_vector_ms
513 );
514
515 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
516 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
517 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
518 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
519
520 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
521 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
522 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
523 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
524 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
525 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
526 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
527
528 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
529 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
530 END GENERATE all_sample;
531
532 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
533 GENERIC MAP(
534 ChannelCount => 8,
535 SampleNbBits => 14,
536 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
537 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
538 PORT MAP (
539 -- CONV
540 cnv_clk => clk_24,
541 cnv_rstn => rstn_24,
542 cnv => ADC_nCS_sig,
543 -- DATA
544 clk => clk_25,
545 rstn => rstn_25,
546 sck => ADC_CLK_sig,
547 sdo => ADC_SDO_sig,
548 -- SAMPLE
549 sample => sample,
550 sample_val => sample_val);
551
552 ADC_nCS <= ADC_nCS_sig;
553 ADC_CLK <= ADC_CLK_sig;
554 ADC_SDO_sig <= ADC_SDO;
555
556 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
557 "0010001000100010" WHEN HK_SEL = "01" ELSE
558 "0100010001000100" WHEN HK_SEL = "10" ELSE
559 (OTHERS => '0');
560
561
562 ----------------------------------------------------------------------
563 --- GPIO -----------------------------------------------------------
564 ----------------------------------------------------------------------
565
566 grgpio0 : grgpio
567 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
568 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
569
570 gpioi.sig_en <= (OTHERS => '0');
571 gpioi.sig_in <= (OTHERS => '0');
572 gpioi.din <= (OTHERS => '0');
573 PROCESS (clk_25, rstn_25)
574 BEGIN -- PROCESS
575 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
576 IO8 <= '0';
577 IO9 <= '0';
578 IO10 <= '0';
579 IO11 <= '0';
580 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
581 CASE gpioo.dout(2 DOWNTO 0) IS
582 WHEN "011" =>
583 IO8 <= observation_reg(8);
584 IO9 <= observation_reg(9);
585 IO10 <= observation_reg(10);
586 IO11 <= observation_reg(11);
587 WHEN "001" =>
588 IO8 <= observation_reg(8 + 12);
589 IO9 <= observation_reg(9 + 12);
590 IO10 <= observation_reg(10 + 12);
591 IO11 <= observation_reg(11 + 12);
592 WHEN "010" =>
593 IO8 <= '0';
594 IO9 <= '0';
595 IO10 <= '0';
596 IO11 <= '0';
597 WHEN "000" =>
598 IO8 <= observation_vector_0(8);
599 IO9 <= observation_vector_0(9);
600 IO10 <= observation_vector_0(10);
601 IO11 <= observation_vector_0(11);
602 WHEN "100" =>
603 IO8 <= observation_vector_1(8);
604 IO9 <= observation_vector_1(9);
605 IO10 <= observation_vector_1(10);
606 IO11 <= observation_vector_1(11);
607 WHEN OTHERS => NULL;
608 END CASE;
609
610 END IF;
611 END PROCESS;
612 -----------------------------------------------------------------------------
613 --
614 -----------------------------------------------------------------------------
615 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
616 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
617 apbo_ext(I) <= apb_none;
618 END GENERATE apbo_ext_not_used;
619 END GENERATE all_apbo_ext;
620
621
622 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
623 ahbo_s_ext(I) <= ahbs_none;
624 END GENERATE all_ahbo_ext;
625
626 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
627 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
628 ahbo_m_ext(I) <= ahbm_none;
629 END GENERATE ahbo_m_ext_not_used;
630 END GENERATE all_ahbo_m_ext;
631
632 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -14,8 +14,8 VHDLSYNFILES= MINI_LFR_top.vhd
14 14 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR_PlaceAndRoute.sdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR_PlaceAndRoute.sdc
19 19 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
20 20 CLEAN=soft-clean
21 21
Show file before | Show file after | Hide comments
1 NO CONTENT: file renamed from designs/MINI-LFR_WFP_MS/run.do to designs/SOLO_LFR_MINI-LFR/run.do
Show file before | Show file after | Hide comments
1 NO CONTENT: file renamed from designs/MINI-LFR_WFP_MS/testbench.vhd to designs/SOLO_LFR_MINI-LFR/testbench.vhd
Show file before | Show file after | Hide comments
1 NO CONTENT: file renamed from designs/MINI-LFR_WFP_MS/wave.do to designs/SOLO_LFR_MINI-LFR/wave.do
Show file before | Show file after | Hide comments
@@ -13,6 +13,13 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16
17 constant LPP_LFR_BOARD_MINI_LFR : std_logic_vector(7 downto 0) := X"00"; -- with fpga A3PE3000
18 constant LPP_LFR_BOARD_LFR_EM : std_logic_vector(7 downto 0) := X"01"; -- with fpga A3PE3000
19 constant LPP_LFR_BOARD_LFR_EQM : std_logic_vector(7 downto 0) := X"02"; -- with fpga A3PE3000
20 constant LPP_LFR_BOARD_LFR_FM : std_logic_vector(7 downto 0) := X"03"; -- with fpga RTAX4000D
21 constant LPP_LFR_BOARD_DISCOSPACE : std_logic_vector(7 downto 0) := X"04"; -- with fpga A3PE3000
22
16 23 -----------------------------------------------------------------------------
17 24 -- TEMP
18 25 -----------------------------------------------------------------------------
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
General Comments 0
You need to be logged in to leave comments. Login now