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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more Cdetails.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Paul LEROY
20 20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26
27 27 LIBRARY staging_lpp;
28 28 --USE lpp.general_purpose.ALL;
29 29 use staging_lpp.PLE_general_purpose.all;
30 30 use staging_lpp.PLE_lpp_fft.all;
31 31
32 32 ENTITY BUTTERFLY_CTRL IS
33 33 PORT (
34 34 rstn : IN STD_LOGIC;
35 35 clk : IN STD_LOGIC;
36 36
37 37 sample_in_val : IN STD_LOGIC;
38 38 sample_out_val : OUT STD_LOGIC;
39 39
40 40 sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
41 41 sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
42 42 sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
43 sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
43 sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 );
44 44 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
45 45 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
46 46 );
47 47 END BUTTERFLY_CTRL;
48 48
49 49 ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS
50 50
51 TYPE fsm_BUTTERFLY_CTRL_T IS ( clearMAC,
52 waiting,
51 TYPE fsm_BUTTERFLY_CTRL_T IS ( waiting,
53 52 add1,
54 53 add2,
55 54 add3,
56 55 add4,
57 56 mult5,
58 57 mac6,
59 58 mac7,
60 59 mult8,
61 60 mac9,
62 61 last10,
63 last11);
62 last11,
63 last12);
64 64 SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T;
65 65
66 66 BEGIN
67 67
68 68 PROCESS (clk, rstn)
69 69
70 70 BEGIN -- PROCESS
71 71 IF rstn = '0' THEN -- asynchronous reset (active low)
72 72 --REG -------------------------------------------------------------------
73 73 sel_xyz <= (OTHERS => '0');
74 74 sel_out <= (OTHERS => '0');
75 75 --ALU -------------------------------------------------------------------
76 76 sel_op1 <= (OTHERS => '0');
77 77 sel_op2 <= (OTHERS => '0');
78 78 alu_ctrl <= ctrl_IDLE;
79 79 alu_comp <= (OTHERS => '0');
80 80 --OUT
81 81 sample_out_val <= '0';
82 82
83 BUTTERFLY_CTRL_STATE <= clearMAC;
83 BUTTERFLY_CTRL_STATE <= waiting;
84 84
85 85 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
86 86
87 87 CASE BUTTERFLY_CTRL_STATE IS
88 88
89 WHEN clearMAC =>
89 WHEN waiting =>
90 90 IF sample_in_val = '1' THEN
91 alu_ctrl <= ctrl_CLRMAC;
92 BUTTERFLY_CTRL_STATE <= waiting;
91 BUTTERFLY_CTRL_STATE <= add1;
93 92 END IF;
93 sel_op1 <= "00000"; -- Are
94 sel_op2 <= "00000"; -- Bre
95 alu_comp <= "00";
96 alu_ctrl <= ctrl_IDLE;
97 sel_out <= "0000";
98 sample_out_val <= '0';
94 99
95 WHEN waiting =>
100 WHEN add1 =>
101 sample_out_val <= '0';
96 102 sel_op1 <= "10000"; -- Are
97 103 sel_op2 <= "10000"; -- Bre
98 104 alu_comp <= "10";
99 BUTTERFLY_CTRL_STATE <= add1;
105 alu_ctrl <= ctrl_ADD;
106 sel_out <= "0000";
107 sample_out_val <= '0';
108 BUTTERFLY_CTRL_STATE <= add2;
100 109
101 WHEN add1 =>
110 WHEN add2 =>
102 111 sample_out_val <= '0';
103 112 sel_op1 <= "01000"; -- Aim
104 113 sel_op2 <= "01000"; -- Bim
105 114 alu_comp <= "10";
106 115 alu_ctrl <= ctrl_ADD;
107 sel_out <= "10000";
108 BUTTERFLY_CTRL_STATE <= add2;
116 sel_out <= "0000";
117 BUTTERFLY_CTRL_STATE <= add3;
109 118
110 WHEN add2 =>
119 WHEN add3 =>
111 120 sample_out_val <= '0';
112 121 sel_op1 <= "10000"; -- Are
113 122 sel_op2 <= "10000"; -- Bre
114 123 alu_comp <= "00";
115 124 alu_ctrl <= ctrl_ADD;
116 sel_out <= "10000";
117 BUTTERFLY_CTRL_STATE <= add3;
125 sel_out <= "0000";
126 BUTTERFLY_CTRL_STATE <= add4;
118 127
119 WHEN add3 =>
128 WHEN add4 =>
120 129 sample_out_val <= '0';
121 130 sel_op1 <= "01000"; -- Aim
122 131 sel_op2 <= "01000"; -- Bim
123 132 alu_comp <= "00";
124 133 alu_ctrl <= ctrl_ADD;
125 sel_out <= "10000";
134 sel_out <= "0000";
126 135 sel_xyz <= "100"; -- X
127 BUTTERFLY_CTRL_STATE <= add4;
136 BUTTERFLY_CTRL_STATE <= mult5;
128 137
129 WHEN add4 =>
138 WHEN mult5 =>
130 139 sample_out_val <= '0';
131 140 sel_op1 <= "00100"; -- X
132 141 sel_op2 <= "00100"; -- c
133 142 alu_comp <= "00";
134 alu_ctrl <= ctrl_ADD;
135 sel_out <= "00000";
136 sel_xyz <= "010";
137 BUTTERFLY_CTRL_STATE <= mult5;
143 alu_ctrl <= ctrl_MULT;
144 sel_out <= "0000";
145 sel_xyz <= "010"; -- Y
146 BUTTERFLY_CTRL_STATE <= mac6;
138 147
139 WHEN mult5 =>
148 WHEN mac6 =>
140 149 sample_out_val <= '0';
141 alu_ctrl <= ctrl_MULT;
142 150 sel_op1 <= "00010"; -- Y
143 151 sel_op2 <= "00100"; -- c
144 152 alu_comp <= "10";
145 sel_out <= "00100";
146 BUTTERFLY_CTRL_STATE <= mac6;
153 alu_ctrl <= ctrl_MAC;
154 sel_out <= "0001"; -- *** /!\ *** --
155 sample_out_val <= '1';
156 sel_xyz <= "000"; -- Y
157 BUTTERFLY_CTRL_STATE <= mac7;
147 158
148 WHEN mac6 =>
159 WHEN mac7 =>
149 160 sample_out_val <= '0';
150 161 sel_op1 <= "00010"; -- Y
151 162 sel_op2 <= "00001"; -- cms
152 163 alu_comp <= "00";
153 164 alu_ctrl <= ctrl_MAC;
154 sel_out <= "10000";
155 BUTTERFLY_CTRL_STATE <= mac7;
156
157 WHEN mac7 =>
158 sample_out_val <= '0';
159 sel_op1 <= "00100"; -- X
160 sel_op2 <= "00010"; -- cps
161 alu_ctrl <= ctrl_MAC;
162 alu_comp <= "00";
163 sel_out <= "10000";
165 sel_out <= "0010"; -- *** /!\ *** --
166 sample_out_val <= '1';
164 167 BUTTERFLY_CTRL_STATE <= mult8;
165 168
166 169 WHEN mult8 =>
167 170 sample_out_val <= '0';
171 sel_op1 <= "00100"; -- X
172 sel_op2 <= "00010"; -- cps
173 alu_comp <= "00";
168 174 alu_ctrl <= ctrl_MULT;
169 sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU
170 sel_op2 <= "00000"; -- 1
171 alu_comp <= "00";
172 sel_out <= "10000";
175 sel_out <= "0000";
176 sample_out_val <= '0';
173 177 BUTTERFLY_CTRL_STATE <= mac9;
174 178
175 179 WHEN mac9 =>
176 180 sample_out_val <= '0';
177 sel_op1 <= "10000";
178 sel_op2 <= "10000";
179 181 alu_ctrl <= ctrl_MAC;
182 sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU
183 sel_op2 <= "00000"; -- 1
180 184 alu_comp <= "10";
181 sel_out <= "10000";
185 sel_out <= "0000";
186 sample_out_val <= '0';
182 187 BUTTERFLY_CTRL_STATE <= last10;
183 188
184 189 WHEN last10 =>
185 190 sample_out_val <= '0';
186 191 sel_op1 <= "10000";
187 192 sel_op2 <= "10000";
193 alu_comp <= "10";
188 194 alu_ctrl <= ctrl_IDLE;
189 alu_comp <= "10";
190 sel_out <= "10000";
195 sel_out <= "0100"; -- *** /!\ *** --
196 sample_out_val <= '1';
191 197 BUTTERFLY_CTRL_STATE <= last11;
192 198
193 199 WHEN last11 =>
194 200 sample_out_val <= '0';
195 alu_ctrl <= ctrl_IDLE;
196 201 alu_comp <= "10";
197 sel_out <= "10000";
202 alu_ctrl <= ctrl_IDLE;
203 sel_out <= "0000";
204 sample_out_val <= '0';
205 BUTTERFLY_CTRL_STATE <= last12;
206
207 WHEN last12 =>
208 sample_out_val <= '0';
209 alu_comp <= "10";
210 alu_ctrl <= ctrl_IDLE;
211 sel_out <= "1000"; -- *** /!\ *** --
212 sample_out_val <= '1';
198 213 BUTTERFLY_CTRL_STATE <= waiting;
199 214
200 215 WHEN OTHERS =>
201 216 NULL;
202 217
203 218 END CASE;
204 219
205 220 END IF;
206 221
207 222 END PROCESS;
208 223
209 224 END ar_BUTTERFLY_CTRL; No newline at end of file
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@@ -1,115 +1,104
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more Cdetails.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Paul LEROY
20 20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26
27 27 LIBRARY staging_lpp;
28 28 USE staging_lpp.PLE_general_purpose.ALL;
29 29 use staging_lpp.PLE_lpp_fft.all;
30 30
31 31 ENTITY BUTTERFLY_TOP IS
32 32 GENERIC (
33 33 Sample_SZ : INTEGER := 16);
34 34 PORT (
35 35 rstn : IN STD_LOGIC;
36 36 clk : IN STD_LOGIC;
37 37
38 38 sample_in_val : IN STD_LOGIC;
39 39 sample_out_val : OUT STD_LOGIC;
40 40
41 41 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
42 42 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
43 43 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
44 44 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
45 45 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
46 46 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
47 47 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
48 48
49 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
50 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
51 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
52 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
53
54 49 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
55 sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0)
50 sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0)
56 51 );
57 52 END BUTTERFLY_TOP;
58 53
59 54 ARCHITECTURE ar_BUTTERFLY_TOP OF BUTTERFLY_TOP IS
60 55
61 56 SIGNAL sel_op1 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
62 57 SIGNAL sel_op2 : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
63 58 SIGNAL sel_xyz : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
64 59 SIGNAL alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 );
65 60 SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
66 61
67 62 BEGIN
68 63
69 alu_ctrl <= alu_ctrl_sig;
70 alu_comp <= alu_comp_sig;
71
72 64 BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW
73 65 GENERIC MAP (
74 66 Sample_SZ => 16)
75 67 PORT MAP (
76 68 rstn => rstn,
77 69 clk => clk,
78 70
79 71 Are => Are,
80 72 Aim => Aim,
81 73 Bre => Bre,
82 74 Bim => Bim,
83 75 c_in => c_in,
84 76 cps_in => cps_in,
85 77 cms_in => cms_in,
86 78
87 op1 => op1,
88 op2 => op2,
89
90 79 out_alu => butterfly_out,
91 80
92 81 sel_op1 => sel_op1,
93 82 sel_op2 => sel_op2,
94 83 sel_xyz => sel_xyz,
95 84 alu_ctrl => alu_ctrl_sig,
96 85 alu_comp => alu_comp_sig
97 86 );
98 87
99 88 BUTTERFLY_CTRL_1 : BUTTERFLY_CTRL
100 89 PORT MAP(
101 90 rstn => rstn,
102 91 clk => clk,
103 92
104 93 sample_in_val => sample_in_val,
105 94 sample_out_val => sample_out_val,
106 95
107 96 sel_op1 => sel_op1,
108 97 sel_op2 => sel_op2,
109 98 sel_xyz => sel_xyz,
110 99 sel_out => sel_out,
111 100 alu_ctrl => alu_ctrl_sig,
112 101 alu_comp => alu_comp_sig
113 102 );
114 103
115 104 END ar_BUTTERFLY_TOP; No newline at end of file
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@@ -1,129 +1,133
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more Cdetails.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Paul LEROY
20 20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.numeric_std.ALL;
25 25 USE IEEE.std_logic_1164.ALL;
26 26 LIBRARY staging_lpp;
27 27 USE staging_lpp.PLE_general_purpose.ALL;
28 28
29 29 ENTITY BUTTERFLY_DATAFLOW IS
30 30 GENERIC (
31 31 Sample_SZ : INTEGER := 16
32 32 );
33 33 PORT (
34 34 rstn : IN STD_LOGIC;
35 35 clk : IN STD_LOGIC;
36 36
37 37 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
38 38 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
39 39 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
40 40 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
41 41 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
42 42 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
43 43 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
44 44
45 45 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
46 46 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
47 47
48 48 out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
49 49
50 50 sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
51 51 sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
52 52 sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
53 53 alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
54 54 alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )
55 55 );
56 56 END BUTTERFLY_DATAFLOW;
57 57
58 58 ARCHITECTURE ar_BUTTERFLY_DATAFLOW OF BUTTERFLY_DATAFLOW IS
59 59
60 60 SIGNAL X : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
61 61 SIGNAL Y : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
62 62 SIGNAL Z : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
63 63
64 64 SIGNAL ALU_OP1 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
65 65 SIGNAL ALU_OP2 : STD_LOGIC_VECTOR( Sample_SZ-1 DOWNTO 0 );
66 66
67 67 SIGNAL OUT_ALU_SIG : STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
68 68
69 69 BEGIN
70 70
71 71 out_alu <= OUT_ALU_SIG;
72 72
73 73 PROCESS (clk, rstn)
74 74
75 75 BEGIN -- PROCESS
76 76 IF rstn = '0' THEN -- asynchronous reset (active low)
77 77 X <= (OTHERS => '0');
78 78 Y <= (OTHERS => '0');
79 79 Z <= (OTHERS => '0');
80 80
81 81 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
82 82
83 83 if sel_xyz = "100" THEN
84 84 X <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
85 85 elsif sel_xyz = "010" THEN
86 86 Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
87 87 elsif sel_xyz = "001" THEN
88 88 Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
89 else
90 X <= X;
91 Y <= Y;
92 Z <= Z;
89 93 end if;
90 94
91 95 END IF;
92 96
93 97 END PROCESS;
94 98
95 99 op1 <= ALU_OP1;
96 100 op2 <= ALU_OP2;
97 101
98 102 ALU_OP1 <= Are WHEN sel_op1 = "10000" ELSE
99 103 Aim WHEN sel_op1 = "01000" ELSE
100 104 X WHEN sel_op1 = "00100" ELSE
101 105 Y WHEN sel_op1 = "00010" ELSE
102 106 Z WHEN sel_op1 = "00001" ELSE
103 107 STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)) WHEN sel_op1 = "00000" ELSE
104 108 (OTHERS => '0');
105 109
106 110 ALU_OP2 <= Bre WHEN sel_op2 = "10000" ELSE
107 111 Bim WHEN sel_op2 = "01000" ELSE
108 112 c_in WHEN sel_op2 = "00100" ELSE
109 113 cps_in WHEN sel_op2 = "00010" ELSE
110 114 cms_in WHEN sel_op2 = "00001" ELSE
111 115 std_logic_vector(TO_SIGNED(1,Sample_SZ)) WHEN sel_op2 = "00000" ELSE
112 116 (OTHERS => '0');
113 117
114 118 ALU_1: ALU
115 119 GENERIC MAP (
116 120 Arith_en => 1,
117 121 Input_SZ_1 => Sample_SZ,
118 122 Input_SZ_2 => Sample_SZ,
119 123 COMP_EN => 0) -- comp is enable when COMP_EN is 0
120 124 PORT MAP (
121 125 clk => clk,
122 126 reset => rstn,
123 127 ctrl => alu_ctrl,
124 128 comp => alu_comp,
125 129 OP1 => ALU_OP1,
126 130 OP2 => ALU_OP2,
127 131 RES => OUT_ALU_SIG);
128 132
129 133 END ar_BUTTERFLY_DATAFLOW; No newline at end of file
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@@ -1,102 +1,120
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Paul Leroy
20 20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26
27 LIBRARY staging_LPP;
28 USE staging_LPP.PLE_iir_filter.ALL;
29
27 30 PACKAGE PLE_lpp_fft IS
28 31
29 32 COMPONENT BUTTERFLY_DATAFLOW
30 33 GENERIC (
31 34 Sample_SZ : INTEGER := 16);
32 35 PORT (
33 36 rstn : IN STD_LOGIC;
34 37 clk : IN STD_LOGIC;
35 38
36 39 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
37 40 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
38 41 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
39 42 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
40 43 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
41 44 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
42 45 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
43 46
44 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
45 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
46
47 47 out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
48 48
49 49 sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
50 50 sel_op2 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
51 51 sel_xyz : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
52 52 alu_ctrl : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
53 53 alu_comp : IN STD_LOGIC_VECTOR( 1 DOWNTO 0 )
54 54 );
55 55 END COMPONENT;
56 56
57 57 COMPONENT BUTTERFLY_CTRL
58 58 PORT (
59 59 rstn : IN STD_LOGIC;
60 60 clk : IN STD_LOGIC;
61 61
62 62 sample_in_val : IN STD_LOGIC;
63 63 sample_out_val : OUT STD_LOGIC;
64 64
65 65 sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
66 66 sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
67 67 sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
68 sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
68 sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 );
69 69 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
70 70 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
71 71 );
72 72 END COMPONENT;
73 73
74 74 COMPONENT BUTTERFLY_TOP
75 75 GENERIC (
76 76 Sample_SZ : INTEGER := 16);
77 77 PORT (
78 78 rstn : IN STD_LOGIC;
79 79 clk : IN STD_LOGIC;
80 80
81 81 sample_in_val : IN STD_LOGIC;
82 82 sample_out_val : OUT STD_LOGIC;
83 83
84 84 Are : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
85 85 Aim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
86 86 Bre : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
87 87 Bim : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
88 88 c_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
89 89 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
90 90 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
91 91
92 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
93 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
94 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
95 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
92 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
93 sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0)
94 );
95 END COMPONENT;
96 96
97 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
98 sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0)
97 COMPONENT input_buffers_and_coefficients
98 GENERIC(
99 tech : INTEGER := 0;
100 Input_SZ_1 : INTEGER := 16;
101 Mem_use : INTEGER := use_RAM -- 1 use RAM
102 );
103 PORT(
104 rstn : IN STD_LOGIC;
105 clk : IN STD_LOGIC;
106 --*******************
107 -- PLE **************
108 WD_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
109 RD_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
110 WEN_in : IN STD_LOGIC;
111 REN_in : IN STD_LOGIC;
112 RADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
113 WADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
114 start : IN STD_LOGIC
115 --*******************
116 --*******************
99 117 );
100 118 END COMPONENT;
101 119
102 120 END; No newline at end of file
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@@ -1,112 +1,104
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Paul Leroy
20 20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25
26 26 library staging_lpp;
27 27 use staging_lpp.PLE_lpp_fft.all;
28 28
29 29 entity TestBench_BUTTERFLY_TOP is
30 30
31 31 end TestBench_BUTTERFLY_TOP;
32 32
33 33 architecture TestBench_BUTTERFLY_TOP of TestBench_BUTTERFLY_TOP is
34 34
35 35 constant Sample_SZ : integer := 16;
36 36
37 37 signal clk : std_logic:='0';
38 38 signal rstn : std_logic:='0';
39 39
40 40 signal Are : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
41 41 signal Aim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
42 42 signal Bre : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
43 43 signal Bim : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
44 44 signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
45 45 signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
46 46 signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
47 47
48 signal op1 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
49 signal op2 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
50 signal alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 );
51 signal alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
52
53 48 signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 );
54 49
55 signal sel_out : std_logic_vector( 4 downto 0 );
50 signal sel_out : std_logic_vector( 3 downto 0 );
56 51
57 52 signal sample_in_val : std_logic := '0';
58 53 signal sample_out_val : std_logic;
59 54
60 55 begin
61 56
62 57 BUTTERFLY_TOP1 : BUTTERFLY_TOP
63 58 generic map(
64 59 Sample_SZ => Sample_SZ
65 60 )
66 61 port map(
67 62 rstn => rstn,
68 63 clk => clk,
69 64
70 65 sample_in_val => sample_in_val,
71 66 sample_out_val => sample_out_val,
72 67
73 68 Are => Are,
74 69 Aim => Aim,
75 70 Bre => Bre,
76 71 Bim => Bim,
77 72 c_in => c,
78 73 cps_in => cps,
79 74 cms_in => cms,
80 75
81 op1 => op1,
82 op2 => op2,
83 alu_ctrl => alu_ctrl_sig,
84 alu_comp => alu_comp_sig,
85
86 76 butterfly_out => Resultat,
87 77 sel_out => sel_out
88 78 );
89 79
90 80 clk <= not clk after 25 ns;
91 81
92 82 process
93 83 begin
94 84
85 if rstn = '0' then
95 86 wait for 40 ns;
96 87 rstn <= '1';
88 end if;
97 89
98 90 wait for 11 ns;
99 91 Are <= std_logic_vector(TO_SIGNED(100 ,Sample_SZ));
100 92 Aim <= std_logic_vector(TO_SIGNED(110 ,Sample_SZ));
101 93 Bre <= std_logic_vector(TO_SIGNED(-40 ,Sample_SZ));
102 94 Bim <= std_logic_vector(TO_SIGNED(10 ,Sample_SZ));
103 95 c <= std_logic_vector(TO_SIGNED(121 ,Sample_SZ));
104 96 cps <= std_logic_vector(TO_SIGNED(160 ,Sample_SZ));
105 97 cms <= std_logic_vector(TO_SIGNED(82 ,Sample_SZ));
106 98
107 99 wait for 50 ns;
108 100 sample_in_val <= '1';
109 101
110 102 end process;
111 103
112 104 end TestBench_BUTTERFLY_TOP;
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@@ -1,24 +1,36
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench_butterfly_top/are
4 add wave -noupdate -divider TOTO
5 add wave -noupdate /testbench_butterfly_top/aim
6 add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op2
7 add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op1
3 add wave -noupdate /testbench_butterfly_top/clk
4 add wave -noupdate /testbench_butterfly_top/rstn
5 add wave -noupdate -radix decimal /testbench_butterfly_top/are
6 add wave -noupdate -radix decimal /testbench_butterfly_top/aim
7 add wave -noupdate -radix decimal /testbench_butterfly_top/bre
8 add wave -noupdate -radix decimal /testbench_butterfly_top/bim
9 add wave -noupdate -radix decimal /testbench_butterfly_top/c
10 add wave -noupdate -radix decimal /testbench_butterfly_top/cps
11 add wave -noupdate -radix decimal /testbench_butterfly_top/cms
12 add wave -noupdate -radix decimal /testbench_butterfly_top/op1
13 add wave -noupdate -radix decimal /testbench_butterfly_top/op2
14 add wave -noupdate -radix decimal /testbench_butterfly_top/resultat
15 add wave -noupdate /testbench_butterfly_top/alu_ctrl_sig
16 add wave -noupdate /testbench_butterfly_top/alu_comp_sig
17 add wave -noupdate /testbench_butterfly_top/sel_out
18 add wave -noupdate /testbench_butterfly_top/sample_in_val
19 add wave -noupdate /testbench_butterfly_top/sample_out_val
8 20 TreeUpdate [SetDefaultTree]
9 WaveRestoreCursors {{Cursor 1} {0 ps} 0}
10 configure wave -namecolwidth 226
21 WaveRestoreCursors {{Cursor 1} {149541 ps} 0}
22 configure wave -namecolwidth 150
11 23 configure wave -valuecolwidth 100
12 24 configure wave -justifyvalue left
13 25 configure wave -signalnamewidth 0
14 26 configure wave -snapdistance 10
15 27 configure wave -datasetprefix 0
16 28 configure wave -rowmargin 4
17 29 configure wave -childrowmargin 2
18 30 configure wave -gridoffset 0
19 31 configure wave -gridperiod 1000
20 32 configure wave -griddelta 40
21 33 configure wave -timeline 0
22 34 configure wave -timelineunits ns
23 35 update
24 WaveRestoreZoom {0 ps} {1092 ps}
36 WaveRestoreZoom {0 ps} {1050 ns}
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@@ -1,459 +1,467
1 1 --twiddle_factors_128.vhd
2 2
3 library IEEE;
4 use IEEE.numeric_std.all;
5 use IEEE.std_logic_1164.all;
6
7 package PLE_twiddle_factors_128 is
8
3 9 constant Coef_SZ : integer := 16;
4 10 constant NB_Coeffs : integer := 128;
5 11
6 12 --============================================================
7 13 -- create each initial values for each coefs ============
8 14 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
9 15 --============================================================
10 16
11 17 constant c_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
12 18 constant c_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
13 19 constant c_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
14 20 constant c_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
15 21 constant c_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
16 22 constant c_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
17 23 constant c_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
18 24 constant c_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
19 25 constant c_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
20 26 constant c_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
21 27 constant c_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
22 28 constant c_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
23 29 constant c_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
24 30 constant c_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
25 31 constant c_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
26 32 constant c_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
27 33 constant c_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
28 34 constant c_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
29 35 constant c_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
30 36 constant c_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
31 37 constant c_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
32 38 constant c_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
33 39 constant c_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
34 40 constant c_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
35 41 constant c_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
36 42 constant c_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
37 43 constant c_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
38 44 constant c_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
39 45 constant c_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
40 46 constant c_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
41 47 constant c_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
42 48 constant c_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
43 49 constant c_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
44 50 constant c_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
45 51 constant c_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
46 52 constant c_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
47 53 constant c_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
48 54 constant c_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
49 55 constant c_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
50 56 constant c_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
51 57 constant c_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
52 58 constant c_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
53 59 constant c_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
54 60 constant c_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
55 61 constant c_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
56 62 constant c_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
57 63 constant c_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
58 64 constant c_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
59 65 constant c_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
60 66 constant c_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
61 67 constant c_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
62 68 constant c_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
63 69 constant c_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
64 70 constant c_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
65 71 constant c_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
66 72 constant c_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
67 73 constant c_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
68 74 constant c_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
69 75 constant c_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
70 76 constant c_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
71 77 constant c_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
72 78 constant c_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
73 79 constant c_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
74 80 constant c_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
75 81 constant c_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
76 82 constant c_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
77 83 constant c_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
78 84 constant c_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
79 85 constant c_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
80 86 constant c_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
81 87 constant c_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
82 88 constant c_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
83 89 constant c_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
84 90 constant c_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
85 91 constant c_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
86 92 constant c_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
87 93 constant c_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
88 94 constant c_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
89 95 constant c_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
90 96 constant c_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
91 97 constant c_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
92 98 constant c_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
93 99 constant c_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
94 100 constant c_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
95 101 constant c_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
96 102 constant c_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
97 103 constant c_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
98 104 constant c_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
99 105 constant c_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
100 106 constant c_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
101 107 constant c_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
102 108 constant c_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
103 109 constant c_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
104 110 constant c_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
105 111 constant c_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
106 112 constant c_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
107 113 constant c_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
108 114 constant c_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
109 115 constant c_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
110 116 constant c_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
111 117 constant c_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
112 118 constant c_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
113 119 constant c_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
114 120 constant c_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
115 121 constant c_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
116 122 constant c_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
117 123 constant c_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
118 124 constant c_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
119 125 constant c_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
120 126 constant c_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
121 127 constant c_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
122 128 constant c_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
123 129 constant c_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
124 130 constant c_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
125 131 constant c_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
126 132 constant c_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
127 133 constant c_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
128 134 constant c_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
129 135 constant c_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
130 136 constant c_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
131 137 constant c_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
132 138 constant c_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
133 139 constant c_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
134 140 constant c_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
135 141 constant c_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
136 142 constant c_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
137 143 constant c_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
138 144 constant c_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(121,Coef_SZ));
139 145
140 146 --************************************************--
141 147
142 148 constant cps_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
143 149 constant cps_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
144 150 constant cps_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
145 151 constant cps_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
146 152 constant cps_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
147 153 constant cps_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
148 154 constant cps_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
149 155 constant cps_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
150 156 constant cps_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
151 157 constant cps_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
152 158 constant cps_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
153 159 constant cps_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
154 160 constant cps_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
155 161 constant cps_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
156 162 constant cps_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
157 163 constant cps_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
158 164 constant cps_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
159 165 constant cps_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
160 166 constant cps_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
161 167 constant cps_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
162 168 constant cps_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
163 169 constant cps_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
164 170 constant cps_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
165 171 constant cps_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
166 172 constant cps_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
167 173 constant cps_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
168 174 constant cps_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
169 175 constant cps_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
170 176 constant cps_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
171 177 constant cps_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
172 178 constant cps_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
173 179 constant cps_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
174 180 constant cps_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
175 181 constant cps_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
176 182 constant cps_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
177 183 constant cps_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
178 184 constant cps_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
179 185 constant cps_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
180 186 constant cps_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
181 187 constant cps_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
182 188 constant cps_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
183 189 constant cps_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
184 190 constant cps_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
185 191 constant cps_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
186 192 constant cps_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
187 193 constant cps_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
188 194 constant cps_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
189 195 constant cps_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
190 196 constant cps_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
191 197 constant cps_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
192 198 constant cps_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
193 199 constant cps_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
194 200 constant cps_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
195 201 constant cps_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
196 202 constant cps_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
197 203 constant cps_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
198 204 constant cps_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
199 205 constant cps_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
200 206 constant cps_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
201 207 constant cps_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
202 208 constant cps_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
203 209 constant cps_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
204 210 constant cps_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
205 211 constant cps_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
206 212 constant cps_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
207 213 constant cps_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
208 214 constant cps_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
209 215 constant cps_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
210 216 constant cps_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
211 217 constant cps_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
212 218 constant cps_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
213 219 constant cps_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
214 220 constant cps_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
215 221 constant cps_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
216 222 constant cps_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
217 223 constant cps_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
218 224 constant cps_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
219 225 constant cps_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
220 226 constant cps_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
221 227 constant cps_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
222 228 constant cps_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
223 229 constant cps_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
224 230 constant cps_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
225 231 constant cps_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
226 232 constant cps_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
227 233 constant cps_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
228 234 constant cps_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
229 235 constant cps_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
230 236 constant cps_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
231 237 constant cps_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
232 238 constant cps_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
233 239 constant cps_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
234 240 constant cps_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
235 241 constant cps_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
236 242 constant cps_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
237 243 constant cps_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
238 244 constant cps_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
239 245 constant cps_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
240 246 constant cps_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
241 247 constant cps_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
242 248 constant cps_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
243 249 constant cps_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
244 250 constant cps_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
245 251 constant cps_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
246 252 constant cps_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
247 253 constant cps_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
248 254 constant cps_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
249 255 constant cps_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
250 256 constant cps_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
251 257 constant cps_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
252 258 constant cps_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
253 259 constant cps_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
254 260 constant cps_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
255 261 constant cps_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
256 262 constant cps_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
257 263 constant cps_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
258 264 constant cps_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
259 265 constant cps_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
260 266 constant cps_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
261 267 constant cps_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
262 268 constant cps_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
263 269 constant cps_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
264 270 constant cps_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
265 271 constant cps_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
266 272 constant cps_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
267 273 constant cps_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
268 274 constant cps_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
269 275 constant cps_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(160,Coef_SZ));
270 276
271 277 --************************************************--
272 278
273 279 constant cms_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
274 280 constant cms_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
275 281 constant cms_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
276 282 constant cms_3 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
277 283 constant cms_4 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
278 284 constant cms_5 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
279 285 constant cms_6 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
280 286 constant cms_7 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
281 287 constant cms_8 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
282 288 constant cms_9 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
283 289 constant cms_10 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
284 290 constant cms_11 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
285 291 constant cms_12 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
286 292 constant cms_13 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
287 293 constant cms_14 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
288 294 constant cms_15 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
289 295 constant cms_16 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
290 296 constant cms_17 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
291 297 constant cms_18 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
292 298 constant cms_19 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
293 299 constant cms_20 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
294 300 constant cms_21 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
295 301 constant cms_22 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
296 302 constant cms_23 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
297 303 constant cms_24 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
298 304 constant cms_25 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
299 305 constant cms_26 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
300 306 constant cms_27 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
301 307 constant cms_28 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
302 308 constant cms_29 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
303 309 constant cms_30 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
304 310 constant cms_31 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
305 311 constant cms_32 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
306 312 constant cms_33 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
307 313 constant cms_34 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
308 314 constant cms_35 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
309 315 constant cms_36 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
310 316 constant cms_37 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
311 317 constant cms_38 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
312 318 constant cms_39 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
313 319 constant cms_40 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
314 320 constant cms_41 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
315 321 constant cms_42 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
316 322 constant cms_43 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
317 323 constant cms_44 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
318 324 constant cms_45 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
319 325 constant cms_46 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
320 326 constant cms_47 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
321 327 constant cms_48 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
322 328 constant cms_49 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
323 329 constant cms_50 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
324 330 constant cms_51 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
325 331 constant cms_52 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
326 332 constant cms_53 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
327 333 constant cms_54 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
328 334 constant cms_55 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
329 335 constant cms_56 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
330 336 constant cms_57 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
331 337 constant cms_58 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
332 338 constant cms_59 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
333 339 constant cms_60 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
334 340 constant cms_61 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
335 341 constant cms_62 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
336 342 constant cms_63 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
337 343 constant cms_64 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
338 344 constant cms_65 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
339 345 constant cms_66 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
340 346 constant cms_67 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
341 347 constant cms_68 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
342 348 constant cms_69 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
343 349 constant cms_70 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
344 350 constant cms_71 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
345 351 constant cms_72 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
346 352 constant cms_73 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
347 353 constant cms_74 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
348 354 constant cms_75 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
349 355 constant cms_76 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
350 356 constant cms_77 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
351 357 constant cms_78 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
352 358 constant cms_79 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
353 359 constant cms_80 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
354 360 constant cms_81 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
355 361 constant cms_82 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
356 362 constant cms_83 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
357 363 constant cms_84 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
358 364 constant cms_85 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
359 365 constant cms_86 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
360 366 constant cms_87 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
361 367 constant cms_88 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
362 368 constant cms_89 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
363 369 constant cms_90 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
364 370 constant cms_91 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
365 371 constant cms_92 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
366 372 constant cms_93 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
367 373 constant cms_94 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
368 374 constant cms_95 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
369 375 constant cms_96 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
370 376 constant cms_97 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
371 377 constant cms_98 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
372 378 constant cms_99 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
373 379 constant cms_100 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
374 380 constant cms_101 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
375 381 constant cms_102 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
376 382 constant cms_103 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
377 383 constant cms_104 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
378 384 constant cms_105 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
379 385 constant cms_106 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
380 386 constant cms_107 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
381 387 constant cms_108 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
382 388 constant cms_109 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
383 389 constant cms_110 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
384 390 constant cms_111 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
385 391 constant cms_112 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
386 392 constant cms_113 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
387 393 constant cms_114 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
388 394 constant cms_115 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
389 395 constant cms_116 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
390 396 constant cms_117 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
391 397 constant cms_118 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
392 398 constant cms_119 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
393 399 constant cms_120 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
394 400 constant cms_121 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
395 401 constant cms_122 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
396 402 constant cms_123 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
397 403 constant cms_124 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
398 404 constant cms_125 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
399 405 constant cms_126 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
400 406 constant cms_127 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(82,Coef_SZ));
401 407
402 408 --************************************************--
403 409
404 410 constant twiddleFactors_c : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) :=
405 411 (
406 412 c_0 & c_1 & c_2 & c_3 & c_4 & c_5 & c_6 & c_7 &
407 413 c_8 & c_9 & c_10 & c_11 & c_12 & c_13 & c_14 & c_15 &
408 414 c_16 & c_17 & c_18 & c_19 & c_20 & c_21 & c_22 & c_23 &
409 415 c_24 & c_25 & c_26 & c_27 & c_28 & c_29 & c_30 & c_31 &
410 416 c_32 & c_33 & c_34 & c_35 & c_36 & c_37 & c_38 & c_39 &
411 417 c_40 & c_41 & c_42 & c_43 & c_44 & c_45 & c_46 & c_47 &
412 418 c_48 & c_49 & c_50 & c_51 & c_52 & c_53 & c_54 & c_55 &
413 419 c_56 & c_57 & c_58 & c_59 & c_60 & c_61 & c_62 & c_63 &
414 420 c_64 & c_65 & c_66 & c_67 & c_68 & c_69 & c_70 & c_71 &
415 421 c_72 & c_73 & c_74 & c_75 & c_76 & c_77 & c_78 & c_79 &
416 422 c_80 & c_81 & c_82 & c_83 & c_84 & c_85 & c_86 & c_87 &
417 423 c_88 & c_89 & c_90 & c_91 & c_92 & c_93 & c_94 & c_95 &
418 424 c_96 & c_97 & c_98 & c_99 & c_100 & c_101 & c_102 & c_103 &
419 425 c_104 & c_105 & c_106 & c_107 & c_108 & c_109 & c_110 & c_111 &
420 426 c_112 & c_113 & c_114 & c_115 & c_116 & c_117 & c_118 & c_119 &
421 427 c_120 & c_121 & c_122 & c_123 & c_124 & c_125 & c_126 & c_127 );
422 428
423 429 constant twiddleFactors_cps : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) :=
424 430 (
425 431 cps_0 & cps_1 & cps_2 & cps_3 & cps_4 & cps_5 & cps_6 & cps_7 &
426 432 cps_8 & cps_9 & cps_10 & cps_11 & cps_12 & cps_13 & cps_14 & cps_15 &
427 433 cps_16 & cps_17 & cps_18 & cps_19 & cps_20 & cps_21 & cps_22 & cps_23 &
428 434 cps_24 & cps_25 & cps_26 & cps_27 & cps_28 & cps_29 & cps_30 & cps_31 &
429 435 cps_32 & cps_33 & cps_34 & cps_35 & cps_36 & cps_37 & cps_38 & cps_39 &
430 436 cps_40 & cps_41 & cps_42 & cps_43 & cps_44 & cps_45 & cps_46 & cps_47 &
431 437 cps_48 & cps_49 & cps_50 & cps_51 & cps_52 & cps_53 & cps_54 & cps_55 &
432 438 cps_56 & cps_57 & cps_58 & cps_59 & cps_60 & cps_61 & cps_62 & cps_63 &
433 439 cps_64 & cps_65 & cps_66 & cps_67 & cps_68 & cps_69 & cps_70 & cps_71 &
434 440 cps_72 & cps_73 & cps_74 & cps_75 & cps_76 & cps_77 & cps_78 & cps_79 &
435 441 cps_80 & cps_81 & cps_82 & cps_83 & cps_84 & cps_85 & cps_86 & cps_87 &
436 442 cps_88 & cps_89 & cps_90 & cps_91 & cps_92 & cps_93 & cps_94 & cps_95 &
437 443 cps_96 & cps_97 & cps_98 & cps_99 & cps_100 & cps_101 & cps_102 & cps_103 &
438 444 cps_104 & cps_105 & cps_106 & cps_107 & cps_108 & cps_109 & cps_110 & cps_111 &
439 445 cps_112 & cps_113 & cps_114 & cps_115 & cps_116 & cps_117 & cps_118 & cps_119 &
440 446 cps_120 & cps_121 & cps_122 & cps_123 & cps_124 & cps_125 & cps_126 & cps_127 );
441 447
442 448 constant twiddleFactors_cms : std_logic_vector( (NB_Coeffs * Coef_SZ)-1 downto 0) :=
443 449 (
444 450 cms_0 & cms_1 & cms_2 & cms_3 & cms_4 & cms_5 & cms_6 & cms_7 &
445 451 cms_8 & cms_9 & cms_10 & cms_11 & cms_12 & cms_13 & cms_14 & cms_15 &
446 452 cms_16 & cms_17 & cms_18 & cms_19 & cms_20 & cms_21 & cms_22 & cms_23 &
447 453 cms_24 & cms_25 & cms_26 & cms_27 & cms_28 & cms_29 & cms_30 & cms_31 &
448 454 cms_32 & cms_33 & cms_34 & cms_35 & cms_36 & cms_37 & cms_38 & cms_39 &
449 455 cms_40 & cms_41 & cms_42 & cms_43 & cms_44 & cms_45 & cms_46 & cms_47 &
450 456 cms_48 & cms_49 & cms_50 & cms_51 & cms_52 & cms_53 & cms_54 & cms_55 &
451 457 cms_56 & cms_57 & cms_58 & cms_59 & cms_60 & cms_61 & cms_62 & cms_63 &
452 458 cms_64 & cms_65 & cms_66 & cms_67 & cms_68 & cms_69 & cms_70 & cms_71 &
453 459 cms_72 & cms_73 & cms_74 & cms_75 & cms_76 & cms_77 & cms_78 & cms_79 &
454 460 cms_80 & cms_81 & cms_82 & cms_83 & cms_84 & cms_85 & cms_86 & cms_87 &
455 461 cms_88 & cms_89 & cms_90 & cms_91 & cms_92 & cms_93 & cms_94 & cms_95 &
456 462 cms_96 & cms_97 & cms_98 & cms_99 & cms_100 & cms_101 & cms_102 & cms_103 &
457 463 cms_104 & cms_105 & cms_106 & cms_107 & cms_108 & cms_109 & cms_110 & cms_111 &
458 464 cms_112 & cms_113 & cms_114 & cms_115 & cms_116 & cms_117 & cms_118 & cms_119 &
459 465 cms_120 & cms_121 & cms_122 & cms_123 & cms_124 & cms_125 & cms_126 & cms_127 );
466 end;
467
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@@ -1,301 +1,385
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY staging_lpp;
26 26 USE staging_lpp.PLE_general_purpose.ALL;
27 27 --TODO
28 28 --terminer le testbensh puis changer le resize dans les instanciations
29 29 --par un resize sur un vecteur en combi
30 30
31 31
32 32 ENTITY MAC IS
33 33 GENERIC(
34 34 Input_SZ_A : INTEGER := 8;
35 35 Input_SZ_B : INTEGER := 8;
36 36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37 37
38 38 );
39 39 PORT(
40 40 clk : IN STD_LOGIC;
41 41 reset : IN STD_LOGIC;
42 42 clr_MAC : IN STD_LOGIC;
43 43 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
44 44 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
45 45 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
46 46 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
47 47 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
48 48 );
49 49 END MAC;
50 50
51 51
52 52
53 53
54 54 ARCHITECTURE ar_MAC OF MAC IS
55 55
56 56 SIGNAL add, mult : STD_LOGIC;
57 57 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58 58
59 59 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60 60 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61 61 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
62 62
63 63 SIGNAL MACMUXsel : STD_LOGIC;
64 64 SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65 65 SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
66 66
67 67 SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
68 68 SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
69 69
70 70 SIGNAL MACMUX2sel : STD_LOGIC;
71 71
72 72 SIGNAL add_D : STD_LOGIC;
73 SIGNAL add_D_D : STD_LOGIC;
74 SIGNAL mult_D : STD_LOGIC;
73 75 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
74 76 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
77
78 -- SIGNAL OP1_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
79 -- SIGNAL OP2_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
80
75 81 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
76 82 SIGNAL MACMUXsel_D : STD_LOGIC;
83 SIGNAL MACMUXsel_D_D : STD_LOGIC;
77 84 SIGNAL MACMUX2sel_D : STD_LOGIC;
78 85 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
86 SIGNAL MACMUX2sel_D_D_D : STD_LOGIC;
79 87 SIGNAL clr_MAC_D : STD_LOGIC;
80 88 SIGNAL clr_MAC_D_D : STD_LOGIC;
89 SIGNAL clr_MAC_D_D_D : STD_LOGIC;
81 90 SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL MAC_MUL_ADD_2C_D_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
82 92
83 93 SIGNAL load_mult_result : STD_LOGIC;
84 94 SIGNAL load_mult_result_D : STD_LOGIC;
95 SIGNAL load_mult_result_D_D : STD_LOGIC;
85 96
86 97 BEGIN
87 98
88 99
89 100
90 101
91 102 --==============================================================
92 103 --=============M A C C O N T R O L E R=========================
93 104 --==============================================================
94 105 MAC_CONTROLER1 : MAC_CONTROLER
95 106 PORT MAP(
96 107 ctrl => MAC_MUL_ADD,
97 108 MULT => mult,
98 109 ADD => add,
99 110 LOAD_ADDER => load_mult_result,
100 111 MACMUX_sel => MACMUXsel,
101 112 MACMUX2_sel => MACMUX2sel
102 113
103 114 );
104 115 --==============================================================
105 116
106 117
107
108
109 --==============================================================
110 --=============M U L T I P L I E R==============================
111 --==============================================================
112 Multiplieri_nst : Multiplier
113 GENERIC MAP(
114 Input_SZ_A => Input_SZ_A,
115 Input_SZ_B => Input_SZ_B
116 )
117 PORT MAP(
118 clk => clk,
119 reset => reset,
120 mult => mult,
121 OP1 => OP1_2C,
122 OP2 => OP2_2C,
123 RES => MULTout
124 );
125 --==============================================================
126
127 PROCESS (clk, reset)
128 BEGIN -- PROCESS
129 IF reset = '0' THEN -- asynchronous reset (active low)
130 load_mult_result_D <= '0';
131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
132 load_mult_result_D <= load_mult_result;
133 END IF;
134 END PROCESS;
135
136 --==============================================================
137 --======================A D D E R ==============================
138 --==============================================================
139 adder_inst : Adder
140 GENERIC MAP(
141 Input_SZ_A => Input_SZ_A+Input_SZ_B,
142 Input_SZ_B => Input_SZ_A+Input_SZ_B
143 )
144 PORT MAP(
145 clk => clk,
146 reset => reset,
147 clr => clr_MAC_D,
148 load => load_mult_result_D,
149 add => add_D,
150 OP1 => ADDERinA,
151 OP2 => ADDERinB,
152 RES => ADDERout
153 );
154
155 118 --==============================================================
156 119 --===================TWO COMPLEMENTERS==========================
157 120 --==============================================================
158 121 gen_comp : IF COMP_EN = 0 GENERATE
159 122 TWO_COMPLEMENTER1 : TwoComplementer
160 123 GENERIC MAP(
161 124 Input_SZ => Input_SZ_A
162 125 )
163 126 PORT MAP(
164 127 clk => clk,
165 128 reset => reset,
166 129 clr => clr_MAC,
167 130 TwoComp => Comp_2C(0),
168 131 OP => OP1,
169 132 RES => OP1_2C
170 133 );
171 134
172 135 TWO_COMPLEMENTER2 : TwoComplementer
173 136 GENERIC MAP(
174 137 Input_SZ => Input_SZ_B
175 138 )
176 139 PORT MAP(
177 140 clk => clk,
178 141 reset => reset,
179 142 clr => clr_MAC,
180 143 TwoComp => Comp_2C(1),
181 144 OP => OP2,
182 145 RES => OP2_2C
183 146 );
184 147 END GENERATE gen_comp;
185 148
186 149 no_gen_comp : IF COMP_EN = 1 GENERATE
150 process(clk,reset)
151 begin
152 if(reset='0')then
153 OP1_2C <= (others => '0');
154 OP2_2C <= (others => '0');
155 elsif clk'event and clk='1' then
156 if clr_MAC = '1' then
157 OP1_2C <= (others => '0');
158 OP2_2C <= (others => '0');
159 else
160 OP1_2C <= OP1;
187 161 OP2_2C <= OP2;
188 OP1_2C <= OP1;
162 end if;
163 end if;
164 end process;
165
189 166 END GENERATE no_gen_comp;
190 167 --==============================================================
191 168
192 clr_MACREG1 : MAC_REG
169 --==============================================================
170 --=============M U L T I P L I E R==============================
171 --==============================================================
172
173 multREG0 : MAC_REG
193 174 GENERIC MAP(size => 1)
194 175 PORT MAP(
195 176 reset => reset,
196 177 clk => clk,
197 D(0) => clr_MAC,
198 Q(0) => clr_MAC_D
178 D(0) => mult,
179 Q(0) => mult_D
199 180 );
200 181
201 addREG : MAC_REG
202 GENERIC MAP(size => 1)
182 Multiplieri_nst : Multiplier
183 GENERIC MAP(
184 Input_SZ_A => Input_SZ_A,
185 Input_SZ_B => Input_SZ_B
186 )
203 187 PORT MAP(
188 clk => clk,
204 189 reset => reset,
205 clk => clk,
206 D(0) => add,
207 Q(0) => add_D
190 mult => mult_D,
191 OP1 => OP1_2C,
192 OP2 => OP2_2C,
193 RES => MULTout
208 194 );
209 195
210 196 OP1REG : MAC_REG
211 197 GENERIC MAP(size => Input_SZ_A)
212 198 PORT MAP(
213 199 reset => reset,
214 200 clk => clk,
215 201 D => OP1_2C,
216 202 Q => OP1_2C_D
217 203 );
218 204
219
220 205 OP2REG : MAC_REG
221 206 GENERIC MAP(size => Input_SZ_B)
222 207 PORT MAP(
223 208 reset => reset,
224 209 clk => clk,
225 210 D => OP2_2C,
226 211 Q => OP2_2C_D
227 212 );
228 213
214 --==============================================================
215
216 --==============================================================
217 --======================M A C M U X ===========================
218 --==============================================================
219
220 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
221 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
222
223 MACMUXselREG0 : MAC_REG
224 GENERIC MAP(size => 1)
225 PORT MAP(
226 reset => reset,
227 clk => clk,
228 D(0) => MACMUXsel,
229 Q(0) => MACMUXsel_D
230 );
231
232 MACMUXselREG1 : MAC_REG
233 GENERIC MAP(size => 1)
234 PORT MAP(
235 reset => reset,
236 clk => clk,
237 D(0) => MACMUXsel_D,
238 Q(0) => MACMUXsel_D_D
239 );
240
241 MACMUX_inst : MAC_MUX
242 GENERIC MAP(
243 Input_SZ_A => Input_SZ_A+Input_SZ_B,
244 Input_SZ_B => Input_SZ_A+Input_SZ_B
245
246 )
247 PORT MAP(
248 sel => MACMUXsel_D_D,
249 INA1 => ADDERout,
250 INA2 => OP2_2C_D_Resz,
251 INB1 => MULTout,
252 INB2 => OP1_2C_D_Resz,
253 OUTA => ADDERinA,
254 OUTB => ADDERinB
255 );
256
257 --==============================================================
258
259 --==============================================================
260 --======================A D D E R ==============================
261 --==============================================================
262
263 clr_MACREG0 : MAC_REG
264 GENERIC MAP(size => 1)
265 PORT MAP(
266 reset => reset,
267 clk => clk,
268 D(0) => clr_MAC,
269 Q(0) => clr_MAC_D
270 );
271
272 clr_MACREG1 : MAC_REG
273 GENERIC MAP(size => 1)
274 PORT MAP(
275 reset => reset,
276 clk => clk,
277 D(0) => clr_MAC_D,
278 Q(0) => clr_MAC_D_D
279 );
280
281 addREG0 : MAC_REG
282 GENERIC MAP(size => 1)
283 PORT MAP(
284 reset => reset,
285 clk => clk,
286 D(0) => add,
287 Q(0) => add_D
288 );
289
290 addREG1 : MAC_REG
291 GENERIC MAP(size => 1)
292 PORT MAP(
293 reset => reset,
294 clk => clk,
295 D(0) => add_D,
296 Q(0) => add_D_D
297 );
298
299 load_mult_resultREG : MAC_REG
300 GENERIC MAP(size => 1)
301 PORT MAP(
302 reset => reset,
303 clk => clk,
304 D(0) => load_mult_result,
305 Q(0) => load_mult_result_D
306 );
307
308 load_mult_resultREG1 : MAC_REG
309 GENERIC MAP(size => 1)
310 PORT MAP(
311 reset => reset,
312 clk => clk,
313 D(0) => load_mult_result_D,
314 Q(0) => load_mult_result_D_D
315 );
316
317 adder_inst : Adder
318 GENERIC MAP(
319 Input_SZ_A => Input_SZ_A+Input_SZ_B,
320 Input_SZ_B => Input_SZ_A+Input_SZ_B
321 )
322 PORT MAP(
323 clk => clk,
324 reset => reset,
325 clr => clr_MAC_D_D,
326 load => load_mult_result_D_D,
327 add => add_D_D,
328 OP1 => ADDERinA,
329 OP2 => ADDERinB,
330 RES => ADDERout
331 );
332
333 --==============================================================
334
335 --==============================================================
336 --======================M A C M U X2 ==========================
337 --==============================================================
338
229 339 MULToutREG : MAC_REG
230 340 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
231 341 PORT MAP(
232 342 reset => reset,
233 343 clk => clk,
234 344 D => MULTout,
235 345 Q => MULTout_D
236 346 );
237 347
238 MACMUXselREG : MAC_REG
239 GENERIC MAP(size => 1)
240 PORT MAP(
241 reset => reset,
242 clk => clk,
243 D(0) => MACMUXsel,
244 Q(0) => MACMUXsel_D
245 );
246
247 348 MACMUX2selREG : MAC_REG
248 349 GENERIC MAP(size => 1)
249 350 PORT MAP(
250 351 reset => reset,
251 352 clk => clk,
252 353 D(0) => MACMUX2sel,
253 354 Q(0) => MACMUX2sel_D
254 355 );
255 356
256 MACMUX2selREG2 : MAC_REG
357 MACMUX2selREG2_0 : MAC_REG
257 358 GENERIC MAP(size => 1)
258 359 PORT MAP(
259 360 reset => reset,
260 361 clk => clk,
261 362 D(0) => MACMUX2sel_D,
262 363 Q(0) => MACMUX2sel_D_D
263 364 );
264 365
265 --==============================================================
266 --======================M A C M U X ===========================
267 --==============================================================
268 MACMUX_inst : MAC_MUX
269 GENERIC MAP(
270 Input_SZ_A => Input_SZ_A+Input_SZ_B,
271 Input_SZ_B => Input_SZ_A+Input_SZ_B
272
273 )
366 MACMUX2selREG2_1 : MAC_REG
367 GENERIC MAP(size => 1)
274 368 PORT MAP(
275 sel => MACMUXsel_D,
276 INA1 => ADDERout,
277 INA2 => OP2_2C_D_Resz,
278 INB1 => MULTout,
279 INB2 => OP1_2C_D_Resz,
280 OUTA => ADDERinA,
281 OUTB => ADDERinB
369 reset => reset,
370 clk => clk,
371 D(0) => MACMUX2sel_D_D,
372 Q(0) => MACMUX2sel_D_D_D
282 373 );
283 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
284 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
285 --==============================================================
286 374
287
288 --==============================================================
289 --======================M A C M U X2 ==========================
290 --==============================================================
291 375 MAC_MUX2_inst : MAC_MUX2
292 376 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
293 377 PORT MAP(
294 sel => MACMUX2sel_D_D,
378 sel => MACMUX2sel_D_D_D,
295 379 RES2 => MULTout_D,
296 380 RES1 => ADDERout,
297 381 RES => RES
298 382 );
299 383 --==============================================================
300 384
301 END ar_MAC;
385 END ar_MAC; No newline at end of file
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