# HG changeset patch # User paul # Date 2014-03-11 07:57:17 # Node ID a640f532ff4ed9bd2810004d920f2f4b3264af83 # Parent a4d553f7f95e5551cc47f4d2031ec065413a1c09 Sync diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd --- a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_CTRL.vhd @@ -40,7 +40,7 @@ ENTITY BUTTERFLY_CTRL IS sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z - sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); + sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) ); @@ -48,8 +48,7 @@ END BUTTERFLY_CTRL; ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS - TYPE fsm_BUTTERFLY_CTRL_T IS ( clearMAC, - waiting, + TYPE fsm_BUTTERFLY_CTRL_T IS ( waiting, add1, add2, add3, @@ -60,7 +59,8 @@ ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTER mult8, mac9, last10, - last11); + last11, + last12); SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T; BEGIN @@ -80,121 +80,136 @@ PROCESS (clk, rstn) --OUT sample_out_val <= '0'; - BUTTERFLY_CTRL_STATE <= clearMAC; + BUTTERFLY_CTRL_STATE <= waiting; ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge CASE BUTTERFLY_CTRL_STATE IS - WHEN clearMAC => + WHEN waiting => IF sample_in_val = '1' THEN - alu_ctrl <= ctrl_CLRMAC; - BUTTERFLY_CTRL_STATE <= waiting; + BUTTERFLY_CTRL_STATE <= add1; END IF; + sel_op1 <= "00000"; -- Are + sel_op2 <= "00000"; -- Bre + alu_comp <= "00"; + alu_ctrl <= ctrl_IDLE; + sel_out <= "0000"; + sample_out_val <= '0'; - WHEN waiting => + WHEN add1 => + sample_out_val <= '0'; sel_op1 <= "10000"; -- Are sel_op2 <= "10000"; -- Bre alu_comp <= "10"; - BUTTERFLY_CTRL_STATE <= add1; + alu_ctrl <= ctrl_ADD; + sel_out <= "0000"; + sample_out_val <= '0'; + BUTTERFLY_CTRL_STATE <= add2; - WHEN add1 => + WHEN add2 => sample_out_val <= '0'; sel_op1 <= "01000"; -- Aim sel_op2 <= "01000"; -- Bim alu_comp <= "10"; alu_ctrl <= ctrl_ADD; - sel_out <= "10000"; - BUTTERFLY_CTRL_STATE <= add2; + sel_out <= "0000"; + BUTTERFLY_CTRL_STATE <= add3; - WHEN add2 => + WHEN add3 => sample_out_val <= '0'; sel_op1 <= "10000"; -- Are sel_op2 <= "10000"; -- Bre alu_comp <= "00"; alu_ctrl <= ctrl_ADD; - sel_out <= "10000"; - BUTTERFLY_CTRL_STATE <= add3; + sel_out <= "0000"; + BUTTERFLY_CTRL_STATE <= add4; - WHEN add3 => + WHEN add4 => sample_out_val <= '0'; sel_op1 <= "01000"; -- Aim sel_op2 <= "01000"; -- Bim alu_comp <= "00"; alu_ctrl <= ctrl_ADD; - sel_out <= "10000"; + sel_out <= "0000"; sel_xyz <= "100"; -- X - BUTTERFLY_CTRL_STATE <= add4; + BUTTERFLY_CTRL_STATE <= mult5; - WHEN add4 => + WHEN mult5 => sample_out_val <= '0'; sel_op1 <= "00100"; -- X sel_op2 <= "00100"; -- c alu_comp <= "00"; - alu_ctrl <= ctrl_ADD; - sel_out <= "00000"; - sel_xyz <= "010"; - BUTTERFLY_CTRL_STATE <= mult5; + alu_ctrl <= ctrl_MULT; + sel_out <= "0000"; + sel_xyz <= "010"; -- Y + BUTTERFLY_CTRL_STATE <= mac6; - WHEN mult5 => + WHEN mac6 => sample_out_val <= '0'; - alu_ctrl <= ctrl_MULT; sel_op1 <= "00010"; -- Y sel_op2 <= "00100"; -- c alu_comp <= "10"; - sel_out <= "00100"; - BUTTERFLY_CTRL_STATE <= mac6; + alu_ctrl <= ctrl_MAC; + sel_out <= "0001"; -- *** /!\ *** -- + sample_out_val <= '1'; + sel_xyz <= "000"; -- Y + BUTTERFLY_CTRL_STATE <= mac7; - WHEN mac6 => + WHEN mac7 => sample_out_val <= '0'; sel_op1 <= "00010"; -- Y sel_op2 <= "00001"; -- cms alu_comp <= "00"; alu_ctrl <= ctrl_MAC; - sel_out <= "10000"; - BUTTERFLY_CTRL_STATE <= mac7; - - WHEN mac7 => - sample_out_val <= '0'; - sel_op1 <= "00100"; -- X - sel_op2 <= "00010"; -- cps - alu_ctrl <= ctrl_MAC; - alu_comp <= "00"; - sel_out <= "10000"; + sel_out <= "0010"; -- *** /!\ *** -- + sample_out_val <= '1'; BUTTERFLY_CTRL_STATE <= mult8; WHEN mult8 => sample_out_val <= '0'; + sel_op1 <= "00100"; -- X + sel_op2 <= "00010"; -- cps + alu_comp <= "00"; alu_ctrl <= ctrl_MULT; - sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU - sel_op2 <= "00000"; -- 1 - alu_comp <= "00"; - sel_out <= "10000"; + sel_out <= "0000"; + sample_out_val <= '0'; BUTTERFLY_CTRL_STATE <= mac9; WHEN mac9 => sample_out_val <= '0'; - sel_op1 <= "10000"; - sel_op2 <= "10000"; alu_ctrl <= ctrl_MAC; + sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU + sel_op2 <= "00000"; -- 1 alu_comp <= "10"; - sel_out <= "10000"; + sel_out <= "0000"; + sample_out_val <= '0'; BUTTERFLY_CTRL_STATE <= last10; WHEN last10 => sample_out_val <= '0'; sel_op1 <= "10000"; sel_op2 <= "10000"; + alu_comp <= "10"; alu_ctrl <= ctrl_IDLE; - alu_comp <= "10"; - sel_out <= "10000"; + sel_out <= "0100"; -- *** /!\ *** -- + sample_out_val <= '1'; BUTTERFLY_CTRL_STATE <= last11; WHEN last11 => sample_out_val <= '0'; - alu_ctrl <= ctrl_IDLE; alu_comp <= "10"; - sel_out <= "10000"; + alu_ctrl <= ctrl_IDLE; + sel_out <= "0000"; + sample_out_val <= '0'; + BUTTERFLY_CTRL_STATE <= last12; + + WHEN last12 => + sample_out_val <= '0'; + alu_comp <= "10"; + alu_ctrl <= ctrl_IDLE; + sel_out <= "1000"; -- *** /!\ *** -- + sample_out_val <= '1'; BUTTERFLY_CTRL_STATE <= waiting; WHEN OTHERS => diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd --- a/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/BUTTERFLY_TOP.vhd @@ -46,13 +46,8 @@ ENTITY BUTTERFLY_TOP IS cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); - alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); - butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); - sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0) + sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0) ); END BUTTERFLY_TOP; @@ -66,9 +61,6 @@ SIGNAL alu_comp_sig : STD_LOGIC_VECTOR( BEGIN - alu_ctrl <= alu_ctrl_sig; - alu_comp <= alu_comp_sig; - BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW GENERIC MAP ( Sample_SZ => 16) @@ -84,9 +76,6 @@ BEGIN cps_in => cps_in, cms_in => cms_in, - op1 => op1, - op2 => op2, - out_alu => butterfly_out, sel_op1 => sel_op1, diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd --- a/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/LPP_BUTTERFLY_DATAFLOW.vhd @@ -86,6 +86,10 @@ PROCESS (clk, rstn) Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); elsif sel_xyz = "001" THEN Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ)); + else + X <= X; + Y <= Y; + Z <= Z; end if; END IF; diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd --- a/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/lpp_fft.vhd @@ -1,29 +1,32 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Paul Leroy --- Mail : paul.leroy@lpp.polytechnique.fr ----------------------------------------------------------------------------- - - -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Paul Leroy +-- Mail : paul.leroy@lpp.polytechnique.fr +---------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY staging_LPP; +USE staging_LPP.PLE_iir_filter.ALL; + PACKAGE PLE_lpp_fft IS COMPONENT BUTTERFLY_DATAFLOW @@ -41,9 +44,6 @@ COMPONENT BUTTERFLY_DATAFLOW cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z @@ -65,7 +65,7 @@ COMPONENT BUTTERFLY_CTRL sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z - sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); + sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 ); alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) ); @@ -89,13 +89,31 @@ COMPONENT BUTTERFLY_TOP cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); - alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); - alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); + butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); + sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0) + ); +END COMPONENT; - butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0); - sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0) +COMPONENT input_buffers_and_coefficients + GENERIC( + tech : INTEGER := 0; + Input_SZ_1 : INTEGER := 16; + Mem_use : INTEGER := use_RAM -- 1 use RAM + ); + PORT( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + --******************* + -- PLE ************** + WD_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + RD_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + WEN_in : IN STD_LOGIC; + REN_in : IN STD_LOGIC; + RADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + WADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + start : IN STD_LOGIC + --******************* + --******************* ); END COMPONENT; diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/testBench_BUTTERFLY_TOP.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/test/testBench_BUTTERFLY_TOP.vhd --- a/lib/staging/LPP/PLE/dsp/lpp_fft/test/testBench_BUTTERFLY_TOP.vhd +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/testBench_BUTTERFLY_TOP.vhd @@ -44,15 +44,10 @@ signal Bim : std_logic_vector( signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0'); - -signal op1 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); -signal op2 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0); -signal alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -signal alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 ); -signal sel_out : std_logic_vector( 4 downto 0 ); +signal sel_out : std_logic_vector( 3 downto 0 ); signal sample_in_val : std_logic := '0'; signal sample_out_val : std_logic; @@ -78,11 +73,6 @@ port map( cps_in => cps, cms_in => cms, - op1 => op1, - op2 => op2, - alu_ctrl => alu_ctrl_sig, - alu_comp => alu_comp_sig, - butterfly_out => Resultat, sel_out => sel_out ); @@ -92,8 +82,10 @@ clk <= not clk after 25 ns; process begin -wait for 40 ns; - rstn <= '1'; +if rstn = '0' then + wait for 40 ns; + rstn <= '1'; +end if; wait for 11 ns; Are <= std_logic_vector(TO_SIGNED(100 ,Sample_SZ)); diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/test/wave.do b/lib/staging/LPP/PLE/dsp/lpp_fft/test/wave.do --- a/lib/staging/LPP/PLE/dsp/lpp_fft/test/wave.do +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/test/wave.do @@ -1,13 +1,25 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate /testbench_butterfly_top/are -add wave -noupdate -divider TOTO -add wave -noupdate /testbench_butterfly_top/aim -add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op2 -add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op1 +add wave -noupdate /testbench_butterfly_top/clk +add wave -noupdate /testbench_butterfly_top/rstn +add wave -noupdate -radix decimal /testbench_butterfly_top/are +add wave -noupdate -radix decimal /testbench_butterfly_top/aim +add wave -noupdate -radix decimal /testbench_butterfly_top/bre +add wave -noupdate -radix decimal /testbench_butterfly_top/bim +add wave -noupdate -radix decimal /testbench_butterfly_top/c +add wave -noupdate -radix decimal /testbench_butterfly_top/cps +add wave -noupdate -radix decimal /testbench_butterfly_top/cms +add wave -noupdate -radix decimal /testbench_butterfly_top/op1 +add wave -noupdate -radix decimal /testbench_butterfly_top/op2 +add wave -noupdate -radix decimal /testbench_butterfly_top/resultat +add wave -noupdate /testbench_butterfly_top/alu_ctrl_sig +add wave -noupdate /testbench_butterfly_top/alu_comp_sig +add wave -noupdate /testbench_butterfly_top/sel_out +add wave -noupdate /testbench_butterfly_top/sample_in_val +add wave -noupdate /testbench_butterfly_top/sample_out_val TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -configure wave -namecolwidth 226 +WaveRestoreCursors {{Cursor 1} {149541 ps} 0} +configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left configure wave -signalnamewidth 0 @@ -21,4 +33,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ps} {1092 ps} +WaveRestoreZoom {0 ps} {1050 ns} diff --git a/lib/staging/LPP/PLE/dsp/lpp_fft/twiddle_factors_128.vhd b/lib/staging/LPP/PLE/dsp/lpp_fft/twiddle_factors_128.vhd --- a/lib/staging/LPP/PLE/dsp/lpp_fft/twiddle_factors_128.vhd +++ b/lib/staging/LPP/PLE/dsp/lpp_fft/twiddle_factors_128.vhd @@ -1,5 +1,11 @@ --twiddle_factors_128.vhd +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +package PLE_twiddle_factors_128 is + constant Coef_SZ : integer := 16; constant NB_Coeffs : integer := 128; @@ -457,3 +463,5 @@ cms_96 & cms_97 & cms_98 & cms_99 & cms_104 & cms_105 & cms_106 & cms_107 & cms_108 & cms_109 & cms_110 & cms_111 & cms_112 & cms_113 & cms_114 & cms_115 & cms_116 & cms_117 & cms_118 & cms_119 & cms_120 & cms_121 & cms_122 & cms_123 & cms_124 & cms_125 & cms_126 & cms_127 ); +end; + diff --git a/lib/staging/LPP/PLE/general_purpose/MAC.vhd b/lib/staging/LPP/PLE/general_purpose/MAC.vhd --- a/lib/staging/LPP/PLE/general_purpose/MAC.vhd +++ b/lib/staging/LPP/PLE/general_purpose/MAC.vhd @@ -1,301 +1,385 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY staging_lpp; -USE staging_lpp.PLE_general_purpose.ALL; ---TODO ---terminer le testbensh puis changer le resize dans les instanciations ---par un resize sur un vecteur en combi - - -ENTITY MAC IS - GENERIC( - Input_SZ_A : INTEGER := 8; - Input_SZ_B : INTEGER := 8; - COMP_EN : INTEGER := 0 -- 1 => No Comp - - ); - PORT( - clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - clr_MAC : IN STD_LOGIC; - MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); - OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); - RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) - ); -END MAC; - - - - -ARCHITECTURE ar_MAC OF MAC IS - - SIGNAL add, mult : STD_LOGIC; - SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - - SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - - SIGNAL MACMUXsel : STD_LOGIC; - SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - - SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); - SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); - - SIGNAL MACMUX2sel : STD_LOGIC; - - SIGNAL add_D : STD_LOGIC; - SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); - SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); - SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); - SIGNAL MACMUXsel_D : STD_LOGIC; - SIGNAL MACMUX2sel_D : STD_LOGIC; - SIGNAL MACMUX2sel_D_D : STD_LOGIC; - SIGNAL clr_MAC_D : STD_LOGIC; - SIGNAL clr_MAC_D_D : STD_LOGIC; - SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); - - SIGNAL load_mult_result : STD_LOGIC; - SIGNAL load_mult_result_D : STD_LOGIC; - -BEGIN - - - - ---============================================================== ---=============M A C C O N T R O L E R========================= ---============================================================== - MAC_CONTROLER1 : MAC_CONTROLER - PORT MAP( - ctrl => MAC_MUL_ADD, - MULT => mult, - ADD => add, - LOAD_ADDER => load_mult_result, - MACMUX_sel => MACMUXsel, - MACMUX2_sel => MACMUX2sel - - ); ---============================================================== - - - - ---============================================================== ---=============M U L T I P L I E R============================== ---============================================================== - Multiplieri_nst : Multiplier - GENERIC MAP( - Input_SZ_A => Input_SZ_A, - Input_SZ_B => Input_SZ_B - ) - PORT MAP( - clk => clk, - reset => reset, - mult => mult, - OP1 => OP1_2C, - OP2 => OP2_2C, - RES => MULTout - ); ---============================================================== - - PROCESS (clk, reset) - BEGIN -- PROCESS - IF reset = '0' THEN -- asynchronous reset (active low) - load_mult_result_D <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - load_mult_result_D <= load_mult_result; - END IF; - END PROCESS; - ---============================================================== ---======================A D D E R ============================== ---============================================================== - adder_inst : Adder - GENERIC MAP( - Input_SZ_A => Input_SZ_A+Input_SZ_B, - Input_SZ_B => Input_SZ_A+Input_SZ_B - ) - PORT MAP( - clk => clk, - reset => reset, - clr => clr_MAC_D, - load => load_mult_result_D, - add => add_D, - OP1 => ADDERinA, - OP2 => ADDERinB, - RES => ADDERout - ); - ---============================================================== ---===================TWO COMPLEMENTERS========================== ---============================================================== - gen_comp : IF COMP_EN = 0 GENERATE - TWO_COMPLEMENTER1 : TwoComplementer - GENERIC MAP( - Input_SZ => Input_SZ_A - ) - PORT MAP( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => Comp_2C(0), - OP => OP1, - RES => OP1_2C - ); - - TWO_COMPLEMENTER2 : TwoComplementer - GENERIC MAP( - Input_SZ => Input_SZ_B - ) - PORT MAP( - clk => clk, - reset => reset, - clr => clr_MAC, - TwoComp => Comp_2C(1), - OP => OP2, - RES => OP2_2C - ); - END GENERATE gen_comp; - - no_gen_comp : IF COMP_EN = 1 GENERATE - OP2_2C <= OP2; - OP1_2C <= OP1; - END GENERATE no_gen_comp; ---============================================================== - - clr_MACREG1 : MAC_REG - GENERIC MAP(size => 1) - PORT MAP( - reset => reset, - clk => clk, - D(0) => clr_MAC, - Q(0) => clr_MAC_D - ); - - addREG : MAC_REG - GENERIC MAP(size => 1) - PORT MAP( - reset => reset, - clk => clk, - D(0) => add, - Q(0) => add_D - ); - - OP1REG : MAC_REG - GENERIC MAP(size => Input_SZ_A) - PORT MAP( - reset => reset, - clk => clk, - D => OP1_2C, - Q => OP1_2C_D - ); - - - OP2REG : MAC_REG - GENERIC MAP(size => Input_SZ_B) - PORT MAP( - reset => reset, - clk => clk, - D => OP2_2C, - Q => OP2_2C_D - ); - - MULToutREG : MAC_REG - GENERIC MAP(size => Input_SZ_A+Input_SZ_B) - PORT MAP( - reset => reset, - clk => clk, - D => MULTout, - Q => MULTout_D - ); - - MACMUXselREG : MAC_REG - GENERIC MAP(size => 1) - PORT MAP( - reset => reset, - clk => clk, - D(0) => MACMUXsel, - Q(0) => MACMUXsel_D - ); - - MACMUX2selREG : MAC_REG - GENERIC MAP(size => 1) - PORT MAP( - reset => reset, - clk => clk, - D(0) => MACMUX2sel, - Q(0) => MACMUX2sel_D - ); - - MACMUX2selREG2 : MAC_REG - GENERIC MAP(size => 1) - PORT MAP( - reset => reset, - clk => clk, - D(0) => MACMUX2sel_D, - Q(0) => MACMUX2sel_D_D - ); - ---============================================================== ---======================M A C M U X =========================== ---============================================================== - MACMUX_inst : MAC_MUX - GENERIC MAP( - Input_SZ_A => Input_SZ_A+Input_SZ_B, - Input_SZ_B => Input_SZ_A+Input_SZ_B - - ) - PORT MAP( - sel => MACMUXsel_D, - INA1 => ADDERout, - INA2 => OP2_2C_D_Resz, - INB1 => MULTout, - INB2 => OP1_2C_D_Resz, - OUTA => ADDERinA, - OUTB => ADDERinB - ); - OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); - OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); ---============================================================== - - ---============================================================== ---======================M A C M U X2 ========================== ---============================================================== - MAC_MUX2_inst : MAC_MUX2 - GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) - PORT MAP( - sel => MACMUX2sel_D_D, - RES2 => MULTout_D, - RES1 => ADDERout, - RES => RES - ); ---============================================================== - -END ar_MAC; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY staging_lpp; +USE staging_lpp.PLE_general_purpose.ALL; +--TODO +--terminer le testbensh puis changer le resize dans les instanciations +--par un resize sur un vecteur en combi + + +ENTITY MAC IS + GENERIC( + Input_SZ_A : INTEGER := 8; + Input_SZ_B : INTEGER := 8; + COMP_EN : INTEGER := 0 -- 1 => No Comp + + ); + PORT( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0) + ); +END MAC; + + + + +ARCHITECTURE ar_MAC OF MAC IS + + SIGNAL add, mult : STD_LOGIC; + SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL MACMUXsel : STD_LOGIC; + SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + + SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + + SIGNAL MACMUX2sel : STD_LOGIC; + + SIGNAL add_D : STD_LOGIC; + SIGNAL add_D_D : STD_LOGIC; + SIGNAL mult_D : STD_LOGIC; + SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + +-- SIGNAL OP1_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); +-- SIGNAL OP2_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + + SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0); + SIGNAL MACMUXsel_D : STD_LOGIC; + SIGNAL MACMUXsel_D_D : STD_LOGIC; + SIGNAL MACMUX2sel_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D : STD_LOGIC; + SIGNAL MACMUX2sel_D_D_D : STD_LOGIC; + SIGNAL clr_MAC_D : STD_LOGIC; + SIGNAL clr_MAC_D_D : STD_LOGIC; + SIGNAL clr_MAC_D_D_D : STD_LOGIC; + SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL MAC_MUL_ADD_2C_D_D : STD_LOGIC_VECTOR(1 DOWNTO 0); + + SIGNAL load_mult_result : STD_LOGIC; + SIGNAL load_mult_result_D : STD_LOGIC; + SIGNAL load_mult_result_D_D : STD_LOGIC; + +BEGIN + + + + +--============================================================== +--=============M A C C O N T R O L E R========================= +--============================================================== + MAC_CONTROLER1 : MAC_CONTROLER + PORT MAP( + ctrl => MAC_MUL_ADD, + MULT => mult, + ADD => add, + LOAD_ADDER => load_mult_result, + MACMUX_sel => MACMUXsel, + MACMUX2_sel => MACMUX2sel + + ); +--============================================================== + + +--============================================================== +--===================TWO COMPLEMENTERS========================== +--============================================================== + gen_comp : IF COMP_EN = 0 GENERATE + TWO_COMPLEMENTER1 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_A + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(0), + OP => OP1, + RES => OP1_2C + ); + + TWO_COMPLEMENTER2 : TwoComplementer + GENERIC MAP( + Input_SZ => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC, + TwoComp => Comp_2C(1), + OP => OP2, + RES => OP2_2C + ); + END GENERATE gen_comp; + + no_gen_comp : IF COMP_EN = 1 GENERATE + process(clk,reset) + begin + if(reset='0')then + OP1_2C <= (others => '0'); + OP2_2C <= (others => '0'); + elsif clk'event and clk='1' then + if clr_MAC = '1' then + OP1_2C <= (others => '0'); + OP2_2C <= (others => '0'); + else + OP1_2C <= OP1; + OP2_2C <= OP2; + end if; + end if; + end process; + + END GENERATE no_gen_comp; +--============================================================== + +--============================================================== +--=============M U L T I P L I E R============================== +--============================================================== + + multREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => mult, + Q(0) => mult_D + ); + + Multiplieri_nst : Multiplier + GENERIC MAP( + Input_SZ_A => Input_SZ_A, + Input_SZ_B => Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + mult => mult_D, + OP1 => OP1_2C, + OP2 => OP2_2C, + RES => MULTout + ); + + OP1REG : MAC_REG + GENERIC MAP(size => Input_SZ_A) + PORT MAP( + reset => reset, + clk => clk, + D => OP1_2C, + Q => OP1_2C_D + ); + + OP2REG : MAC_REG + GENERIC MAP(size => Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => OP2_2C, + Q => OP2_2C_D + ); + +--============================================================== + +--============================================================== +--======================M A C M U X =========================== +--============================================================== + + OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B)); + OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B)); + + MACMUXselREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUXsel, + Q(0) => MACMUXsel_D + ); + + MACMUXselREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUXsel_D, + Q(0) => MACMUXsel_D_D + ); + + MACMUX_inst : MAC_MUX + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + + ) + PORT MAP( + sel => MACMUXsel_D_D, + INA1 => ADDERout, + INA2 => OP2_2C_D_Resz, + INB1 => MULTout, + INB2 => OP1_2C_D_Resz, + OUTA => ADDERinA, + OUTB => ADDERinB + ); + +--============================================================== + +--============================================================== +--======================A D D E R ============================== +--============================================================== + + clr_MACREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => clr_MAC, + Q(0) => clr_MAC_D + ); + + clr_MACREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => clr_MAC_D, + Q(0) => clr_MAC_D_D + ); + + addREG0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => add, + Q(0) => add_D + ); + + addREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => add_D, + Q(0) => add_D_D + ); + + load_mult_resultREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => load_mult_result, + Q(0) => load_mult_result_D + ); + + load_mult_resultREG1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => load_mult_result_D, + Q(0) => load_mult_result_D_D + ); + + adder_inst : Adder + GENERIC MAP( + Input_SZ_A => Input_SZ_A+Input_SZ_B, + Input_SZ_B => Input_SZ_A+Input_SZ_B + ) + PORT MAP( + clk => clk, + reset => reset, + clr => clr_MAC_D_D, + load => load_mult_result_D_D, + add => add_D_D, + OP1 => ADDERinA, + OP2 => ADDERinB, + RES => ADDERout + ); + +--============================================================== + +--============================================================== +--======================M A C M U X2 ========================== +--============================================================== + + MULToutREG : MAC_REG + GENERIC MAP(size => Input_SZ_A+Input_SZ_B) + PORT MAP( + reset => reset, + clk => clk, + D => MULTout, + Q => MULTout_D + ); + + MACMUX2selREG : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel, + Q(0) => MACMUX2sel_D + ); + + MACMUX2selREG2_0 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel_D, + Q(0) => MACMUX2sel_D_D + ); + + MACMUX2selREG2_1 : MAC_REG + GENERIC MAP(size => 1) + PORT MAP( + reset => reset, + clk => clk, + D(0) => MACMUX2sel_D_D, + Q(0) => MACMUX2sel_D_D_D + ); + + MAC_MUX2_inst : MAC_MUX2 + GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B) + PORT MAP( + sel => MACMUX2sel_D_D_D, + RES2 => MULTout_D, + RES1 => ADDERout, + RES => RES + ); +--============================================================== + +END ar_MAC; \ No newline at end of file