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@@ -40,7 +40,7 ENTITY BUTTERFLY_CTRL IS
40 40 sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
41 41 sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
42 42 sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
43 sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
43 sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 );
44 44 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
45 45 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
46 46 );
@@ -48,8 +48,7 END BUTTERFLY_CTRL;
48 48
49 49 ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTERFLY_CTRL IS
50 50
51 TYPE fsm_BUTTERFLY_CTRL_T IS ( clearMAC,
52 waiting,
51 TYPE fsm_BUTTERFLY_CTRL_T IS ( waiting,
53 52 add1,
54 53 add2,
55 54 add3,
@@ -60,7 +59,8 ARCHITECTURE ar_BUTTERFLY_CTRL OF BUTTER
60 59 mult8,
61 60 mac9,
62 61 last10,
63 last11);
62 last11,
63 last12);
64 64 SIGNAL BUTTERFLY_CTRL_STATE : fsm_BUTTERFLY_CTRL_T;
65 65
66 66 BEGIN
@@ -80,121 +80,136 PROCESS (clk, rstn)
80 80 --OUT
81 81 sample_out_val <= '0';
82 82
83 BUTTERFLY_CTRL_STATE <= clearMAC;
83 BUTTERFLY_CTRL_STATE <= waiting;
84 84
85 85 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
86 86
87 87 CASE BUTTERFLY_CTRL_STATE IS
88 88
89 WHEN clearMAC =>
89 WHEN waiting =>
90 90 IF sample_in_val = '1' THEN
91 alu_ctrl <= ctrl_CLRMAC;
92 BUTTERFLY_CTRL_STATE <= waiting;
91 BUTTERFLY_CTRL_STATE <= add1;
93 92 END IF;
93 sel_op1 <= "00000"; -- Are
94 sel_op2 <= "00000"; -- Bre
95 alu_comp <= "00";
96 alu_ctrl <= ctrl_IDLE;
97 sel_out <= "0000";
98 sample_out_val <= '0';
94 99
95 WHEN waiting =>
100 WHEN add1 =>
101 sample_out_val <= '0';
96 102 sel_op1 <= "10000"; -- Are
97 103 sel_op2 <= "10000"; -- Bre
98 104 alu_comp <= "10";
99 BUTTERFLY_CTRL_STATE <= add1;
105 alu_ctrl <= ctrl_ADD;
106 sel_out <= "0000";
107 sample_out_val <= '0';
108 BUTTERFLY_CTRL_STATE <= add2;
100 109
101 WHEN add1 =>
110 WHEN add2 =>
102 111 sample_out_val <= '0';
103 112 sel_op1 <= "01000"; -- Aim
104 113 sel_op2 <= "01000"; -- Bim
105 114 alu_comp <= "10";
106 115 alu_ctrl <= ctrl_ADD;
107 sel_out <= "10000";
108 BUTTERFLY_CTRL_STATE <= add2;
116 sel_out <= "0000";
117 BUTTERFLY_CTRL_STATE <= add3;
109 118
110 WHEN add2 =>
119 WHEN add3 =>
111 120 sample_out_val <= '0';
112 121 sel_op1 <= "10000"; -- Are
113 122 sel_op2 <= "10000"; -- Bre
114 123 alu_comp <= "00";
115 124 alu_ctrl <= ctrl_ADD;
116 sel_out <= "10000";
117 BUTTERFLY_CTRL_STATE <= add3;
125 sel_out <= "0000";
126 BUTTERFLY_CTRL_STATE <= add4;
118 127
119 WHEN add3 =>
128 WHEN add4 =>
120 129 sample_out_val <= '0';
121 130 sel_op1 <= "01000"; -- Aim
122 131 sel_op2 <= "01000"; -- Bim
123 132 alu_comp <= "00";
124 133 alu_ctrl <= ctrl_ADD;
125 sel_out <= "10000";
134 sel_out <= "0000";
126 135 sel_xyz <= "100"; -- X
127 BUTTERFLY_CTRL_STATE <= add4;
136 BUTTERFLY_CTRL_STATE <= mult5;
128 137
129 WHEN add4 =>
138 WHEN mult5 =>
130 139 sample_out_val <= '0';
131 140 sel_op1 <= "00100"; -- X
132 141 sel_op2 <= "00100"; -- c
133 142 alu_comp <= "00";
134 alu_ctrl <= ctrl_ADD;
135 sel_out <= "00000";
136 sel_xyz <= "010";
137 BUTTERFLY_CTRL_STATE <= mult5;
143 alu_ctrl <= ctrl_MULT;
144 sel_out <= "0000";
145 sel_xyz <= "010"; -- Y
146 BUTTERFLY_CTRL_STATE <= mac6;
138 147
139 WHEN mult5 =>
148 WHEN mac6 =>
140 149 sample_out_val <= '0';
141 alu_ctrl <= ctrl_MULT;
142 150 sel_op1 <= "00010"; -- Y
143 151 sel_op2 <= "00100"; -- c
144 152 alu_comp <= "10";
145 sel_out <= "00100";
146 BUTTERFLY_CTRL_STATE <= mac6;
153 alu_ctrl <= ctrl_MAC;
154 sel_out <= "0001"; -- *** /!\ *** --
155 sample_out_val <= '1';
156 sel_xyz <= "000"; -- Y
157 BUTTERFLY_CTRL_STATE <= mac7;
147 158
148 WHEN mac6 =>
159 WHEN mac7 =>
149 160 sample_out_val <= '0';
150 161 sel_op1 <= "00010"; -- Y
151 162 sel_op2 <= "00001"; -- cms
152 163 alu_comp <= "00";
153 164 alu_ctrl <= ctrl_MAC;
154 sel_out <= "10000";
155 BUTTERFLY_CTRL_STATE <= mac7;
156
157 WHEN mac7 =>
158 sample_out_val <= '0';
159 sel_op1 <= "00100"; -- X
160 sel_op2 <= "00010"; -- cps
161 alu_ctrl <= ctrl_MAC;
162 alu_comp <= "00";
163 sel_out <= "10000";
165 sel_out <= "0010"; -- *** /!\ *** --
166 sample_out_val <= '1';
164 167 BUTTERFLY_CTRL_STATE <= mult8;
165 168
166 169 WHEN mult8 =>
167 170 sample_out_val <= '0';
171 sel_op1 <= "00100"; -- X
172 sel_op2 <= "00010"; -- cps
173 alu_comp <= "00";
168 174 alu_ctrl <= ctrl_MULT;
169 sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU
170 sel_op2 <= "00000"; -- 1
171 alu_comp <= "00";
172 sel_out <= "10000";
175 sel_out <= "0000";
176 sample_out_val <= '0';
173 177 BUTTERFLY_CTRL_STATE <= mac9;
174 178
175 179 WHEN mac9 =>
176 180 sample_out_val <= '0';
177 sel_op1 <= "10000";
178 sel_op2 <= "10000";
179 181 alu_ctrl <= ctrl_MAC;
182 sel_op1 <= "00000"; -- Z is taken directly from the output of the ALU
183 sel_op2 <= "00000"; -- 1
180 184 alu_comp <= "10";
181 sel_out <= "10000";
185 sel_out <= "0000";
186 sample_out_val <= '0';
182 187 BUTTERFLY_CTRL_STATE <= last10;
183 188
184 189 WHEN last10 =>
185 190 sample_out_val <= '0';
186 191 sel_op1 <= "10000";
187 192 sel_op2 <= "10000";
193 alu_comp <= "10";
188 194 alu_ctrl <= ctrl_IDLE;
189 alu_comp <= "10";
190 sel_out <= "10000";
195 sel_out <= "0100"; -- *** /!\ *** --
196 sample_out_val <= '1';
191 197 BUTTERFLY_CTRL_STATE <= last11;
192 198
193 199 WHEN last11 =>
194 200 sample_out_val <= '0';
195 alu_ctrl <= ctrl_IDLE;
196 201 alu_comp <= "10";
197 sel_out <= "10000";
202 alu_ctrl <= ctrl_IDLE;
203 sel_out <= "0000";
204 sample_out_val <= '0';
205 BUTTERFLY_CTRL_STATE <= last12;
206
207 WHEN last12 =>
208 sample_out_val <= '0';
209 alu_comp <= "10";
210 alu_ctrl <= ctrl_IDLE;
211 sel_out <= "1000"; -- *** /!\ *** --
212 sample_out_val <= '1';
198 213 BUTTERFLY_CTRL_STATE <= waiting;
199 214
200 215 WHEN OTHERS =>
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@@ -46,13 +46,8 ENTITY BUTTERFLY_TOP IS
46 46 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
47 47 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
48 48
49 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
50 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
51 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
52 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
53
54 49 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
55 sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0)
50 sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0)
56 51 );
57 52 END BUTTERFLY_TOP;
58 53
@@ -66,9 +61,6 SIGNAL alu_comp_sig : STD_LOGIC_VECTOR(
66 61
67 62 BEGIN
68 63
69 alu_ctrl <= alu_ctrl_sig;
70 alu_comp <= alu_comp_sig;
71
72 64 BUTTERFLY_DATAFLOW_1 : BUTTERFLY_DATAFLOW
73 65 GENERIC MAP (
74 66 Sample_SZ => 16)
@@ -84,9 +76,6 BEGIN
84 76 cps_in => cps_in,
85 77 cms_in => cms_in,
86 78
87 op1 => op1,
88 op2 => op2,
89
90 79 out_alu => butterfly_out,
91 80
92 81 sel_op1 => sel_op1,
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@@ -86,6 +86,10 PROCESS (clk, rstn)
86 86 Y <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
87 87 elsif sel_xyz = "001" THEN
88 88 Z <= STD_LOGIC_VECTOR(resize(SIGNED(OUT_ALU_SIG), Sample_SZ));
89 else
90 X <= X;
91 Y <= Y;
92 Z <= Z;
89 93 end if;
90 94
91 95 END IF;
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@@ -1,29 +1,32
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Paul Leroy
20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Paul Leroy
20 -- Mail : paul.leroy@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 LIBRARY staging_LPP;
28 USE staging_LPP.PLE_iir_filter.ALL;
29
27 30 PACKAGE PLE_lpp_fft IS
28 31
29 32 COMPONENT BUTTERFLY_DATAFLOW
@@ -41,9 +44,6 COMPONENT BUTTERFLY_DATAFLOW
41 44 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
42 45 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
43 46
44 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
45 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
46
47 47 out_alu : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
48 48
49 49 sel_op1 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
@@ -65,7 +65,7 COMPONENT BUTTERFLY_CTRL
65 65 sel_op1 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Are Aim X Y Z
66 66 sel_op2 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 ); -- Bre Bim C_in cps_in cms_in
67 67 sel_xyz : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 ); -- X Y Z
68 sel_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
68 sel_out : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0 );
69 69 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
70 70 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 )
71 71 );
@@ -89,13 +89,31 COMPONENT BUTTERFLY_TOP
89 89 cps_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
90 90 cms_in : IN STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
91 91
92 op1 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
93 op2 : OUT STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
94 alu_ctrl : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0 );
95 alu_comp : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 );
92 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
93 sel_out : OUT STD_LOGIC_VECTOR ( 3 DOWNTO 0)
94 );
95 END COMPONENT;
96 96
97 butterfly_out : OUT STD_LOGIC_VECTOR ( 2*Sample_SZ-1 DOWNTO 0);
98 sel_out : OUT STD_LOGIC_VECTOR ( 4 DOWNTO 0)
97 COMPONENT input_buffers_and_coefficients
98 GENERIC(
99 tech : INTEGER := 0;
100 Input_SZ_1 : INTEGER := 16;
101 Mem_use : INTEGER := use_RAM -- 1 use RAM
102 );
103 PORT(
104 rstn : IN STD_LOGIC;
105 clk : IN STD_LOGIC;
106 --*******************
107 -- PLE **************
108 WD_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
109 RD_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
110 WEN_in : IN STD_LOGIC;
111 REN_in : IN STD_LOGIC;
112 RADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
113 WADDR_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
114 start : IN STD_LOGIC
115 --*******************
116 --*******************
99 117 );
100 118 END COMPONENT;
101 119
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@@ -44,15 +44,10 signal Bim : std_logic_vector(
44 44 signal c : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
45 45 signal cps : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
46 46 signal cms : std_logic_vector( Sample_SZ-1 downto 0 ) := ( others => '0');
47
48 signal op1 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
49 signal op2 : STD_LOGIC_VECTOR ( Sample_SZ-1 DOWNTO 0);
50 signal alu_ctrl_sig : STD_LOGIC_VECTOR( 2 DOWNTO 0 );
51 signal alu_comp_sig : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
52 47
53 48 signal Resultat : std_logic_vector( 2*Sample_SZ-1 downto 0 );
54 49
55 signal sel_out : std_logic_vector( 4 downto 0 );
50 signal sel_out : std_logic_vector( 3 downto 0 );
56 51
57 52 signal sample_in_val : std_logic := '0';
58 53 signal sample_out_val : std_logic;
@@ -78,11 +73,6 port map(
78 73 cps_in => cps,
79 74 cms_in => cms,
80 75
81 op1 => op1,
82 op2 => op2,
83 alu_ctrl => alu_ctrl_sig,
84 alu_comp => alu_comp_sig,
85
86 76 butterfly_out => Resultat,
87 77 sel_out => sel_out
88 78 );
@@ -92,8 +82,10 clk <= not clk after 25 ns;
92 82 process
93 83 begin
94 84
95 wait for 40 ns;
96 rstn <= '1';
85 if rstn = '0' then
86 wait for 40 ns;
87 rstn <= '1';
88 end if;
97 89
98 90 wait for 11 ns;
99 91 Are <= std_logic_vector(TO_SIGNED(100 ,Sample_SZ));
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@@ -1,13 +1,25
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench_butterfly_top/are
4 add wave -noupdate -divider TOTO
5 add wave -noupdate /testbench_butterfly_top/aim
6 add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op2
7 add wave -noupdate -expand -group INPUT /testbench_butterfly_top/op1
3 add wave -noupdate /testbench_butterfly_top/clk
4 add wave -noupdate /testbench_butterfly_top/rstn
5 add wave -noupdate -radix decimal /testbench_butterfly_top/are
6 add wave -noupdate -radix decimal /testbench_butterfly_top/aim
7 add wave -noupdate -radix decimal /testbench_butterfly_top/bre
8 add wave -noupdate -radix decimal /testbench_butterfly_top/bim
9 add wave -noupdate -radix decimal /testbench_butterfly_top/c
10 add wave -noupdate -radix decimal /testbench_butterfly_top/cps
11 add wave -noupdate -radix decimal /testbench_butterfly_top/cms
12 add wave -noupdate -radix decimal /testbench_butterfly_top/op1
13 add wave -noupdate -radix decimal /testbench_butterfly_top/op2
14 add wave -noupdate -radix decimal /testbench_butterfly_top/resultat
15 add wave -noupdate /testbench_butterfly_top/alu_ctrl_sig
16 add wave -noupdate /testbench_butterfly_top/alu_comp_sig
17 add wave -noupdate /testbench_butterfly_top/sel_out
18 add wave -noupdate /testbench_butterfly_top/sample_in_val
19 add wave -noupdate /testbench_butterfly_top/sample_out_val
8 20 TreeUpdate [SetDefaultTree]
9 WaveRestoreCursors {{Cursor 1} {0 ps} 0}
10 configure wave -namecolwidth 226
21 WaveRestoreCursors {{Cursor 1} {149541 ps} 0}
22 configure wave -namecolwidth 150
11 23 configure wave -valuecolwidth 100
12 24 configure wave -justifyvalue left
13 25 configure wave -signalnamewidth 0
@@ -21,4 +33,4 configure wave -griddelta 40
21 33 configure wave -timeline 0
22 34 configure wave -timelineunits ns
23 35 update
24 WaveRestoreZoom {0 ps} {1092 ps}
36 WaveRestoreZoom {0 ps} {1050 ns}
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@@ -1,5 +1,11
1 1 --twiddle_factors_128.vhd
2 2
3 library IEEE;
4 use IEEE.numeric_std.all;
5 use IEEE.std_logic_1164.all;
6
7 package PLE_twiddle_factors_128 is
8
3 9 constant Coef_SZ : integer := 16;
4 10 constant NB_Coeffs : integer := 128;
5 11
@@ -457,3 +463,5 cms_96 & cms_97 & cms_98 & cms_99 &
457 463 cms_104 & cms_105 & cms_106 & cms_107 & cms_108 & cms_109 & cms_110 & cms_111 &
458 464 cms_112 & cms_113 & cms_114 & cms_115 & cms_116 & cms_117 & cms_118 & cms_119 &
459 465 cms_120 & cms_121 & cms_122 & cms_123 & cms_124 & cms_125 & cms_126 & cms_127 );
466 end;
467
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@@ -1,301 +1,385
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY staging_lpp;
26 USE staging_lpp.PLE_general_purpose.ALL;
27 --TODO
28 --terminer le testbensh puis changer le resize dans les instanciations
29 --par un resize sur un vecteur en combi
30
31
32 ENTITY MAC IS
33 GENERIC(
34 Input_SZ_A : INTEGER := 8;
35 Input_SZ_B : INTEGER := 8;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37
38 );
39 PORT(
40 clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clr_MAC : IN STD_LOGIC;
43 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
44 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
45 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
46 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
47 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
48 );
49 END MAC;
50
51
52
53
54 ARCHITECTURE ar_MAC OF MAC IS
55
56 SIGNAL add, mult : STD_LOGIC;
57 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58
59 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
62
63 SIGNAL MACMUXsel : STD_LOGIC;
64 SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65 SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
66
67 SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
68 SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
69
70 SIGNAL MACMUX2sel : STD_LOGIC;
71
72 SIGNAL add_D : STD_LOGIC;
73 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
74 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
75 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
76 SIGNAL MACMUXsel_D : STD_LOGIC;
77 SIGNAL MACMUX2sel_D : STD_LOGIC;
78 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
79 SIGNAL clr_MAC_D : STD_LOGIC;
80 SIGNAL clr_MAC_D_D : STD_LOGIC;
81 SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
82
83 SIGNAL load_mult_result : STD_LOGIC;
84 SIGNAL load_mult_result_D : STD_LOGIC;
85
86 BEGIN
87
88
89
90
91 --==============================================================
92 --=============M A C C O N T R O L E R=========================
93 --==============================================================
94 MAC_CONTROLER1 : MAC_CONTROLER
95 PORT MAP(
96 ctrl => MAC_MUL_ADD,
97 MULT => mult,
98 ADD => add,
99 LOAD_ADDER => load_mult_result,
100 MACMUX_sel => MACMUXsel,
101 MACMUX2_sel => MACMUX2sel
102
103 );
104 --==============================================================
105
106
107
108
109 --==============================================================
110 --=============M U L T I P L I E R==============================
111 --==============================================================
112 Multiplieri_nst : Multiplier
113 GENERIC MAP(
114 Input_SZ_A => Input_SZ_A,
115 Input_SZ_B => Input_SZ_B
116 )
117 PORT MAP(
118 clk => clk,
119 reset => reset,
120 mult => mult,
121 OP1 => OP1_2C,
122 OP2 => OP2_2C,
123 RES => MULTout
124 );
125 --==============================================================
126
127 PROCESS (clk, reset)
128 BEGIN -- PROCESS
129 IF reset = '0' THEN -- asynchronous reset (active low)
130 load_mult_result_D <= '0';
131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
132 load_mult_result_D <= load_mult_result;
133 END IF;
134 END PROCESS;
135
136 --==============================================================
137 --======================A D D E R ==============================
138 --==============================================================
139 adder_inst : Adder
140 GENERIC MAP(
141 Input_SZ_A => Input_SZ_A+Input_SZ_B,
142 Input_SZ_B => Input_SZ_A+Input_SZ_B
143 )
144 PORT MAP(
145 clk => clk,
146 reset => reset,
147 clr => clr_MAC_D,
148 load => load_mult_result_D,
149 add => add_D,
150 OP1 => ADDERinA,
151 OP2 => ADDERinB,
152 RES => ADDERout
153 );
154
155 --==============================================================
156 --===================TWO COMPLEMENTERS==========================
157 --==============================================================
158 gen_comp : IF COMP_EN = 0 GENERATE
159 TWO_COMPLEMENTER1 : TwoComplementer
160 GENERIC MAP(
161 Input_SZ => Input_SZ_A
162 )
163 PORT MAP(
164 clk => clk,
165 reset => reset,
166 clr => clr_MAC,
167 TwoComp => Comp_2C(0),
168 OP => OP1,
169 RES => OP1_2C
170 );
171
172 TWO_COMPLEMENTER2 : TwoComplementer
173 GENERIC MAP(
174 Input_SZ => Input_SZ_B
175 )
176 PORT MAP(
177 clk => clk,
178 reset => reset,
179 clr => clr_MAC,
180 TwoComp => Comp_2C(1),
181 OP => OP2,
182 RES => OP2_2C
183 );
184 END GENERATE gen_comp;
185
186 no_gen_comp : IF COMP_EN = 1 GENERATE
187 OP2_2C <= OP2;
188 OP1_2C <= OP1;
189 END GENERATE no_gen_comp;
190 --==============================================================
191
192 clr_MACREG1 : MAC_REG
193 GENERIC MAP(size => 1)
194 PORT MAP(
195 reset => reset,
196 clk => clk,
197 D(0) => clr_MAC,
198 Q(0) => clr_MAC_D
199 );
200
201 addREG : MAC_REG
202 GENERIC MAP(size => 1)
203 PORT MAP(
204 reset => reset,
205 clk => clk,
206 D(0) => add,
207 Q(0) => add_D
208 );
209
210 OP1REG : MAC_REG
211 GENERIC MAP(size => Input_SZ_A)
212 PORT MAP(
213 reset => reset,
214 clk => clk,
215 D => OP1_2C,
216 Q => OP1_2C_D
217 );
218
219
220 OP2REG : MAC_REG
221 GENERIC MAP(size => Input_SZ_B)
222 PORT MAP(
223 reset => reset,
224 clk => clk,
225 D => OP2_2C,
226 Q => OP2_2C_D
227 );
228
229 MULToutREG : MAC_REG
230 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
231 PORT MAP(
232 reset => reset,
233 clk => clk,
234 D => MULTout,
235 Q => MULTout_D
236 );
237
238 MACMUXselREG : MAC_REG
239 GENERIC MAP(size => 1)
240 PORT MAP(
241 reset => reset,
242 clk => clk,
243 D(0) => MACMUXsel,
244 Q(0) => MACMUXsel_D
245 );
246
247 MACMUX2selREG : MAC_REG
248 GENERIC MAP(size => 1)
249 PORT MAP(
250 reset => reset,
251 clk => clk,
252 D(0) => MACMUX2sel,
253 Q(0) => MACMUX2sel_D
254 );
255
256 MACMUX2selREG2 : MAC_REG
257 GENERIC MAP(size => 1)
258 PORT MAP(
259 reset => reset,
260 clk => clk,
261 D(0) => MACMUX2sel_D,
262 Q(0) => MACMUX2sel_D_D
263 );
264
265 --==============================================================
266 --======================M A C M U X ===========================
267 --==============================================================
268 MACMUX_inst : MAC_MUX
269 GENERIC MAP(
270 Input_SZ_A => Input_SZ_A+Input_SZ_B,
271 Input_SZ_B => Input_SZ_A+Input_SZ_B
272
273 )
274 PORT MAP(
275 sel => MACMUXsel_D,
276 INA1 => ADDERout,
277 INA2 => OP2_2C_D_Resz,
278 INB1 => MULTout,
279 INB2 => OP1_2C_D_Resz,
280 OUTA => ADDERinA,
281 OUTB => ADDERinB
282 );
283 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
284 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
285 --==============================================================
286
287
288 --==============================================================
289 --======================M A C M U X2 ==========================
290 --==============================================================
291 MAC_MUX2_inst : MAC_MUX2
292 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
293 PORT MAP(
294 sel => MACMUX2sel_D_D,
295 RES2 => MULTout_D,
296 RES1 => ADDERout,
297 RES => RES
298 );
299 --==============================================================
300
301 END ar_MAC;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY staging_lpp;
26 USE staging_lpp.PLE_general_purpose.ALL;
27 --TODO
28 --terminer le testbensh puis changer le resize dans les instanciations
29 --par un resize sur un vecteur en combi
30
31
32 ENTITY MAC IS
33 GENERIC(
34 Input_SZ_A : INTEGER := 8;
35 Input_SZ_B : INTEGER := 8;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37
38 );
39 PORT(
40 clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clr_MAC : IN STD_LOGIC;
43 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
44 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
45 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
46 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
47 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
48 );
49 END MAC;
50
51
52
53
54 ARCHITECTURE ar_MAC OF MAC IS
55
56 SIGNAL add, mult : STD_LOGIC;
57 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
58
59 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
62
63 SIGNAL MACMUXsel : STD_LOGIC;
64 SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65 SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
66
67 SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
68 SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
69
70 SIGNAL MACMUX2sel : STD_LOGIC;
71
72 SIGNAL add_D : STD_LOGIC;
73 SIGNAL add_D_D : STD_LOGIC;
74 SIGNAL mult_D : STD_LOGIC;
75 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
76 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
77
78 -- SIGNAL OP1_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
79 -- SIGNAL OP2_2C_D_reg : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
80
81 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
82 SIGNAL MACMUXsel_D : STD_LOGIC;
83 SIGNAL MACMUXsel_D_D : STD_LOGIC;
84 SIGNAL MACMUX2sel_D : STD_LOGIC;
85 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
86 SIGNAL MACMUX2sel_D_D_D : STD_LOGIC;
87 SIGNAL clr_MAC_D : STD_LOGIC;
88 SIGNAL clr_MAC_D_D : STD_LOGIC;
89 SIGNAL clr_MAC_D_D_D : STD_LOGIC;
90 SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL MAC_MUL_ADD_2C_D_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
92
93 SIGNAL load_mult_result : STD_LOGIC;
94 SIGNAL load_mult_result_D : STD_LOGIC;
95 SIGNAL load_mult_result_D_D : STD_LOGIC;
96
97 BEGIN
98
99
100
101
102 --==============================================================
103 --=============M A C C O N T R O L E R=========================
104 --==============================================================
105 MAC_CONTROLER1 : MAC_CONTROLER
106 PORT MAP(
107 ctrl => MAC_MUL_ADD,
108 MULT => mult,
109 ADD => add,
110 LOAD_ADDER => load_mult_result,
111 MACMUX_sel => MACMUXsel,
112 MACMUX2_sel => MACMUX2sel
113
114 );
115 --==============================================================
116
117
118 --==============================================================
119 --===================TWO COMPLEMENTERS==========================
120 --==============================================================
121 gen_comp : IF COMP_EN = 0 GENERATE
122 TWO_COMPLEMENTER1 : TwoComplementer
123 GENERIC MAP(
124 Input_SZ => Input_SZ_A
125 )
126 PORT MAP(
127 clk => clk,
128 reset => reset,
129 clr => clr_MAC,
130 TwoComp => Comp_2C(0),
131 OP => OP1,
132 RES => OP1_2C
133 );
134
135 TWO_COMPLEMENTER2 : TwoComplementer
136 GENERIC MAP(
137 Input_SZ => Input_SZ_B
138 )
139 PORT MAP(
140 clk => clk,
141 reset => reset,
142 clr => clr_MAC,
143 TwoComp => Comp_2C(1),
144 OP => OP2,
145 RES => OP2_2C
146 );
147 END GENERATE gen_comp;
148
149 no_gen_comp : IF COMP_EN = 1 GENERATE
150 process(clk,reset)
151 begin
152 if(reset='0')then
153 OP1_2C <= (others => '0');
154 OP2_2C <= (others => '0');
155 elsif clk'event and clk='1' then
156 if clr_MAC = '1' then
157 OP1_2C <= (others => '0');
158 OP2_2C <= (others => '0');
159 else
160 OP1_2C <= OP1;
161 OP2_2C <= OP2;
162 end if;
163 end if;
164 end process;
165
166 END GENERATE no_gen_comp;
167 --==============================================================
168
169 --==============================================================
170 --=============M U L T I P L I E R==============================
171 --==============================================================
172
173 multREG0 : MAC_REG
174 GENERIC MAP(size => 1)
175 PORT MAP(
176 reset => reset,
177 clk => clk,
178 D(0) => mult,
179 Q(0) => mult_D
180 );
181
182 Multiplieri_nst : Multiplier
183 GENERIC MAP(
184 Input_SZ_A => Input_SZ_A,
185 Input_SZ_B => Input_SZ_B
186 )
187 PORT MAP(
188 clk => clk,
189 reset => reset,
190 mult => mult_D,
191 OP1 => OP1_2C,
192 OP2 => OP2_2C,
193 RES => MULTout
194 );
195
196 OP1REG : MAC_REG
197 GENERIC MAP(size => Input_SZ_A)
198 PORT MAP(
199 reset => reset,
200 clk => clk,
201 D => OP1_2C,
202 Q => OP1_2C_D
203 );
204
205 OP2REG : MAC_REG
206 GENERIC MAP(size => Input_SZ_B)
207 PORT MAP(
208 reset => reset,
209 clk => clk,
210 D => OP2_2C,
211 Q => OP2_2C_D
212 );
213
214 --==============================================================
215
216 --==============================================================
217 --======================M A C M U X ===========================
218 --==============================================================
219
220 OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
221 OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
222
223 MACMUXselREG0 : MAC_REG
224 GENERIC MAP(size => 1)
225 PORT MAP(
226 reset => reset,
227 clk => clk,
228 D(0) => MACMUXsel,
229 Q(0) => MACMUXsel_D
230 );
231
232 MACMUXselREG1 : MAC_REG
233 GENERIC MAP(size => 1)
234 PORT MAP(
235 reset => reset,
236 clk => clk,
237 D(0) => MACMUXsel_D,
238 Q(0) => MACMUXsel_D_D
239 );
240
241 MACMUX_inst : MAC_MUX
242 GENERIC MAP(
243 Input_SZ_A => Input_SZ_A+Input_SZ_B,
244 Input_SZ_B => Input_SZ_A+Input_SZ_B
245
246 )
247 PORT MAP(
248 sel => MACMUXsel_D_D,
249 INA1 => ADDERout,
250 INA2 => OP2_2C_D_Resz,
251 INB1 => MULTout,
252 INB2 => OP1_2C_D_Resz,
253 OUTA => ADDERinA,
254 OUTB => ADDERinB
255 );
256
257 --==============================================================
258
259 --==============================================================
260 --======================A D D E R ==============================
261 --==============================================================
262
263 clr_MACREG0 : MAC_REG
264 GENERIC MAP(size => 1)
265 PORT MAP(
266 reset => reset,
267 clk => clk,
268 D(0) => clr_MAC,
269 Q(0) => clr_MAC_D
270 );
271
272 clr_MACREG1 : MAC_REG
273 GENERIC MAP(size => 1)
274 PORT MAP(
275 reset => reset,
276 clk => clk,
277 D(0) => clr_MAC_D,
278 Q(0) => clr_MAC_D_D
279 );
280
281 addREG0 : MAC_REG
282 GENERIC MAP(size => 1)
283 PORT MAP(
284 reset => reset,
285 clk => clk,
286 D(0) => add,
287 Q(0) => add_D
288 );
289
290 addREG1 : MAC_REG
291 GENERIC MAP(size => 1)
292 PORT MAP(
293 reset => reset,
294 clk => clk,
295 D(0) => add_D,
296 Q(0) => add_D_D
297 );
298
299 load_mult_resultREG : MAC_REG
300 GENERIC MAP(size => 1)
301 PORT MAP(
302 reset => reset,
303 clk => clk,
304 D(0) => load_mult_result,
305 Q(0) => load_mult_result_D
306 );
307
308 load_mult_resultREG1 : MAC_REG
309 GENERIC MAP(size => 1)
310 PORT MAP(
311 reset => reset,
312 clk => clk,
313 D(0) => load_mult_result_D,
314 Q(0) => load_mult_result_D_D
315 );
316
317 adder_inst : Adder
318 GENERIC MAP(
319 Input_SZ_A => Input_SZ_A+Input_SZ_B,
320 Input_SZ_B => Input_SZ_A+Input_SZ_B
321 )
322 PORT MAP(
323 clk => clk,
324 reset => reset,
325 clr => clr_MAC_D_D,
326 load => load_mult_result_D_D,
327 add => add_D_D,
328 OP1 => ADDERinA,
329 OP2 => ADDERinB,
330 RES => ADDERout
331 );
332
333 --==============================================================
334
335 --==============================================================
336 --======================M A C M U X2 ==========================
337 --==============================================================
338
339 MULToutREG : MAC_REG
340 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
341 PORT MAP(
342 reset => reset,
343 clk => clk,
344 D => MULTout,
345 Q => MULTout_D
346 );
347
348 MACMUX2selREG : MAC_REG
349 GENERIC MAP(size => 1)
350 PORT MAP(
351 reset => reset,
352 clk => clk,
353 D(0) => MACMUX2sel,
354 Q(0) => MACMUX2sel_D
355 );
356
357 MACMUX2selREG2_0 : MAC_REG
358 GENERIC MAP(size => 1)
359 PORT MAP(
360 reset => reset,
361 clk => clk,
362 D(0) => MACMUX2sel_D,
363 Q(0) => MACMUX2sel_D_D
364 );
365
366 MACMUX2selREG2_1 : MAC_REG
367 GENERIC MAP(size => 1)
368 PORT MAP(
369 reset => reset,
370 clk => clk,
371 D(0) => MACMUX2sel_D_D,
372 Q(0) => MACMUX2sel_D_D_D
373 );
374
375 MAC_MUX2_inst : MAC_MUX2
376 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
377 PORT MAP(
378 sel => MACMUX2sel_D_D_D,
379 RES2 => MULTout_D,
380 RES1 => ADDERout,
381 RES => RES
382 );
383 --==============================================================
384
385 END ar_MAC; No newline at end of file
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