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update leon3_soc.vhd (add "ENTITY gaisler" in front of each instantiation of leon3s and leon3ft)
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1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 LIBRARY iap;
43 LIBRARY iap;
44 USE iap.memctrl.ALL;
44 USE iap.memctrl.ALL;
45
45
46
46
47 ENTITY leon3_soc IS
47 ENTITY leon3_soc IS
48 GENERIC (
48 GENERIC (
49 fabtech : INTEGER := apa3e;
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
51 padtech : INTEGER := inferred;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
55 pclow : INTEGER := 2;
56 --
56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 0;
60 --
60 --
61 NB_CPU : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
69 --
69 --
70 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_MASTER : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
73 --
73 --
74 ADDRESS_SIZE : INTEGER := 20;
74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0
75 USES_IAP_MEMCTRLR : INTEGER := 0
76
76
77 );
77 );
78 PORT (
78 PORT (
79 clk : IN STD_ULOGIC;
79 clk : IN STD_ULOGIC;
80 reset : IN STD_ULOGIC;
80 reset : IN STD_ULOGIC;
81
81
82 errorn : OUT STD_ULOGIC;
82 errorn : OUT STD_ULOGIC;
83
83
84 -- UART AHB ---------------------------------------------------------------
84 -- UART AHB ---------------------------------------------------------------
85 ahbrxd : IN STD_ULOGIC; -- DSU rx data
85 ahbrxd : IN STD_ULOGIC; -- DSU rx data
86 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
86 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
87
87
88 -- UART APB ---------------------------------------------------------------
88 -- UART APB ---------------------------------------------------------------
89 urxd1 : IN STD_ULOGIC; -- UART1 rx data
89 urxd1 : IN STD_ULOGIC; -- UART1 rx data
90 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
90 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
91
91
92 -- RAM --------------------------------------------------------------------
92 -- RAM --------------------------------------------------------------------
93 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
93 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
94 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 nSRAM_BE0 : OUT STD_LOGIC;
95 nSRAM_BE0 : OUT STD_LOGIC;
96 nSRAM_BE1 : OUT STD_LOGIC;
96 nSRAM_BE1 : OUT STD_LOGIC;
97 nSRAM_BE2 : OUT STD_LOGIC;
97 nSRAM_BE2 : OUT STD_LOGIC;
98 nSRAM_BE3 : OUT STD_LOGIC;
98 nSRAM_BE3 : OUT STD_LOGIC;
99 nSRAM_WE : OUT STD_LOGIC;
99 nSRAM_WE : OUT STD_LOGIC;
100 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
100 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 nSRAM_OE : OUT STD_LOGIC;
101 nSRAM_OE : OUT STD_LOGIC;
102 nSRAM_READY : IN STD_LOGIC;
102 nSRAM_READY : IN STD_LOGIC;
103 SRAM_MBE : INOUT STD_LOGIC;
103 SRAM_MBE : INOUT STD_LOGIC;
104 -- APB --------------------------------------------------------------------
104 -- APB --------------------------------------------------------------------
105 apbi_ext : OUT apb_slv_in_type;
105 apbi_ext : OUT apb_slv_in_type;
106 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
106 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
107 -- AHB_Slave --------------------------------------------------------------
107 -- AHB_Slave --------------------------------------------------------------
108 ahbi_s_ext : OUT ahb_slv_in_type;
108 ahbi_s_ext : OUT ahb_slv_in_type;
109 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
109 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
110 -- AHB_Master -------------------------------------------------------------
110 -- AHB_Master -------------------------------------------------------------
111 ahbi_m_ext : OUT AHB_Mst_In_Type;
111 ahbi_m_ext : OUT AHB_Mst_In_Type;
112 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
112 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
113
113
114 );
114 );
115 END;
115 END;
116
116
117 ARCHITECTURE Behavioral OF leon3_soc IS
117 ARCHITECTURE Behavioral OF leon3_soc IS
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 -- CONFIG -------------------------------------------------------------------
120 -- CONFIG -------------------------------------------------------------------
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122
122
123 -- Clock generator
123 -- Clock generator
124 CONSTANT CFG_CLKMUL : INTEGER := (1);
124 CONSTANT CFG_CLKMUL : INTEGER := (1);
125 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
125 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
126 CONSTANT CFG_OCLKDIV : INTEGER := (1);
126 CONSTANT CFG_OCLKDIV : INTEGER := (1);
127 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
127 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
128 -- LEON3 processor core
128 -- LEON3 processor core
129 CONSTANT CFG_LEON3 : INTEGER := 1;
129 CONSTANT CFG_LEON3 : INTEGER := 1;
130 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
130 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
131 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
131 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
132 CONSTANT CFG_V8 : INTEGER := 0;
132 CONSTANT CFG_V8 : INTEGER := 0;
133 CONSTANT CFG_MAC : INTEGER := 0;
133 CONSTANT CFG_MAC : INTEGER := 0;
134 CONSTANT CFG_SVT : INTEGER := 0;
134 CONSTANT CFG_SVT : INTEGER := 0;
135 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
135 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
136 CONSTANT CFG_LDDEL : INTEGER := (1);
136 CONSTANT CFG_LDDEL : INTEGER := (1);
137 CONSTANT CFG_NWP : INTEGER := (0);
137 CONSTANT CFG_NWP : INTEGER := (0);
138 CONSTANT CFG_PWD : INTEGER := 1*2;
138 CONSTANT CFG_PWD : INTEGER := 1*2;
139 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
139 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
140 -- 1*(8 + 16 * 0) => grfpu-light
140 -- 1*(8 + 16 * 0) => grfpu-light
141 -- 1*(8 + 16 * 1) => netlist
141 -- 1*(8 + 16 * 1) => netlist
142 -- 0*(8 + 16 * 0) => No FPU
142 -- 0*(8 + 16 * 0) => No FPU
143 -- 0*(8 + 16 * 1) => No FPU;
143 -- 0*(8 + 16 * 1) => No FPU;
144 CONSTANT CFG_ICEN : INTEGER := 1;
144 CONSTANT CFG_ICEN : INTEGER := 1;
145 CONSTANT CFG_ISETS : INTEGER := 1;
145 CONSTANT CFG_ISETS : INTEGER := 1;
146 CONSTANT CFG_ISETSZ : INTEGER := 4;
146 CONSTANT CFG_ISETSZ : INTEGER := 4;
147 CONSTANT CFG_ILINE : INTEGER := 4;
147 CONSTANT CFG_ILINE : INTEGER := 4;
148 CONSTANT CFG_IREPL : INTEGER := 0;
148 CONSTANT CFG_IREPL : INTEGER := 0;
149 CONSTANT CFG_ILOCK : INTEGER := 0;
149 CONSTANT CFG_ILOCK : INTEGER := 0;
150 CONSTANT CFG_ILRAMEN : INTEGER := 0;
150 CONSTANT CFG_ILRAMEN : INTEGER := 0;
151 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
151 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
152 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
152 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
153 CONSTANT CFG_DCEN : INTEGER := 1;
153 CONSTANT CFG_DCEN : INTEGER := 1;
154 CONSTANT CFG_DSETS : INTEGER := 1;
154 CONSTANT CFG_DSETS : INTEGER := 1;
155 CONSTANT CFG_DSETSZ : INTEGER := 4;
155 CONSTANT CFG_DSETSZ : INTEGER := 4;
156 CONSTANT CFG_DLINE : INTEGER := 4;
156 CONSTANT CFG_DLINE : INTEGER := 4;
157 CONSTANT CFG_DREPL : INTEGER := 0;
157 CONSTANT CFG_DREPL : INTEGER := 0;
158 CONSTANT CFG_DLOCK : INTEGER := 0;
158 CONSTANT CFG_DLOCK : INTEGER := 0;
159 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
159 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
160 CONSTANT CFG_DLRAMEN : INTEGER := 0;
160 CONSTANT CFG_DLRAMEN : INTEGER := 0;
161 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
161 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
162 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
162 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
163 CONSTANT CFG_MMUEN : INTEGER := 0;
163 CONSTANT CFG_MMUEN : INTEGER := 0;
164 CONSTANT CFG_ITLBNUM : INTEGER := 2;
164 CONSTANT CFG_ITLBNUM : INTEGER := 2;
165 CONSTANT CFG_DTLBNUM : INTEGER := 2;
165 CONSTANT CFG_DTLBNUM : INTEGER := 2;
166 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
166 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
167 CONSTANT CFG_TLB_REP : INTEGER := 1;
167 CONSTANT CFG_TLB_REP : INTEGER := 1;
168
168
169 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
169 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
170 CONSTANT CFG_ITBSZ : INTEGER := 0;
170 CONSTANT CFG_ITBSZ : INTEGER := 0;
171 CONSTANT CFG_ATBSZ : INTEGER := 0;
171 CONSTANT CFG_ATBSZ : INTEGER := 0;
172
172
173 -- AMBA settings
173 -- AMBA settings
174 CONSTANT CFG_DEFMST : INTEGER := (0);
174 CONSTANT CFG_DEFMST : INTEGER := (0);
175 CONSTANT CFG_RROBIN : INTEGER := 1;
175 CONSTANT CFG_RROBIN : INTEGER := 1;
176 CONSTANT CFG_SPLIT : INTEGER := 0;
176 CONSTANT CFG_SPLIT : INTEGER := 0;
177 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
177 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
178 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
178 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
179
179
180 -- DSU UART
180 -- DSU UART
181 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
181 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
182
182
183 -- LEON2 memory controller
183 -- LEON2 memory controller
184 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
184 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
185
185
186 -- UART 1
186 -- UART 1
187 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
187 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
188 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
188 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
189
189
190 -- LEON3 interrupt controller
190 -- LEON3 interrupt controller
191 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
191 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
192
192
193 -- Modular timer
193 -- Modular timer
194 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
194 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
195 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
195 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
196 CONSTANT CFG_GPT_SW : INTEGER := (8);
196 CONSTANT CFG_GPT_SW : INTEGER := (8);
197 CONSTANT CFG_GPT_TW : INTEGER := (32);
197 CONSTANT CFG_GPT_TW : INTEGER := (32);
198 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
198 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
199 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
199 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
200 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
200 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
201 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
201 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
202 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205 -- SIGNALs
205 -- SIGNALs
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
207 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
208 -- CLK & RST --
208 -- CLK & RST --
209 SIGNAL clk2x : STD_ULOGIC;
209 SIGNAL clk2x : STD_ULOGIC;
210 SIGNAL clkmn : STD_ULOGIC;
210 SIGNAL clkmn : STD_ULOGIC;
211 SIGNAL clkm : STD_ULOGIC;
211 SIGNAL clkm : STD_ULOGIC;
212 SIGNAL rstn : STD_ULOGIC;
212 SIGNAL rstn : STD_ULOGIC;
213 SIGNAL rstraw : STD_ULOGIC;
213 SIGNAL rstraw : STD_ULOGIC;
214 SIGNAL pciclk : STD_ULOGIC;
214 SIGNAL pciclk : STD_ULOGIC;
215 SIGNAL sdclkl : STD_ULOGIC;
215 SIGNAL sdclkl : STD_ULOGIC;
216 SIGNAL cgi : clkgen_in_type;
216 SIGNAL cgi : clkgen_in_type;
217 SIGNAL cgo : clkgen_out_type;
217 SIGNAL cgo : clkgen_out_type;
218 --- AHB / APB
218 --- AHB / APB
219 SIGNAL apbi : apb_slv_in_type;
219 SIGNAL apbi : apb_slv_in_type;
220 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
220 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
221 SIGNAL ahbsi : ahb_slv_in_type;
221 SIGNAL ahbsi : ahb_slv_in_type;
222 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
222 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
223 SIGNAL ahbmi : ahb_mst_in_type;
223 SIGNAL ahbmi : ahb_mst_in_type;
224 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
224 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
225 --UART
225 --UART
226 SIGNAL ahbuarti : uart_in_type;
226 SIGNAL ahbuarti : uart_in_type;
227 SIGNAL ahbuarto : uart_out_type;
227 SIGNAL ahbuarto : uart_out_type;
228 SIGNAL apbuarti : uart_in_type;
228 SIGNAL apbuarti : uart_in_type;
229 SIGNAL apbuarto : uart_out_type;
229 SIGNAL apbuarto : uart_out_type;
230 --MEM CTRLR
230 --MEM CTRLR
231 SIGNAL memi : memory_in_type;
231 SIGNAL memi : memory_in_type;
232 SIGNAL memo : memory_out_type;
232 SIGNAL memo : memory_out_type;
233 SIGNAL wpo : wprot_out_type;
233 SIGNAL wpo : wprot_out_type;
234 SIGNAL sdo : sdram_out_type;
234 SIGNAL sdo : sdram_out_type;
235 SIGNAL mbe : STD_LOGIC; -- enable memory programming
235 SIGNAL mbe : STD_LOGIC; -- enable memory programming
236 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
236 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
237 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
237 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
238 SIGNAL nSRAM_OE_s : STD_LOGIC;
238 SIGNAL nSRAM_OE_s : STD_LOGIC;
239 --IRQ
239 --IRQ
240 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
240 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
241 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
241 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
242 --Timer
242 --Timer
243 SIGNAL gpti : gptimer_in_type;
243 SIGNAL gpti : gptimer_in_type;
244 SIGNAL gpto : gptimer_out_type;
244 SIGNAL gpto : gptimer_out_type;
245 --DSU
245 --DSU
246 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
246 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
247 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
247 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
248 SIGNAL dsui : dsu_in_type;
248 SIGNAL dsui : dsu_in_type;
249 SIGNAL dsuo : dsu_out_type;
249 SIGNAL dsuo : dsu_out_type;
250 -----------------------------------------------------------------------------
250 -----------------------------------------------------------------------------
251
251
252
252
253 BEGIN
253 BEGIN
254
254
255
255
256 ----------------------------------------------------------------------
256 ----------------------------------------------------------------------
257 --- Reset and Clock generation -------------------------------------
257 --- Reset and Clock generation -------------------------------------
258 ----------------------------------------------------------------------
258 ----------------------------------------------------------------------
259
259
260 cgi.pllctrl <= "00";
260 cgi.pllctrl <= "00";
261 cgi.pllrst <= rstraw;
261 cgi.pllrst <= rstraw;
262
262
263 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
263 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
264
264
265 clkgen0 : clkgen -- clock generator
265 clkgen0 : clkgen -- clock generator
266 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
266 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
267 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
267 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
268 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
268 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
269
269
270 ----------------------------------------------------------------------
270 ----------------------------------------------------------------------
271 --- LEON3 processor / DSU / IRQ ------------------------------------
271 --- LEON3 processor / DSU / IRQ ------------------------------------
272 ----------------------------------------------------------------------
272 ----------------------------------------------------------------------
273
273
274 l3 : IF CFG_LEON3 = 1 GENERATE
274 l3 : IF CFG_LEON3 = 1 GENERATE
275 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
275 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
276 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
276 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
277 u0 : leon3s -- LEON3 processor
277 u0 : ENTITY gaisler.leon3s -- LEON3 processor
278 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
278 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
279 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
279 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
280 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
280 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
281 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
281 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
282 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
282 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
283 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
283 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
284 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
284 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
285 irqi(i), irqo(i), dbgi(i), dbgo(i));
285 irqi(i), irqo(i), dbgi(i), dbgo(i));
286 END GENERATE leon3_non_radhard;
286 END GENERATE leon3_non_radhard;
287
287
288 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
288 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
289 cpu : leon3ft
289 cpu : ENTITY gaisler.leon3ft
290 GENERIC MAP (
290 GENERIC MAP (
291 HINDEX => i, --: integer; --CPU_HINDEX,
291 HINDEX => i, --: integer; --CPU_HINDEX,
292 FABTECH => fabtech, --CFG_TECH,
292 FABTECH => fabtech, --CFG_TECH,
293 MEMTECH => memtech, --CFG_TECH,
293 MEMTECH => memtech, --CFG_TECH,
294 NWINDOWS => CFG_NWIN, --CFG_NWIN,
294 NWINDOWS => CFG_NWIN, --CFG_NWIN,
295 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
295 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
296 FPU => CFG_FPU, --CFG_FPU,
296 FPU => CFG_FPU, --CFG_FPU,
297 V8 => CFG_V8, --CFG_V8,
297 V8 => CFG_V8, --CFG_V8,
298 CP => 0, --CFG_CP,
298 CP => 0, --CFG_CP,
299 MAC => CFG_MAC, --CFG_MAC,
299 MAC => CFG_MAC, --CFG_MAC,
300 PCLOW => pclow, --CFG_PCLOW,
300 PCLOW => pclow, --CFG_PCLOW,
301 NOTAG => 0, --CFG_NOTAG,
301 NOTAG => 0, --CFG_NOTAG,
302 NWP => CFG_NWP, --CFG_NWP,
302 NWP => CFG_NWP, --CFG_NWP,
303 ICEN => CFG_ICEN, --CFG_ICEN,
303 ICEN => CFG_ICEN, --CFG_ICEN,
304 IREPL => CFG_IREPL, --CFG_IREPL,
304 IREPL => CFG_IREPL, --CFG_IREPL,
305 ISETS => CFG_ISETS, --CFG_ISETS,
305 ISETS => CFG_ISETS, --CFG_ISETS,
306 ILINESIZE => CFG_ILINE, --CFG_ILINE,
306 ILINESIZE => CFG_ILINE, --CFG_ILINE,
307 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
307 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
308 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
308 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
309 DCEN => CFG_DCEN, --CFG_DCEN,
309 DCEN => CFG_DCEN, --CFG_DCEN,
310 DREPL => CFG_DREPL, --CFG_DREPL,
310 DREPL => CFG_DREPL, --CFG_DREPL,
311 DSETS => CFG_DSETS, --CFG_DSETS,
311 DSETS => CFG_DSETS, --CFG_DSETS,
312 DLINESIZE => CFG_DLINE, --CFG_DLINE,
312 DLINESIZE => CFG_DLINE, --CFG_DLINE,
313 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
313 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
314 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
314 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
315 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
315 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
316 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
316 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
317 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
317 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
318 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
318 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
319 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
319 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
320 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
320 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
321 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
321 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
322 MMUEN => CFG_MMUEN, --CFG_MMUEN,
322 MMUEN => CFG_MMUEN, --CFG_MMUEN,
323 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
323 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
324 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
324 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
325 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
325 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
326 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
326 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
327 LDDEL => CFG_LDDEL, --CFG_LDDEL,
327 LDDEL => CFG_LDDEL, --CFG_LDDEL,
328 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
328 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
329 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
329 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
330 PWD => CFG_PWD, --CFG_PWD,
330 PWD => CFG_PWD, --CFG_PWD,
331 SVT => CFG_SVT, --CFG_SVT,
331 SVT => CFG_SVT, --CFG_SVT,
332 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
332 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
333 SMP => CFG_NCPU-1, --CFG_NCPU-1,
333 SMP => CFG_NCPU-1, --CFG_NCPU-1,
334 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
334 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
335 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
335 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
336 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
336 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
337 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
337 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
338 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
338 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
339 CACHED => 0, --: integer; --CFG_DFIXED,
339 CACHED => 0, --: integer; --CFG_DFIXED,
340 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
340 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
341 SCANTEST => 0, --: integer; --CFG_SCANTEST,
341 SCANTEST => 0, --: integer; --CFG_SCANTEST,
342 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
342 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
343 BP => 1) --CFG_BP
343 BP => 1) --CFG_BP
344 PORT MAP ( --
344 PORT MAP ( --
345 rstn => rstn, --rst_n,
345 rstn => rstn, --rst_n,
346 clk => clkm, --clk,
346 clk => clkm, --clk,
347 ahbi => ahbmi, --ahbmi,
347 ahbi => ahbmi, --ahbmi,
348 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
348 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
349 ahbsi => ahbsi, --ahbsi,
349 ahbsi => ahbsi, --ahbsi,
350 ahbso => ahbso, --ahbso,
350 ahbso => ahbso, --ahbso,
351 irqi => irqi(i), --irqi(CPU_HINDEX),
351 irqi => irqi(i), --irqi(CPU_HINDEX),
352 irqo => irqo(i), --irqo(CPU_HINDEX),
352 irqo => irqo(i), --irqo(CPU_HINDEX),
353 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
353 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
354 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
354 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
355 gclk => clkm --clk
355 gclk => clkm --clk
356 );
356 );
357 END GENERATE leon3_radhard_i;
357 END GENERATE leon3_radhard_i;
358
358
359 END GENERATE;
359 END GENERATE;
360 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
360 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
361
361
362 dsugen : IF CFG_DSU = 1 GENERATE
362 dsugen : IF CFG_DSU = 1 GENERATE
363 dsu0 : dsu3 -- LEON3 Debug Support Unit
363 dsu0 : dsu3 -- LEON3 Debug Support Unit
364 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
364 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
365 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
365 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
366 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
366 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
367 dsui.enable <= '1';
367 dsui.enable <= '1';
368 dsui.break <= '0';
368 dsui.break <= '0';
369 END GENERATE;
369 END GENERATE;
370 END GENERATE;
370 END GENERATE;
371
371
372 nodsu : IF CFG_DSU = 0 GENERATE
372 nodsu : IF CFG_DSU = 0 GENERATE
373 ahbso(2) <= ahbs_none;
373 ahbso(2) <= ahbs_none;
374 dsuo.tstop <= '0';
374 dsuo.tstop <= '0';
375 dsuo.active <= '0';
375 dsuo.active <= '0';
376 END GENERATE;
376 END GENERATE;
377
377
378 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
378 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
379 irqctrl0 : irqmp -- interrupt controller
379 irqctrl0 : irqmp -- interrupt controller
380 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
380 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
381 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
381 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
382 END GENERATE;
382 END GENERATE;
383 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
383 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
384 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
384 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
385 irqi(i).irl <= "0000";
385 irqi(i).irl <= "0000";
386 END GENERATE;
386 END GENERATE;
387 apbo(2) <= apb_none;
387 apbo(2) <= apb_none;
388 END GENERATE;
388 END GENERATE;
389
389
390 ----------------------------------------------------------------------
390 ----------------------------------------------------------------------
391 --- Memory controllers ---------------------------------------------
391 --- Memory controllers ---------------------------------------------
392 ----------------------------------------------------------------------
392 ----------------------------------------------------------------------
393 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
393 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
394 memctrlr : mctrl GENERIC MAP (
394 memctrlr : mctrl GENERIC MAP (
395 hindex => 0,
395 hindex => 0,
396 pindex => 0,
396 pindex => 0,
397 paddr => 0,
397 paddr => 0,
398 srbanks => 1
398 srbanks => 1
399 )
399 )
400 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
400 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
401 memi.bexcn <= '1';
401 memi.bexcn <= '1';
402 memi.brdyn <= '1';
402 memi.brdyn <= '1';
403
403
404 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
404 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
405 nSRAM_OE_s <= memo.ramoen(0);
405 nSRAM_OE_s <= memo.ramoen(0);
406 END GENERATE;
406 END GENERATE;
407
407
408 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
408 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
409 memctrlr : srctrle_0ws
409 memctrlr : srctrle_0ws
410 GENERIC MAP(
410 GENERIC MAP(
411 hindex => 0,
411 hindex => 0,
412 pindex => 0,
412 pindex => 0,
413 paddr => 0,
413 paddr => 0,
414 srbanks => 2,
414 srbanks => 2,
415 banksz => 8, --512k * 32
415 banksz => 8, --512k * 32
416 rmw => 1,
416 rmw => 1,
417 --Aeroflex memory generics:
417 --Aeroflex memory generics:
418 mprog => 1, -- program memory by default values after reset
418 mprog => 1, -- program memory by default values after reset
419 mpsrate => 12, -- default scrub rate period
419 mpsrate => 12, -- default scrub rate period
420 mpb2s => 4, -- default busy to scrub delay
420 mpb2s => 4, -- default busy to scrub delay
421 mpapb => 1, -- instantiate apb register
421 mpapb => 1, -- instantiate apb register
422 mchipcnt => 2,
422 mchipcnt => 2,
423 mpenall => 1 -- when 0 program only E1 chip, else program all dies
423 mpenall => 1 -- when 0 program only E1 chip, else program all dies
424 )
424 )
425 PORT MAP (
425 PORT MAP (
426 rst => rstn,
426 rst => rstn,
427 clk => clkm,
427 clk => clkm,
428 ahbsi => ahbsi,
428 ahbsi => ahbsi,
429 ahbso => ahbso(0),
429 ahbso => ahbso(0),
430 apbi => apbi,
430 apbi => apbi,
431 apbo => apbo(0),
431 apbo => apbo(0),
432 sri => memi,
432 sri => memi,
433 sro => memo,
433 sro => memo,
434 --Aeroflex memory signals:
434 --Aeroflex memory signals:
435 ucerr => OPEN, -- uncorrectable error signal
435 ucerr => OPEN, -- uncorrectable error signal
436 mbe => mbe, -- enable memory programming
436 mbe => mbe, -- enable memory programming
437 mbe_drive => mbe_drive -- drive the MBE memory signal
437 mbe_drive => mbe_drive -- drive the MBE memory signal
438 );
438 );
439
439
440 memi.brdyn <= nSRAM_READY;
440 memi.brdyn <= nSRAM_READY;
441
441
442 mbe_pad : iopad
442 mbe_pad : iopad
443 GENERIC MAP(tech => padtech)
443 GENERIC MAP(tech => padtech)
444 PORT MAP(pad => SRAM_MBE,
444 PORT MAP(pad => SRAM_MBE,
445 i => mbe,
445 i => mbe,
446 en => mbe_drive,
446 en => mbe_drive,
447 o => memi.bexcn);
447 o => memi.bexcn);
448
448
449 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
449 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
450 nSRAM_OE_s <= memo.oen;
450 nSRAM_OE_s <= memo.oen;
451
451
452 END GENERATE;
452 END GENERATE;
453
453
454
454
455 memi.writen <= '1';
455 memi.writen <= '1';
456 memi.wrn <= "1111";
456 memi.wrn <= "1111";
457 memi.bwidth <= "10";
457 memi.bwidth <= "10";
458
458
459 bdr : FOR i IN 0 TO 3 GENERATE
459 bdr : FOR i IN 0 TO 3 GENERATE
460 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
460 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
461 PORT MAP (
461 PORT MAP (
462 data(31-i*8 DOWNTO 24-i*8),
462 data(31-i*8 DOWNTO 24-i*8),
463 memo.data(31-i*8 DOWNTO 24-i*8),
463 memo.data(31-i*8 DOWNTO 24-i*8),
464 memo.bdrive(i),
464 memo.bdrive(i),
465 memi.data(31-i*8 DOWNTO 24-i*8));
465 memi.data(31-i*8 DOWNTO 24-i*8));
466 END GENERATE;
466 END GENERATE;
467
467
468 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
468 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
469 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
469 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
470 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
470 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
471 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
471 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
472 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
472 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
473 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
473 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
474 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
474 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
475 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
475 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
476 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
476 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
477
477
478
478
479
479
480 ----------------------------------------------------------------------
480 ----------------------------------------------------------------------
481 --- AHB CONTROLLER -------------------------------------------------
481 --- AHB CONTROLLER -------------------------------------------------
482 ----------------------------------------------------------------------
482 ----------------------------------------------------------------------
483 ahb0 : ahbctrl -- AHB arbiter/multiplexer
483 ahb0 : ahbctrl -- AHB arbiter/multiplexer
484 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
484 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
485 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
485 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
486 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
486 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
487 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
487 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
488
488
489 ----------------------------------------------------------------------
489 ----------------------------------------------------------------------
490 --- AHB UART -------------------------------------------------------
490 --- AHB UART -------------------------------------------------------
491 ----------------------------------------------------------------------
491 ----------------------------------------------------------------------
492 dcomgen : IF CFG_AHB_UART = 1 GENERATE
492 dcomgen : IF CFG_AHB_UART = 1 GENERATE
493 dcom0 : ahbuart
493 dcom0 : ahbuart
494 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
494 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
495 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
495 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
496 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
496 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
497 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
497 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
498 END GENERATE;
498 END GENERATE;
499 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
499 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
500
500
501 ----------------------------------------------------------------------
501 ----------------------------------------------------------------------
502 --- APB Bridge -----------------------------------------------------
502 --- APB Bridge -----------------------------------------------------
503 ----------------------------------------------------------------------
503 ----------------------------------------------------------------------
504 apb0 : apbctrl -- AHB/APB bridge
504 apb0 : apbctrl -- AHB/APB bridge
505 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
505 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
506 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
506 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
507
507
508 ----------------------------------------------------------------------
508 ----------------------------------------------------------------------
509 --- GPT Timer ------------------------------------------------------
509 --- GPT Timer ------------------------------------------------------
510 ----------------------------------------------------------------------
510 ----------------------------------------------------------------------
511 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
511 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
512 timer0 : gptimer -- timer unit
512 timer0 : gptimer -- timer unit
513 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
513 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
514 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
514 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
515 nbits => CFG_GPT_TW)
515 nbits => CFG_GPT_TW)
516 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
516 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
517 gpti.dhalt <= dsuo.tstop;
517 gpti.dhalt <= dsuo.tstop;
518 gpti.extclk <= '0';
518 gpti.extclk <= '0';
519 END GENERATE;
519 END GENERATE;
520 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
520 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
521
521
522
522
523 ----------------------------------------------------------------------
523 ----------------------------------------------------------------------
524 --- APB UART -------------------------------------------------------
524 --- APB UART -------------------------------------------------------
525 ----------------------------------------------------------------------
525 ----------------------------------------------------------------------
526 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
526 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
527 uart1 : apbuart -- UART 1
527 uart1 : apbuart -- UART 1
528 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
528 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
529 fifosize => CFG_UART1_FIFO)
529 fifosize => CFG_UART1_FIFO)
530 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
530 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
531 apbuarti.rxd <= urxd1;
531 apbuarti.rxd <= urxd1;
532 apbuarti.extclk <= '0';
532 apbuarti.extclk <= '0';
533 utxd1 <= apbuarto.txd;
533 utxd1 <= apbuarto.txd;
534 apbuarti.ctsn <= '0';
534 apbuarti.ctsn <= '0';
535 END GENERATE;
535 END GENERATE;
536 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
536 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
537
537
538 -------------------------------------------------------------------------------
538 -------------------------------------------------------------------------------
539 -- AMBA BUS -------------------------------------------------------------------
539 -- AMBA BUS -------------------------------------------------------------------
540 -------------------------------------------------------------------------------
540 -------------------------------------------------------------------------------
541
541
542 -- APB --------------------------------------------------------------------
542 -- APB --------------------------------------------------------------------
543 apbi_ext <= apbi;
543 apbi_ext <= apbi;
544 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
544 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
545 max_16_apb : IF I + 5 < 16 GENERATE
545 max_16_apb : IF I + 5 < 16 GENERATE
546 apbo(I+5) <= apbo_ext(I+5);
546 apbo(I+5) <= apbo_ext(I+5);
547 END GENERATE max_16_apb;
547 END GENERATE max_16_apb;
548 END GENERATE all_apb;
548 END GENERATE all_apb;
549 -- AHB_Slave --------------------------------------------------------------
549 -- AHB_Slave --------------------------------------------------------------
550 ahbi_s_ext <= ahbsi;
550 ahbi_s_ext <= ahbsi;
551 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
551 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
552 max_16_ahbs : IF I + 3 < 16 GENERATE
552 max_16_ahbs : IF I + 3 < 16 GENERATE
553 ahbso(I+3) <= ahbo_s_ext(I+3);
553 ahbso(I+3) <= ahbo_s_ext(I+3);
554 END GENERATE max_16_ahbs;
554 END GENERATE max_16_ahbs;
555 END GENERATE all_ahbs;
555 END GENERATE all_ahbs;
556 -- AHB_Master -------------------------------------------------------------
556 -- AHB_Master -------------------------------------------------------------
557 ahbi_m_ext <= ahbmi;
557 ahbi_m_ext <= ahbmi;
558 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
558 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
559 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
559 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
560 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
560 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
561 END GENERATE max_16_ahbm;
561 END GENERATE max_16_ahbm;
562 END GENERATE all_ahbm;
562 END GENERATE all_ahbm;
563
563
564
564
565
565
566 END Behavioral; No newline at end of file
566 END Behavioral;
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