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ICI4 EGSE doesn't need anymore actell PLL uses gaisler clkgen....
Alexis Jeandet -
r220:9cd9574d2765 alexis
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1 #!/bin/bash
2 #"======================================================================================="
3 #"---------------------------------------------------------------------------------------"
4 #" LPP VHDL lib makeDirs "
5 #" Copyright (C) 2010 Laboratory of Plasmas Physic. "
6 #"======================================================================================="
7 #----------------------------------------------------------------------------------------
8 # This file is a part of the LPP VHDL IP LIBRARY
9 # Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
10 #
11 # This program is free software; you can redistribute it and/or modify
12 # it under the terms of the GNU General Public License as published by
13 # the Free Software Foundation; either version 3 of the License, or
14 # (at your option) any later version.
15 #
16 # This program is distributed in the hope that it will be useful,
17 # but WITHOUT ANY WARRANTY; without even the implied warranty of
18 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 # GNU General Public License for more details.
20 #
21 # You should have received a copy of the GNU General Public License
22 # along with this program; if not, write to the Free Software
23 # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #----------------------------------------------------------------------------------------
25
26 function fullpath() {
27 if test $# -gt 0
28 then
29 cd $1
30 echo `pwd`
31 fi
32 }
33
34 function relpath() {
35 if test $# -gt 1
36 then
37 source=`fullpath $1`
38 target=`fullpath $2`
39
40 common_part=$source # for now
41 result="" # for now
42
43 while [[ "${target#$common_part}" == "${target}" ]]; do
44 # no match, means that candidate common part is not correct
45 # go up one level (reduce common part)
46 common_part="$(dirname $common_part)"
47 # and record that we went back, with correct / handling
48 if [[ -z $result ]]; then
49 result=".."
50 else
51 result="../$result"
52 fi
53 done
54
55 if [[ $common_part == "/" ]]; then
56 # special case for root (no common path)
57 result="$result/"
58 fi
59
60 # since we now have identified the common part,
61 # compute the non-common part
62 forward_part="${target#$common_part}"
63
64 # and now stick all parts together
65 if [[ -n $result ]] && [[ -n $forward_part ]]; then
66 result="$result$forward_part"
67 elif [[ -n $forward_part ]]; then
68 # extra slash removal
69 result="${forward_part:1}"
70 fi
71
72 echo $result
73 fi
74 }
75
76 PATH1=`pwd`
77 echo `relpath $PATH1 $GRLIB` No newline at end of file
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@@ -1,282 +1,288
1 1 -- TOP_GSE.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5 library lpp;
6 6 use lpp.lpp_usb.all;
7 7 use lpp.Rocket_PCM_Encoder.all;
8 8 use lpp.iir_filter.all;
9 9 use lpp.general_purpose.all;
10 10 library techmap;
11 11 use techmap.gencomp.all;
12 12 use work.config.all;
13 13
14 14
15 15 entity TOP_EGSE2 is
16 16 generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64;Simu : integer :=0);
17 17 port(
18 18 Clock : in std_logic;
19 19 reset : in std_logic;
20 20 DataRTX : in std_logic;
21 21 DataRTX_echo : out std_logic;
22 22 SCLK : out std_logic;
23 23 Gate : out std_logic;
24 24 Major_Frame : out std_logic;
25 25 Minor_Frame : out std_logic;
26 26 if_clk : out STD_LOGIC;
27 27 flagb : in STD_LOGIC;
28 28 slwr : out STD_LOGIC;
29 29 slrd : out std_logic;
30 30 pktend : out STD_LOGIC;
31 31 sloe : out STD_LOGIC;
32 32 fdbusw : out std_logic_vector (7 downto 0);
33 33 fifoadr : out std_logic_vector (1 downto 0);
34 34 BUS0 : out std_logic;
35 35 BUS12 : out std_logic;
36 36 BUS13 : out std_logic;
37 37 BUS14 : out std_logic
38 38 );
39 39 end TOP_EGSE2;
40 40
41 41
42 42
43 43 architecture ar_TOP_EGSE2 of TOP_EGSE2 is
44 44
45 45 component CLKINT
46 46 port( A : in std_logic := 'U';
47 47 Y : out std_logic
48 48 );
49 49 end component;
50 50
51 51 signal clk : std_logic;
52 52 signal clk_48 : std_logic;
53 53 signal sclkint : std_logic;
54 54 signal RaZ : std_logic;
55 55 signal rstn : std_logic;
56 56 signal WordCount : integer range 0 to WordCnt-1;
57 57 signal WordClk : std_logic;
58 58 signal MinFCnt : integer range 0 to MinFCount-1;
59 59 signal MinF : std_logic;
60 60 signal MinFclk : std_logic;
61 61 signal MajF : std_logic;
62 62 signal GateLF : std_logic;
63 63 signal GateHF : std_logic;
64 64 signal GateDC : std_logic;
65 65 signal GateR : std_logic;
66 66 signal Gateint : std_logic;
67 67 signal NwDat : std_logic;
68 68 signal NwDatR : std_logic;
69 69 signal DATA : std_logic_vector(WordSize-1 downto 0);
70 70 signal MinFVector : std_logic_vector(WordSize-1 downto 0);
71 71
72 72 Signal PROTO_WEN : std_logic;
73 73 Signal PROTO_DATAIN : std_logic_vector (WordSize-1 downto 0);
74 74 Signal PROTO_FULL : std_logic;
75 75 Signal PROTO_WR : std_logic;
76 76 Signal PROTO_DATAOUT : std_logic_vector (WordSize-1 downto 0);
77 77
78 78 Signal clk80 : std_logic;
79 79
80 signal cgi : clkgen_in_type;
81 signal cgo : clkgen_out_type;
80 82
81 83
82 84 begin
83 85
84 86
85 87 DataRTX_echo <= DataRTX; --P48
86 88
87 89
88 90 ck_int0 : CLKINT
89 91 port map(Clock,clk_48);
90 92
91 DEFPLL: IF simu = 0 generate
92 PLL : entity work.PLL0
93 port map(
94 POWERDOWN => '1',
95 CLKA => clk_48,
96 LOCK => RaZ,
97 GLA => clk80,
98 GLB => clk --33.3MHz
99 );
100 end generate;
93 RaZ <= cgo.clklock;
101 94
95 CLKGEN : entity clkgen
96 generic map(
97 tech => CFG_CLKTECH,
98 clk_mul => CFG_CLKMUL,
99 clk_div => CFG_CLKDIV,
100 freq => BOARDFREQ, -- clock frequency in KHz
101 clk_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkA
102 clkb_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkB
103 clkc_odiv => CFG_OCLKDIV) -- Proasic3/Fusion output divider clkC
104 port map(
105 clkin => clk_48,
106 pciclkin => '0',
107 clk => clk, -- main clock
108 clkn => open, -- inverted main clock
109 clk2x => open, -- 2x clock
110 sdclk => open, -- SDRAM clock
111 pciclk => open, -- PCI clock
112 cgi => cgi,
113 cgo => cgo,
114 clk4x => open, -- 4x clock
115 clk1xu => open, -- unscaled 1X clock
116 clk2xu => open, -- unscaled 2X clock
117 clkb => clk80, -- Proasic3/Fusion clkB
118 clkc => open); -- Proasic3/Fusion clkC
102 119
103 SIMPLL: IF simu = 1 generate
104 PLL : entity work.PLL0Sim
105 port map(
106 POWERDOWN => '1',
107 CLKA => clk_48,
108 LOCK => RaZ,
109 GLA => clk80,
110 GLB => clk
111 );
112 end generate;
113 120
114 121
115 122 gene3_3M : entity Clk_Divider2
116 123 generic map(N => 10)
117 124 port map(
118 125 clk_in => clk,
119 126 clk_out => sclkint
120 127 );
121 128
122 129 Wcounter : entity Word_Cntr
123 130 generic map(WordSize => WordSize ,N => WordCnt)
124 131 port map(
125 132 Sclk => Sclkint,
126 133 reset => rstn,
127 134 WordClk => WordClk,
128 135 Cnt_out => WordCount
129 136 );
130 137
131 138 MFGEN0 : entity work.MinF_Gen
132 139 generic map(WordCnt => WordCnt)
133 140 port map(
134 141 clk => Sclkint,
135 142 reset => rstn,
136 143 WordCnt_in => WordCount,
137 144 WordClk => WordClk,
138 145 MinF_Clk => MinF
139 146 );
140 147
141 148 MinFcounter : entity Word_Cntr
142 149 generic map(WordSize => WordCnt ,N => MinFCount)
143 150 port map(
144 151 Sclk => WordClk,
145 152 reset => rstn,
146 153 WordClk => MinFclk,
147 154 Cnt_out => MinFCnt
148 155 );
149 156
150 157 MFGEN1 : entity work.MajF_Gen
151 158 generic map(WordCnt => WordCnt,MinFCount => MinFCount)
152 159 port map(
153 160 clk => Sclkint,
154 161 reset => rstn,
155 162 WordCnt_in => WordCount,
156 163 MinfCnt_in => MinFCnt,
157 164 WordClk => WordClk,
158 165 MajF_Clk => MajF
159 166 );
160 167
161 168 LFGATEGEN0 : entity work.LF_GATE_GEN
162 169 generic map(WordCnt => WordCnt)
163 170 port map(
164 171 clk => Sclkint,
165 172 Wcount => WordCount,
166 173 Gate => GateLF
167 174 );
168 175
169 176 DCGATEGEN0 : entity work.DC_GATE_GEN
170 177 generic map(WordCnt => WordCnt)
171 178 port map(
172 179 clk => Sclkint,
173 180 Wcount => WordCount,
174 181 Gate => GateDC
175 182 );
176 183
177 184 --GateDC <= '0';
178 185 --GateLF <= '0';
179 186
180 187 HFGATEGEN0 :
181 188 GateHF <= '1' when WordCount = 120 else
182 189 '1' when WordCount = 121 else '0';
183 190
184 191
185 192
186 193 SD0 : entity Serial_driver2
187 194 generic map(Sz => WordSize)
188 195 port map(
189 196 Sclk => Sclkint,
190 197 rstn => rstn,
191 198 Sdata => DataRTX,
192 199 Gate => GateR,
193 200 NwDat => NwDat,
194 201 Data => DATA
195 202 );
196 203
197 204
198 205
199 206 proto: entity work.ICI_EGSE_PROTOCOL
200 207 generic map(WordSize => WordSize,WordCnt => WordCnt,MinFCount => MinFCount,Simu => 0)
201 208 port map(
202 209 clk => clk,
203 210 -- reset => not MinF,
204 211 reset => rstn,
205 212 WEN => PROTO_WEN,
206 213 MinfCnt_in => MinfCnt,
207 214 WordCnt_in => WordCount,
208 215 DATAIN => PROTO_DATAIN,
209 216 FULL => PROTO_FULL,
210 217 WR => PROTO_WR,
211 218 DATAOUT => PROTO_DATAOUT
212 219 );
213 220
214 221
215 222
216 223 USB2: entity work.FX2_WithFIFO
217 224 generic map(CFG_MEMTECH,use_RAM)
218 225 port map(
219 226 clk => clk,
220 227 if_clk => if_clk,
221 228 reset => rstn,
222 229 flagb => flagb,
223 230 slwr => slwr,
224 231 slrd => slrd,
225 232 pktend => pktend,
226 233 sloe => sloe,
227 234 fdbusw => fdbusw,
228 235 fifoadr => fifoadr,
229 236 FULL => PROTO_FULL,
230 237 wen => PROTO_WR,
231 238 Data => PROTO_DATAOUT
232 239 );
233 240
234 241
235 242 rstn <= reset and RaZ;
236 243 SCLK <= Sclkint;
237 244
238 245 Major_Frame <= MajF;
239 246 --Minor_Frame <= MinF;
240 247 Minor_Frame <= MinFclk;
241 248 gateint <= GateDC or GateLF or GateHF;
242 249 Gate <= gateint;
243 250
244 251 process(Sclkint,rstn)
245 252 begin
246 253 if rstn = '0' then
247 254 GateR <= '0';
248 255 elsif Sclkint'event and Sclkint = '0' then
249 256 GateR <= Gateint;
250 257 end if;
251 258 end process;
252 259
253 260 BUS0 <= WordClk;
254 261 BUS12 <= MinFVector(0);
255 262 BUS13 <= MinFclk;
256 263 BUS14 <= '1' when WordCount = 0 else '0';
257 264
258 265 MinFVector <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));
259 266
260 267
261 268 process(clk,rstn)
262 269 begin
263 270 if rstn = '0' then
264 271 PROTO_DATAIN <= (others => '0');
265 272 PROTO_WEN <= '1';
266 273 elsif clk'event and clk = '1' then
267 274 NwDatR <= NwDat;
268 275 if NwDat = '1' and NwDatR = '0' then
269 276 PROTO_DATAIN <= std_logic_vector(unsigned(PROTO_DATAIN) + 1 );
270 277 PROTO_WEN <= '0';
271 278 else
272 279 PROTO_WEN <= '1';
273 280 end if;
274 281 end if;
275 282 end process;
276 283
277 284 end ar_TOP_EGSE2;
278 285
279 286
280 287
281 288
282
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@@ -1,98 +1,109
1 1 -- ICI_EGSE_PROTOCOL.vhd
2 2 -- ICI_EGSE_PROTOCOL.vhd
3 3 library IEEE;
4 4 use IEEE.std_logic_1164.all;
5 5 use IEEE.numeric_std.all;
6 6
7 7 entity ICI_EGSE_PROTOCOL is
8 8 generic(WordSize : integer := 8;WordCnt : integer :=144;MinFCount : integer := 64;Simu : integer :=0);
9 9 port(
10 10 clk : in std_logic;
11 11 reset : in std_logic;
12 12 WEN : in std_logic;
13 13 WordCnt_in : in integer range 0 to WordCnt-1;
14 14 MinfCnt_in : in integer range 0 to MinFCount-1;
15 15 DATAIN : in std_logic_vector (WordSize-1 downto 0);
16 16 FULL : in std_logic;
17 17 WR : out std_logic;
18 18 DATAOUT : out std_logic_vector (WordSize-1 downto 0)
19 19 );
20 20 end ICI_EGSE_PROTOCOL;
21 21
22 22
23 23 architecture ar_ICI_EGSE_PROTOCOL of ICI_EGSE_PROTOCOL is
24 24
25 25 type DATA_pipe_t is array(NATURAL RANGE <>) of std_logic_vector (WordSize-1 downto 0);
26 26
27 signal DATA_pipe : DATA_pipe_t(10 downto 0);
28 signal WR_pipe : std_logic_vector(10 downto 0);
27 signal DATA_pipe : DATA_pipe_t(12 downto 0);
28 signal WR_pipe : std_logic_vector(12 downto 0);
29 29 signal headerSended : std_logic := '0';
30
30 signal counter : std_logic_vector(7 downto 0):=(others => '0');
31 31
32 32 begin
33 33
34 34 WR <= WR_pipe(0);
35 35
36 36 DATAOUT <= DATA_pipe(0);
37 37
38 38
39 39 process(reset,clk)
40 40 begin
41 41 if reset = '0' then
42 WR_pipe(10 downto 0) <= (others => '1');
43 rstloop: for i in 0 to 10 loop
42 WR_pipe(12 downto 0) <= (others => '1');
43 counter <= (others => '0');
44 rstloop: for i in 0 to 12 loop
44 45 DATA_pipe(i) <= X"00";
45 46 end loop;
46 47 headerSended <= '0';
47 48 elsif clk'event and clk ='1' then
48 49 if WordCnt_in = 1 and headerSended = '0' then
50 counter <= (others => '0');
49 51 WR_pipe(4 downto 1) <= (others => '0');
50 52 WR_pipe(1) <= '0';
51 53 WR_pipe(3) <= '0';
52 54 WR_pipe(5) <= '0';
53 55 WR_pipe(7) <= '0';
54 56 WR_pipe(9) <= '0';
55 DATA_pipe(1) <= X"0F";
57 WR_pipe(11) <= '0';
58 DATA_pipe(1) <= counter; -- Size
56 59 DATA_pipe(3) <= X"5a";
57 DATA_pipe(5) <= X"a5";
58 DATA_pipe(7) <= X"F0";
59 DATA_pipe(9) <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize));
60 DATA_pipe(5) <= X"f0";
61 DATA_pipe(7) <= X"0f";
62 DATA_pipe(9) <= X"a5";
63 DATA_pipe(11) <= std_logic_vector(TO_UNSIGNED(MinfCnt_in,WordSize));
60 64 WR_pipe(0) <= '1';
61 65 WR_pipe(2) <= '1';
62 66 WR_pipe(4) <= '1';
63 67 WR_pipe(6) <= '1';
64 68 WR_pipe(8) <= '1';
65 69 WR_pipe(10) <= '1';
70 WR_pipe(12) <= '1';
66 71 DATA_pipe(0) <= X"00";
67 72 DATA_pipe(2) <= X"00";
68 73 DATA_pipe(4) <= X"00";
69 74 DATA_pipe(6) <= X"00";
70 75 DATA_pipe(10) <= X"00";
76 DATA_pipe(12) <= X"00";
71 77 headerSended <= '1';
72 78 elsif (FULL = '0') then
73 79 if WordCnt_in /= 1 then
74 80 headerSended <= '0';
75 81 end if;
76 82 DATA_pipe(0) <= DATA_pipe(1);
77 83 DATA_pipe(1) <= DATA_pipe(2);
78 84 DATA_pipe(2) <= DATA_pipe(3);
79 85 DATA_pipe(3) <= DATA_pipe(4);
80 86 DATA_pipe(4) <= DATA_pipe(5);
81 87 DATA_pipe(5) <= DATA_pipe(6);
82 88 DATA_pipe(6) <= DATA_pipe(7);
83 89 DATA_pipe(7) <= DATA_pipe(8);
84 90 DATA_pipe(8) <= DATA_pipe(9);
85 91 DATA_pipe(9) <= DATA_pipe(10);
86 DATA_pipe(10) <= DATAIN;
87 WR_pipe(10 downto 0) <= WEN & WR_pipe(10 downto 1);
92 DATA_pipe(10) <= DATA_pipe(11);
93 DATA_pipe(11) <= DATA_pipe(12);
94 DATA_pipe(12) <= DATAIN;
95 WR_pipe(12 downto 0) <= WEN & WR_pipe(12 downto 1);
96 if(WR_pipe(0) = '0') then
97 counter <= std_logic_vector(UNSIGNED(counter) + 1);
98 end if;
88 99 else
89 100 WR_pipe(0) <= '1';
90 101 if WordCnt_in /= 1 then
91 102 headerSended <= '0';
92 103 end if;
93 104 end if;
94 105 end if;
95 106 end process;
96 107
97 108
98 109 end ar_ICI_EGSE_PROTOCOL; No newline at end of file
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@@ -1,34 +1,36
1 GRLIB=../..
1 #GRLIB=../..
2 2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 5 TOP=TOP_EGSE2
4 6 BOARD=GSE_ICI
5 7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
6 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
8 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
9 11 EFFORT=high
10 12 XSTOPT=
11 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 14 VHDLSYNFILES=config.vhd EGSE_ICI.vhd DC_GATE_GEN.vhd LF_GATE_GEN.vhd MajF_Gen.vhd MinF_Gen.vhd Serial_driver.vhd ICI_EGSE_PROTOCOL.vhd
13 15 VHDLSIMFILES=testbench.vhd
14 16 SIMTOP=testbench
15 17 SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
16 18 SDC=$(GRLIB)/boards/$(BOARD)/default.sdc
17 19 PDC=$(GRLIB)/boards/$(BOARD)/GSE_ICI.pdc
18 20 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
19 21 CLEAN=soft-clean
20 22
21 23 TECHLIBS = proasic3
22 24 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
23 25 tmtc openchip hynix ihp gleichmann micron usbhc spw fmf gsi eth spansion esa
24 26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 spacewire leon3 leon3ft can greth net gr1553b ./amba_lcd_16x2_ctrlr ./lpp_waveform \
26 28 ./lpp_dma
27 29
28 30 FILESKIP = i2cmst.vhd
29 31
30 32 include $(GRLIB)/bin/Makefile
31 33 include $(GRLIB)/software/leon3/Makefile
32 34
33 35 ################## project specific targets ##########################
34 36
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@@ -1,40 +1,41
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design test bench configuration
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 ------------------------------------------------------------------------------
15 15
16 16
17 17 library techmap;
18 18 use techmap.gencomp.all;
19 19
20 20 package config is
21 21
22 22
23 23 -- Technology and synthesis options
24 24 constant CFG_FABTECH : integer := apa3;
25 25 constant CFG_MEMTECH : integer := apa3;
26 26 constant CFG_PADTECH : integer := inferred;
27 27 constant CFG_NOASYNC : integer := 0;
28 28 constant CFG_SCAN : integer := 0;
29 29
30 30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (5);
33 constant CFG_CLKDIV : integer := (10);
34 constant CFG_OCLKDIV : integer := (1);
31 constant CFG_CLKTECH : integer := apa3;
32 constant CFG_CLKMUL : integer := (25);
33 constant CFG_CLKDIV : integer := (9);
34 constant CFG_OCLKDIV : integer := (4);
35 35 constant CFG_PCIDLL : integer := 0;
36 36 constant CFG_PCISYSCLK: integer := 0;
37 37 constant CFG_CLK_NOFB : integer := 0;
38 constant BOARDFREQ : integer := 48000;
38 39
39 40
40 41 end;
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