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Restored previous ALU version as ALU_V0 for IIR filter first version...
jeandet -
r226:9c9d4ca3fdbf alexis
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1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 library lpp;
4 use lpp.lpp_ad_conv.all;
5 use lpp.lpp_amba.all;
6 use lpp.apb_devices_list.all;
7 use lpp.general_purpose.all;
8 use lpp.Rocket_PCM_Encoder.all;
9 use lpp.iir_filter.all;
10 use work.config.all;
11
12
13 entity IIR_FILTER_TOP is
14 generic
15 (
16 V2 : integer :=0 -- IF 1 uses V2 else use V1
17 );
18 port
19 (
20 rstn : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22
23 SMPclk : IN STD_LOGIC;
24 LF1_IN : IN std_logic_vector(15 downto 0);
25 LF2_IN : IN std_logic_vector(15 downto 0);
26 LF3_IN : IN std_logic_vector(15 downto 0);
27
28 SMPCLKOut : OUT STD_LOGIC;
29 LF1_OUT : OUT std_logic_vector(15 downto 0);
30 LF2_OUT : OUT std_logic_vector(15 downto 0);
31 LF3_OUT : OUT std_logic_vector(15 downto 0)
32 );
33 end IIR_FILTER_TOP;
34
35 architecture AR_IIR_FILTER_TOP of IIR_FILTER_TOP is
36 signal sps : Samples(2 DOWNTO 0);
37
38 signal LFX : Samples(2 DOWNTO 0);
39 signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
40 signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
41 signal sample_out_val : std_logic;
42 signal LF_ADC_SpPulse : std_logic;
43
44 begin
45
46 sps(0) <= LF1_IN;
47 sps(1) <= LF2_IN;
48 sps(2) <= LF3_IN;
49
50 LF1_OUT <= LFX(0);
51 LF2_OUT <= LFX(1);
52 LF3_OUT <= LFX(2);
53
54 SMPCLKOut <= sample_out_val;
55
56 loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE
57
58 loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE
59 process(rstn,clk)
60 begin
61 if rstn ='0' then
62 Filter_sp_in(I,J) <= '0';
63 -- LFX(I) <= (others => '0');
64 elsif clk'event and clk ='1' then
65 if sample_out_val = '1' then
66 LFX(I)(J) <= Filter_sp_out(I,J);
67 Filter_sp_in(I,J) <= sps(I)(J);
68 end if;
69 end if;
70 end process;
71 END GENERATE;
72 END GENERATE;
73
74 V2FILTER: IF V2 = 1 GENERATE
75
76 smpPulse: entity work.OneShot
77 Port map(
78 reset => rstn,
79 clk => clk,
80 input => SMPclk,
81 output => LF_ADC_SpPulse
82 );
83
84 FilterV2: IIR_CEL_CTRLR_v2
85 GENERIC map(
86 tech => CFG_MEMTECH,
87 Mem_use => use_RAM,
88 Sample_SZ => Sample_SZ,
89 Coef_SZ => Coef_SZ,
90 Coef_Nb => 25,
91 Coef_sel_SZ => 5,
92 Cels_count => 5,
93 ChanelsCount => ChanelsCount
94 )
95 PORT map(
96 rstn => rstn,
97 clk => clk,
98
99 virg_pos => virgPos,
100 coefs => CoefsInitValCst_v2,
101
102 sample_in_val => LF_ADC_SpPulse,
103 sample_in => Filter_sp_in,
104
105 sample_out_val => sample_out_val,
106 sample_out => Filter_sp_out
107 );
108
109
110
111 END GENERATE;
112
113 V1FILTER: IF V2 /= 1 GENERATE
114
115 sample_out_val <= SMPclk;
116
117
118 FilterV1: IIR_CEL_CTRLR
119 generic map(
120 tech => CFG_MEMTECH,
121 Sample_SZ => Sample_SZ,
122 ChanelsCount => 3,
123 Coef_SZ => Coef_SZ,
124 CoefCntPerCel=> CoefCntPerCel,
125 Cels_count => Cels_count,
126 Mem_use => use_RAM
127 )
128 port map(
129 reset => rstn,
130 clk => clk,
131 sample_clk => SMPclk,
132 sample_in => Filter_sp_in,
133 sample_out => Filter_sp_out,
134 virg_pos => virgPos,
135 GOtest => open,
136 coefs => CoefsInitValCst
137 );
138
139 END GENERATE;
140
141
142 end AR_IIR_FILTER_TOP;
143
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27 --IDLE = 0000
28 --MAC = 0001
29 --MULT = 0010 and set MULT in ADD reg
30 --ADD = 0011
31 --CLRMAC = 0100
32
33
34 ENTITY ALU_V0 IS
35 GENERIC(
36 Arith_en : INTEGER := 1;
37 Logic_en : INTEGER := 1;
38 Input_SZ_1 : INTEGER := 16;
39 Input_SZ_2 : INTEGER := 9
40
41 );
42 PORT(
43 clk : IN STD_LOGIC;
44 reset : IN STD_LOGIC;
45 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
47 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
48 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
49 );
50 END ENTITY;
51
52 ARCHITECTURE ar_ALU OF ALU_V0 IS
53
54 SIGNAL clr_MAC : STD_LOGIC := '1';
55
56 BEGIN
57 clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0';
58
59 arith : IF Arith_en = 1 GENERATE
60 MACinst : MAC_V0
61 GENERIC MAP(Input_SZ_1, Input_SZ_2)
62 PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
63 END GENERATE;
64
65 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27
28
29
30 entity Adder_V0 is
31 generic(
32 Input_SZ_A : integer := 16;
33 Input_SZ_B : integer := 16
34
35 );
36 port(
37 clk : in std_logic;
38 reset : in std_logic;
39 clr : in std_logic;
40 add : in std_logic;
41 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
42 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
43 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
44 );
45 end entity;
46
47
48
49
50 architecture ar_Adder of Adder_V0 is
51
52 signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
53 signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
54
55 begin
56
57 RES <= REG;
58 RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
59
60 process(clk,reset)
61 begin
62 if reset = '0' then
63 REG <= (others => '0');
64 elsif clk'event and clk ='1' then
65 if clr = '1' then
66 REG <= (others => '0');
67 elsif add = '1' then
68 REG <= RESADD;
69 end if;
70 end if;
71 end process;
72 end ar_Adder;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 library IEEE;
7 use IEEE.numeric_std.all;
8 use IEEE.std_logic_1164.all;
9 library lpp;
10 use lpp.general_purpose.all;
11 --TODO
12 --terminer le testbensh puis changer le resize dans les instanciations
13 --par un resize sur un vecteur en combi
14
15
16
17
18
19 entity MAC_V0 is
20 generic(
21 Input_SZ_A : integer := 8;
22 Input_SZ_B : integer := 8
23
24 );
25 port(
26 clk : in std_logic;
27 reset : in std_logic;
28 clr_MAC : in std_logic;
29 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
30 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
31 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
32 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
33 );
34 end MAC_V0;
35
36
37
38
39 architecture ar_MAC of MAC_V0 is
40
41
42
43
44
45 signal add,mult : std_logic;
46 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
47
48 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
50 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
51
52
53 signal MACMUXsel : std_logic;
54 signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
55 signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56
57
58
59 signal MACMUX2sel : std_logic;
60
61 signal add_D : std_logic;
62 signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0);
63 signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0);
64 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
65 signal MACMUXsel_D : std_logic;
66 signal MACMUX2sel_D : std_logic;
67 signal MACMUX2sel_D_D : std_logic;
68 signal clr_MAC_D : std_logic;
69 signal clr_MAC_D_D : std_logic;
70
71
72
73
74
75 begin
76
77
78
79
80 --==============================================================
81 --=============M A C C O N T R O L E R=========================
82 --==============================================================
83 MAC_CONTROLER1 : MAC_CONTROLER
84 port map(
85 ctrl => MAC_MUL_ADD,
86 MULT => mult,
87 ADD => add,
88 MACMUX_sel => MACMUXsel,
89 MACMUX2_sel => MACMUX2sel
90
91 );
92 --==============================================================
93
94
95
96
97 --==============================================================
98 --=============M U L T I P L I E R==============================
99 --==============================================================
100 Multiplieri_nst : Multiplier
101 generic map(
102 Input_SZ_A => Input_SZ_A,
103 Input_SZ_B => Input_SZ_B
104 )
105 port map(
106 clk => clk,
107 reset => reset,
108 mult => mult,
109 OP1 => OP1,
110 OP2 => OP2,
111 RES => MULTout
112 );
113
114 --==============================================================
115
116
117
118
119 --==============================================================
120 --======================A D D E R ==============================
121 --==============================================================
122 adder_inst : Adder_V0
123 generic map(
124 Input_SZ_A => Input_SZ_A+Input_SZ_B,
125 Input_SZ_B => Input_SZ_A+Input_SZ_B
126 )
127 port map(
128 clk => clk,
129 reset => reset,
130 clr => clr_MAC_D,
131 add => add_D,
132 OP1 => ADDERinA,
133 OP2 => ADDERinB,
134 RES => ADDERout
135 );
136
137 --==============================================================
138
139
140 clr_MACREG1 : MAC_REG
141 generic map(size => 1)
142 port map(
143 reset => reset,
144 clk => clk,
145 D(0) => clr_MAC,
146 Q(0) => clr_MAC_D
147 );
148
149 clr_MACREG2 : MAC_REG
150 generic map(size => 1)
151 port map(
152 reset => reset,
153 clk => clk,
154 D(0) => clr_MAC_D,
155 Q(0) => clr_MAC_D_D
156 );
157
158 addREG : MAC_REG
159 generic map(size => 1)
160 port map(
161 reset => reset,
162 clk => clk,
163 D(0) => add,
164 Q(0) => add_D
165 );
166
167 OP1REG : MAC_REG
168 generic map(size => Input_SZ_A)
169 port map(
170 reset => reset,
171 clk => clk,
172 D => OP1,
173 Q => OP1_D
174 );
175
176
177 OP2REG : MAC_REG
178 generic map(size => Input_SZ_B)
179 port map(
180 reset => reset,
181 clk => clk,
182 D => OP2,
183 Q => OP2_D
184 );
185
186
187 MULToutREG : MAC_REG
188 generic map(size => Input_SZ_A+Input_SZ_B)
189 port map(
190 reset => reset,
191 clk => clk,
192 D => MULTout,
193 Q => MULTout_D
194 );
195
196
197 MACMUXselREG : MAC_REG
198 generic map(size => 1)
199 port map(
200 reset => reset,
201 clk => clk,
202 D(0) => MACMUXsel,
203 Q(0) => MACMUXsel_D
204 );
205
206 MACMUX2selREG : MAC_REG
207 generic map(size => 1)
208 port map(
209 reset => reset,
210 clk => clk,
211 D(0) => MACMUX2sel,
212 Q(0) => MACMUX2sel_D
213 );
214
215 MACMUX2selREG2 : MAC_REG
216 generic map(size => 1)
217 port map(
218 reset => reset,
219 clk => clk,
220 D(0) => MACMUX2sel_D,
221 Q(0) => MACMUX2sel_D_D
222 );
223
224 --==============================================================
225 --======================M A C M U X ===========================
226 --==============================================================
227 MACMUX_inst : MAC_MUX
228 generic map(
229 Input_SZ_A => Input_SZ_A+Input_SZ_B,
230 Input_SZ_B => Input_SZ_A+Input_SZ_B
231
232 )
233 port map(
234 sel => MACMUXsel_D,
235 INA1 => ADDERout,
236 INA2 => OP2_D_Resz,
237 INB1 => MULTout,
238 INB2 => OP1_D_Resz,
239 OUTA => ADDERinA,
240 OUTB => ADDERinB
241 );
242 OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B));
243 OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B));
244 --==============================================================
245
246
247 --==============================================================
248 --======================M A C M U X2 ==========================
249 --==============================================================
250 MAC_MUX2_inst : MAC_MUX2
251 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
252 port map(
253 sel => MACMUX2sel_D_D,
254 RES2 => MULTout_D,
255 RES1 => ADDERout,
256 RES => RES
257 );
258
259
260 --==============================================================
261
262 end ar_MAC;
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@@ -1,80 +1,81
1 SCRIPTSDIR=scripts/
1 SCRIPTSDIR=scripts/
2 LIBDIR=lib/
2 LIBDIR=lib/
3 BOARDSDIR=boards/
3 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
4 DESIGNSDIR=designs/
5
5
6
6
7 .PHONY:doc
7 .PHONY:doc
8
8
9
9
10 all: help
10 all: help
11
11
12 help:
12 help:
13 @echo
13 @echo
14 @echo " batch targets:"
14 @echo " batch targets:"
15 @echo
15 @echo
16 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
16 @echo " make link : link lpp library to GRLIB at : $(GRLIB)"
17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
18 @echo " make dist : create a tar file for using into an other computer"
18 @echo " make dist : create a tar file for using into an other computer"
19 @echo " make Patched-dist : create a tar file for with a patched grlib for using"
19 @echo " make Patched-dist : create a tar file for with a patched grlib for using"
20 @echo " into an other computer"
20 @echo " into an other computer"
21 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
21 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
22 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
22 @echo " make init : add a GPL HEADER in all vhdl Files, init all files"
23 @echo " make doc : make documentation for VHDL IPs"
23 @echo " make doc : make documentation for VHDL IPs"
24 @echo " make pdf : make pdf documentation for VHDL IPs"
24 @echo " make pdf : make pdf documentation for VHDL IPs"
25 @echo " make C-libs : make C drivers for APB devices"
25 @echo " make C-libs : make C drivers for APB devices"
26 @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
26 @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes"
27 @echo
27 @echo
28
28
29
29
30
30
31 allGPL:
31 allGPL:
32 @echo "Scanning VHDL files ..."
32 @echo "Scanning VHDL files ..."
33 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
33 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib
34 @echo "Scanning C files ..."
34 @echo "Scanning C files ..."
35 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
35 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers
36 @echo "Scanning H files ..."
36 @echo "Scanning H files ..."
37 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
37 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers
38
38
39 init: C-libs
39 init: C-libs
40 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
40 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
41 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
41 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
42
42
43 C-libs:APB_devs
43 C-libs:APB_devs
44 make -C LPP_drivers
44 make -C LPP_drivers
45
45
46
46
47 APB_devs:
47 APB_devs:
48 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
48 sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh
49
49
50
50
51 Patch-GRLIB: init doc
51 Patch-GRLIB: init doc
52 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
52 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
53
53
54 link:
54 link:
55 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
55 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
56 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
56 sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
57 sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
57
58
58 dist: init
59 dist: init
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
60 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
60
61
61
62
62 Patched-dist: Patch-GRLIB
63 Patched-dist: Patch-GRLIB
63 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
64 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
64
65
65
66
66 doc:
67 doc:
67 mkdir -p doc/html
68 mkdir -p doc/html
68 cp doc/ressources/*.jpg doc/html/
69 cp doc/ressources/*.jpg doc/html/
69 cp doc/ressources/doxygen.css doc/html/
70 cp doc/ressources/doxygen.css doc/html/
70 make -C lib/lpp doc
71 make -C lib/lpp doc
71 make -C LPP_drivers doc
72 make -C LPP_drivers doc
72
73
73
74
74 pdf: doc
75 pdf: doc
75 sh $(SCRIPTSDIR)/doc.sh
76 sh $(SCRIPTSDIR)/doc.sh
76
77
77
78
78
79
79
80
80
81
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@@ -1,288 +1,343
1 library IEEE;
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4 library lpp;
4 library lpp;
5 use lpp.lpp_ad_conv.all;
5 use lpp.lpp_ad_conv.all;
6 use lpp.lpp_amba.all;
6 use lpp.lpp_amba.all;
7 use lpp.apb_devices_list.all;
7 use lpp.apb_devices_list.all;
8 use lpp.general_purpose.all;
8 use lpp.general_purpose.all;
9 use lpp.Rocket_PCM_Encoder.all;
9 use lpp.Rocket_PCM_Encoder.all;
10
10
11 use work.config.all;
12
11
13
12 entity DC_ACQ_TOP is
14 entity DC_ACQ_TOP is
13 generic(
15 generic(
14 WordSize : integer := 8;
16 WordSize : integer := 8;
15 WordCnt : integer := 144;
17 WordCnt : integer := 144;
16 MinFCount : integer := 64;
18 MinFCount : integer := 64;
17 EnableSR : integer := 1;
19 EnableSR : integer := 1;
18 FakeADC : integer := 0
20 CstDATA : integer := 0;
21 FakeADC : integer := 0;
22 CDS : integer := 0
19 );
23 );
20 port(
24 port(
21
25
22 reset : in std_logic;
26 reset : in std_logic;
23 clk : in std_logic;
27 clk : in std_logic;
24 SyncSig : in STD_LOGIC;
28 SyncSig : in STD_LOGIC;
25 minorF : in std_logic;
29 minorF : in std_logic;
26 majorF : in std_logic;
30 majorF : in std_logic;
27 sclk : in std_logic;
31 sclk : in std_logic;
28 WordClk : in std_logic;
32 WordClk : in std_logic;
29
33
30 DC_ADC_Sclk : out std_logic;
34 DC_ADC_Sclk : out std_logic;
31 DC_ADC_IN : in std_logic_vector(1 downto 0);
35 DC_ADC_IN : in std_logic_vector(1 downto 0);
32 DC_ADC_ClkDiv : out std_logic;
36 DC_ADC_ClkDiv : out std_logic;
33 DC_ADC_FSynch : out std_logic;
37 DC_ADC_FSynch : out std_logic;
34 SET_RESET0 : out std_logic;
38 SET_RESET0 : out std_logic;
35 SET_RESET1 : out std_logic;
39 SET_RESET1 : out std_logic;
36
40
37 AMR1X : out std_logic_vector(23 downto 0);
41 AMR1X : out std_logic_vector(23 downto 0);
38 AMR1Y : out std_logic_vector(23 downto 0);
42 AMR1Y : out std_logic_vector(23 downto 0);
39 AMR1Z : out std_logic_vector(23 downto 0);
43 AMR1Z : out std_logic_vector(23 downto 0);
40
44
41 AMR2X : out std_logic_vector(23 downto 0);
45 AMR2X : out std_logic_vector(23 downto 0);
42 AMR2Y : out std_logic_vector(23 downto 0);
46 AMR2Y : out std_logic_vector(23 downto 0);
43 AMR2Z : out std_logic_vector(23 downto 0);
47 AMR2Z : out std_logic_vector(23 downto 0);
44
48
45 AMR3X : out std_logic_vector(23 downto 0);
49 AMR3X : out std_logic_vector(23 downto 0);
46 AMR3Y : out std_logic_vector(23 downto 0);
50 AMR3Y : out std_logic_vector(23 downto 0);
47 AMR3Z : out std_logic_vector(23 downto 0);
51 AMR3Z : out std_logic_vector(23 downto 0);
48
52
49 AMR4X : out std_logic_vector(23 downto 0);
53 AMR4X : out std_logic_vector(23 downto 0);
50 AMR4Y : out std_logic_vector(23 downto 0);
54 AMR4Y : out std_logic_vector(23 downto 0);
51 AMR4Z : out std_logic_vector(23 downto 0);
55 AMR4Z : out std_logic_vector(23 downto 0);
52
56
53 Temp1 : out std_logic_vector(23 downto 0);
57 Temp1 : out std_logic_vector(23 downto 0);
54 Temp2 : out std_logic_vector(23 downto 0);
58 Temp2 : out std_logic_vector(23 downto 0);
55 Temp3 : out std_logic_vector(23 downto 0);
59 Temp3 : out std_logic_vector(23 downto 0);
56 Temp4 : out std_logic_vector(23 downto 0)
60 Temp4 : out std_logic_vector(23 downto 0)
57 );
61 );
58 end DC_ACQ_TOP;
62 end DC_ACQ_TOP;
59
63
60 architecture Behavioral of DC_ACQ_TOP is
64 architecture Behavioral of DC_ACQ_TOP is
61
65
62 signal DC_ADC_SmplClk : std_logic;
66 signal DC_ADC_SmplClk : std_logic;
63 signal LF_ADC_SmplClk : std_logic;
67 signal LF_ADC_SmplClk : std_logic;
64 signal SET_RESET0_sig : std_logic;
68 signal SET_RESET0_sig : std_logic;
65 signal SET_RESET1_sig : std_logic;
69 signal SET_RESET1_sig : std_logic;
66 signal SET_RESET_counter : integer range 0 to 31:=0;
70 signal SET_RESET_counter : integer range 0 to 31:=0;
67
71
68 signal AMR1X_Sync : std_logic_vector(23 downto 0);
72 signal AMR1X_Sync : std_logic_vector(23 downto 0);
69 signal AMR1Y_Sync : std_logic_vector(23 downto 0);
73 signal AMR1Y_Sync : std_logic_vector(23 downto 0);
70 signal AMR1Z_Sync : std_logic_vector(23 downto 0);
74 signal AMR1Z_Sync : std_logic_vector(23 downto 0);
71
75
72 signal AMR2X_Sync : std_logic_vector(23 downto 0);
76 signal AMR2X_Sync : std_logic_vector(23 downto 0);
73 signal AMR2Y_Sync : std_logic_vector(23 downto 0);
77 signal AMR2Y_Sync : std_logic_vector(23 downto 0);
74 signal AMR2Z_Sync : std_logic_vector(23 downto 0);
78 signal AMR2Z_Sync : std_logic_vector(23 downto 0);
75
79
76 signal AMR3X_Sync : std_logic_vector(23 downto 0);
80 signal AMR3X_Sync : std_logic_vector(23 downto 0);
77 signal AMR3Y_Sync : std_logic_vector(23 downto 0);
81 signal AMR3Y_Sync : std_logic_vector(23 downto 0);
78 signal AMR3Z_Sync : std_logic_vector(23 downto 0);
82 signal AMR3Z_Sync : std_logic_vector(23 downto 0);
79
83
80 signal AMR4X_Sync : std_logic_vector(23 downto 0);
84 signal AMR4X_Sync : std_logic_vector(23 downto 0);
81 signal AMR4Y_Sync : std_logic_vector(23 downto 0);
85 signal AMR4Y_Sync : std_logic_vector(23 downto 0);
82 signal AMR4Z_Sync : std_logic_vector(23 downto 0);
86 signal AMR4Z_Sync : std_logic_vector(23 downto 0);
83
87
84 signal Temp1_Sync : std_logic_vector(23 downto 0);
88 signal Temp1_Sync : std_logic_vector(23 downto 0);
85 signal Temp2_Sync : std_logic_vector(23 downto 0);
89 signal Temp2_Sync : std_logic_vector(23 downto 0);
86 signal Temp3_Sync : std_logic_vector(23 downto 0);
90 signal Temp3_Sync : std_logic_vector(23 downto 0);
87 signal Temp4_Sync : std_logic_vector(23 downto 0);
91 signal Temp4_Sync : std_logic_vector(23 downto 0);
88
92
89 begin
93 begin
90
94
91 ------------------------------------------------------------------
95 ------------------------------------------------------------------
92 --
96 --
93 -- DC sampling clock generation
97 -- DC sampling clock generation
94 --
98 --
95 ------------------------------------------------------------------
99 ------------------------------------------------------------------
96
100
97
101
98 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
102 DC_SMPL_CLK0 : entity work.LF_SMPL_CLK
99 --generic map(36)
103 --generic map(36)
100 generic map(288)
104 generic map(288)
101 port map(
105 port map(
102 reset => reset,
106 reset => reset,
103 wclk => WordClk,
107 wclk => WordClk,
104 SMPL_CLK => DC_ADC_SmplClk
108 SMPL_CLK => DC_ADC_SmplClk
105 );
109 );
106 ------------------------------------------------------------------
110 ------------------------------------------------------------------
107
111
108
112
109
113
110
114
111 ------------------------------------------------------------------
115 ------------------------------------------------------------------
112 --
116 --
113 -- DC ADC
117 -- DC ADC
114 --
118 --
115 ------------------------------------------------------------------
119 ------------------------------------------------------------------
116 ADC : IF FakeADC /=1 GENERATE
120 ADC1: IF CstDATA /= 1 GENERATE
117
121 ADC : IF FakeADC /=1 GENERATE
118 DC_ADC0 : DUAL_ADS1278_DRIVER
122
119 port map(
123 DC_ADC0 : DUAL_ADS1278_DRIVER
120 Clk => clk,
124 port map(
121 reset => reset,
125 Clk => clk,
122 SpiClk => DC_ADC_Sclk,
126 reset => reset,
123 DIN => DC_ADC_IN,
127 SpiClk => DC_ADC_Sclk,
124 SmplClk => DC_ADC_SmplClk,
128 DIN => DC_ADC_IN,
125 OUT00 => AMR1X_Sync,
129 SmplClk => DC_ADC_SmplClk,
126 OUT01 => AMR1Y_Sync,
130 OUT00 => AMR1X_Sync,
127 OUT02 => AMR1Z_Sync,
131 OUT01 => AMR1Y_Sync,
128 OUT03 => AMR2X_Sync,
132 OUT02 => AMR1Z_Sync,
129 OUT04 => AMR2Y_Sync,
133 OUT03 => AMR2X_Sync,
130 OUT05 => AMR2Z_Sync,
134 OUT04 => AMR2Y_Sync,
131 OUT06 => Temp1_Sync,
135 OUT05 => AMR2Z_Sync,
132 OUT07 => Temp2_Sync,
136 OUT06 => Temp1_Sync,
133 OUT10 => AMR3X_Sync,
137 OUT07 => Temp2_Sync,
134 OUT11 => AMR3Y_Sync,
138 OUT10 => AMR3X_Sync,
135 OUT12 => AMR3Z_Sync,
139 OUT11 => AMR3Y_Sync,
136 OUT13 => AMR4X_Sync,
140 OUT12 => AMR3Z_Sync,
137 OUT14 => AMR4Y_Sync,
141 OUT13 => AMR4X_Sync,
138 OUT15 => AMR4Z_Sync,
142 OUT14 => AMR4Y_Sync,
139 OUT16 => Temp3_Sync,
143 OUT15 => AMR4Z_Sync,
140 OUT17 => Temp4_Sync,
144 OUT16 => Temp3_Sync,
141 FSynch => DC_ADC_FSynch
145 OUT17 => Temp4_Sync,
142 );
146 FSynch => DC_ADC_FSynch
143 END GENERATE;
147 );
148 END GENERATE;
144
149
145 NOADC: IF FakeADC=1 GENERATE
150 NOADC: IF FakeADC=1 GENERATE
146
151
147 DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER
152 DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER
148 port map(
153 port map(
149 Clk => clk,
154 Clk => clk,
150 reset => reset,
155 reset => reset,
151 SpiClk => DC_ADC_Sclk,
156 SpiClk => DC_ADC_Sclk,
152 DIN => DC_ADC_IN,
157 DIN => DC_ADC_IN,
153 SmplClk => DC_ADC_SmplClk,
158 SmplClk => DC_ADC_SmplClk,
154 OUT00 => AMR1X_Sync,
159 OUT00 => AMR1X_Sync,
155 OUT01 => AMR1Y_Sync,
160 OUT01 => AMR1Y_Sync,
156 OUT02 => AMR1Z_Sync,
161 OUT02 => AMR1Z_Sync,
157 OUT03 => AMR2X_Sync,
162 OUT03 => AMR2X_Sync,
158 OUT04 => AMR2Y_Sync,
163 OUT04 => AMR2Y_Sync,
159 OUT05 => AMR2Z_Sync,
164 OUT05 => AMR2Z_Sync,
160 OUT06 => Temp1_Sync,
165 OUT06 => Temp1_Sync,
161 OUT07 => Temp2_Sync,
166 OUT07 => Temp2_Sync,
162 OUT10 => AMR3X_Sync,
167 OUT10 => AMR3X_Sync,
163 OUT11 => AMR3Y_Sync,
168 OUT11 => AMR3Y_Sync,
164 OUT12 => AMR3Z_Sync,
169 OUT12 => AMR3Z_Sync,
165 OUT13 => AMR4X_Sync,
170 OUT13 => AMR4X_Sync,
166 OUT14 => AMR4Y_Sync,
171 OUT14 => AMR4Y_Sync,
167 OUT15 => AMR4Z_Sync,
172 OUT15 => AMR4Z_Sync,
168 OUT16 => Temp3_Sync,
173 OUT16 => Temp3_Sync,
169 OUT17 => Temp4_Sync,
174 OUT17 => Temp4_Sync,
170 FSynch => DC_ADC_FSynch
175 FSynch => DC_ADC_FSynch
171 );
176 );
177 END GENERATE;
178
172 END GENERATE;
179 END GENERATE;
173 ------------------------------------------------------------------
180 ------------------------------------------------------------------
174
181
182 NOADC: IF CstDATA = 1 GENERATE
183
184 AMR1X_Sync <= AMR1Xcst;
185 AMR1Y_Sync <= AMR1Ycst;
186 AMR1Z_Sync <= AMR1Zcst;
187 AMR2X_Sync <= AMR2Xcst;
188 AMR2Y_Sync <= AMR2Ycst;
189 AMR2Z_Sync <= AMR2Zcst;
190 Temp1_Sync <= Temp1cst;
191 Temp2_Sync <= Temp2cst;
192 AMR3X_Sync <= AMR3Xcst;
193 AMR3Y_Sync <= AMR3Ycst;
194 AMR3Z_Sync <= AMR3Zcst;
195 AMR4X_Sync <= AMR4Xcst;
196 AMR4Y_Sync <= AMR4Ycst;
197 AMR4Z_Sync <= AMR4Zcst;
198 Temp3_Sync <= Temp3cst;
199 Temp4_Sync <= Temp4cst;
200
201
202
203
204
205 END GENERATE;
206
175
207
176
208
177
209
178 ------------------------------------------------------------------
210 ------------------------------------------------------------------
179 --
211 --
180 -- SET/RESET GEN
212 -- SET/RESET GEN
181 --
213 --
182 ------------------------------------------------------------------
214 ------------------------------------------------------------------
183
215
184 SR: IF EnableSR /=0 GENERATE
216 SR: IF EnableSR /=0 GENERATE
185 process(reset,DC_ADC_SmplClk)
217 process(reset,DC_ADC_SmplClk)
186 begin
218 begin
187 if reset = '0' then
219 if reset = '0' then
188 SET_RESET0_sig <= '0';
220 SET_RESET0_sig <= '0';
189 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
221 elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then
190 if(SET_RESET_counter = 31) then
222 if(SET_RESET_counter = 31) then
191 SET_RESET0_sig <= not SET_RESET0_sig;
223 SET_RESET0_sig <= not SET_RESET0_sig;
192 SET_RESET_counter <= 0;
224 SET_RESET_counter <= 0;
193 else
225 else
194 SET_RESET_counter <= SET_RESET_counter +1;
226 SET_RESET_counter <= SET_RESET_counter +1;
195 end if;
227 end if;
196 end if;
228 end if;
197 end process;
229 end process;
198
230
199 END GENERATE;
231 END GENERATE;
200 NOSR: IF EnableSR=0 GENERATE
232 NOSR: IF EnableSR=0 GENERATE
201 SET_RESET0_sig <= '0';
233 SET_RESET0_sig <= '0';
202 END GENERATE;
234 END GENERATE;
203
235
204 SET_RESET1_sig <= SET_RESET0_sig;
236 SET_RESET1_sig <= SET_RESET0_sig;
205 SET_RESET0 <= SET_RESET0_sig;
237 SET_RESET0 <= SET_RESET0_sig;
206 SET_RESET1 <= SET_RESET1_sig;
238 SET_RESET1 <= SET_RESET1_sig;
207 ------------------------------------------------------------------
239 ------------------------------------------------------------------
208 ------------------------------------------------------------------
240 ------------------------------------------------------------------
209
241
210
242
211 ------------------------------------------------------------------
243 ------------------------------------------------------------------
212 --
244 --
213 -- Cross domain clock synchronisation
245 -- Cross domain clock synchronisation
214 --
246 --
215 ------------------------------------------------------------------
247 ------------------------------------------------------------------
216
248
217
249 IF CDS =1 GENERATE
218
250
219 AMR1Xsync: entity work.Fast2SlowSync
251 AMR1Xsync: entity work.Fast2SlowSync
220 generic map(N => 24)
252 generic map(N => 24)
221 port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X);
253 port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X);
222 AMR1Ysync: entity work.Fast2SlowSync
254 AMR1Ysync: entity work.Fast2SlowSync
223 generic map(N => 24)
255 generic map(N => 24)
224 port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y);
256 port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y);
225 AMR1Zsync: entity work.Fast2SlowSync
257 AMR1Zsync: entity work.Fast2SlowSync
226 generic map(N => 24)
258 generic map(N => 24)
227 port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z);
259 port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z);
228
260
229 AMR2Xsync: entity work.Fast2SlowSync
261 AMR2Xsync: entity work.Fast2SlowSync
230 generic map(N => 24)
262 generic map(N => 24)
231 port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X);
263 port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X);
232 AMR2Ysync: entity work.Fast2SlowSync
264 AMR2Ysync: entity work.Fast2SlowSync
233 generic map(N => 24)
265 generic map(N => 24)
234 port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y);
266 port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y);
235 AMR2Zsync: entity work.Fast2SlowSync
267 AMR2Zsync: entity work.Fast2SlowSync
236 generic map(N => 24)
268 generic map(N => 24)
237 port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z);
269 port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z);
238
270
239 AMR3Xsync: entity work.Fast2SlowSync
271 AMR3Xsync: entity work.Fast2SlowSync
240 generic map(N => 24)
272 generic map(N => 24)
241 port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X);
273 port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X);
242 AMR3Ysync: entity work.Fast2SlowSync
274 AMR3Ysync: entity work.Fast2SlowSync
243 generic map(N => 24)
275 generic map(N => 24)
244 port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y);
276 port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y);
245 AMR3Zsync: entity work.Fast2SlowSync
277 AMR3Zsync: entity work.Fast2SlowSync
246 generic map(N => 24)
278 generic map(N => 24)
247 port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z);
279 port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z);
248
280
249
281
250 AMR4Xsync: entity work.Fast2SlowSync
282 AMR4Xsync: entity work.Fast2SlowSync
251 generic map(N => 24)
283 generic map(N => 24)
252 port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X);
284 port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X);
253 AMR4Ysync: entity work.Fast2SlowSync
285 AMR4Ysync: entity work.Fast2SlowSync
254 generic map(N => 24)
286 generic map(N => 24)
255 port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y);
287 port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y);
256 AMR4Zsync: entity work.Fast2SlowSync
288 AMR4Zsync: entity work.Fast2SlowSync
257 generic map(N => 24)
289 generic map(N => 24)
258 port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z);
290 port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z);
259
291
260
292
261 TEMP1sync: entity work.Fast2SlowSync
293 TEMP1sync: entity work.Fast2SlowSync
262 generic map(N => 24)
294 generic map(N => 24)
263 port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1);
295 port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1);
264 TEMP2sync: entity work.Fast2SlowSync
296 TEMP2sync: entity work.Fast2SlowSync
265 generic map(N => 24)
297 generic map(N => 24)
266 port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2);
298 port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2);
267 TEMP3sync: entity work.Fast2SlowSync
299 TEMP3sync: entity work.Fast2SlowSync
268 generic map(N => 24)
300 generic map(N => 24)
269 port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3);
301 port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3);
270 TEMP4sync: entity work.Fast2SlowSync
302 TEMP4sync: entity work.Fast2SlowSync
271 generic map(N => 24)
303 generic map(N => 24)
272 port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
304 port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4);
273
305
306 END GENERATE;
307
308 IF CDS /= 1 GENERATE
309
310
311 AMR1X_Sync <= AMR1X;
312 AMR1Y_Sync <= AMR1Y;
313 AMR1Z_Sync <= AMR1Z;
314 AMR2X_Sync <= AMR2X;
315 AMR2Y_Sync <= AMR2Y;
316 AMR2Z_Sync <= AMR2Z;
317 Temp1_Sync <= Temp1;
318 Temp2_Sync <= Temp2;
319 AMR3X_Sync <= AMR3X;
320 AMR3Y_Sync <= AMR3Y;
321 AMR3Z_Sync <= AMR3Z;
322 AMR4X_Sync <= AMR4X;
323 AMR4Y_Sync <= AMR4Y;
324 AMR4Z_Sync <= AMR4Z;
325 Temp3_Sync <= Temp3;
326 Temp4_Sync <= Temp4;
327
328 END GENERATE;
274 ------------------------------------------------------------------
329 ------------------------------------------------------------------
275
330
276
331
277 end Behavioral;
332 end Behavioral;
278
333
279
334
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283
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Show file before | Show file after | Hide comments
@@ -1,221 +1,215
1 library IEEE;
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
2 use IEEE.STD_LOGIC_1164.ALL;
3 library lpp;
3 library lpp;
4 use lpp.lpp_ad_conv.all;
4 use lpp.lpp_ad_conv.all;
5 use lpp.lpp_amba.all;
5 use lpp.lpp_amba.all;
6 use lpp.apb_devices_list.all;
6 use lpp.apb_devices_list.all;
7 use lpp.general_purpose.all;
7 use lpp.general_purpose.all;
8 use lpp.Rocket_PCM_Encoder.all;
8 use lpp.Rocket_PCM_Encoder.all;
9 use lpp.iir_filter.all;
9 use lpp.iir_filter.all;
10 use work.config.all;
10 use work.config.all;
11
11
12 entity LF_ACQ_TOP is
12 entity LF_ACQ_TOP is
13 generic(
13 generic(
14 WordSize : integer := 8;
14 WordSize : integer := 8;
15 WordCnt : integer := 144;
15 WordCnt : integer := 144;
16 MinFCount : integer := 64;
16 MinFCount : integer := 64;
17 CstDATA : integer := 0;
17 CstDATA : integer := 0;
18 IIRFilter : integer := 1
18 IIRFilter : integer := 0
19 );
19 );
20 port(
20 port(
21
21
22 reset : in std_logic;
22 reset : in std_logic;
23 clk : in std_logic;
23 clk : in std_logic;
24 SyncSig : in STD_LOGIC;
24 SyncSig : in STD_LOGIC;
25 minorF : in std_logic;
25 minorF : in std_logic;
26 majorF : in std_logic;
26 majorF : in std_logic;
27 sclk : in std_logic;
27 sclk : in std_logic;
28 WordClk : in std_logic;
28 WordClk : in std_logic;
29 LF_SCK : out std_logic;
29 LF_SCK : out std_logic;
30 LF_CNV : out std_logic;
30 LF_CNV : out std_logic;
31 LF_SDO1 : in std_logic;
31 LF_SDO1 : in std_logic;
32 LF_SDO2 : in std_logic;
32 LF_SDO2 : in std_logic;
33 LF_SDO3 : in std_logic;
33 LF_SDO3 : in std_logic;
34 LF1 : out std_logic_vector(15 downto 0);
34 LF1 : out std_logic_vector(15 downto 0);
35 LF2 : out std_logic_vector(15 downto 0);
35 LF2 : out std_logic_vector(15 downto 0);
36 LF3 : out std_logic_vector(15 downto 0)
36 LF3 : out std_logic_vector(15 downto 0)
37 );
37 );
38 end LF_ACQ_TOP;
38 end LF_ACQ_TOP;
39
39
40 architecture AR_LF_ACQ_TOP of LF_ACQ_TOP is
40 architecture AR_LF_ACQ_TOP of LF_ACQ_TOP is
41
41
42 signal LF_ADC_SmplClk : std_logic;
42 signal LF_ADC_SmplClk : std_logic;
43
43
44 signal LF_ADC_SpPulse : std_logic;
44 signal LF_ADC_SpPulse : std_logic;
45 signal SDO : STD_LOGIC_VECTOR(2 DOWNTO 0);
45 signal SDO : STD_LOGIC_VECTOR(2 DOWNTO 0);
46 signal sps : Samples(2 DOWNTO 0);
46 signal sps : Samples(2 DOWNTO 0);
47
47
48 signal LFX : Samples(2 DOWNTO 0);
48 signal LFX : Samples(2 DOWNTO 0);
49 signal sample_val : std_logic;
49 signal sample_val : std_logic;
50 signal AD_in : AD7688_in(2 DOWNTO 0);
50 signal AD_in : AD7688_in(2 DOWNTO 0);
51 signal AD_out : AD7688_out;
51 signal AD_out : AD7688_out;
52 signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
52 signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0);
53 signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
53 signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0);
54 signal sample_out_val : std_logic;
54 signal sample_out_val : std_logic;
55
55
56 signal LF1_sync : std_logic_vector(15 downto 0);
57 signal LF2_sync : std_logic_vector(15 downto 0);
58 signal LF3_sync : std_logic_vector(15 downto 0);
59
56 begin
60 begin
57
61
58
62
59 AD_in(0).sdi <= LF_SDO1;
63 AD_in(0).sdi <= LF_SDO1;
60 AD_in(1).sdi <= LF_SDO2;
64 AD_in(1).sdi <= LF_SDO2;
61 AD_in(2).sdi <= LF_SDO3;
65 AD_in(2).sdi <= LF_SDO3;
62 LF_SCK <= AD_out.SCK;
66 LF_SCK <= AD_out.SCK;
63 LF_CNV <= AD_out.CNV;
67 LF_CNV <= AD_out.CNV;
64
68
65
69
66 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
70 LF_SMPL_CLK0 : entity work.LF_SMPL_CLK
67 generic map(6)
71 generic map(6)
68 port map(
72 port map(
69 reset => reset,
73 reset => reset,
70 wclk => WordClk,
74 wclk => WordClk,
71 SMPL_CLK => LF_ADC_SmplClk
75 SMPL_CLK => LF_ADC_SmplClk
72 );
76 );
73
77
74
78
75 ADC: IF CstDATA =0 GENERATE
79 ADC: IF CstDATA =0 GENERATE
76 ADCs: AD7688_drvr
80 ADCs: AD7688_drvr
77 GENERIC map
81 GENERIC map
78 (
82 (
79 ChanelCount => 3,
83 ChanelCount => 3,
80 clkkHz => 48000
84 clkkHz => 48000
81 )
85 )
82 PORT map
86 PORT map
83 (
87 (
84 clk => clk,
88 clk => clk,
85 rstn => reset,
89 rstn => reset,
86 enable => '1',
90 enable => '1',
87 smplClk => LF_ADC_SmplClk,
91 smplClk => LF_ADC_SmplClk,
88 DataReady => sample_val,
92 DataReady => sample_val,
89 smpout => sps,
93 smpout => sps,
90 AD_in => AD_in,
94 AD_in => AD_in,
91 AD_out => AD_out
95 AD_out => AD_out
92 );
96 );
93
97
94 smpPulse: entity work.OneShot
98 smpPulse: entity work.OneShot
95 Port map(
99 Port map(
96 reset => reset,
100 reset => reset,
97 clk => clk,
101 clk => clk,
98 input => LF_ADC_SmplClk,
102 input => LF_ADC_SmplClk,
99 output => LF_ADC_SpPulse
103 output => LF_ADC_SpPulse
100 );
104 );
101
105
102
106
103
107
104 Filter: IIR_CEL_CTRLR_v2
105 GENERIC map(
106 tech => CFG_MEMTECH,
107 Mem_use => use_RAM,
108 Sample_SZ => Sample_SZ,
109 Coef_SZ => Coef_SZ,
110 Coef_Nb => 25,
111 Coef_sel_SZ => 5,
112 Cels_count => 5,
113 ChanelsCount => ChanelsCount
114 )
115 PORT map(
116 rstn => reset,
117 clk => clk,
118
119 virg_pos => virgPos,
120 coefs => CoefsInitValCst_v2,
121
122 sample_in_val => LF_ADC_SpPulse,
123 sample_in => Filter_sp_in,
124
125 sample_out_val => sample_out_val,
126 sample_out => Filter_sp_out
127 );
128
108
129 NOfilt: IF IIRFilter = 0 GENERATE
109 NOfilt: IF IIRFilter = 0 GENERATE
130 process(reset,clk)
110 process(reset,clk)
131 begin
111 begin
132 if reset ='0' then
112 if reset ='0' then
133 LF1 <= (others => '0');
113 LF1_sync <= (others => '0');
134 LF2 <= (others => '0');
114 LF2_sync <= (others => '0');
135 LF3 <= (others => '0');
115 LF3_sync <= (others => '0');
136 elsif clk'event and clk ='1' then
116 elsif clk'event and clk ='1' then
137 if sample_val = '1' then
117 if sample_val = '1' then
138 LF1 <= sps(0);
118 LF1_sync <= sps(0);
139 LF2 <= sps(1);
119 LF2_sync <= sps(1);
140 LF3 <= sps(2);
120 LF3_sync <= sps(2);
141 end if;
121 end if;
142 end if;
122 end if;
143 end process;
123 end process;
144 END GENERATE;
124 END GENERATE;
125
126
145 filt: IF IIRFilter /= 0 GENERATE
127 filt: IF IIRFilter /= 0 GENERATE
146
128
147 LF1 <= LFX(0);
148 LF2 <= LFX(1);
149 LF3 <= LFX(2);
150
129
151 loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE
130 filtertop: entity work.IIR_FILTER_TOP
131 generic map
132 (
133 V2 => 0
134 )
135 port map
136 (
137 rstn => reset,
138 clk => clk,
152
139
153 loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE
140 SMPclk => LF_ADC_SmplClk,
154 process(reset,clk)
141 LF1_IN => sps(0),
155 begin
142 LF2_IN => sps(1),
156 if reset ='0' then
143 LF3_IN => sps(2),
157 Filter_sp_in(I,J) <= '0';
144
158 -- LFX(I) <= (others => '0');
145 SMPCLKOut => open,
159 elsif clk'event and clk ='1' then
146 LF1_OUT => LF1_sync,
160 if sample_out_val = '1' then
147 LF2_OUT => LF2_sync,
161 LFX(I)(J) <= Filter_sp_out(I,J);
148 LF3_OUT => LF3_sync
162 Filter_sp_in(I,J) <= sps(I)(J);
149 );
163 end if;
150
164 end if;
165 end process;
166 END GENERATE;
167 END GENERATE;
168 END GENERATE;
151 END GENERATE;
169
152
170
153
171
154
172
155
173 END GENERATE;
156 END GENERATE;
174
157
175 CST: IF CstDATA /=0 GENERATE
158 CST: IF CstDATA /=0 GENERATE
176
159
177 LF1 <= LF1cst;
160 LF1_sync <= LF1cst;
178 LF2 <= LF2cst;
161 LF2_sync <= LF2cst;
179 LF3 <= LF3cst;
162 LF3_sync <= LF3cst;
180
163
181 END GENERATE;
164 END GENERATE;
182
165
183
166
184
167
168 LF1sync: entity work.Fast2SlowSync
169 generic map(N => 16)
170 port map( LF1_sync,clk,sclk,SyncSig,LF1);
171
172 LF2sync: entity work.Fast2SlowSync
173 generic map(N => 16)
174 port map( LF2_sync,clk,sclk,SyncSig,LF2);
175
176 LF3sync: entity work.Fast2SlowSync
177 generic map(N => 16)
178 port map( LF3_sync,clk,sclk,SyncSig,LF3);
185
179
186 --Filter: IIR_CEL_FILTER
180 --Filter: IIR_CEL_FILTER
187 -- GENERIC map(
181 -- GENERIC map(
188 -- tech => CFG_MEMTECH,
182 -- tech => CFG_MEMTECH,
189 -- Sample_SZ => Sample_SZ,
183 -- Sample_SZ => Sample_SZ,
190 -- ChanelsCount => ChanelsCount,
184 -- ChanelsCount => ChanelsCount,
191 -- Coef_SZ => Coef_SZ,
185 -- Coef_SZ => Coef_SZ,
192 -- CoefCntPerCel => CoefCntPerCel,
186 -- CoefCntPerCel => CoefCntPerCel,
193 -- Cels_count => Cels_count,
187 -- Cels_count => Cels_count,
194 -- Mem_use => use_RAM
188 -- Mem_use => use_RAM
195 -- )
189 -- )
196 -- PORT map(
190 -- PORT map(
197 -- reset => reset,
191 -- reset => reset,
198 -- clk => clk,
192 -- clk => clk,
199 -- sample_clk => LF_ADC_SmplClk,
193 -- sample_clk => LF_ADC_SmplClk,
200 -- regs_in : IN in_IIR_CEL_reg;
194 -- regs_in : IN in_IIR_CEL_reg;
201 -- regs_out : IN out_IIR_CEL_reg;
195 -- regs_out : IN out_IIR_CEL_reg;
202 -- sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
196 -- sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
203 -- sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
197 -- sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
204 -- GOtest : OUT STD_LOGIC;
198 -- GOtest : OUT STD_LOGIC;
205 -- coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
199 -- coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
206 --
200 --
207 -- );
201 -- );
208
202
209
203
210
204
211
205
212 end AR_LF_ACQ_TOP;
206 end AR_LF_ACQ_TOP;
213
207
214
208
215
209
216
210
217
211
218
212
219
213
220
214
221
215
Show file before | Show file after | Hide comments
@@ -1,60 +1,61
1 include .config
1 include .config
2
2
3 #GRLIB=$(GRLIB)
3 #GRLIB=$(GRLIB)
4 TOP=ici4
4 TOP=ici4
5 BOARD=ICI4-main-BD
5 BOARD=ICI4-main-BD
6 #BOARD=SP601
6 #BOARD=SP601
7 include ../../boards/$(BOARD)/Makefile.inc
7 include ../../boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
9 #UCF=$(GRLIB)/boards/$(BOARD)/ICI3.ucf
10 UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf
10 UCF=../../boards/$(BOARD)/ICI4-Main-BD.ucf
11 QSF=../../boards/$(BOARD)/$(TOP).qsf
11 QSF=../../boards/$(BOARD)/$(TOP).qsf
12 EFFORT=high
12 EFFORT=high
13 ISEMAPOPT="-timing"
13 ISEMAPOPT="-timing"
14 XSTOPT=""
14 XSTOPT=""
15 SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
15 SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
16 VHDLOPTSYNFILES= \
16 VHDLOPTSYNFILES= \
17 ICI4HDL/Convertisseur_config.vhd \
17 ICI4HDL/Convertisseur_config.vhd \
18 ICI4HDL/Convertisseur_Data.vhd \
18 ICI4HDL/Convertisseur_Data.vhd \
19 ICI4HDL/DC_FRAME_PLACER.vhd \
19 ICI4HDL/DC_FRAME_PLACER.vhd \
20 ICI4HDL/DC_SMPL_CLK.vhd \
20 ICI4HDL/DC_SMPL_CLK.vhd \
21 ICI4HDL/LF_FRAME_PLACER.vhd \
21 ICI4HDL/LF_FRAME_PLACER.vhd \
22 ICI4HDL/LF_SMPL_CLK.vhd \
22 ICI4HDL/LF_SMPL_CLK.vhd \
23 ICI4HDL/Fast2SlowSync.vhd \
23 ICI4HDL/Fast2SlowSync.vhd \
24 ICI4HDL/Slow2FastSync.vhd \
24 ICI4HDL/Slow2FastSync.vhd \
25 ICI4HDL/CrossDomainSyncGen.vhd \
25 ICI4HDL/CrossDomainSyncGen.vhd \
26 ICI4HDL/TM_MODULE.vhd \
26 ICI4HDL/TM_MODULE.vhd \
27 ICI4HDL/DC_ACQ_TOP.vhd \
27 ICI4HDL/DC_ACQ_TOP.vhd \
28 ICI4HDL/LF_ACQ_TOP.vhd \
28 ICI4HDL/LF_ACQ_TOP.vhd \
29 ICI4HDL/FAKE_ADC.vhd \
29 ICI4HDL/FAKE_ADC.vhd \
30 ICI4HDL/OneShot.vhd
30 ICI4HDL/OneShot.vhd \
31 ICI4HDL/IIR_FILTER_TOP.vhd
31
32
32
33
33 VHDLSYNFILES= \
34 VHDLSYNFILES= \
34 config.vhd ici4.vhd
35 config.vhd ici4.vhd
35 VHDLSIMFILES=testbench.vhd
36 VHDLSIMFILES=testbench.vhd
36 SIMTOP=testbench
37 SIMTOP=testbench
37 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
38 #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
38 SDCFILE=default.sdc
39 SDCFILE=default.sdc
39 BITGEN=../../boards/$(BOARD)/default.ut
40 BITGEN=../../boards/$(BOARD)/default.ut
40 CLEAN=soft-clean
41 CLEAN=soft-clean
41 VCOMOPT=-explicit
42 VCOMOPT=-explicit
42 TECHLIBS = secureip unisim
43 TECHLIBS = secureip unisim
43
44
44 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
45 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
45 tmtc openchip cypress ihp gleichmann gsi fmf spansion
46 tmtc openchip cypress ihp gleichmann gsi fmf spansion
46 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
47 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
47 leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
48 leon4 leon4b64 l2cache gr1553b iommu haps ascs slink coremp7 pwm \
48 ac97 hcan usb
49 ac97 hcan usb
49 DIRADD =
50 DIRADD =
50 FILEADD =
51 FILEADD =
51 FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
52 FILESKIP = grcan.vhd ddr2.v mobile_ddr.v
52
53
53 include $(GRLIB)/bin/Makefile
54 include $(GRLIB)/bin/Makefile
54 include $(GRLIB)/software/leon3/Makefile
55 include $(GRLIB)/software/leon3/Makefile
55
56
56
57
57 ################## project specific targets ##########################
58 ################## project specific targets ##########################
58
59
59 flash:
60 flash:
60 xc3sprog -c ftdi -p 1 ici4.bit
61 xc3sprog -c ftdi -p 1 ici4.bit
Show file before | Show file after | Hide comments
@@ -1,246 +1,248
1 library ieee;
1 library ieee;
2 use ieee.std_logic_1164.all;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
3 use IEEE.numeric_std.all;
4 library grlib, techmap;
4 library grlib, techmap;
5 use grlib.amba.all;
5 use grlib.amba.all;
6 use grlib.amba.all;
6 use grlib.amba.all;
7 use grlib.stdlib.all;
7 use grlib.stdlib.all;
8 use techmap.gencomp.all;
8 use techmap.gencomp.all;
9 use techmap.allclkgen.all;
9 use techmap.allclkgen.all;
10 library gaisler;
10 library gaisler;
11 use gaisler.memctrl.all;
11 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
14 use gaisler.misc.all;
15 --use gaisler.sim.all;
15 --use gaisler.sim.all;
16 library lpp;
16 library lpp;
17 use lpp.lpp_ad_conv.all;
17 use lpp.lpp_ad_conv.all;
18 use lpp.lpp_amba.all;
18 use lpp.lpp_amba.all;
19 use lpp.apb_devices_list.all;
19 use lpp.apb_devices_list.all;
20 use lpp.general_purpose.all;
20 use lpp.general_purpose.all;
21 use lpp.Rocket_PCM_Encoder.all;
21 use lpp.Rocket_PCM_Encoder.all;
22
22
23
23
24 use work.Convertisseur_config.all;
24 use work.Convertisseur_config.all;
25
25
26
26
27 use work.config.all;
27 use work.config.all;
28 --==================================================================
28 --==================================================================
29 --
29 --
30 --
30 --
31 -- FPGA FREQ = 48MHz
31 -- FPGA FREQ = 48MHz
32 -- ADC Oscillator frequency = 12MHz
32 -- ADC Oscillator frequency = 12MHz
33 --
33 --
34 --
34 --
35 --==================================================================
35 --==================================================================
36
36
37 entity ici4 is
37 entity ici4 is
38 generic (
38 generic (
39 fabtech : integer := CFG_FABTECH;
39 fabtech : integer := CFG_FABTECH;
40 memtech : integer := CFG_MEMTECH;
40 memtech : integer := CFG_MEMTECH;
41 padtech : integer := CFG_PADTECH;
41 padtech : integer := CFG_PADTECH;
42 clktech : integer := CFG_CLKTECH;
42 clktech : integer := CFG_CLKTECH;
43 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
43 WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64
44 );
44 );
45 port (
45 port (
46 reset : in std_ulogic;
46 reset : in std_ulogic;
47 clk : in std_ulogic;
47 clk : in std_ulogic;
48 sclk : in std_logic;
48 sclk : in std_logic;
49 Gate : in std_logic;
49 Gate : in std_logic;
50 MinF : in std_logic;
50 MinF : in std_logic;
51 MajF : in std_logic;
51 MajF : in std_logic;
52 Data : out std_logic;
52 Data : out std_logic;
53 LF_SCK : out std_logic;
53 LF_SCK : out std_logic;
54 LF_CNV : out std_logic;
54 LF_CNV : out std_logic;
55 LF_SDO1 : in std_logic;
55 LF_SDO1 : in std_logic;
56 LF_SDO2 : in std_logic;
56 LF_SDO2 : in std_logic;
57 LF_SDO3 : in std_logic;
57 LF_SDO3 : in std_logic;
58 DC_ADC_Sclk : out std_logic;
58 DC_ADC_Sclk : out std_logic;
59 DC_ADC_IN : in std_logic_vector(1 downto 0);
59 DC_ADC_IN : in std_logic_vector(1 downto 0);
60 DC_ADC_ClkDiv : out std_logic;
60 DC_ADC_ClkDiv : out std_logic;
61 DC_ADC_FSynch : out std_logic;
61 DC_ADC_FSynch : out std_logic;
62 SET_RESET0 : out std_logic;
62 SET_RESET0 : out std_logic;
63 SET_RESET1 : out std_logic;
63 SET_RESET1 : out std_logic;
64 LED : out std_logic
64 LED : out std_logic
65 );
65 );
66 end;
66 end;
67
67
68 architecture rtl of ici4 is
68 architecture rtl of ici4 is
69
69
70 signal clk_buf,reset_buf : std_logic;
70 signal clk_buf,reset_buf : std_logic;
71
71
72 Constant FramePlacerCount : integer := 2;
72 Constant FramePlacerCount : integer := 2;
73
73
74
74
75 signal WordCount : integer range 0 to WordCnt-1;
75 signal WordCount : integer range 0 to WordCnt-1;
76 signal WordClk : std_logic;
76 signal WordClk : std_logic;
77
77
78
78
79 signal AMR1X : std_logic_vector(23 downto 0);
79 signal AMR1X : std_logic_vector(23 downto 0);
80 signal AMR1Y : std_logic_vector(23 downto 0);
80 signal AMR1Y : std_logic_vector(23 downto 0);
81 signal AMR1Z : std_logic_vector(23 downto 0);
81 signal AMR1Z : std_logic_vector(23 downto 0);
82
82
83 signal AMR2X : std_logic_vector(23 downto 0);
83 signal AMR2X : std_logic_vector(23 downto 0);
84 signal AMR2Y : std_logic_vector(23 downto 0);
84 signal AMR2Y : std_logic_vector(23 downto 0);
85 signal AMR2Z : std_logic_vector(23 downto 0);
85 signal AMR2Z : std_logic_vector(23 downto 0);
86
86
87 signal AMR3X : std_logic_vector(23 downto 0);
87 signal AMR3X : std_logic_vector(23 downto 0);
88 signal AMR3Y : std_logic_vector(23 downto 0);
88 signal AMR3Y : std_logic_vector(23 downto 0);
89 signal AMR3Z : std_logic_vector(23 downto 0);
89 signal AMR3Z : std_logic_vector(23 downto 0);
90
90
91 signal AMR4X : std_logic_vector(23 downto 0);
91 signal AMR4X : std_logic_vector(23 downto 0);
92 signal AMR4Y : std_logic_vector(23 downto 0);
92 signal AMR4Y : std_logic_vector(23 downto 0);
93 signal AMR4Z : std_logic_vector(23 downto 0);
93 signal AMR4Z : std_logic_vector(23 downto 0);
94
94
95
95
96 signal TEMP1 : std_logic_vector(23 downto 0);
96 signal TEMP1 : std_logic_vector(23 downto 0);
97 signal TEMP2 : std_logic_vector(23 downto 0);
97 signal TEMP2 : std_logic_vector(23 downto 0);
98 signal TEMP3 : std_logic_vector(23 downto 0);
98 signal TEMP3 : std_logic_vector(23 downto 0);
99 signal TEMP4 : std_logic_vector(23 downto 0);
99 signal TEMP4 : std_logic_vector(23 downto 0);
100
100
101 signal LF1 : std_logic_vector(15 downto 0);
101 signal LF1 : std_logic_vector(15 downto 0);
102 signal LF2 : std_logic_vector(15 downto 0);
102 signal LF2 : std_logic_vector(15 downto 0);
103 signal LF3 : std_logic_vector(15 downto 0);
103 signal LF3 : std_logic_vector(15 downto 0);
104
104
105 signal data_int : std_logic;
105 signal data_int : std_logic;
106
106
107 signal CrossDomainSync : std_logic;
107 signal CrossDomainSync : std_logic;
108
108
109 begin
109 begin
110
110
111
111
112 LED <= not data_int;
112 LED <= not data_int;
113 data <= data_int;
113 data <= data_int;
114
114
115
115
116
116
117 CDS0 : entity work.CrossDomainSyncGen
117 CDS0 : entity work.CrossDomainSyncGen
118 Port map(
118 Port map(
119 reset => reset,
119 reset => reset,
120 ClockS => sclk,
120 ClockS => sclk,
121 ClockF => clk,
121 ClockF => clk,
122 SyncSignal => CrossDomainSync
122 SyncSignal => CrossDomainSync
123 );
123 );
124
124
125 TM : entity work.TM_MODULE
125 TM : entity work.TM_MODULE
126 generic map(
126 generic map(
127 WordSize => WordSize,
127 WordSize => WordSize,
128 WordCnt => WordCnt,
128 WordCnt => WordCnt,
129 MinFCount => MinFCount
129 MinFCount => MinFCount
130 )
130 )
131 port map(
131 port map(
132
132
133 reset =>reset,
133 reset =>reset,
134 clk =>clk,
134 clk =>clk,
135 MinF =>MinF,
135 MinF =>MinF,
136 MajF =>MajF,
136 MajF =>MajF,
137 sclk =>sclk,
137 sclk =>sclk,
138 gate =>gate,
138 gate =>gate,
139 data =>data_int,
139 data =>data_int,
140 WordClk =>WordClk,
140 WordClk =>WordClk,
141
141
142
142
143 LF1 => LF1,
143 LF1 => LF1,
144 LF2 => LF2,
144 LF2 => LF2,
145 LF3 => LF3,
145 LF3 => LF3,
146
146
147 AMR1X => AMR1X,
147 AMR1X => AMR1X,
148 AMR1Y => AMR1Y,
148 AMR1Y => AMR1Y,
149 AMR1Z => AMR1Z,
149 AMR1Z => AMR1Z,
150
150
151 AMR2X => AMR2X,
151 AMR2X => AMR2X,
152 AMR2Y => AMR2Y,
152 AMR2Y => AMR2Y,
153 AMR2Z => AMR2Z,
153 AMR2Z => AMR2Z,
154
154
155 AMR3X => AMR3X,
155 AMR3X => AMR3X,
156 AMR3Y => AMR3Y,
156 AMR3Y => AMR3Y,
157 AMR3Z => AMR3Z,
157 AMR3Z => AMR3Z,
158
158
159 AMR4X => AMR4X,
159 AMR4X => AMR4X,
160 AMR4Y => AMR4Y,
160 AMR4Y => AMR4Y,
161 AMR4Z => AMR4Z,
161 AMR4Z => AMR4Z,
162
162
163 Temp1 => Temp1,
163 Temp1 => Temp1,
164 Temp2 => Temp2,
164 Temp2 => Temp2,
165 Temp3 => Temp3,
165 Temp3 => Temp3,
166 Temp4 => Temp4
166 Temp4 => Temp4
167 );
167 );
168
168
169 DC_ADC0:entity work.DC_ACQ_TOP
169 DC_ADC0:entity work.DC_ACQ_TOP
170 generic map (
170 generic map (
171 WordSize => WordSize,
171 WordSize => WordSize,
172 WordCnt => WordCnt,
172 WordCnt => WordCnt,
173 MinFCount => MinFCount,
173 MinFCount => MinFCount,
174 EnableSR => 0,
174 EnableSR => 0,
175 FakeADC => 1
175 CstDATA => SEND_CONSTANT_DATA,
176 FakeADC => 0
176 )
177 )
177 port map(
178 port map(
178
179
179 reset => reset,
180 reset => reset,
180 clk => clk,
181 clk => clk,
181 SyncSig => CrossDomainSync,
182 SyncSig => CrossDomainSync,
182 minorF => minF,
183 minorF => minF,
183 majorF => majF,
184 majorF => majF,
184 sclk => sclk,
185 sclk => sclk,
185 WordClk => WordClk,
186 WordClk => WordClk,
186
187
187 DC_ADC_Sclk => DC_ADC_Sclk,
188 DC_ADC_Sclk => DC_ADC_Sclk,
188 DC_ADC_IN => DC_ADC_IN,
189 DC_ADC_IN => DC_ADC_IN,
189 DC_ADC_ClkDiv => DC_ADC_ClkDiv,
190 DC_ADC_ClkDiv => DC_ADC_ClkDiv,
190 DC_ADC_FSynch => DC_ADC_FSynch,
191 DC_ADC_FSynch => DC_ADC_FSynch,
191 SET_RESET0 => SET_RESET0,
192 SET_RESET0 => SET_RESET0,
192 SET_RESET1 => SET_RESET1,
193 SET_RESET1 => SET_RESET1,
193
194
194 AMR1X => AMR1X,
195 AMR1X => AMR1X,
195 AMR1Y => AMR1Y,
196 AMR1Y => AMR1Y,
196 AMR1Z => AMR1Z,
197 AMR1Z => AMR1Z,
197
198
198 AMR2X => AMR2X,
199 AMR2X => AMR2X,
199 AMR2Y => AMR2Y,
200 AMR2Y => AMR2Y,
200 AMR2Z => AMR2Z,
201 AMR2Z => AMR2Z,
201
202
202 AMR3X => AMR3X,
203 AMR3X => AMR3X,
203 AMR3Y => AMR3Y,
204 AMR3Y => AMR3Y,
204 AMR3Z => AMR3Z,
205 AMR3Z => AMR3Z,
205
206
206 AMR4X => AMR4X,
207 AMR4X => AMR4X,
207 AMR4Y => AMR4Y,
208 AMR4Y => AMR4Y,
208 AMR4Z => AMR4Z,
209 AMR4Z => AMR4Z,
209
210
210 Temp1 => Temp1,
211 Temp1 => Temp1,
211 Temp2 => Temp2,
212 Temp2 => Temp2,
212 Temp3 => Temp3,
213 Temp3 => Temp3,
213 Temp4 => Temp4
214 Temp4 => Temp4
214 );
215 );
215
216
216
217
217 LF: entity work.LF_ACQ_TOP
218 LF: entity work.LF_ACQ_TOP
218 generic map(
219 generic map(
219 WordSize => WordSize,
220 WordSize => WordSize,
220 WordCnt => WordCnt,
221 WordCnt => WordCnt,
221 MinFCount => MinFCount,
222 MinFCount => MinFCount,
222 CstDATA => 0
223 CstDATA => SEND_CONSTANT_DATA,
224 IIRFilter => 0
223 )
225 )
224 port map(
226 port map(
225
227
226 reset => reset,
228 reset => reset,
227 clk => clk,
229 clk => clk,
228 SyncSig => CrossDomainSync,
230 SyncSig => CrossDomainSync,
229 minorF => minF,
231 minorF => minF,
230 majorF => majF,
232 majorF => majF,
231 sclk => sclk,
233 sclk => sclk,
232 WordClk => WordClk,
234 WordClk => WordClk,
233 LF_SCK => LF_SCK,
235 LF_SCK => LF_SCK,
234 LF_CNV => LF_CNV,
236 LF_CNV => LF_CNV,
235 LF_SDO1 => LF_SDO1,
237 LF_SDO1 => LF_SDO1,
236 LF_SDO2 => LF_SDO2,
238 LF_SDO2 => LF_SDO2,
237 LF_SDO3 => LF_SDO3,
239 LF_SDO3 => LF_SDO3,
238 LF1 => LF1,
240 LF1 => LF1,
239 LF2 => LF2,
241 LF2 => LF2,
240 LF3 => LF3
242 LF3 => LF3
241 );
243 );
242
244
243 end rtl;
245 end rtl;
244
246
245
247
246
248
Show file before | Show file after | Hide comments
@@ -1,338 +1,338
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 library IEEE;
23 library IEEE;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use IEEE.std_logic_1164.all;
25 use IEEE.std_logic_1164.all;
26 library lpp;
26 library lpp;
27 use lpp.iir_filter.all;
27 use lpp.iir_filter.all;
28 use lpp.general_purpose.all;
28 use lpp.general_purpose.all;
29
29
30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
30 --TODO amliorer la gestion de la RAM et de la flexibilit du filtre
31
31
32 entity IIR_CEL_CTRLR is
32 entity IIR_CEL_CTRLR is
33 generic(
33 generic(
34 tech : integer := 0;
34 tech : integer := 0;
35 Sample_SZ : integer := 16;
35 Sample_SZ : integer := 16;
36 ChanelsCount : integer := 1;
36 ChanelsCount : integer := 1;
37 Coef_SZ : integer := 9;
37 Coef_SZ : integer := 9;
38 CoefCntPerCel: integer := 6;
38 CoefCntPerCel: integer := 6;
39 Cels_count : integer := 5;
39 Cels_count : integer := 5;
40 Mem_use : integer := use_RAM
40 Mem_use : integer := use_RAM
41 );
41 );
42 port(
42 port(
43 reset : in std_logic;
43 reset : in std_logic;
44 clk : in std_logic;
44 clk : in std_logic;
45 sample_clk : in std_logic;
45 sample_clk : in std_logic;
46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
46 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
47 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
48 virg_pos : in integer;
48 virg_pos : in integer;
49 GOtest : out std_logic;
49 GOtest : out std_logic;
50 coefs : in std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0)
50 coefs : in std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0)
51 );
51 );
52 end IIR_CEL_CTRLR;
52 end IIR_CEL_CTRLR;
53
53
54
54
55
55
56
56
57 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
57 architecture ar_IIR_CEL_CTRLR of IIR_CEL_CTRLR is
58
58
59 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
59 subtype sampleVect is std_logic_vector(Sample_SZ-1 downto 0);
60
60
61 signal smpl_clk_old : std_logic := '0';
61 signal smpl_clk_old : std_logic := '0';
62 signal WD_sel : std_logic := '0';
62 signal WD_sel : std_logic := '0';
63 signal Read : std_logic := '0';
63 signal Read : std_logic := '0';
64 signal SVG_ADDR : std_logic := '0';
64 signal SVG_ADDR : std_logic := '0';
65 signal count : std_logic := '0';
65 signal count : std_logic := '0';
66 signal Write : std_logic := '0';
66 signal Write : std_logic := '0';
67 signal WADDR_sel : std_logic := '0';
67 signal WADDR_sel : std_logic := '0';
68 signal GO_0 : std_logic := '0';
68 signal GO_0 : std_logic := '0';
69
69
70 signal RAM_sample_in : sampleVect;
70 signal RAM_sample_in : sampleVect;
71 signal RAM_sample_in_bk: sampleVect;
71 signal RAM_sample_in_bk: sampleVect;
72 signal RAM_sample_out : sampleVect;
72 signal RAM_sample_out : sampleVect;
73 signal ALU_ctrl : std_logic_vector(3 downto 0);
73 signal ALU_ctrl : std_logic_vector(3 downto 0);
74 signal ALU_sample_in : sampleVect;
74 signal ALU_sample_in : sampleVect;
75 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
75 signal ALU_Coef_in : std_logic_vector(Coef_SZ-1 downto 0);
76 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
76 signal ALU_out : std_logic_vector(Sample_SZ+Coef_SZ-1 downto 0);
77 signal curentCel : integer range 0 to Cels_count-1 := 0;
77 signal curentCel : integer range 0 to Cels_count-1 := 0;
78 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
78 signal curentChan : integer range 0 to ChanelsCount-1 := 0;
79
79
80
80
81 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
81 type sampleBuffT is array(ChanelsCount-1 downto 0) of sampleVect;
82
82
83 signal sample_in_BUFF : sampleBuffT;
83 signal sample_in_BUFF : sampleBuffT;
84 signal sample_out_BUFF : sampleBuffT;
84 signal sample_out_BUFF : sampleBuffT;
85
85
86 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
86 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
87 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
87 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
88
88
89 type CoefsRegT is record
89 type CoefsRegT is record
90 numCoefs : CoefTblT;
90 numCoefs : CoefTblT;
91 denCoefs : CoefTblT;
91 denCoefs : CoefTblT;
92 end record;
92 end record;
93
93
94 signal CoefsReg : CoefsRegT;
94 signal CoefsReg : CoefsRegT;
95
95
96 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
96 type fsmIIR_CEL_T is (waiting,pipe1,computeb1,computeb2,computea1,computea2,next_cel,pipe2,pipe3,next_chan);
97
97
98 signal IIR_CEL_STATE : fsmIIR_CEL_T;
98 signal IIR_CEL_STATE : fsmIIR_CEL_T;
99
99
100 begin
100 begin
101 GOtest <= GO_0;
101 GOtest <= GO_0;
102
102
103 --coefsConnectL0: for z in 0 to Cels_count-1 generate
103 --coefsConnectL0: for z in 0 to Cels_count-1 generate
104 -- coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
104 -- coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
105 -- coefsConnectL2: for x in 0 to Coef_SZ-1 generate
105 -- coefsConnectL2: for x in 0 to Coef_SZ-1 generate
106 -- CoefsReg.numCoefs(z)(y)(x) <= coefs(x + (((2*y))*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
106 -- CoefsReg.numCoefs(z)(y)(x) <= coefs(x + (((2*y))*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
107 -- CoefsReg.denCoefs(z)(y)(x) <= coefs(x + (((2*y)+1)*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
107 -- CoefsReg.denCoefs(z)(y)(x) <= coefs(x + (((2*y)+1)*Coef_SZ) + (z*Coef_SZ*CoefCntPerCel));
108 -- end generate;
108 -- end generate;
109 -- end generate;
109 -- end generate;
110 --end generate;
110 --end generate;
111
111
112 coefsConnectL0: for z in 0 to Cels_count-1 generate
112 coefsConnectL0: for z in 0 to Cels_count-1 generate
113 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
113 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
114 CoefsReg.numCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
114 CoefsReg.numCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
115 CoefsReg.denCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
115 CoefsReg.denCoefs(z)(y) <= coefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
116 end generate;
116 end generate;
117 end generate;
117 end generate;
118
118
119
119
120
120
121
121
122 RAM_CTRLR2inst : RAM_CTRLR2
122 RAM_CTRLR2inst : RAM_CTRLR2
123 generic map(tech,Sample_SZ,Mem_use)
123 generic map(tech,Sample_SZ,Mem_use)
124 port map(
124 port map(
125 reset => reset,
125 reset => reset,
126 clk => clk,
126 clk => clk,
127 WD_sel => WD_sel,
127 WD_sel => WD_sel,
128 Read => Read,
128 Read => Read,
129 WADDR_sel => WADDR_sel,
129 WADDR_sel => WADDR_sel,
130 count => count,
130 count => count,
131 SVG_ADDR => SVG_ADDR,
131 SVG_ADDR => SVG_ADDR,
132 Write => Write,
132 Write => Write,
133 GO_0 => GO_0,
133 GO_0 => GO_0,
134 sample_in => RAM_sample_in,
134 sample_in => RAM_sample_in,
135 sample_out => RAM_sample_out
135 sample_out => RAM_sample_out
136 );
136 );
137
137
138
138
139
139
140 ALU_inst :ALU
140 ALU_inst : ALU_V0
141 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
141 generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ)
142 port map(
142 port map(
143 clk => clk,
143 clk => clk,
144 reset => reset,
144 reset => reset,
145 ctrl => ALU_ctrl,
145 ctrl => ALU_ctrl,
146 OP1 => ALU_sample_in,
146 OP1 => ALU_sample_in,
147 OP2 => ALU_coef_in,
147 OP2 => ALU_coef_in,
148 RES => ALU_out
148 RES => ALU_out
149 );
149 );
150
150
151
151
152
152
153
153
154
154
155
155
156 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
156 WD_sel <= '0' when (IIR_CEL_STATE = waiting or IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb2) else '1';
157 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
157 Read <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
158 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
158 WADDR_sel <= '1' when IIR_CEL_STATE = computea1 else '0';
159 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
159 count <= '1' when (IIR_CEL_STATE = pipe1 or IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1) else '0';
160 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
160 SVG_ADDR <= '1' when IIR_CEL_STATE = computeb2 else '0';
161 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
161 --Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or (IIR_CEL_STATE = computea1 and not(curentChan = 0 and curentCel = 0)) or IIR_CEL_STATE = computea2) else '0';
162 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
162 Write <= '1' when (IIR_CEL_STATE = computeb1 or IIR_CEL_STATE = computeb2 or IIR_CEL_STATE = computea1 or IIR_CEL_STATE = computea2) else '0';
163
163
164 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
164 GO_0 <= '1' when IIR_CEL_STATE = waiting else '0';
165
165
166
166
167
167
168
168
169
169
170
170
171
171
172 process(clk,reset)
172 process(clk,reset)
173 variable result : std_logic_vector(Sample_SZ-1 downto 0);
173 variable result : std_logic_vector(Sample_SZ-1 downto 0);
174
174
175 begin
175 begin
176
176
177 if reset = '0' then
177 if reset = '0' then
178
178
179 smpl_clk_old <= '0';
179 smpl_clk_old <= '0';
180 RAM_sample_in <= (others=> '0');
180 RAM_sample_in <= (others=> '0');
181 ALU_ctrl <= IDLE;
181 ALU_ctrl <= IDLE_V0;
182 ALU_sample_in <= (others=> '0');
182 ALU_sample_in <= (others=> '0');
183 ALU_Coef_in <= (others=> '0');
183 ALU_Coef_in <= (others=> '0');
184 RAM_sample_in_bk<= (others=> '0');
184 RAM_sample_in_bk<= (others=> '0');
185 curentCel <= 0;
185 curentCel <= 0;
186 curentChan <= 0;
186 curentChan <= 0;
187 IIR_CEL_STATE <= waiting;
187 IIR_CEL_STATE <= waiting;
188 resetL0 : for i in 0 to ChanelsCount-1 loop
188 resetL0 : for i in 0 to ChanelsCount-1 loop
189 sample_in_BUFF(i) <= (others => '0');
189 sample_in_BUFF(i) <= (others => '0');
190 sample_out_BUFF(i) <= (others => '0');
190 sample_out_BUFF(i) <= (others => '0');
191 resetL1: for j in 0 to Sample_SZ-1 loop
191 resetL1: for j in 0 to Sample_SZ-1 loop
192 sample_out(i,j) <= '0';
192 sample_out(i,j) <= '0';
193 end loop;
193 end loop;
194 end loop;
194 end loop;
195
195
196 elsif clk'event and clk = '1' then
196 elsif clk'event and clk = '1' then
197
197
198 smpl_clk_old <= sample_clk;
198 smpl_clk_old <= sample_clk;
199
199
200 case IIR_CEL_STATE is
200 case IIR_CEL_STATE is
201
201
202 when waiting =>
202 when waiting =>
203 if sample_clk = '1' and smpl_clk_old = '0' then
203 if sample_clk = '1' and smpl_clk_old = '0' then
204 IIR_CEL_STATE <= pipe1;
204 IIR_CEL_STATE <= pipe1;
205 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
205 RAM_sample_in <= std_logic_vector(sample_in_BUFF(0));
206 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
206 ALU_sample_in <= std_logic_vector(sample_in_BUFF(0));
207
207
208 else
208 else
209 ALU_ctrl <= IDLE;
209 ALU_ctrl <= IDLE_V0;
210 smplConnectL0: for i in 0 to ChanelsCount-1 loop
210 smplConnectL0: for i in 0 to ChanelsCount-1 loop
211 smplConnectL1: for j in 0 to Sample_SZ-1 loop
211 smplConnectL1: for j in 0 to Sample_SZ-1 loop
212 sample_in_BUFF(i)(j) <= sample_in(i,j);
212 sample_in_BUFF(i)(j) <= sample_in(i,j);
213 sample_out(i,j) <= sample_out_BUFF(i)(j);
213 sample_out(i,j) <= sample_out_BUFF(i)(j);
214 end loop;
214 end loop;
215 end loop;
215 end loop;
216 end if;
216 end if;
217 curentCel <= 0;
217 curentCel <= 0;
218 curentChan <= 0;
218 curentChan <= 0;
219
219
220 when pipe1 =>
220 when pipe1 =>
221 IIR_CEL_STATE <= computeb1;
221 IIR_CEL_STATE <= computeb1;
222 ALU_ctrl <= MAC_op;
222 ALU_ctrl <= MAC_op_V0;
223 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
223 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0));
224
224
225 when computeb1 =>
225 when computeb1 =>
226
226
227 ALU_ctrl <= MAC_op;
227 ALU_ctrl <= MAC_op_V0;
228 ALU_sample_in <= RAM_sample_out;
228 ALU_sample_in <= RAM_sample_out;
229 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
229 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1));
230 IIR_CEL_STATE <= computeb2;
230 IIR_CEL_STATE <= computeb2;
231 RAM_sample_in <= RAM_sample_in_bk;
231 RAM_sample_in <= RAM_sample_in_bk;
232 when computeb2 =>
232 when computeb2 =>
233 ALU_sample_in <= RAM_sample_out;
233 ALU_sample_in <= RAM_sample_out;
234 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
234 ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(2));
235 IIR_CEL_STATE <= computea1;
235 IIR_CEL_STATE <= computea1;
236
236
237
237
238 when computea1 =>
238 when computea1 =>
239 ALU_sample_in <= RAM_sample_out;
239 ALU_sample_in <= RAM_sample_out;
240 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
240 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(1));
241 IIR_CEL_STATE <= computea2;
241 IIR_CEL_STATE <= computea2;
242
242
243
243
244 when computea2 =>
244 when computea2 =>
245 ALU_sample_in <= RAM_sample_out;
245 ALU_sample_in <= RAM_sample_out;
246 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
246 ALU_Coef_in <= std_logic_vector(CoefsReg.DenCoefs(curentCel)(2));
247 IIR_CEL_STATE <= next_cel;
247 IIR_CEL_STATE <= next_cel;
248
248
249
249
250 when next_cel =>
250 when next_cel =>
251 ALU_ctrl <= clr_mac;
251 ALU_ctrl <= clr_mac_V0;
252 IIR_CEL_STATE <= pipe2;
252 IIR_CEL_STATE <= pipe2;
253
253
254 when pipe2 =>
254 when pipe2 =>
255 IIR_CEL_STATE <= pipe3;
255 IIR_CEL_STATE <= pipe3;
256
256
257
257
258 when pipe3 =>
258 when pipe3 =>
259
259
260 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
260 result := ALU_out(Sample_SZ+virg_pos-1 downto virg_pos);
261
261
262 sample_out_BUFF(0) <= result;
262 sample_out_BUFF(0) <= result;
263 RAM_sample_in_bk <= result;
263 RAM_sample_in_bk <= result;
264 RAM_sample_in <= result;
264 RAM_sample_in <= result;
265 if curentCel = Cels_count-1 then
265 if curentCel = Cels_count-1 then
266 IIR_CEL_STATE <= next_chan;
266 IIR_CEL_STATE <= next_chan;
267 curentCel <= 0;
267 curentCel <= 0;
268 else
268 else
269 curentCel <= curentCel + 1;
269 curentCel <= curentCel + 1;
270 IIR_CEL_STATE <= pipe1;
270 IIR_CEL_STATE <= pipe1;
271 ALU_sample_in <= result;
271 ALU_sample_in <= result;
272 end if;
272 end if;
273 when next_chan =>
273 when next_chan =>
274
274
275 rotate : for i in 1 to ChanelsCount-1 loop
275 rotate : for i in 1 to ChanelsCount-1 loop
276 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
276 sample_in_BUFF(i-1) <= sample_in_BUFF(i);
277 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
277 sample_out_BUFF(i-1) <= sample_out_BUFF(i);
278 end loop;
278 end loop;
279 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
279 sample_in_BUFF(ChanelsCount-1) <= sample_in_BUFF(0);
280 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
280 sample_out_BUFF(ChanelsCount-1)<= sample_out_BUFF(0);
281
281
282 if curentChan = (ChanelsCount-1) then
282 if curentChan = (ChanelsCount-1) then
283 IIR_CEL_STATE <= waiting;
283 IIR_CEL_STATE <= waiting;
284 ALU_ctrl <= clr_mac;
284 ALU_ctrl <= clr_mac_V0;
285 elsif ChanelsCount>1 then
285 elsif ChanelsCount>1 then
286 curentChan <= curentChan + 1;
286 curentChan <= curentChan + 1;
287 IIR_CEL_STATE <= pipe1;
287 IIR_CEL_STATE <= pipe1;
288 ALU_sample_in <= sample_in_BUFF(1);
288 ALU_sample_in <= sample_in_BUFF(1);
289 RAM_sample_in <= sample_in_BUFF(1);
289 RAM_sample_in <= sample_in_BUFF(1);
290 end if;
290 end if;
291 end case;
291 end case;
292
292
293 end if;
293 end if;
294 end process;
294 end process;
295
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301 end ar_IIR_CEL_CTRLR;
301 end ar_IIR_CEL_CTRLR;
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@@ -1,19 +1,19
1 APB_IIR_CEL.vhd
1 APB_IIR_CEL.vhd
2 APB_IIR_Filter.vhd
2 APB_IIR_Filter.vhd
3 FILTER.vhd
4 FILTER_RAM_CTRLR.vhd
5 FILTERcfg.vhd
3 FILTERcfg.vhd
6 FilterCTRLR.vhd
4 FilterCTRLR.vhd
7 IIR_CEL_CTRLR.vhd
5 FILTER_RAM_CTRLR.vhd
8 IIR_CEL_CTRLR_v2.vhd
6 FILTER.vhd
9 IIR_CEL_CTRLR_v2_CONTROL.vhd
7 IIR_CEL_CTRLR_v2_CONTROL.vhd
10 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
9 IIR_CEL_CTRLR_v2.vhd
10 IIR_CEL_CTRLR.vhd
11 IIR_CEL_FILTER.vhd
11 IIR_CEL_FILTER.vhd
12 RAM.vhd
12 iir_filter.vhd
13 RAM_CEL_N.vhd
13 RAM_CEL.vhd
14 RAM_CEL.vhd
14 RAM_CEL_N.vhd
15 RAM_CTRLR2.vhd
15 RAM_CTRLR2.vhd
16 RAM_CTRLR_v2.vhd
16 RAM_CTRLR_v2.vhd
17 RAM.vhd
17 Top_Filtre_IIR.vhd
18 Top_Filtre_IIR.vhd
18 Top_IIR.vhd
19 Top_IIR.vhd
19 iir_filter.vhd
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@@ -1,11 +1,11
1 APB_FFT_half.vhd
1 APB_FFT.vhd
2 APB_FFT.vhd
2 APB_FFT_half.vhd
3 Driver_FFT.vhd
3 Driver_FFT.vhd
4 FFTamont.vhd
5 FFTaval.vhd
4 FFT.vhd
6 FFT.vhd
5 FFT.vhd.bak
7 FFT.vhd.bak
6 FFTamont.vhd
7 FFTaval.vhd
8 Flag_Extremum.vhd
8 Flag_Extremum.vhd
9 Flag_Extremum.vhd.bak
9 Flag_Extremum.vhd.bak
10 Linker_FFT.vhd
10 Linker_FFT.vhd
11 lpp_fft.vhd
11 lpp_fft.vhd
Show file before | Show file after | Hide comments
@@ -1,272 +1,331
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 --UPDATE
22 --UPDATE
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27
27
28 LIBRARY ieee;
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
29 USE ieee.std_logic_1164.ALL;
30
30
31
31
32
32
33 PACKAGE general_purpose IS
33 PACKAGE general_purpose IS
34
34
35
35
36
36
37 COMPONENT Clk_divider IS
37 COMPONENT Clk_divider IS
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 TargetFreq_Hz : INTEGER := 50000);
39 TargetFreq_Hz : INTEGER := 50000);
40 PORT (clk : IN STD_LOGIC;
40 PORT (clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clk_divided : OUT STD_LOGIC);
42 clk_divided : OUT STD_LOGIC);
43 END COMPONENT;
43 END COMPONENT;
44
44
45
45
46 COMPONENT Clk_divider2 IS
46 COMPONENT Clk_divider2 IS
47 generic(N : integer := 16);
47 generic(N : integer := 16);
48 port(
48 port(
49 clk_in : in std_logic;
49 clk_in : in std_logic;
50 clk_out : out std_logic);
50 clk_out : out std_logic);
51 END COMPONENT;
51 END COMPONENT;
52
52
53 COMPONENT Adder IS
53 COMPONENT Adder IS
54 GENERIC(
54 GENERIC(
55 Input_SZ_A : INTEGER := 16;
55 Input_SZ_A : INTEGER := 16;
56 Input_SZ_B : INTEGER := 16
56 Input_SZ_B : INTEGER := 16
57
57
58 );
58 );
59 PORT(
59 PORT(
60 clk : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
61 reset : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
62 clr : IN STD_LOGIC;
63 load : IN STD_LOGIC;
63 load : IN STD_LOGIC;
64 add : IN STD_LOGIC;
64 add : IN STD_LOGIC;
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 );
68 );
69 END COMPONENT;
69 END COMPONENT;
70
70
71 COMPONENT Adder_V0 is
72 generic(
73 Input_SZ_A : integer := 16;
74 Input_SZ_B : integer := 16
75
76 );
77 port(
78 clk : in std_logic;
79 reset : in std_logic;
80 clr : in std_logic;
81 add : in std_logic;
82 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
83 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
84 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
85 );
86 end COMPONENT;
87
71 COMPONENT ADDRcntr IS
88 COMPONENT ADDRcntr IS
72 PORT(
89 PORT(
73 clk : IN STD_LOGIC;
90 clk : IN STD_LOGIC;
74 reset : IN STD_LOGIC;
91 reset : IN STD_LOGIC;
75 count : IN STD_LOGIC;
92 count : IN STD_LOGIC;
76 clr : IN STD_LOGIC;
93 clr : IN STD_LOGIC;
77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
94 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
78 );
95 );
79 END COMPONENT;
96 END COMPONENT;
80
97
81 COMPONENT ALU IS
98 COMPONENT ALU IS
82 GENERIC(
99 GENERIC(
83 Arith_en : INTEGER := 1;
100 Arith_en : INTEGER := 1;
84 Logic_en : INTEGER := 1;
101 Logic_en : INTEGER := 1;
85 Input_SZ_1 : INTEGER := 16;
102 Input_SZ_1 : INTEGER := 16;
86 Input_SZ_2 : INTEGER := 9;
103 Input_SZ_2 : INTEGER := 9;
87 COMP_EN : INTEGER := 0 -- 1 => No Comp
104 COMP_EN : INTEGER := 0 -- 1 => No Comp
88
105
89 );
106 );
90 PORT(
107 PORT(
91 clk : IN STD_LOGIC;
108 clk : IN STD_LOGIC;
92 reset : IN STD_LOGIC;
109 reset : IN STD_LOGIC;
93 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
110 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
94 comp : IN STD_LOGIC_VECTOR(1 downto 0);
111 comp : IN STD_LOGIC_VECTOR(1 downto 0);
95 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
112 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
96 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
113 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
97 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
114 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
98 );
115 );
99 END COMPONENT;
116 END COMPONENT;
100
117
118 COMPONENT ALU_V0 IS
119 GENERIC(
120 Arith_en : INTEGER := 1;
121 Logic_en : INTEGER := 1;
122 Input_SZ_1 : INTEGER := 16;
123 Input_SZ_2 : INTEGER := 9
124
125 );
126 PORT(
127 clk : IN STD_LOGIC;
128 reset : IN STD_LOGIC;
129 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
130 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
131 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
132 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
133 );
134 END COMPONENT;
135
136 COMPONENT MAC_V0 is
137 generic(
138 Input_SZ_A : integer := 8;
139 Input_SZ_B : integer := 8
140
141 );
142 port(
143 clk : in std_logic;
144 reset : in std_logic;
145 clr_MAC : in std_logic;
146 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
147 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
148 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
149 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
150 );
151 end COMPONENT;
152
101 ---------------------------------------------------------
153 ---------------------------------------------------------
102 -------- // S�lection grace a l'entr�e "ctrl" \\ --------
154 -------- // Sélection grace a l'entrée "ctrl" \\ --------
103 ---------------------------------------------------------
155 ---------------------------------------------------------
104 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
156 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
105 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
157 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
106 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
158 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
107 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
159 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
108 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
160 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
161
162
163 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
164 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
165 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
166 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
167 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
109 ---------------------------------------------------------
168 ---------------------------------------------------------
110
169
111 COMPONENT MAC IS
170 COMPONENT MAC IS
112 GENERIC(
171 GENERIC(
113 Input_SZ_A : INTEGER := 8;
172 Input_SZ_A : INTEGER := 8;
114 Input_SZ_B : INTEGER := 8;
173 Input_SZ_B : INTEGER := 8;
115 COMP_EN : INTEGER := 0 -- 1 => No Comp
174 COMP_EN : INTEGER := 0 -- 1 => No Comp
116 );
175 );
117 PORT(
176 PORT(
118 clk : IN STD_LOGIC;
177 clk : IN STD_LOGIC;
119 reset : IN STD_LOGIC;
178 reset : IN STD_LOGIC;
120 clr_MAC : IN STD_LOGIC;
179 clr_MAC : IN STD_LOGIC;
121 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
180 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
181 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
123 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
182 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
124 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
183 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
125 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
184 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
126 );
185 );
127 END COMPONENT;
186 END COMPONENT;
128
187
129 COMPONENT TwoComplementer is
188 COMPONENT TwoComplementer is
130 generic(
189 generic(
131 Input_SZ : integer := 16);
190 Input_SZ : integer := 16);
132 port(
191 port(
133 clk : in std_logic; --! Horloge du composant
192 clk : in std_logic; --! Horloge du composant
134 reset : in std_logic; --! Reset general du composant
193 reset : in std_logic; --! Reset general du composant
135 clr : in std_logic; --! Un reset sp�cifique au programme
194 clr : in std_logic; --! Un reset spécifique au programme
136 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
195 TwoComp : in std_logic; --! Autorise l'utilisation du complément
137 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
196 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée
138 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
197 RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non
139 );
198 );
140 end COMPONENT;
199 end COMPONENT;
141
200
142 COMPONENT MAC_CONTROLER IS
201 COMPONENT MAC_CONTROLER IS
143 PORT(
202 PORT(
144 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
203 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
145 MULT : OUT STD_LOGIC;
204 MULT : OUT STD_LOGIC;
146 ADD : OUT STD_LOGIC;
205 ADD : OUT STD_LOGIC;
147 LOAD_ADDER : out std_logic;
206 LOAD_ADDER : out std_logic;
148 MACMUX_sel : OUT STD_LOGIC;
207 MACMUX_sel : OUT STD_LOGIC;
149 MACMUX2_sel : OUT STD_LOGIC
208 MACMUX2_sel : OUT STD_LOGIC
150 );
209 );
151 END COMPONENT;
210 END COMPONENT;
152
211
153 COMPONENT MAC_MUX IS
212 COMPONENT MAC_MUX IS
154 GENERIC(
213 GENERIC(
155 Input_SZ_A : INTEGER := 16;
214 Input_SZ_A : INTEGER := 16;
156 Input_SZ_B : INTEGER := 16
215 Input_SZ_B : INTEGER := 16
157
216
158 );
217 );
159 PORT(
218 PORT(
160 sel : IN STD_LOGIC;
219 sel : IN STD_LOGIC;
161 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
220 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
221 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
163 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
222 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
164 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
223 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
165 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
224 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
166 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
225 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
167 );
226 );
168 END COMPONENT;
227 END COMPONENT;
169
228
170
229
171 COMPONENT MAC_MUX2 IS
230 COMPONENT MAC_MUX2 IS
172 GENERIC(Input_SZ : INTEGER := 16);
231 GENERIC(Input_SZ : INTEGER := 16);
173 PORT(
232 PORT(
174 sel : IN STD_LOGIC;
233 sel : IN STD_LOGIC;
175 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
234 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
176 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
235 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
177 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
236 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
178 );
237 );
179 END COMPONENT;
238 END COMPONENT;
180
239
181
240
182 COMPONENT MAC_REG IS
241 COMPONENT MAC_REG IS
183 GENERIC(size : INTEGER := 16);
242 GENERIC(size : INTEGER := 16);
184 PORT(
243 PORT(
185 reset : IN STD_LOGIC;
244 reset : IN STD_LOGIC;
186 clk : IN STD_LOGIC;
245 clk : IN STD_LOGIC;
187 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
246 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
188 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
247 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
189 );
248 );
190 END COMPONENT;
249 END COMPONENT;
191
250
192
251
193 COMPONENT MUX2 IS
252 COMPONENT MUX2 IS
194 GENERIC(Input_SZ : INTEGER := 16);
253 GENERIC(Input_SZ : INTEGER := 16);
195 PORT(
254 PORT(
196 sel : IN STD_LOGIC;
255 sel : IN STD_LOGIC;
197 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
256 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
198 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
257 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
199 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
258 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
200 );
259 );
201 END COMPONENT;
260 END COMPONENT;
202
261
203 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
262 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
204 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
263 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
205
264
206 COMPONENT MUXN
265 COMPONENT MUXN
207 GENERIC (
266 GENERIC (
208 Input_SZ : INTEGER;
267 Input_SZ : INTEGER;
209 NbStage : INTEGER);
268 NbStage : INTEGER);
210 PORT (
269 PORT (
211 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
270 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
212 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
271 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
213 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
272 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
214 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
273 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
215 END COMPONENT;
274 END COMPONENT;
216
275
217
276
218
277
219 COMPONENT Multiplier IS
278 COMPONENT Multiplier IS
220 GENERIC(
279 GENERIC(
221 Input_SZ_A : INTEGER := 16;
280 Input_SZ_A : INTEGER := 16;
222 Input_SZ_B : INTEGER := 16
281 Input_SZ_B : INTEGER := 16
223
282
224 );
283 );
225 PORT(
284 PORT(
226 clk : IN STD_LOGIC;
285 clk : IN STD_LOGIC;
227 reset : IN STD_LOGIC;
286 reset : IN STD_LOGIC;
228 mult : IN STD_LOGIC;
287 mult : IN STD_LOGIC;
229 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
288 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
230 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
289 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
231 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
290 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
232 );
291 );
233 END COMPONENT;
292 END COMPONENT;
234
293
235 COMPONENT REG IS
294 COMPONENT REG IS
236 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
295 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
237 PORT(
296 PORT(
238 reset : IN STD_LOGIC;
297 reset : IN STD_LOGIC;
239 clk : IN STD_LOGIC;
298 clk : IN STD_LOGIC;
240 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
299 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
241 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
300 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
242 );
301 );
243 END COMPONENT;
302 END COMPONENT;
244
303
245
304
246
305
247 COMPONENT RShifter IS
306 COMPONENT RShifter IS
248 GENERIC(
307 GENERIC(
249 Input_SZ : INTEGER := 16;
308 Input_SZ : INTEGER := 16;
250 shift_SZ : INTEGER := 4
309 shift_SZ : INTEGER := 4
251 );
310 );
252 PORT(
311 PORT(
253 clk : IN STD_LOGIC;
312 clk : IN STD_LOGIC;
254 reset : IN STD_LOGIC;
313 reset : IN STD_LOGIC;
255 shift : IN STD_LOGIC;
314 shift : IN STD_LOGIC;
256 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
315 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
257 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
316 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
258 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
317 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
259 );
318 );
260 END COMPONENT;
319 END COMPONENT;
261
320
262 COMPONENT SYNC_FF
321 COMPONENT SYNC_FF
263 GENERIC (
322 GENERIC (
264 NB_FF_OF_SYNC : INTEGER);
323 NB_FF_OF_SYNC : INTEGER);
265 PORT (
324 PORT (
266 clk : IN STD_LOGIC;
325 clk : IN STD_LOGIC;
267 rstn : IN STD_LOGIC;
326 rstn : IN STD_LOGIC;
268 A : IN STD_LOGIC;
327 A : IN STD_LOGIC;
269 A_sync : OUT STD_LOGIC);
328 A_sync : OUT STD_LOGIC);
270 END COMPONENT;
329 END COMPONENT;
271
330
272 END;
331 END;
Show file before | Show file after | Hide comments
@@ -1,18 +1,24
1 Adder_V0.vhd
2 Adder.vhd
1 ADDRcntr.vhd
3 ADDRcntr.vhd
4 ALU_V0.vhd
5 ALU_V0.vhd~
2 ALU.vhd
6 ALU.vhd
3 Adder.vhd
4 Clk_Divider2.vhd
7 Clk_Divider2.vhd
8 Clk_Divider2.vhd~
5 Clk_divider.vhd
9 Clk_divider.vhd
6 MAC.vhd
10 general_purpose.vhd
11 general_purpose.vhd~
7 MAC_CONTROLER.vhd
12 MAC_CONTROLER.vhd
13 MAC_MUX2.vhd
8 MAC_MUX.vhd
14 MAC_MUX.vhd
9 MAC_MUX2.vhd
10 MAC_REG.vhd
15 MAC_REG.vhd
16 MAC_V0.vhd
17 MAC.vhd
18 Multiplier.vhd
11 MUX2.vhd
19 MUX2.vhd
12 MUXN.vhd
20 MUXN.vhd
13 Multiplier.vhd
14 REG.vhd
21 REG.vhd
22 Shifter.vhd
15 SYNC_FF.vhd
23 SYNC_FF.vhd
16 Shifter.vhd
17 TwoComplementer.vhd
24 TwoComplementer.vhd
18 general_purpose.vhd
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@@ -1,13 +1,19
1 AD7688_drvr_sync.vhd
1 AD7688_drvr.vhd
2 AD7688_drvr.vhd
2 AD7688_drvr_sync.vhd
3 AD7688_drvr.vhd.orig
3 AD7688_spi_if.vhd
4 AD7688_spi_if.vhd
4 ADS1274_drvr.vhd
5 ADS1274_drvr.vhd
6 ADS1274_drvr.vhd~
5 ADS1278_drvr.vhd
7 ADS1278_drvr.vhd
8 ADS1278_drvr.vhd~
6 ADS7886_drvr.vhd
9 ADS7886_drvr.vhd
7 RHF1401.vhd
8 WriteGen_ADC.vhd
9 dual_ADS1278_drvr.vhd
10 dual_ADS1278_drvr.vhd
11 dual_ADS1278_drvr.vhd~
10 lpp_ad_Conv.vhd
12 lpp_ad_Conv.vhd
13 lpp_ad_Conv.vhd~
14 lpp_ad_Conv.vhd.orig
11 lpp_apb_ad_conv.vhd
15 lpp_apb_ad_conv.vhd
16 RHF1401.vhd
17 top_ad_conv_RHF1401.vhd
12 top_ad_conv.vhd
18 top_ad_conv.vhd
13 top_ad_conv_RHF1401.vhd
19 WriteGen_ADC.vhd
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@@ -1,4 +1,4
1 apb_devices_list.vhd
1 APB_MULTI_DIODE.vhd
2 APB_MULTI_DIODE.vhd
2 APB_SIMPLE_DIODE.vhd
3 APB_SIMPLE_DIODE.vhd
3 apb_devices_list.vhd
4 lpp_amba.vhd
4 lpp_amba.vhd
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@@ -1,3 +1,3
1 bootrom.vhd
1 bootrom.vhd
2 lpp_bootloader_pkg.vhd
2 lpp_bootloader.vhd
3 lpp_bootloader.vhd
3 lpp_bootloader_pkg.vhd
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@@ -1,8 +1,8
1 fifo_latency_correction.vhd
1 fifo_latency_correction.vhd
2 lpp_dma.vhd
3 lpp_dma_apbreg.vhd
2 lpp_dma_apbreg.vhd
4 lpp_dma_fsm.vhd
3 lpp_dma_fsm.vhd
5 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
6 lpp_dma_pkg.vhd
5 lpp_dma_pkg.vhd
7 lpp_dma_send_16word.vhd
6 lpp_dma_send_16word.vhd
8 lpp_dma_send_1word.vhd
7 lpp_dma_send_1word.vhd
8 lpp_dma.vhd
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@@ -1,17 +1,17
1 ALU_Driver.vhd
1 ALU_Driver.vhd
2 ALU_Driver.vhd.bak
2 ALU_Driver.vhd.bak
3 APB_Matrix.vhd
3 APB_Matrix.vhd
4 Dispatch.vhd
4 Dispatch.vhd
5 DriveInputs.vhd
5 DriveInputs.vhd
6 GetResult.vhd
6 GetResult.vhd
7 lpp_matrix.vhd
7 MatriceSpectrale.vhd
8 MatriceSpectrale.vhd
8 MatriceSpectrale.vhd.bak
9 MatriceSpectrale.vhd.bak
9 Matrix.vhd
10 Matrix.vhd
10 ReUse_CTRLR.vhd
11 ReUse_CTRLR.vhd
11 SpectralMatrix.vhd
12 SpectralMatrix.vhd
12 SpectralMatrix.vhd.bak
13 SpectralMatrix.vhd.bak
13 Starter.vhd
14 Starter.vhd
14 TopMatrix_PDR.vhd
15 TopMatrix_PDR.vhd
16 Top_MatrixSpec.vhd
15 TopSpecMatrix.vhd
17 TopSpecMatrix.vhd
16 Top_MatrixSpec.vhd
17 lpp_matrix.vhd
Show file before | Show file after | Hide comments
@@ -1,11 +1,11
1 APB_FIFO.vhd
1 APB_FIFO.vhd
2 APB_FIFO.vhd.bak
2 APB_FIFO.vhd.bak
3 FIFO_pipeline.vhd
3 FIFO_pipeline.vhd
4 FillFifo.vhd
4 FillFifo.vhd
5 SSRAM_plugin.vhd
5 lpp_FIFO.vhd
6 SSRAM_plugin_vsim.vhd
7 lppFIFOxN.vhd
6 lppFIFOxN.vhd
8 lppFIFOxN.vhd.bak
7 lppFIFOxN.vhd.bak
9 lpp_FIFO.vhd
10 lpp_memory.vhd
8 lpp_memory.vhd
11 lpp_memory.vhd.bak
9 lpp_memory.vhd.bak
10 SSRAM_plugin.vhd
11 SSRAM_plugin_vsim.vhd
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@@ -1,15 +1,15
1 lpp_lfr.vhd
2 lpp_lfr_apbreg.vhd
1 lpp_lfr_apbreg.vhd
3 lpp_lfr_filter.vhd
2 lpp_lfr_filter.vhd
4 lpp_lfr_ms.vhd
3 lpp_lfr_ms.vhd
5 lpp_lfr_pkg.vhd
4 lpp_lfr_pkg.vhd
5 lpp_lfr.vhd
6 lpp_top_acq.vhd
6 lpp_top_acq.vhd
7 lpp_top_acq.vhd.bak
7 lpp_top_acq.vhd.bak
8 lpp_top_apbreg.vhd
8 lpp_top_apbreg.vhd
9 lpp_top_lfr.vhd
10 lpp_top_lfr_pkg.vhd
9 lpp_top_lfr_pkg.vhd
11 lpp_top_lfr_pkg.vhd.bak
10 lpp_top_lfr_pkg.vhd.bak
12 lpp_top_lfr_wf_picker.vhd
11 lpp_top_lfr.vhd
13 lpp_top_lfr_wf_picker_ip.vhd
12 lpp_top_lfr_wf_picker_ip.vhd
14 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
13 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
14 lpp_top_lfr_wf_picker.vhd
15 top_wf_picker.vhd
15 top_wf_picker.vhd
Show file before | Show file after | Hide comments
@@ -1,13 +1,13
1 lpp_waveform.vhd
2 lpp_waveform_burst.vhd
1 lpp_waveform_burst.vhd
3 lpp_waveform_dma.vhd
4 lpp_waveform_dma_genvalid.vhd
2 lpp_waveform_dma_genvalid.vhd
5 lpp_waveform_dma_selectaddress.vhd
3 lpp_waveform_dma_selectaddress.vhd
6 lpp_waveform_dma_send_Nword.vhd
4 lpp_waveform_dma_send_Nword.vhd
7 lpp_waveform_fifo.vhd
5 lpp_waveform_dma.vhd
8 lpp_waveform_fifo_arbiter.vhd
6 lpp_waveform_fifo_arbiter.vhd
9 lpp_waveform_fifo_ctrl.vhd
7 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo.vhd
10 lpp_waveform_pkg.vhd
9 lpp_waveform_pkg.vhd
10 lpp_waveform_snapshot_controler.vhd
11 lpp_waveform_snapshot.vhd
11 lpp_waveform_snapshot.vhd
12 lpp_waveform_snapshot_controler.vhd
13 lpp_waveform_valid_ack.vhd
12 lpp_waveform_valid_ack.vhd
13 lpp_waveform.vhd
Show file before | Show file after | Hide comments
1 NO CONTENT: file was removed
NO CONTENT: file was removed
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