@@ -0,0 +1,143 | |||
|
1 | library IEEE; | |
|
2 | use IEEE.STD_LOGIC_1164.ALL; | |
|
3 | library lpp; | |
|
4 | use lpp.lpp_ad_conv.all; | |
|
5 | use lpp.lpp_amba.all; | |
|
6 | use lpp.apb_devices_list.all; | |
|
7 | use lpp.general_purpose.all; | |
|
8 | use lpp.Rocket_PCM_Encoder.all; | |
|
9 | use lpp.iir_filter.all; | |
|
10 | use work.config.all; | |
|
11 | ||
|
12 | ||
|
13 | entity IIR_FILTER_TOP is | |
|
14 | generic | |
|
15 | ( | |
|
16 | V2 : integer :=0 -- IF 1 uses V2 else use V1 | |
|
17 | ); | |
|
18 | port | |
|
19 | ( | |
|
20 | rstn : IN STD_LOGIC; | |
|
21 | clk : IN STD_LOGIC; | |
|
22 | ||
|
23 | SMPclk : IN STD_LOGIC; | |
|
24 | LF1_IN : IN std_logic_vector(15 downto 0); | |
|
25 | LF2_IN : IN std_logic_vector(15 downto 0); | |
|
26 | LF3_IN : IN std_logic_vector(15 downto 0); | |
|
27 | ||
|
28 | SMPCLKOut : OUT STD_LOGIC; | |
|
29 | LF1_OUT : OUT std_logic_vector(15 downto 0); | |
|
30 | LF2_OUT : OUT std_logic_vector(15 downto 0); | |
|
31 | LF3_OUT : OUT std_logic_vector(15 downto 0) | |
|
32 | ); | |
|
33 | end IIR_FILTER_TOP; | |
|
34 | ||
|
35 | architecture AR_IIR_FILTER_TOP of IIR_FILTER_TOP is | |
|
36 | signal sps : Samples(2 DOWNTO 0); | |
|
37 | ||
|
38 | signal LFX : Samples(2 DOWNTO 0); | |
|
39 | signal Filter_sp_in : samplT(2 DOWNTO 0, 15 DOWNTO 0); | |
|
40 | signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0); | |
|
41 | signal sample_out_val : std_logic; | |
|
42 | signal LF_ADC_SpPulse : std_logic; | |
|
43 | ||
|
44 | begin | |
|
45 | ||
|
46 | sps(0) <= LF1_IN; | |
|
47 | sps(1) <= LF2_IN; | |
|
48 | sps(2) <= LF3_IN; | |
|
49 | ||
|
50 | LF1_OUT <= LFX(0); | |
|
51 | LF2_OUT <= LFX(1); | |
|
52 | LF3_OUT <= LFX(2); | |
|
53 | ||
|
54 | SMPCLKOut <= sample_out_val; | |
|
55 | ||
|
56 | loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE | |
|
57 | ||
|
58 | loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE | |
|
59 | process(rstn,clk) | |
|
60 | begin | |
|
61 | if rstn ='0' then | |
|
62 | Filter_sp_in(I,J) <= '0'; | |
|
63 | -- LFX(I) <= (others => '0'); | |
|
64 | elsif clk'event and clk ='1' then | |
|
65 | if sample_out_val = '1' then | |
|
66 | LFX(I)(J) <= Filter_sp_out(I,J); | |
|
67 | Filter_sp_in(I,J) <= sps(I)(J); | |
|
68 | end if; | |
|
69 | end if; | |
|
70 | end process; | |
|
71 | END GENERATE; | |
|
72 | END GENERATE; | |
|
73 | ||
|
74 | V2FILTER: IF V2 = 1 GENERATE | |
|
75 | ||
|
76 | smpPulse: entity work.OneShot | |
|
77 | Port map( | |
|
78 | reset => rstn, | |
|
79 | clk => clk, | |
|
80 | input => SMPclk, | |
|
81 | output => LF_ADC_SpPulse | |
|
82 | ); | |
|
83 | ||
|
84 | FilterV2: IIR_CEL_CTRLR_v2 | |
|
85 | GENERIC map( | |
|
86 | tech => CFG_MEMTECH, | |
|
87 | Mem_use => use_RAM, | |
|
88 | Sample_SZ => Sample_SZ, | |
|
89 | Coef_SZ => Coef_SZ, | |
|
90 | Coef_Nb => 25, | |
|
91 | Coef_sel_SZ => 5, | |
|
92 | Cels_count => 5, | |
|
93 | ChanelsCount => ChanelsCount | |
|
94 | ) | |
|
95 | PORT map( | |
|
96 | rstn => rstn, | |
|
97 | clk => clk, | |
|
98 | ||
|
99 | virg_pos => virgPos, | |
|
100 | coefs => CoefsInitValCst_v2, | |
|
101 | ||
|
102 | sample_in_val => LF_ADC_SpPulse, | |
|
103 | sample_in => Filter_sp_in, | |
|
104 | ||
|
105 | sample_out_val => sample_out_val, | |
|
106 | sample_out => Filter_sp_out | |
|
107 | ); | |
|
108 | ||
|
109 | ||
|
110 | ||
|
111 | END GENERATE; | |
|
112 | ||
|
113 | V1FILTER: IF V2 /= 1 GENERATE | |
|
114 | ||
|
115 | sample_out_val <= SMPclk; | |
|
116 | ||
|
117 | ||
|
118 | FilterV1: IIR_CEL_CTRLR | |
|
119 | generic map( | |
|
120 | tech => CFG_MEMTECH, | |
|
121 | Sample_SZ => Sample_SZ, | |
|
122 | ChanelsCount => 3, | |
|
123 | Coef_SZ => Coef_SZ, | |
|
124 | CoefCntPerCel=> CoefCntPerCel, | |
|
125 | Cels_count => Cels_count, | |
|
126 | Mem_use => use_RAM | |
|
127 | ) | |
|
128 | port map( | |
|
129 | reset => rstn, | |
|
130 | clk => clk, | |
|
131 | sample_clk => SMPclk, | |
|
132 | sample_in => Filter_sp_in, | |
|
133 | sample_out => Filter_sp_out, | |
|
134 | virg_pos => virgPos, | |
|
135 | GOtest => open, | |
|
136 | coefs => CoefsInitValCst | |
|
137 | ); | |
|
138 | ||
|
139 | END GENERATE; | |
|
140 | ||
|
141 | ||
|
142 | end AR_IIR_FILTER_TOP; | |
|
143 |
@@ -0,0 +1,65 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.numeric_std.ALL; | |
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
25 | LIBRARY lpp; | |
|
26 | USE lpp.general_purpose.ALL; | |
|
27 | --IDLE = 0000 | |
|
28 | --MAC = 0001 | |
|
29 | --MULT = 0010 and set MULT in ADD reg | |
|
30 | --ADD = 0011 | |
|
31 | --CLRMAC = 0100 | |
|
32 | ||
|
33 | ||
|
34 | ENTITY ALU_V0 IS | |
|
35 | GENERIC( | |
|
36 | Arith_en : INTEGER := 1; | |
|
37 | Logic_en : INTEGER := 1; | |
|
38 | Input_SZ_1 : INTEGER := 16; | |
|
39 | Input_SZ_2 : INTEGER := 9 | |
|
40 | ||
|
41 | ); | |
|
42 | PORT( | |
|
43 | clk : IN STD_LOGIC; | |
|
44 | reset : IN STD_LOGIC; | |
|
45 | ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
46 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
47 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |
|
48 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |
|
49 | ); | |
|
50 | END ENTITY; | |
|
51 | ||
|
52 | ARCHITECTURE ar_ALU OF ALU_V0 IS | |
|
53 | ||
|
54 | SIGNAL clr_MAC : STD_LOGIC := '1'; | |
|
55 | ||
|
56 | BEGIN | |
|
57 | clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0'; | |
|
58 | ||
|
59 | arith : IF Arith_en = 1 GENERATE | |
|
60 | MACinst : MAC_V0 | |
|
61 | GENERIC MAP(Input_SZ_1, Input_SZ_2) | |
|
62 | PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES); | |
|
63 | END GENERATE; | |
|
64 | ||
|
65 | END ARCHITECTURE; |
@@ -0,0 +1,72 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Alexis Jeandet | |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
|
21 | ---------------------------------------------------------------------------- | |
|
22 | library IEEE; | |
|
23 | use IEEE.numeric_std.all; | |
|
24 | use IEEE.std_logic_1164.all; | |
|
25 | library lpp; | |
|
26 | use lpp.general_purpose.all; | |
|
27 | ||
|
28 | ||
|
29 | ||
|
30 | entity Adder_V0 is | |
|
31 | generic( | |
|
32 | Input_SZ_A : integer := 16; | |
|
33 | Input_SZ_B : integer := 16 | |
|
34 | ||
|
35 | ); | |
|
36 | port( | |
|
37 | clk : in std_logic; | |
|
38 | reset : in std_logic; | |
|
39 | clr : in std_logic; | |
|
40 | add : in std_logic; | |
|
41 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
|
42 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
|
43 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) | |
|
44 | ); | |
|
45 | end entity; | |
|
46 | ||
|
47 | ||
|
48 | ||
|
49 | ||
|
50 | architecture ar_Adder of Adder_V0 is | |
|
51 | ||
|
52 | signal REG : std_logic_vector(Input_SZ_A-1 downto 0); | |
|
53 | signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0); | |
|
54 | ||
|
55 | begin | |
|
56 | ||
|
57 | RES <= REG; | |
|
58 | RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A)); | |
|
59 | ||
|
60 | process(clk,reset) | |
|
61 | begin | |
|
62 | if reset = '0' then | |
|
63 | REG <= (others => '0'); | |
|
64 | elsif clk'event and clk ='1' then | |
|
65 | if clr = '1' then | |
|
66 | REG <= (others => '0'); | |
|
67 | elsif add = '1' then | |
|
68 | REG <= RESADD; | |
|
69 | end if; | |
|
70 | end if; | |
|
71 | end process; | |
|
72 | end ar_Adder; |
@@ -0,0 +1,262 | |||
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | library IEEE; | |
|
7 | use IEEE.numeric_std.all; | |
|
8 | use IEEE.std_logic_1164.all; | |
|
9 | library lpp; | |
|
10 | use lpp.general_purpose.all; | |
|
11 | --TODO | |
|
12 | --terminer le testbensh puis changer le resize dans les instanciations | |
|
13 | --par un resize sur un vecteur en combi | |
|
14 | ||
|
15 | ||
|
16 | ||
|
17 | ||
|
18 | ||
|
19 | entity MAC_V0 is | |
|
20 | generic( | |
|
21 | Input_SZ_A : integer := 8; | |
|
22 | Input_SZ_B : integer := 8 | |
|
23 | ||
|
24 | ); | |
|
25 | port( | |
|
26 | clk : in std_logic; | |
|
27 | reset : in std_logic; | |
|
28 | clr_MAC : in std_logic; | |
|
29 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); | |
|
30 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
|
31 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
|
32 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
|
33 | ); | |
|
34 | end MAC_V0; | |
|
35 | ||
|
36 | ||
|
37 | ||
|
38 | ||
|
39 | architecture ar_MAC of MAC_V0 is | |
|
40 | ||
|
41 | ||
|
42 | ||
|
43 | ||
|
44 | ||
|
45 | signal add,mult : std_logic; | |
|
46 | signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
|
47 | ||
|
48 | signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
|
49 | signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
|
50 | signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
|
51 | ||
|
52 | ||
|
53 | signal MACMUXsel : std_logic; | |
|
54 | signal OP1_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
|
55 | signal OP2_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
|
56 | ||
|
57 | ||
|
58 | ||
|
59 | signal MACMUX2sel : std_logic; | |
|
60 | ||
|
61 | signal add_D : std_logic; | |
|
62 | signal OP1_D : std_logic_vector(Input_SZ_A-1 downto 0); | |
|
63 | signal OP2_D : std_logic_vector(Input_SZ_B-1 downto 0); | |
|
64 | signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); | |
|
65 | signal MACMUXsel_D : std_logic; | |
|
66 | signal MACMUX2sel_D : std_logic; | |
|
67 | signal MACMUX2sel_D_D : std_logic; | |
|
68 | signal clr_MAC_D : std_logic; | |
|
69 | signal clr_MAC_D_D : std_logic; | |
|
70 | ||
|
71 | ||
|
72 | ||
|
73 | ||
|
74 | ||
|
75 | begin | |
|
76 | ||
|
77 | ||
|
78 | ||
|
79 | ||
|
80 | --============================================================== | |
|
81 | --=============M A C C O N T R O L E R========================= | |
|
82 | --============================================================== | |
|
83 | MAC_CONTROLER1 : MAC_CONTROLER | |
|
84 | port map( | |
|
85 | ctrl => MAC_MUL_ADD, | |
|
86 | MULT => mult, | |
|
87 | ADD => add, | |
|
88 | MACMUX_sel => MACMUXsel, | |
|
89 | MACMUX2_sel => MACMUX2sel | |
|
90 | ||
|
91 | ); | |
|
92 | --============================================================== | |
|
93 | ||
|
94 | ||
|
95 | ||
|
96 | ||
|
97 | --============================================================== | |
|
98 | --=============M U L T I P L I E R============================== | |
|
99 | --============================================================== | |
|
100 | Multiplieri_nst : Multiplier | |
|
101 | generic map( | |
|
102 | Input_SZ_A => Input_SZ_A, | |
|
103 | Input_SZ_B => Input_SZ_B | |
|
104 | ) | |
|
105 | port map( | |
|
106 | clk => clk, | |
|
107 | reset => reset, | |
|
108 | mult => mult, | |
|
109 | OP1 => OP1, | |
|
110 | OP2 => OP2, | |
|
111 | RES => MULTout | |
|
112 | ); | |
|
113 | ||
|
114 | --============================================================== | |
|
115 | ||
|
116 | ||
|
117 | ||
|
118 | ||
|
119 | --============================================================== | |
|
120 | --======================A D D E R ============================== | |
|
121 | --============================================================== | |
|
122 | adder_inst : Adder_V0 | |
|
123 | generic map( | |
|
124 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
|
125 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
|
126 | ) | |
|
127 | port map( | |
|
128 | clk => clk, | |
|
129 | reset => reset, | |
|
130 | clr => clr_MAC_D, | |
|
131 | add => add_D, | |
|
132 | OP1 => ADDERinA, | |
|
133 | OP2 => ADDERinB, | |
|
134 | RES => ADDERout | |
|
135 | ); | |
|
136 | ||
|
137 | --============================================================== | |
|
138 | ||
|
139 | ||
|
140 | clr_MACREG1 : MAC_REG | |
|
141 | generic map(size => 1) | |
|
142 | port map( | |
|
143 | reset => reset, | |
|
144 | clk => clk, | |
|
145 | D(0) => clr_MAC, | |
|
146 | Q(0) => clr_MAC_D | |
|
147 | ); | |
|
148 | ||
|
149 | clr_MACREG2 : MAC_REG | |
|
150 | generic map(size => 1) | |
|
151 | port map( | |
|
152 | reset => reset, | |
|
153 | clk => clk, | |
|
154 | D(0) => clr_MAC_D, | |
|
155 | Q(0) => clr_MAC_D_D | |
|
156 | ); | |
|
157 | ||
|
158 | addREG : MAC_REG | |
|
159 | generic map(size => 1) | |
|
160 | port map( | |
|
161 | reset => reset, | |
|
162 | clk => clk, | |
|
163 | D(0) => add, | |
|
164 | Q(0) => add_D | |
|
165 | ); | |
|
166 | ||
|
167 | OP1REG : MAC_REG | |
|
168 | generic map(size => Input_SZ_A) | |
|
169 | port map( | |
|
170 | reset => reset, | |
|
171 | clk => clk, | |
|
172 | D => OP1, | |
|
173 | Q => OP1_D | |
|
174 | ); | |
|
175 | ||
|
176 | ||
|
177 | OP2REG : MAC_REG | |
|
178 | generic map(size => Input_SZ_B) | |
|
179 | port map( | |
|
180 | reset => reset, | |
|
181 | clk => clk, | |
|
182 | D => OP2, | |
|
183 | Q => OP2_D | |
|
184 | ); | |
|
185 | ||
|
186 | ||
|
187 | MULToutREG : MAC_REG | |
|
188 | generic map(size => Input_SZ_A+Input_SZ_B) | |
|
189 | port map( | |
|
190 | reset => reset, | |
|
191 | clk => clk, | |
|
192 | D => MULTout, | |
|
193 | Q => MULTout_D | |
|
194 | ); | |
|
195 | ||
|
196 | ||
|
197 | MACMUXselREG : MAC_REG | |
|
198 | generic map(size => 1) | |
|
199 | port map( | |
|
200 | reset => reset, | |
|
201 | clk => clk, | |
|
202 | D(0) => MACMUXsel, | |
|
203 | Q(0) => MACMUXsel_D | |
|
204 | ); | |
|
205 | ||
|
206 | MACMUX2selREG : MAC_REG | |
|
207 | generic map(size => 1) | |
|
208 | port map( | |
|
209 | reset => reset, | |
|
210 | clk => clk, | |
|
211 | D(0) => MACMUX2sel, | |
|
212 | Q(0) => MACMUX2sel_D | |
|
213 | ); | |
|
214 | ||
|
215 | MACMUX2selREG2 : MAC_REG | |
|
216 | generic map(size => 1) | |
|
217 | port map( | |
|
218 | reset => reset, | |
|
219 | clk => clk, | |
|
220 | D(0) => MACMUX2sel_D, | |
|
221 | Q(0) => MACMUX2sel_D_D | |
|
222 | ); | |
|
223 | ||
|
224 | --============================================================== | |
|
225 | --======================M A C M U X =========================== | |
|
226 | --============================================================== | |
|
227 | MACMUX_inst : MAC_MUX | |
|
228 | generic map( | |
|
229 | Input_SZ_A => Input_SZ_A+Input_SZ_B, | |
|
230 | Input_SZ_B => Input_SZ_A+Input_SZ_B | |
|
231 | ||
|
232 | ) | |
|
233 | port map( | |
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234 | sel => MACMUXsel_D, | |
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235 | INA1 => ADDERout, | |
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236 | INA2 => OP2_D_Resz, | |
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237 | INB1 => MULTout, | |
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238 | INB2 => OP1_D_Resz, | |
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239 | OUTA => ADDERinA, | |
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240 | OUTB => ADDERinB | |
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241 | ); | |
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242 | OP1_D_Resz <= std_logic_vector(resize(signed(OP1_D),Input_SZ_A+Input_SZ_B)); | |
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243 | OP2_D_Resz <= std_logic_vector(resize(signed(OP2_D),Input_SZ_A+Input_SZ_B)); | |
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244 | --============================================================== | |
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245 | ||
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246 | ||
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247 | --============================================================== | |
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248 | --======================M A C M U X2 ========================== | |
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249 | --============================================================== | |
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250 | MAC_MUX2_inst : MAC_MUX2 | |
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251 | generic map(Input_SZ => Input_SZ_A+Input_SZ_B) | |
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252 | port map( | |
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253 | sel => MACMUX2sel_D_D, | |
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254 | RES2 => MULTout_D, | |
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255 | RES1 => ADDERout, | |
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256 | RES => RES | |
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257 | ); | |
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258 | ||
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259 | ||
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260 | --============================================================== | |
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261 | ||
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262 | end ar_MAC; |
@@ -52,6 +52,7 Patch-GRLIB: init doc | |||
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52 | 52 | sh $(SCRIPTSDIR)/patch.sh $(GRLIB) |
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53 | 53 | |
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54 | 54 | link: |
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55 | sh $(SCRIPTSDIR)/vhdlsynPatcher.sh | |
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55 | 56 |
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56 | 57 | sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB) |
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57 | 58 |
@@ -8,6 +8,8 use lpp.apb_devices_list.all; | |||
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8 | 8 | use lpp.general_purpose.all; |
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9 | 9 | use lpp.Rocket_PCM_Encoder.all; |
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10 | 10 | |
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11 | use work.config.all; | |
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12 | ||
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11 | 13 | |
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12 | 14 | entity DC_ACQ_TOP is |
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13 | 15 | generic( |
@@ -15,7 +17,9 generic( | |||
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15 | 17 | WordCnt : integer := 144; |
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16 | 18 | MinFCount : integer := 64; |
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17 | 19 | EnableSR : integer := 1; |
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18 |
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20 | CstDATA : integer := 0; | |
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21 | FakeADC : integer := 0; | |
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22 | CDS : integer := 0 | |
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19 | 23 | ); |
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20 | 24 | port( |
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21 | 25 | |
@@ -113,65 +117,93 port map( | |||
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113 | 117 | -- DC ADC |
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114 | 118 | -- |
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115 | 119 | ------------------------------------------------------------------ |
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116 |
ADC |
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117 | ||
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118 | DC_ADC0 : DUAL_ADS1278_DRIVER | |
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119 | port map( | |
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120 | Clk => clk, | |
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121 | reset => reset, | |
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122 | SpiClk => DC_ADC_Sclk, | |
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123 | DIN => DC_ADC_IN, | |
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124 |
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125 | OUT00 => AMR1X_Sync, | |
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126 |
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127 |
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128 |
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129 |
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130 |
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131 |
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132 |
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133 |
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134 |
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135 |
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136 |
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137 |
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138 |
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139 |
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140 |
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141 | FSynch => DC_ADC_FSynch | |
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142 | ); | |
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143 | END GENERATE; | |
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120 | ADC1: IF CstDATA /= 1 GENERATE | |
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121 | ADC : IF FakeADC /=1 GENERATE | |
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122 | ||
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123 | DC_ADC0 : DUAL_ADS1278_DRIVER | |
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124 | port map( | |
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125 | Clk => clk, | |
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126 | reset => reset, | |
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127 | SpiClk => DC_ADC_Sclk, | |
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128 | DIN => DC_ADC_IN, | |
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129 | SmplClk => DC_ADC_SmplClk, | |
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130 | OUT00 => AMR1X_Sync, | |
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131 | OUT01 => AMR1Y_Sync, | |
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132 | OUT02 => AMR1Z_Sync, | |
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133 | OUT03 => AMR2X_Sync, | |
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134 | OUT04 => AMR2Y_Sync, | |
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135 | OUT05 => AMR2Z_Sync, | |
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136 | OUT06 => Temp1_Sync, | |
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137 | OUT07 => Temp2_Sync, | |
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138 | OUT10 => AMR3X_Sync, | |
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139 | OUT11 => AMR3Y_Sync, | |
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140 | OUT12 => AMR3Z_Sync, | |
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141 | OUT13 => AMR4X_Sync, | |
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142 | OUT14 => AMR4Y_Sync, | |
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143 | OUT15 => AMR4Z_Sync, | |
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144 | OUT16 => Temp3_Sync, | |
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145 | OUT17 => Temp4_Sync, | |
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146 | FSynch => DC_ADC_FSynch | |
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147 | ); | |
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148 | END GENERATE; | |
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144 | 149 | |
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145 | NOADC: IF FakeADC=1 GENERATE | |
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146 | ||
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147 | DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER | |
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148 | port map( | |
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149 |
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150 |
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151 |
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152 |
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153 |
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154 |
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155 |
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156 |
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157 |
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158 |
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159 |
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160 |
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161 |
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162 |
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163 |
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164 |
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165 |
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166 |
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167 |
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168 |
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169 |
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170 |
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171 | ); | |
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150 | NOADC: IF FakeADC=1 GENERATE | |
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151 | ||
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152 | DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER | |
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153 | port map( | |
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154 | Clk => clk, | |
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155 | reset => reset, | |
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156 | SpiClk => DC_ADC_Sclk, | |
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157 | DIN => DC_ADC_IN, | |
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158 | SmplClk => DC_ADC_SmplClk, | |
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159 | OUT00 => AMR1X_Sync, | |
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160 | OUT01 => AMR1Y_Sync, | |
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161 | OUT02 => AMR1Z_Sync, | |
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162 | OUT03 => AMR2X_Sync, | |
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163 | OUT04 => AMR2Y_Sync, | |
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164 | OUT05 => AMR2Z_Sync, | |
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165 | OUT06 => Temp1_Sync, | |
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166 | OUT07 => Temp2_Sync, | |
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167 | OUT10 => AMR3X_Sync, | |
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168 | OUT11 => AMR3Y_Sync, | |
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169 | OUT12 => AMR3Z_Sync, | |
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170 | OUT13 => AMR4X_Sync, | |
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171 | OUT14 => AMR4Y_Sync, | |
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172 | OUT15 => AMR4Z_Sync, | |
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173 | OUT16 => Temp3_Sync, | |
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174 | OUT17 => Temp4_Sync, | |
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175 | FSynch => DC_ADC_FSynch | |
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176 | ); | |
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177 | END GENERATE; | |
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178 | ||
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172 | 179 | END GENERATE; |
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173 | 180 | ------------------------------------------------------------------ |
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174 | 181 | |
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182 | NOADC: IF CstDATA = 1 GENERATE | |
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183 | ||
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184 | AMR1X_Sync <= AMR1Xcst; | |
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185 | AMR1Y_Sync <= AMR1Ycst; | |
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186 | AMR1Z_Sync <= AMR1Zcst; | |
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187 | AMR2X_Sync <= AMR2Xcst; | |
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188 | AMR2Y_Sync <= AMR2Ycst; | |
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189 | AMR2Z_Sync <= AMR2Zcst; | |
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190 | Temp1_Sync <= Temp1cst; | |
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191 | Temp2_Sync <= Temp2cst; | |
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192 | AMR3X_Sync <= AMR3Xcst; | |
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193 | AMR3Y_Sync <= AMR3Ycst; | |
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194 | AMR3Z_Sync <= AMR3Zcst; | |
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195 | AMR4X_Sync <= AMR4Xcst; | |
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196 | AMR4Y_Sync <= AMR4Ycst; | |
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197 | AMR4Z_Sync <= AMR4Zcst; | |
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198 | Temp3_Sync <= Temp3cst; | |
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199 | Temp4_Sync <= Temp4cst; | |
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200 | ||
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201 | ||
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202 | ||
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203 | ||
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204 | ||
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205 | END GENERATE; | |
|
206 | ||
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175 | 207 | |
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176 | 208 | |
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177 | 209 | |
@@ -214,7 +246,7 SET_RESET1 <= SET_RESET1_sig; | |||
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214 | 246 | -- |
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215 | 247 | ------------------------------------------------------------------ |
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216 | 248 | |
|
217 | ||
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249 | IF CDS =1 GENERATE | |
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218 | 250 | |
|
219 | 251 | AMR1Xsync: entity work.Fast2SlowSync |
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220 | 252 | generic map(N => 24) |
@@ -271,6 +303,29 TEMP4sync: entity work.Fast2SlowSync | |||
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271 | 303 | generic map(N => 24) |
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272 | 304 | port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4); |
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273 | 305 | |
|
306 | END GENERATE; | |
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307 | ||
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308 | IF CDS /= 1 GENERATE | |
|
309 | ||
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310 | ||
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311 | AMR1X_Sync <= AMR1X; | |
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312 | AMR1Y_Sync <= AMR1Y; | |
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313 | AMR1Z_Sync <= AMR1Z; | |
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314 | AMR2X_Sync <= AMR2X; | |
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315 | AMR2Y_Sync <= AMR2Y; | |
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316 | AMR2Z_Sync <= AMR2Z; | |
|
317 | Temp1_Sync <= Temp1; | |
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318 | Temp2_Sync <= Temp2; | |
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319 | AMR3X_Sync <= AMR3X; | |
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320 | AMR3Y_Sync <= AMR3Y; | |
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321 | AMR3Z_Sync <= AMR3Z; | |
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322 | AMR4X_Sync <= AMR4X; | |
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323 | AMR4Y_Sync <= AMR4Y; | |
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324 | AMR4Z_Sync <= AMR4Z; | |
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325 | Temp3_Sync <= Temp3; | |
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326 | Temp4_Sync <= Temp4; | |
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327 | ||
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328 | END GENERATE; | |
|
274 | 329 | ------------------------------------------------------------------ |
|
275 | 330 | |
|
276 | 331 |
@@ -15,7 +15,7 generic( | |||
|
15 | 15 | WordCnt : integer := 144; |
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16 | 16 | MinFCount : integer := 64; |
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17 | 17 | CstDATA : integer := 0; |
|
18 |
IIRFilter : integer := |
|
|
18 | IIRFilter : integer := 0 | |
|
19 | 19 | ); |
|
20 | 20 | port( |
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21 | 21 | |
@@ -53,6 +53,10 signal Filter_sp_in : samplT(2 DOWN | |||
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53 | 53 | signal Filter_sp_out : samplT(2 DOWNTO 0, 15 DOWNTO 0); |
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54 | 54 | signal sample_out_val : std_logic; |
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55 | 55 | |
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56 | signal LF1_sync : std_logic_vector(15 downto 0); | |
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57 | signal LF2_sync : std_logic_vector(15 downto 0); | |
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58 | signal LF3_sync : std_logic_vector(15 downto 0); | |
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59 | ||
|
56 | 60 | begin |
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57 | 61 | |
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58 | 62 | |
@@ -101,70 +105,49 smpPulse: entity work.OneShot | |||
|
101 | 105 | |
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102 | 106 | |
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103 | 107 | |
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104 | Filter: IIR_CEL_CTRLR_v2 | |
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105 | GENERIC map( | |
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106 | tech => CFG_MEMTECH, | |
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107 | Mem_use => use_RAM, | |
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108 | Sample_SZ => Sample_SZ, | |
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109 | Coef_SZ => Coef_SZ, | |
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110 | Coef_Nb => 25, | |
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111 | Coef_sel_SZ => 5, | |
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112 | Cels_count => 5, | |
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113 | ChanelsCount => ChanelsCount | |
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114 | ) | |
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115 | PORT map( | |
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116 | rstn => reset, | |
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117 | clk => clk, | |
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118 | ||
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119 | virg_pos => virgPos, | |
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120 | coefs => CoefsInitValCst_v2, | |
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121 | ||
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122 | sample_in_val => LF_ADC_SpPulse, | |
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123 | sample_in => Filter_sp_in, | |
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124 | ||
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125 | sample_out_val => sample_out_val, | |
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126 | sample_out => Filter_sp_out | |
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127 | ); | |
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128 | 108 | |
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129 | 109 | NOfilt: IF IIRFilter = 0 GENERATE |
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130 | 110 | process(reset,clk) |
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131 | 111 | begin |
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132 | 112 | if reset ='0' then |
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133 | LF1 <= (others => '0'); | |
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134 | LF2 <= (others => '0'); | |
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135 | LF3 <= (others => '0'); | |
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113 | LF1_sync <= (others => '0'); | |
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114 | LF2_sync <= (others => '0'); | |
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115 | LF3_sync <= (others => '0'); | |
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136 | 116 | elsif clk'event and clk ='1' then |
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137 | 117 | if sample_val = '1' then |
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138 | LF1 <= sps(0); | |
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139 | LF2 <= sps(1); | |
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140 | LF3 <= sps(2); | |
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118 | LF1_sync <= sps(0); | |
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119 | LF2_sync <= sps(1); | |
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120 | LF3_sync <= sps(2); | |
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141 | 121 | end if; |
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142 | 122 | end if; |
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143 | 123 | end process; |
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144 | 124 | END GENERATE; |
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125 | ||
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126 | ||
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145 | 127 | filt: IF IIRFilter /= 0 GENERATE |
|
146 | 128 | |
|
147 | LF1 <= LFX(0); | |
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148 | LF2 <= LFX(1); | |
|
149 | LF3 <= LFX(2); | |
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150 | 129 | |
|
151 | loop_all_sample : FOR J IN 15 DOWNTO 0 GENERATE | |
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130 | filtertop: entity work.IIR_FILTER_TOP | |
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131 | generic map | |
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132 | ( | |
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133 | V2 => 0 | |
|
134 | ) | |
|
135 | port map | |
|
136 | ( | |
|
137 | rstn => reset, | |
|
138 | clk => clk, | |
|
152 | 139 | |
|
153 | loop_all_chanel : FOR I IN 2 DOWNTO 0 GENERATE | |
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154 | process(reset,clk) | |
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155 | begin | |
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156 | if reset ='0' then | |
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157 | Filter_sp_in(I,J) <= '0'; | |
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158 | -- LFX(I) <= (others => '0'); | |
|
159 | elsif clk'event and clk ='1' then | |
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160 | if sample_out_val = '1' then | |
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161 | LFX(I)(J) <= Filter_sp_out(I,J); | |
|
162 | Filter_sp_in(I,J) <= sps(I)(J); | |
|
163 | end if; | |
|
164 | end if; | |
|
165 | end process; | |
|
166 | END GENERATE; | |
|
167 | END GENERATE; | |
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140 | SMPclk => LF_ADC_SmplClk, | |
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141 | LF1_IN => sps(0), | |
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142 | LF2_IN => sps(1), | |
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143 | LF3_IN => sps(2), | |
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144 | ||
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145 | SMPCLKOut => open, | |
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146 | LF1_OUT => LF1_sync, | |
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147 | LF2_OUT => LF2_sync, | |
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148 | LF3_OUT => LF3_sync | |
|
149 | ); | |
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150 | ||
|
168 | 151 | END GENERATE; |
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169 | 152 | |
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170 | 153 | |
@@ -174,14 +157,25 END GENERATE; | |||
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174 | 157 | |
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175 | 158 | CST: IF CstDATA /=0 GENERATE |
|
176 | 159 | |
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177 | LF1 <= LF1cst; | |
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178 | LF2 <= LF2cst; | |
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179 | LF3 <= LF3cst; | |
|
160 | LF1_sync <= LF1cst; | |
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161 | LF2_sync <= LF2cst; | |
|
162 | LF3_sync <= LF3cst; | |
|
180 | 163 | |
|
181 | 164 | END GENERATE; |
|
182 | 165 | |
|
183 | 166 | |
|
184 | 167 | |
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168 | LF1sync: entity work.Fast2SlowSync | |
|
169 | generic map(N => 16) | |
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170 | port map( LF1_sync,clk,sclk,SyncSig,LF1); | |
|
171 | ||
|
172 | LF2sync: entity work.Fast2SlowSync | |
|
173 | generic map(N => 16) | |
|
174 | port map( LF2_sync,clk,sclk,SyncSig,LF2); | |
|
175 | ||
|
176 | LF3sync: entity work.Fast2SlowSync | |
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177 | generic map(N => 16) | |
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178 | port map( LF3_sync,clk,sclk,SyncSig,LF3); | |
|
185 | 179 | |
|
186 | 180 | --Filter: IIR_CEL_FILTER |
|
187 | 181 | -- GENERIC map( |
@@ -27,7 +27,8 VHDLOPTSYNFILES= \ | |||
|
27 | 27 | ICI4HDL/DC_ACQ_TOP.vhd \ |
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28 | 28 | ICI4HDL/LF_ACQ_TOP.vhd \ |
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29 | 29 | ICI4HDL/FAKE_ADC.vhd \ |
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30 | ICI4HDL/OneShot.vhd | |
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30 | ICI4HDL/OneShot.vhd \ | |
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31 | ICI4HDL/IIR_FILTER_TOP.vhd | |
|
31 | 32 | |
|
32 | 33 | |
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33 | 34 | VHDLSYNFILES= \ |
@@ -172,7 +172,8 generic map ( | |||
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172 | 172 | WordCnt => WordCnt, |
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173 | 173 | MinFCount => MinFCount, |
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174 | 174 | EnableSR => 0, |
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175 | FakeADC => 1 | |
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175 | CstDATA => SEND_CONSTANT_DATA, | |
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176 | FakeADC => 0 | |
|
176 | 177 | ) |
|
177 | 178 | port map( |
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178 | 179 | |
@@ -219,7 +220,8 generic map( | |||
|
219 | 220 | WordSize => WordSize, |
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220 | 221 | WordCnt => WordCnt, |
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221 | 222 | MinFCount => MinFCount, |
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222 | CstDATA => 0 | |
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223 | CstDATA => SEND_CONSTANT_DATA, | |
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224 | IIRFilter => 0 | |
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223 | 225 | ) |
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224 | 226 | port map( |
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225 | 227 |
@@ -137,7 +137,7 port map( | |||
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137 | 137 | |
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138 | 138 | |
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139 | 139 | |
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140 | ALU_inst :ALU | |
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140 | ALU_inst : ALU_V0 | |
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141 | 141 | generic map(Logic_en => 0,Input_SZ_1 => Sample_SZ, Input_SZ_2 => Coef_SZ) |
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142 | 142 | port map( |
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143 | 143 | clk => clk, |
@@ -178,7 +178,7 if reset = '0' then | |||
|
178 | 178 | |
|
179 | 179 | smpl_clk_old <= '0'; |
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180 | 180 | RAM_sample_in <= (others=> '0'); |
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181 | ALU_ctrl <= IDLE; | |
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181 | ALU_ctrl <= IDLE_V0; | |
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182 | 182 | ALU_sample_in <= (others=> '0'); |
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183 | 183 | ALU_Coef_in <= (others=> '0'); |
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184 | 184 | RAM_sample_in_bk<= (others=> '0'); |
@@ -206,7 +206,7 elsif clk'event and clk = '1' then | |||
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206 | 206 | ALU_sample_in <= std_logic_vector(sample_in_BUFF(0)); |
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207 | 207 | |
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208 | 208 | else |
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209 | ALU_ctrl <= IDLE; | |
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209 | ALU_ctrl <= IDLE_V0; | |
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210 | 210 | smplConnectL0: for i in 0 to ChanelsCount-1 loop |
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211 | 211 | smplConnectL1: for j in 0 to Sample_SZ-1 loop |
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212 | 212 | sample_in_BUFF(i)(j) <= sample_in(i,j); |
@@ -219,12 +219,12 elsif clk'event and clk = '1' then | |||
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219 | 219 | |
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220 | 220 | when pipe1 => |
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221 | 221 | IIR_CEL_STATE <= computeb1; |
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222 | ALU_ctrl <= MAC_op; | |
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222 | ALU_ctrl <= MAC_op_V0; | |
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223 | 223 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(0)); |
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224 | 224 | |
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225 | 225 | when computeb1 => |
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226 | 226 | |
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227 | ALU_ctrl <= MAC_op; | |
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227 | ALU_ctrl <= MAC_op_V0; | |
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228 | 228 | ALU_sample_in <= RAM_sample_out; |
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229 | 229 | ALU_Coef_in <= std_logic_vector(CoefsReg.NumCoefs(curentCel)(1)); |
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230 | 230 | IIR_CEL_STATE <= computeb2; |
@@ -248,7 +248,7 elsif clk'event and clk = '1' then | |||
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248 | 248 | |
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249 | 249 | |
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250 | 250 | when next_cel => |
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251 | ALU_ctrl <= clr_mac; | |
|
251 | ALU_ctrl <= clr_mac_V0; | |
|
252 | 252 | IIR_CEL_STATE <= pipe2; |
|
253 | 253 | |
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254 | 254 | when pipe2 => |
@@ -281,7 +281,7 rotate : for i in 1 to ChanelsCount-1 | |||
|
281 | 281 | |
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282 | 282 | if curentChan = (ChanelsCount-1) then |
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283 | 283 | IIR_CEL_STATE <= waiting; |
|
284 | ALU_ctrl <= clr_mac; | |
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284 | ALU_ctrl <= clr_mac_V0; | |
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285 | 285 | elsif ChanelsCount>1 then |
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286 | 286 | curentChan <= curentChan + 1; |
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287 | 287 | IIR_CEL_STATE <= pipe1; |
@@ -1,19 +1,19 | |||
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1 | 1 | APB_IIR_CEL.vhd |
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2 | 2 | APB_IIR_Filter.vhd |
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3 | FILTER.vhd | |
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4 | FILTER_RAM_CTRLR.vhd | |
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5 | 3 | FILTERcfg.vhd |
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6 | 4 | FilterCTRLR.vhd |
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7 |
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8 | IIR_CEL_CTRLR_v2.vhd | |
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5 | FILTER_RAM_CTRLR.vhd | |
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6 | FILTER.vhd | |
|
9 | 7 | IIR_CEL_CTRLR_v2_CONTROL.vhd |
|
10 | 8 | IIR_CEL_CTRLR_v2_DATAFLOW.vhd |
|
9 | IIR_CEL_CTRLR_v2.vhd | |
|
10 | IIR_CEL_CTRLR.vhd | |
|
11 | 11 | IIR_CEL_FILTER.vhd |
|
12 | RAM.vhd | |
|
12 | iir_filter.vhd | |
|
13 | RAM_CEL_N.vhd | |
|
13 | 14 | RAM_CEL.vhd |
|
14 | RAM_CEL_N.vhd | |
|
15 | 15 | RAM_CTRLR2.vhd |
|
16 | 16 | RAM_CTRLR_v2.vhd |
|
17 | RAM.vhd | |
|
17 | 18 | Top_Filtre_IIR.vhd |
|
18 | 19 | Top_IIR.vhd |
|
19 | iir_filter.vhd |
@@ -1,10 +1,10 | |||
|
1 | APB_FFT_half.vhd | |
|
1 | 2 | APB_FFT.vhd |
|
2 | APB_FFT_half.vhd | |
|
3 | 3 | Driver_FFT.vhd |
|
4 | FFTamont.vhd | |
|
5 | FFTaval.vhd | |
|
4 | 6 | FFT.vhd |
|
5 | 7 | FFT.vhd.bak |
|
6 | FFTamont.vhd | |
|
7 | FFTaval.vhd | |
|
8 | 8 | Flag_Extremum.vhd |
|
9 | 9 | Flag_Extremum.vhd.bak |
|
10 | 10 | Linker_FFT.vhd |
@@ -68,6 +68,23 PACKAGE general_purpose IS | |||
|
68 | 68 | ); |
|
69 | 69 | END COMPONENT; |
|
70 | 70 | |
|
71 | COMPONENT Adder_V0 is | |
|
72 | generic( | |
|
73 | Input_SZ_A : integer := 16; | |
|
74 | Input_SZ_B : integer := 16 | |
|
75 | ||
|
76 | ); | |
|
77 | port( | |
|
78 | clk : in std_logic; | |
|
79 | reset : in std_logic; | |
|
80 | clr : in std_logic; | |
|
81 | add : in std_logic; | |
|
82 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
|
83 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
|
84 | RES : out std_logic_vector(Input_SZ_A-1 downto 0) | |
|
85 | ); | |
|
86 | end COMPONENT; | |
|
87 | ||
|
71 | 88 | COMPONENT ADDRcntr IS |
|
72 | 89 | PORT( |
|
73 | 90 | clk : IN STD_LOGIC; |
@@ -98,14 +115,56 PACKAGE general_purpose IS | |||
|
98 | 115 | ); |
|
99 | 116 | END COMPONENT; |
|
100 | 117 | |
|
118 | COMPONENT ALU_V0 IS | |
|
119 | GENERIC( | |
|
120 | Arith_en : INTEGER := 1; | |
|
121 | Logic_en : INTEGER := 1; | |
|
122 | Input_SZ_1 : INTEGER := 16; | |
|
123 | Input_SZ_2 : INTEGER := 9 | |
|
124 | ||
|
125 | ); | |
|
126 | PORT( | |
|
127 | clk : IN STD_LOGIC; | |
|
128 | reset : IN STD_LOGIC; | |
|
129 | ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
130 | OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |
|
131 | OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); | |
|
132 | RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0) | |
|
133 | ); | |
|
134 | END COMPONENT; | |
|
135 | ||
|
136 | COMPONENT MAC_V0 is | |
|
137 | generic( | |
|
138 | Input_SZ_A : integer := 8; | |
|
139 | Input_SZ_B : integer := 8 | |
|
140 | ||
|
141 | ); | |
|
142 | port( | |
|
143 | clk : in std_logic; | |
|
144 | reset : in std_logic; | |
|
145 | clr_MAC : in std_logic; | |
|
146 | MAC_MUL_ADD : in std_logic_vector(1 downto 0); | |
|
147 | OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); | |
|
148 | OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); | |
|
149 | RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) | |
|
150 | ); | |
|
151 | end COMPONENT; | |
|
152 | ||
|
101 | 153 | --------------------------------------------------------- |
|
102 |
-------- // S |
|
|
154 | -------- // Sélection grace a l'entrée "ctrl" \\ -------- | |
|
103 | 155 | --------------------------------------------------------- |
|
104 | 156 | Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000"; |
|
105 | 157 | Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001"; |
|
106 | 158 | Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010"; |
|
107 | 159 | Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011"; |
|
108 | 160 | Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100"; |
|
161 | ||
|
162 | ||
|
163 | Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000"; | |
|
164 | Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001"; | |
|
165 | Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010"; | |
|
166 | Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011"; | |
|
167 | Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100"; | |
|
109 | 168 | --------------------------------------------------------- |
|
110 | 169 | |
|
111 | 170 | COMPONENT MAC IS |
@@ -132,10 +191,10 Constant ctrl_CLRMAC : std_logic_vector( | |||
|
132 | 191 | port( |
|
133 | 192 | clk : in std_logic; --! Horloge du composant |
|
134 | 193 | reset : in std_logic; --! Reset general du composant |
|
135 |
clr : in std_logic; --! Un reset sp |
|
|
136 |
TwoComp : in std_logic; --! Autorise l'utilisation du compl |
|
|
137 |
OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op |
|
|
138 |
RES : out std_logic_vector(Input_SZ-1 downto 0) --! R |
|
|
194 | clr : in std_logic; --! Un reset spécifique au programme | |
|
195 | TwoComp : in std_logic; --! Autorise l'utilisation du complément | |
|
196 | OP : in std_logic_vector(Input_SZ-1 downto 0); --! Opérande d'entrée | |
|
197 | RES : out std_logic_vector(Input_SZ-1 downto 0) --! Résultat, opérande complémenté ou non | |
|
139 | 198 | ); |
|
140 | 199 | end COMPONENT; |
|
141 | 200 |
@@ -1,18 +1,24 | |||
|
1 | Adder_V0.vhd | |
|
2 | Adder.vhd | |
|
1 | 3 | ADDRcntr.vhd |
|
4 | ALU_V0.vhd | |
|
5 | ALU_V0.vhd~ | |
|
2 | 6 | ALU.vhd |
|
3 | Adder.vhd | |
|
4 | 7 | Clk_Divider2.vhd |
|
8 | Clk_Divider2.vhd~ | |
|
5 | 9 | Clk_divider.vhd |
|
6 | MAC.vhd | |
|
10 | general_purpose.vhd | |
|
11 | general_purpose.vhd~ | |
|
7 | 12 | MAC_CONTROLER.vhd |
|
13 | MAC_MUX2.vhd | |
|
8 | 14 | MAC_MUX.vhd |
|
9 | MAC_MUX2.vhd | |
|
10 | 15 | MAC_REG.vhd |
|
16 | MAC_V0.vhd | |
|
17 | MAC.vhd | |
|
18 | Multiplier.vhd | |
|
11 | 19 | MUX2.vhd |
|
12 | 20 | MUXN.vhd |
|
13 | Multiplier.vhd | |
|
14 | 21 | REG.vhd |
|
22 | Shifter.vhd | |
|
15 | 23 | SYNC_FF.vhd |
|
16 | Shifter.vhd | |
|
17 | 24 | TwoComplementer.vhd |
|
18 | general_purpose.vhd |
@@ -1,13 +1,19 | |||
|
1 | AD7688_drvr_sync.vhd | |
|
1 | 2 | AD7688_drvr.vhd |
|
2 |
AD7688_drvr |
|
|
3 | AD7688_drvr.vhd.orig | |
|
3 | 4 | AD7688_spi_if.vhd |
|
4 | 5 | ADS1274_drvr.vhd |
|
6 | ADS1274_drvr.vhd~ | |
|
5 | 7 | ADS1278_drvr.vhd |
|
8 | ADS1278_drvr.vhd~ | |
|
6 | 9 | ADS7886_drvr.vhd |
|
7 | RHF1401.vhd | |
|
8 | WriteGen_ADC.vhd | |
|
9 | 10 | dual_ADS1278_drvr.vhd |
|
11 | dual_ADS1278_drvr.vhd~ | |
|
10 | 12 | lpp_ad_Conv.vhd |
|
13 | lpp_ad_Conv.vhd~ | |
|
14 | lpp_ad_Conv.vhd.orig | |
|
11 | 15 | lpp_apb_ad_conv.vhd |
|
16 | RHF1401.vhd | |
|
17 | top_ad_conv_RHF1401.vhd | |
|
12 | 18 | top_ad_conv.vhd |
|
13 | top_ad_conv_RHF1401.vhd | |
|
19 | WriteGen_ADC.vhd |
@@ -1,4 +1,4 | |||
|
1 | apb_devices_list.vhd | |
|
1 | 2 | APB_MULTI_DIODE.vhd |
|
2 | 3 | APB_SIMPLE_DIODE.vhd |
|
3 | apb_devices_list.vhd | |
|
4 | 4 | lpp_amba.vhd |
@@ -1,3 +1,3 | |||
|
1 | 1 | bootrom.vhd |
|
2 | lpp_bootloader_pkg.vhd | |
|
2 | 3 | lpp_bootloader.vhd |
|
3 | lpp_bootloader_pkg.vhd |
@@ -1,8 +1,8 | |||
|
1 | 1 | fifo_latency_correction.vhd |
|
2 | lpp_dma.vhd | |
|
3 | 2 | lpp_dma_apbreg.vhd |
|
4 | 3 | lpp_dma_fsm.vhd |
|
5 | 4 | lpp_dma_ip.vhd |
|
6 | 5 | lpp_dma_pkg.vhd |
|
7 | 6 | lpp_dma_send_16word.vhd |
|
8 | 7 | lpp_dma_send_1word.vhd |
|
8 | lpp_dma.vhd |
@@ -4,6 +4,7 APB_Matrix.vhd | |||
|
4 | 4 | Dispatch.vhd |
|
5 | 5 | DriveInputs.vhd |
|
6 | 6 | GetResult.vhd |
|
7 | lpp_matrix.vhd | |
|
7 | 8 | MatriceSpectrale.vhd |
|
8 | 9 | MatriceSpectrale.vhd.bak |
|
9 | 10 | Matrix.vhd |
@@ -12,6 +13,5 SpectralMatrix.vhd | |||
|
12 | 13 | SpectralMatrix.vhd.bak |
|
13 | 14 | Starter.vhd |
|
14 | 15 | TopMatrix_PDR.vhd |
|
16 | Top_MatrixSpec.vhd | |
|
15 | 17 | TopSpecMatrix.vhd |
|
16 | Top_MatrixSpec.vhd | |
|
17 | lpp_matrix.vhd |
@@ -2,10 +2,10 APB_FIFO.vhd | |||
|
2 | 2 | APB_FIFO.vhd.bak |
|
3 | 3 | FIFO_pipeline.vhd |
|
4 | 4 | FillFifo.vhd |
|
5 | SSRAM_plugin.vhd | |
|
6 | SSRAM_plugin_vsim.vhd | |
|
5 | lpp_FIFO.vhd | |
|
7 | 6 | lppFIFOxN.vhd |
|
8 | 7 | lppFIFOxN.vhd.bak |
|
9 | lpp_FIFO.vhd | |
|
10 | 8 | lpp_memory.vhd |
|
11 | 9 | lpp_memory.vhd.bak |
|
10 | SSRAM_plugin.vhd | |
|
11 | SSRAM_plugin_vsim.vhd |
@@ -1,15 +1,15 | |||
|
1 | lpp_lfr.vhd | |
|
2 | 1 | lpp_lfr_apbreg.vhd |
|
3 | 2 | lpp_lfr_filter.vhd |
|
4 | 3 | lpp_lfr_ms.vhd |
|
5 | 4 | lpp_lfr_pkg.vhd |
|
5 | lpp_lfr.vhd | |
|
6 | 6 | lpp_top_acq.vhd |
|
7 | 7 | lpp_top_acq.vhd.bak |
|
8 | 8 | lpp_top_apbreg.vhd |
|
9 | lpp_top_lfr.vhd | |
|
10 | 9 | lpp_top_lfr_pkg.vhd |
|
11 | 10 | lpp_top_lfr_pkg.vhd.bak |
|
12 |
lpp_top_lfr |
|
|
11 | lpp_top_lfr.vhd | |
|
13 | 12 | lpp_top_lfr_wf_picker_ip.vhd |
|
14 | 13 | lpp_top_lfr_wf_picker_ip_whitout_filter.vhd |
|
14 | lpp_top_lfr_wf_picker.vhd | |
|
15 | 15 | top_wf_picker.vhd |
@@ -1,13 +1,13 | |||
|
1 | lpp_waveform.vhd | |
|
2 | 1 | lpp_waveform_burst.vhd |
|
3 | lpp_waveform_dma.vhd | |
|
4 | 2 | lpp_waveform_dma_genvalid.vhd |
|
5 | 3 | lpp_waveform_dma_selectaddress.vhd |
|
6 | 4 | lpp_waveform_dma_send_Nword.vhd |
|
7 |
lpp_waveform_ |
|
|
5 | lpp_waveform_dma.vhd | |
|
8 | 6 | lpp_waveform_fifo_arbiter.vhd |
|
9 | 7 | lpp_waveform_fifo_ctrl.vhd |
|
8 | lpp_waveform_fifo.vhd | |
|
10 | 9 | lpp_waveform_pkg.vhd |
|
10 | lpp_waveform_snapshot_controler.vhd | |
|
11 | 11 | lpp_waveform_snapshot.vhd |
|
12 | lpp_waveform_snapshot_controler.vhd | |
|
13 | 12 | lpp_waveform_valid_ack.vhd |
|
13 | lpp_waveform.vhd |
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