##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Reverted IIR filters RAM bug correction /!\ for test purpose only
Jean-christophe Pellion -
r678:98208521c583 broken_iir_ram_simu broken_iir_ram draft
parent child
Show More
Show file before | Show file after | Hide comments
@@ -108,21 +108,13 BEGIN
108 BEGIN -- PROCESS
108 BEGIN -- PROCESS
109 IF rstn = '0' THEN -- asynchronous reset (active low)
109 IF rstn = '0' THEN -- asynchronous reset (active low)
110 counter <= (OTHERS => '0');
110 counter <= (OTHERS => '0');
111 rst_mem_done_s <= '0';
111 rst_mem_done_s <= '1';
112 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
112 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
113 if rst_mem_done_s = '0' then
114 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
115 else
116 IF raddr_rst = '1' THEN
113 IF raddr_rst = '1' THEN
117 counter <= (OTHERS => '0');
114 counter <= (OTHERS => '0');
118 ELSIF raddr_add1 = '1' THEN
115 ELSIF raddr_add1 = '1' THEN
119 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
116 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
120 END IF;
117 END IF;
121 end if;
122 if counter = x"FF" then
123 rst_mem_done_s <= '1';
124 end if;
125
126 END IF;
118 END IF;
127 END PROCESS;
119 END PROCESS;
128 RADDR <= counter;
120 RADDR <= counter;
General Comments 0
You need to be logged in to leave comments. Login now