@@ -108,21 +108,13 BEGIN | |||
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108 | 108 | BEGIN -- PROCESS |
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109 | 109 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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110 | 110 | counter <= (OTHERS => '0'); |
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111 |
rst_mem_done_s <= ' |
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111 | rst_mem_done_s <= '1'; | |
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112 | 112 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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113 | if rst_mem_done_s = '0' then | |
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113 | IF raddr_rst = '1' THEN | |
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114 | counter <= (OTHERS => '0'); | |
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115 | ELSIF raddr_add1 = '1' THEN | |
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114 | 116 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); |
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115 | else | |
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116 | IF raddr_rst = '1' THEN | |
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117 | counter <= (OTHERS => '0'); | |
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118 | ELSIF raddr_add1 = '1' THEN | |
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119 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); | |
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120 | END IF; | |
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121 | end if; | |
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122 | if counter = x"FF" then | |
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123 | rst_mem_done_s <= '1'; | |
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124 | end if; | |
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125 | ||
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117 | END IF; | |
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126 | 118 | END IF; |
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127 | 119 | END PROCESS; |
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128 | 120 | RADDR <= counter; |
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