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Reverted IIR filters RAM bug correction /!\ for test purpose only
Jean-christophe Pellion -
r678:98208521c583 broken_iir_ram_simu broken_iir_ram draft
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.FILTERcfg.ALL;
27 USE lpp.FILTERcfg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29 LIBRARY techmap;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
30 USE techmap.gencomp.ALL;
31
31
32 ENTITY RAM_CTRLR_v2 IS
32 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
33 GENERIC(
34 tech : INTEGER := 0;
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM;
36 Mem_use : INTEGER := use_RAM;
37 FILENAME : STRING:= ""
37 FILENAME : STRING:= ""
38 );
38 );
39 PORT(
39 PORT(
40 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
41 clk : IN STD_LOGIC;
41 clk : IN STD_LOGIC;
42 -- ram init done
42 -- ram init done
43 init_mem_done: out STD_LOGIC;
43 init_mem_done: out STD_LOGIC;
44 -- R/W Ctrl
44 -- R/W Ctrl
45 ram_write : IN STD_LOGIC;
45 ram_write : IN STD_LOGIC;
46 ram_read : IN STD_LOGIC;
46 ram_read : IN STD_LOGIC;
47 -- ADDR Ctrl
47 -- ADDR Ctrl
48 raddr_rst : IN STD_LOGIC;
48 raddr_rst : IN STD_LOGIC;
49 raddr_add1 : IN STD_LOGIC;
49 raddr_add1 : IN STD_LOGIC;
50 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
51 -- Data
51 -- Data
52 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
52 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
53 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
53 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
54 );
54 );
55 END RAM_CTRLR_v2;
55 END RAM_CTRLR_v2;
56
56
57
57
58 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
58 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
59
59
60 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
60 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
61 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
61 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
62 SIGNAL WEN, REN : STD_LOGIC;
62 SIGNAL WEN, REN : STD_LOGIC;
63 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
63 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
64 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
64 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
65 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
65 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
66
66
67 signal rst_mem_done_s : std_logic;
67 signal rst_mem_done_s : std_logic;
68 signal ram_write_s : std_logic;
68 signal ram_write_s : std_logic;
69
69
70 BEGIN
70 BEGIN
71
71
72 init_mem_done <= rst_mem_done_s;
72 init_mem_done <= rst_mem_done_s;
73
73
74 sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0');
74 sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0');
75 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0');
75 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0');
76 ram_write_s <= ram_write when rst_mem_done_s = '1' else '1';
76 ram_write_s <= ram_write when rst_mem_done_s = '1' else '1';
77 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
78 -- RAM
78 -- RAM
79 -----------------------------------------------------------------------------
79 -----------------------------------------------------------------------------
80
80
81 memCEL : IF Mem_use = use_CEL GENERATE
81 memCEL : IF Mem_use = use_CEL GENERATE
82 WEN <= NOT ram_write_s;
82 WEN <= NOT ram_write_s;
83 REN <= NOT ram_read;
83 REN <= NOT ram_read;
84 RAMblk : RAM_CEL
84 RAMblk : RAM_CEL
85 GENERIC MAP(Input_SZ_1, 8,FILENAME)
85 GENERIC MAP(Input_SZ_1, 8,FILENAME)
86 PORT MAP(
86 PORT MAP(
87 WD => WD,
87 WD => WD,
88 RD => RD,
88 RD => RD,
89 WEN => WEN,
89 WEN => WEN,
90 REN => REN,
90 REN => REN,
91 WADDR => WADDR,
91 WADDR => WADDR,
92 RADDR => RADDR,
92 RADDR => RADDR,
93 RWCLK => clk,
93 RWCLK => clk,
94 RESET => rstn
94 RESET => rstn
95 ) ;
95 ) ;
96 END GENERATE;
96 END GENERATE;
97
97
98 memRAM : IF Mem_use = use_RAM GENERATE
98 memRAM : IF Mem_use = use_RAM GENERATE
99 SRAM : syncram_2p
99 SRAM : syncram_2p
100 GENERIC MAP(tech, 8, Input_SZ_1)
100 GENERIC MAP(tech, 8, Input_SZ_1)
101 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD);
101 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD);
102 END GENERATE;
102 END GENERATE;
103
103
104 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
105 -- RADDR
105 -- RADDR
106 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 PROCESS (clk, rstn)
107 PROCESS (clk, rstn)
108 BEGIN -- PROCESS
108 BEGIN -- PROCESS
109 IF rstn = '0' THEN -- asynchronous reset (active low)
109 IF rstn = '0' THEN -- asynchronous reset (active low)
110 counter <= (OTHERS => '0');
110 counter <= (OTHERS => '0');
111 rst_mem_done_s <= '0';
111 rst_mem_done_s <= '1';
112 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
112 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
113 if rst_mem_done_s = '0' then
113 IF raddr_rst = '1' THEN
114 counter <= (OTHERS => '0');
115 ELSIF raddr_add1 = '1' THEN
114 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
116 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
115 else
117 END IF;
116 IF raddr_rst = '1' THEN
117 counter <= (OTHERS => '0');
118 ELSIF raddr_add1 = '1' THEN
119 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
120 END IF;
121 end if;
122 if counter = x"FF" then
123 rst_mem_done_s <= '1';
124 end if;
125
126 END IF;
118 END IF;
127 END PROCESS;
119 END PROCESS;
128 RADDR <= counter;
120 RADDR <= counter;
129
121
130 -----------------------------------------------------------------------------
122 -----------------------------------------------------------------------------
131 -- WADDR
123 -- WADDR
132 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
133 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else
125 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else
134 STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
126 STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
135 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
127 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
136 STD_LOGIC_VECTOR(UNSIGNED(counter));
128 STD_LOGIC_VECTOR(UNSIGNED(counter));
137
129
138
130
139 END ar_RAM_CTRLR_v2;
131 END ar_RAM_CTRLR_v2;
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