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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31
32
33 entity FFTDriver is
34 generic (
35 pindex : integer := 0;
36 paddr : integer := 0;
37 pmask : integer := 16#fff#;
38 pirq : integer := 0;
39 abits : integer := 8;
40 LPP_DEVICE : integer;
41 Data_sz : integer := 16;
42 Addr_sz : integer := 8;
43 addr_max_int : integer := 256);
44 port (
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
47 Rz : out std_logic;
48 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
53 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
54 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
55 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
57 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
58 );
59 end FFTDriver;
60
61 architecture ar_FFTDriver of FFTDriver is
62
63 constant REVISION : integer := 1;
64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68
69 type DEVICE_ctrlr_Reg is record
70 DEVICE_Cfg : std_logic_vector(3 downto 0);
71 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
72 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
73 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
74 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
75 end record;
76
77 signal Rec : DEVICE_ctrlr_Reg;
78 signal Rdata : std_logic_vector(31 downto 0);
79
80 signal FlagWR : std_logic;
81 begin
82
83 Rz <= Rec.DEVICE_Cfg(0);
84 ReadEnable <= Rec.DEVICE_Cfg(1);
85 Rec.DEVICE_Cfg(2) <= FlagEmpty;
86 Rec.DEVICE_Cfg(3) <= FlagFull;
87
88 DataIn <= Rec.DEVICE_DataW;
89 Rec.DEVICE_DataR <= DataOut;
90 Rec.DEVICE_AddrW <= AddrIn;
91 Rec.DEVICE_AddrR <= AddrOut;
92
93
94
95 process(rst,clk)
96 begin
97 if(rst='0')then
98 Rec.DEVICE_DataW <= (others => '0');
99 Rec.DEVICE_Cfg(0) <= '0';
100 Rec.DEVICE_Cfg(1) <= '0';
101 FlagWR <= '0';
102
103 elsif(clk'event and clk='1')then
104
105 --APB Write OP
106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
107 case apbi.paddr(abits-1 downto 2) is
108 when "000000" =>
109 FlagWR <= '1';
110 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
111 When "000010" =>
112 Rec.DEVICE_Cfg(0) <= apbi.pwdata(0);
113 Rec.DEVICE_Cfg(1) <= apbi.pwdata(4);
114 when others =>
115 null;
116 end case;
117 else
118 FlagWR <= '0';
119 end if;
120
121 --APB Read OP
122 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
123 case apbi.paddr(abits-1 downto 2) is
124 when "000000" =>
125 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
126 when "000001" =>
127 Rdata(31 downto 8) <= X"AAAAAA";
128 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
129 when "000101" =>
130 Rdata(31 downto 8) <= X"AAAAAA";
131 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
132 when "000010" =>
133 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
134 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
135 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
136 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
137 Rdata(31 downto 16) <= X"CCCC";
138 when others =>
139 Rdata <= (others => '0');
140 end case;
141 end if;
142
143 end if;
144 apbo.pconfig <= pconfig;
145 end process;
146
147 apbo.prdata <= Rdata when apbi.penable = '1';
148 WriteEnable <= FlagWR;
149
150 end ar_FFTDriver; No newline at end of file
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fft.all;
31 use lpp.lpp_fft.all;
32 use lpp.lpp_memory.all;
32 use lpp.lpp_memory.all;
33 use work.fft_components.all;
33 use work.fft_components.all;
34
34
35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
36
36
37 entity APB_FFT is
37 entity APB_FFT is
38 generic (
38 generic (
39 pindex : integer := 0;
39 pindex : integer := 0;
40 paddr : integer := 0;
40 paddr : integer := 0;
41 pmask : integer := 16#fff#;
41 pmask : integer := 16#fff#;
42 pirq : integer := 0;
42 pirq : integer := 0;
43 abits : integer := 8;
43 abits : integer := 8;
44 Data_sz : integer := 16;
44 Data_sz : integer := 32;
45 Addr_sz : integer := 8;
45 Addr_sz : integer := 8;
46 addr_max_int : integer := 256);
46 addr_max_int : integer := 256);
47 port (
47 port (
48 clk : in std_logic; --! Horloge du composant
48 clk : in std_logic; --! Horloge du composant
49 rst : in std_logic; --! Reset general du composant
49 rst : in std_logic; --! Reset general du composant
50 full,empty : out std_logic;
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
50 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
56 );
53 end APB_FFT;
57 end APB_FFT;
54
58
55
59
56 architecture ar_APB_FFT of APB_FFT is
60 architecture ar_APB_FFT of APB_FFT is
57
61
58 signal ReadEnable : std_logic;
62 signal ReadEnable : std_logic;
59 signal WriteEnable : std_logic;
63 signal WriteEnable : std_logic;
60 signal FlagEmpty : std_logic;
64 signal FlagEmpty : std_logic;
61 signal FlagFull : std_logic;
65 signal FlagFull : std_logic;
62 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
66 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0);
63 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
67 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0);
68 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0);
69 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
70 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
71 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
64 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
72 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
65 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
73 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
66
74
67 signal start : std_logic;
75 signal start : std_logic;
68 signal load : std_logic;
76 signal load : std_logic;
69 signal rdy : std_logic;
77 signal rdy : std_logic;
70 signal DummyIn : std_logic_vector(Data_sz-1 downto 0);
78 signal raz : std_logic;
71
79
72
80
73 begin
81 begin
74
82
75 APB : ApbDriver
83 APB : ApbDriver
76 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
84 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
85 port map(clk,rst,raz,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
78
86
79
87
80 Extremum : Flag_Extremum
88 Extremum : Flag_Extremum
81 port map(clk,raz,load,rdy,WriteEnable,ReadEnable,FlagFull,FlagEmpty);
89 port map(clk,raz,load,rdy,FlagFull,FlagEmpty);
82
90
83
91
84 DEVICE : CoreFFT
92 DEVICE : CoreFFT
85 generic map(
93 generic map(
86 LOGPTS => gLOGPTS,
94 LOGPTS => gLOGPTS,
87 LOGLOGPTS => gLOGLOGPTS,
95 LOGLOGPTS => gLOGLOGPTS,
88 WSIZE => gWSIZE,
96 WSIZE => gWSIZE,
89 TWIDTH => gTWIDTH,
97 TWIDTH => gTWIDTH,
90 DWIDTH => gDWIDTH,
98 DWIDTH => gDWIDTH,
91 TDWIDTH => gTDWIDTH,
99 TDWIDTH => gTDWIDTH,
92 RND_MODE => gRND_MODE,
100 RND_MODE => gRND_MODE,
93 SCALE_MODE => gSCALE_MODE,
101 SCALE_MODE => gSCALE_MODE,
94 PTS => gPTS,
102 PTS => gPTS,
95 HALFPTS => gHALFPTS,
103 HALFPTS => gHALFPTS,
96 inBuf_RWDLY => gInBuf_RWDLY)
104 inBuf_RWDLY => gInBuf_RWDLY)
97 port map(clk,start,rst,WriteEnable,ReadEnable,DummyIn,DataIn,load,open,open,DataOut,open,rdy);
105 port map(clk,start,raz,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
106
107 start <= not rst;
108
109 DataIn_re <= DataIn(31 downto 16);
110 DataIn_im <= DataIn(15 downto 0);
111 DataOut <= DataOut_re & DataOut_im;
112
98
113
99 start <= not rst;
114 full <= FlagFull;
100 --FlagFull <= not load;
115 empty <= FlagEmpty;
101 --FlagEmpty <= not rdy;
116 WR <= WriteEnable;
102 DummyIn <= (others => '0');
117 RE <= ReadEnable;
118 flg_load <= load;
119 flg_rdy <= rdy;
120 RZ <= raz;
121
103
122
104 end ar_APB_FFT; No newline at end of file
123 end ar_APB_FFT;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
25 use work.FFT_config.all;
26
26
27 entity Flag_Extremum is
27 entity Flag_Extremum is
28 port(
28 port(
29 clk,raz : in std_logic;
29 clk,raz : in std_logic;
30 load : in std_logic;
30 load : in std_logic;
31 y_rdy : in std_logic;
31 y_rdy : in std_logic;
32 d_valid_WR : in std_logic;
33 read_y_RE : in std_logic;
34 full : out std_logic;
32 full : out std_logic;
35 empty : out std_logic
33 empty : out std_logic
36 );
34 );
37 end Flag_Extremum;
35 end Flag_Extremum;
38
36
39 architecture ar_Flag_Extremum of Flag_Extremum is
37 architecture ar_Flag_Extremum of Flag_Extremum is
40
38
41 type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3);
39 --type etat is (eA,eB,eC,e0,e1,e2);
42 signal ect : etat;
40 --signal ect : etat;
43
41
44 signal load_reg : std_logic;
42 signal load_reg : std_logic;
45 signal y_rdy_reg : std_logic;
43 signal y_rdy_reg : std_logic;
46 signal RE_reg : std_logic;
47 signal WR_reg : std_logic;
48
44
49 begin
45 begin
50 process (clk,raz)
46 process (clk,raz)
51 begin
47 begin
52 if(raz='0')then
48 if(raz='0')then
53 full <= '0';
49 full <= '1';
54 empty <= '1';
50 empty <= '1';
55 ect <= eA;
51 -- ect <= eA;
56
52
57 elsif(clk' event and clk='1')then
53 elsif(clk' event and clk='1')then
58 load_reg <= load;
54 -- load_reg <= load;
59 y_rdy_reg <= y_rdy;
55 -- y_rdy_reg <= y_rdy;
60 RE_reg <= read_y_RE;
61 WR_reg <= d_valid_WR;
62
63 case ect is
64
56
65 when eA =>
57 if(load='1' and y_rdy='0')then
66 if(WR_reg='0' and d_valid_WR='1')then
58 full <= '0';
67 empty <= '0';
59 empty <= '1';
68 ect <= eB;
60
69 end if;
61 elsif(y_rdy='1')then
70
62 full <= '1';
71 when eB =>
63 empty <= '0';
72 if(load_reg='1' and load='0')then
64
73 ect <= eC;
65 else
74 end if;
66 full <= '1';
75
67 empty <= '1';
76 when eC =>
68
77 if(load_reg='1' and load='0')then
69 end if;
78 full <= '1';
70
79 ect <= eD;
71 -- case ect is
80 end if;
81
72
82 when eD =>
73 -- when eA =>
83 if(RE_reg='0' and read_y_RE='1')then
74 -- if(load_reg='0' and load='1')then
84 full <= '0';
75 -- full <= '0';
85 ect <= eX;
76 -- ect <= eB;
86 end if;
77 -- end if;
87
78 --
88 when eX =>
79 -- when eB =>
89 empty <= '1';
80 -- if(load_reg='1' and load='0')then
90 ect <= e0;
81 -- ect <= eC;
91
82 -- end if;
92 when e0 =>
83 --
93 if(WR_reg='0' and d_valid_WR='1')then
84 -- when eC =>
94 empty <= '0';
85 -- if(load_reg='1' and load='0')then
95 ect <= e1;
86 -- full <= '1';
96 end if;
87 -- ect <= e0;
97
88 -- end if;
98 when e1 =>
89
99 if(load_reg='1' and load='0')then
90 --===================================================================================
100 full <= '1';
101 ect <= e2;
102 end if;
103
91
104 when e2 =>
92 -- when e0 =>
105 if(RE_reg='0' and read_y_RE='1')then
93 -- if(load_reg='0' and load='1')then
106 full <= '0';
94 -- full <= '0';
107 ect <= e3;
95 -- ect <= e1;
108 end if;
96 -- end if;
109
97 --
110 when e3 =>
98 -- when e1 =>
111 if(y_rdy_reg='1' and y_rdy='0')then
99 -- if(load_reg='1' and load='0')then
112 empty <= '1';
100 -- full <= '1';
113 ect <= e0;
101 -- empty <= '0';
114 end if;
102 -- ect <= e2;
115
103 -- end if;
116 end case;
104 --
105 -- when e2 =>
106 -- if(y_rdy_reg='1' and y_rdy='0')then
107 -- empty <= '1';
108 -- ect <= e0;
109 -- end if;
110 --
111 --
112 -- end case;
117 end if;
113 end if;
118 end process;
114 end process;
119
115
120 end ar_Flag_Extremum;
116 end ar_Flag_Extremum;
121
117
122
118
123
119
124
120
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@@ -1,142 +1,144
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
30 use work.fft_components.all;
31
31
32
32
33 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
33 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
34
34
35 package lpp_fft is
35 package lpp_fft is
36
36
37 component APB_FFT is
37 component APB_FFT is
38 generic (
38 generic (
39 pindex : integer := 0;
39 pindex : integer := 0;
40 paddr : integer := 0;
40 paddr : integer := 0;
41 pmask : integer := 16#fff#;
41 pmask : integer := 16#fff#;
42 pirq : integer := 0;
42 pirq : integer := 0;
43 abits : integer := 8;
43 abits : integer := 8;
44 Data_sz : integer := 16;
44 Data_sz : integer := 32;
45 Addr_sz : integer := 8;
45 Addr_sz : integer := 8;
46 addr_max_int : integer := 256);
46 addr_max_int : integer := 256);
47 port (
47 port (
48 clk : in std_logic;
48 clk : in std_logic; --! Horloge du composant
49 rst : in std_logic;
49 rst : in std_logic; --! Reset general du composant
50 apbi : in apb_slv_in_type;
50 full,empty : out std_logic;
51 apbo : out apb_slv_out_type
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
54 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
56 );
53 end component;
57 end component;
54
58
55
59
56 component Flag_Extremum is
60 component Flag_Extremum is
57 port(
61 port(
58 clk,raz : in std_logic;
62 clk,raz : in std_logic;
59 load : in std_logic;
63 load : in std_logic;
60 y_rdy : in std_logic;
64 y_rdy : in std_logic;
61 d_valid_WR : in std_logic;
62 read_y_RE : in std_logic;
63 full : out std_logic;
65 full : out std_logic;
64 empty : out std_logic
66 empty : out std_logic
65 );
67 );
66 end component;
68 end component;
67
69
68
70
69 component CoreFFT IS
71 component CoreFFT IS
70 GENERIC (
72 GENERIC (
71 LOGPTS : integer := gLOGPTS;
73 LOGPTS : integer := gLOGPTS;
72 LOGLOGPTS : integer := gLOGLOGPTS;
74 LOGLOGPTS : integer := gLOGLOGPTS;
73 WSIZE : integer := gWSIZE;
75 WSIZE : integer := gWSIZE;
74 TWIDTH : integer := gTWIDTH;
76 TWIDTH : integer := gTWIDTH;
75 DWIDTH : integer := gDWIDTH;
77 DWIDTH : integer := gDWIDTH;
76 TDWIDTH : integer := gTDWIDTH;
78 TDWIDTH : integer := gTDWIDTH;
77 RND_MODE : integer := gRND_MODE;
79 RND_MODE : integer := gRND_MODE;
78 SCALE_MODE : integer := gSCALE_MODE;
80 SCALE_MODE : integer := gSCALE_MODE;
79 PTS : integer := gPTS;
81 PTS : integer := gPTS;
80 HALFPTS : integer := gHALFPTS;
82 HALFPTS : integer := gHALFPTS;
81 inBuf_RWDLY : integer := gInBuf_RWDLY );
83 inBuf_RWDLY : integer := gInBuf_RWDLY );
82 PORT (
84 PORT (
83 clk,ifiStart,ifiNreset : IN std_logic;
85 clk,ifiStart,ifiNreset : IN std_logic;
84 ifiD_valid, ifiRead_y : IN std_logic;
86 ifiD_valid, ifiRead_y : IN std_logic;
85 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
87 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
86 ifoLoad, ifoPong : OUT std_logic;
88 ifoLoad, ifoPong : OUT std_logic;
87 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
89 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
88 ifoY_valid, ifoY_rdy : OUT std_logic);
90 ifoY_valid, ifoY_rdy : OUT std_logic);
89 END component;
91 END component;
90
92
91
93
92 component actar is
94 component actar is
93 port( DataA : in std_logic_vector(15 downto 0); DataB : in
95 port( DataA : in std_logic_vector(15 downto 0); DataB : in
94 std_logic_vector(15 downto 0); Mult : out
96 std_logic_vector(15 downto 0); Mult : out
95 std_logic_vector(31 downto 0);Clock : in std_logic) ;
97 std_logic_vector(31 downto 0);Clock : in std_logic) ;
96 end component;
98 end component;
97
99
98 component actram is
100 component actram is
99 port( DI : in std_logic_vector(31 downto 0); DO : out
101 port( DI : in std_logic_vector(31 downto 0); DO : out
100 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
102 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
101 WADDR : in std_logic_vector(6 downto 0); RADDR : in
103 WADDR : in std_logic_vector(6 downto 0); RADDR : in
102 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
104 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
103 std_logic) ;
105 std_logic) ;
104 end component;
106 end component;
105
107
106 component switch IS
108 component switch IS
107 GENERIC ( DWIDTH : integer := 32 );
109 GENERIC ( DWIDTH : integer := 32 );
108 PORT (
110 PORT (
109 clk, sel, validIn : IN std_logic;
111 clk, sel, validIn : IN std_logic;
110 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
112 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
111 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
113 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
112 validOut : OUT std_logic);
114 validOut : OUT std_logic);
113 END component;
115 END component;
114
116
115 component twid_rA IS
117 component twid_rA IS
116 GENERIC (LOGPTS : integer := 8;
118 GENERIC (LOGPTS : integer := 8;
117 LOGLOGPTS : integer := 3 );
119 LOGLOGPTS : integer := 3 );
118 PORT (clk : IN std_logic;
120 PORT (clk : IN std_logic;
119 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
121 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
120 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
122 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
121 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
123 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
122 END component;
124 END component;
123
125
124 component counter IS
126 component counter IS
125 GENERIC (
127 GENERIC (
126 WIDTH : integer := 7;
128 WIDTH : integer := 7;
127 TERMCOUNT : integer := 127 );
129 TERMCOUNT : integer := 127 );
128 PORT (
130 PORT (
129 clk, nGrst, rst, cntEn : IN std_logic;
131 clk, nGrst, rst, cntEn : IN std_logic;
130 tc : OUT std_logic;
132 tc : OUT std_logic;
131 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
133 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
132 END component;
134 END component;
133
135
134
136
135 component twiddle IS
137 component twiddle IS
136 PORT (
138 PORT (
137 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
139 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
138 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
140 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
139 END component;
141 END component;
140
142
141
143
142 end; No newline at end of file
144 end;
Show file before | Show file after | Hide comments
@@ -1,154 +1,159
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31
31
32 --! Driver APB "GοΏ½nοΏ½rique" qui va faire le lien entre le bus Amba et la FIFO
32 --! Driver APB "GοΏ½nοΏ½rique" qui va faire le lien entre le bus Amba et la FIFO
33
33
34 entity ApbDriver is
34 entity ApbDriver is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 LPP_DEVICE : integer;
41 LPP_DEVICE : integer;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 RZ : out std_logic;
48 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
53 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
53 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
54 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
54 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
55 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
55 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
57 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
57 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
58 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
58 );
59 );
59 end ApbDriver;
60 end ApbDriver;
60
61
61 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
62 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
62
63
63 architecture ar_ApbDriver of ApbDriver is
64 architecture ar_ApbDriver of ApbDriver is
64
65
65 constant REVISION : integer := 1;
66 constant REVISION : integer := 1;
66
67
67 constant pconfig : apb_config_type := (
68 constant pconfig : apb_config_type := (
68 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
69 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
69 1 => apb_iobar(paddr, pmask));
70 1 => apb_iobar(paddr, pmask));
70
71
71 type DEVICE_ctrlr_Reg is record
72 type DEVICE_ctrlr_Reg is record
72 DEVICE_Cfg : std_logic_vector(3 downto 0);
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
73 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
74 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
74 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
75 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
75 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
76 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
76 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
77 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
77 end record;
78 end record;
78
79
79 signal Rec : DEVICE_ctrlr_Reg;
80 signal Rec : DEVICE_ctrlr_Reg;
80 signal Rdata : std_logic_vector(31 downto 0);
81 signal Rdata : std_logic_vector(31 downto 0);
81
82
82 signal FlagRE : std_logic;
83 signal FlagRE : std_logic;
83 signal FlagWR : std_logic;
84 signal FlagWR : std_logic;
84 begin
85 begin
85
86
86 Rec.DEVICE_Cfg(0) <= FlagRE;
87 Rec.DEVICE_Cfg(0) <= FlagRE;
87 Rec.DEVICE_Cfg(1) <= FlagWR;
88 Rec.DEVICE_Cfg(1) <= FlagWR;
88 Rec.DEVICE_Cfg(2) <= FlagEmpty;
89 Rec.DEVICE_Cfg(2) <= FlagEmpty;
89 Rec.DEVICE_Cfg(3) <= FlagFull;
90 Rec.DEVICE_Cfg(3) <= FlagFull;
91 Rz <= Rec.DEVICE_Cfg(4);
90
92
91 DataIn <= Rec.DEVICE_DataW;
93 DataIn <= Rec.DEVICE_DataW;
92 Rec.DEVICE_DataR <= DataOut;
94 Rec.DEVICE_DataR <= DataOut;
93 Rec.DEVICE_AddrW <= AddrIn;
95 Rec.DEVICE_AddrW <= AddrIn;
94 Rec.DEVICE_AddrR <= AddrOut;
96 Rec.DEVICE_AddrR <= AddrOut;
95
97
96
98
97
99
98 process(rst,clk)
100 process(rst,clk)
99 begin
101 begin
100 if(rst='0')then
102 if(rst='0')then
101 Rec.DEVICE_DataW <= (others => '0');
103 Rec.DEVICE_DataW <= (others => '0');
104 Rec.DEVICE_Cfg(4) <= '0';
102 FlagWR <= '0';
105 FlagWR <= '0';
103 FlagRE <= '0';
106 FlagRE <= '0';
104
107
105 elsif(clk'event and clk='1')then
108 elsif(clk'event and clk='1')then
106
109
107 --APB Write OP
110 --APB Write OP
108 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
111 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
109 case apbi.paddr(abits-1 downto 2) is
112 case apbi.paddr(abits-1 downto 2) is
110 when "000000" =>
113 when "000000" =>
111 FlagWR <= '1';
114 FlagWR <= '1';
112 Rec.DEVICE_DataW <= apbi.pwdata(15 downto 0);
115 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
116 when "000010" =>
117 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
113 when others =>
118 when others =>
114 null;
119 null;
115 end case;
120 end case;
116 else
121 else
117 FlagWR <= '0';
122 FlagWR <= '0';
118 end if;
123 end if;
119
124
120 --APB Read OP
125 --APB Read OP
121 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
126 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
122 case apbi.paddr(abits-1 downto 2) is
127 case apbi.paddr(abits-1 downto 2) is
123 when "000000" =>
128 when "000000" =>
124 FlagRE <= '1';
129 FlagRE <= '1';
125 Rdata(31 downto 16) <= X"DDDD";
130 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
126 Rdata(15 downto 0) <= Rec.DEVICE_DataR;
127 when "000001" =>
131 when "000001" =>
128 Rdata(31 downto 8) <= X"AAAAAA";
132 Rdata(31 downto 8) <= X"AAAAAA";
129 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
133 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
130 when "000101" =>
134 when "000101" =>
131 Rdata(31 downto 8) <= X"AAAAAA";
135 Rdata(31 downto 8) <= X"AAAAAA";
132 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
136 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
133 when "000010" =>
137 when "000010" =>
134 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
138 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
135 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
139 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
136 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
140 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
137 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
141 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
138 Rdata(31 downto 16) <= X"CCCC";
142 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
143 Rdata(31 downto 20) <= X"CCC";
139 when others =>
144 when others =>
140 Rdata <= (others => '0');
145 Rdata <= (others => '0');
141 end case;
146 end case;
142 else
147 else
143 FlagRE <= '0';
148 FlagRE <= '0';
144 end if;
149 end if;
145
150
146 end if;
151 end if;
147 apbo.pconfig <= pconfig;
152 apbo.pconfig <= pconfig;
148 end process;
153 end process;
149
154
150 apbo.prdata <= Rdata when apbi.penable = '1';
155 apbo.prdata <= Rdata when apbi.penable = '1';
151 WriteEnable <= FlagWR;
156 WriteEnable <= FlagWR;
152 ReadEnable <= FlagRE;
157 ReadEnable <= FlagRE;
153
158
154 end ar_ApbDriver; No newline at end of file
159 end ar_ApbDriver;
Show file before | Show file after | Hide comments
@@ -1,233 +1,234
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30
30
31 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
32
32
33 package lpp_memory is
33 package lpp_memory is
34
34
35 --===========================================================|
35 --===========================================================|
36 --================= FIFOW SRAM FIFOR ========================|
36 --================= FIFOW SRAM FIFOR ========================|
37 --===========================================================|
37 --===========================================================|
38
38
39 component APB_FIFO is
39 component APB_FIFO is
40 generic (
40 generic (
41 pindex : integer := 0;
41 pindex : integer := 0;
42 paddr : integer := 0;
42 paddr : integer := 0;
43 pmask : integer := 16#fff#;
43 pmask : integer := 16#fff#;
44 pirq : integer := 0;
44 pirq : integer := 0;
45 abits : integer := 8;
45 abits : integer := 8;
46 Data_sz : integer := 16;
46 Data_sz : integer := 16;
47 Addr_sz : integer := 8;
47 Addr_sz : integer := 8;
48 addr_max_int : integer := 256);
48 addr_max_int : integer := 256);
49 port (
49 port (
50 clk : in std_logic;
50 clk : in std_logic;
51 rst : in std_logic;
51 rst : in std_logic;
52 apbi : in apb_slv_in_type;
52 apbi : in apb_slv_in_type;
53 apbo : out apb_slv_out_type
53 apbo : out apb_slv_out_type
54 );
54 );
55 end component;
55 end component;
56
56
57
57
58 component ApbDriver is
58 component ApbDriver is
59 generic (
59 generic (
60 pindex : integer := 0;
60 pindex : integer := 0;
61 paddr : integer := 0;
61 paddr : integer := 0;
62 pmask : integer := 16#fff#;
62 pmask : integer := 16#fff#;
63 pirq : integer := 0;
63 pirq : integer := 0;
64 abits : integer := 8;
64 abits : integer := 8;
65 LPP_DEVICE : integer;
65 LPP_DEVICE : integer;
66 Data_sz : integer := 16;
66 Data_sz : integer := 16;
67 Addr_sz : integer := 8;
67 Addr_sz : integer := 8;
68 addr_max_int : integer := 256);
68 addr_max_int : integer := 256);
69 port (
69 port (
70 clk : in std_logic;
70 clk : in std_logic;
71 rst : in std_logic;
71 rst : in std_logic;
72 RZ : out std_logic;
72 ReadEnable : in std_logic;
73 ReadEnable : in std_logic;
73 WriteEnable : in std_logic;
74 WriteEnable : in std_logic;
74 FlagEmpty : in std_logic;
75 FlagEmpty : in std_logic;
75 FlagFull : in std_logic;
76 FlagFull : in std_logic;
76 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
79 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
79 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
80 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
80 apbi : in apb_slv_in_type;
81 apbi : in apb_slv_in_type;
81 apbo : out apb_slv_out_type
82 apbo : out apb_slv_out_type
82 );
83 );
83 end component;
84 end component;
84
85
85
86
86 component Top_FIFO is
87 component Top_FIFO is
87 generic(
88 generic(
88 Data_sz : integer := 16;
89 Data_sz : integer := 16;
89 Addr_sz : integer := 8;
90 Addr_sz : integer := 8;
90 addr_max_int : integer := 256
91 addr_max_int : integer := 256
91 );
92 );
92 port(
93 port(
93 clk,raz : in std_logic; --! Horloge et reset general du composant
94 clk,raz : in std_logic; --! Horloge et reset general du composant
94 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
95 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
95 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
96 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
96 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
97 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
97 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
98 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
98 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
99 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
99 full : out std_logic; --! Flag, MοΏ½moire pleine
100 full : out std_logic; --! Flag, MοΏ½moire pleine
100 empty : out std_logic; --! Flag, MοΏ½moire vide
101 empty : out std_logic; --! Flag, MοΏ½moire vide
101 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
102 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
102 );
103 );
103 end component;
104 end component;
104
105
105
106
106 component Fifo_Read is
107 component Fifo_Read is
107 generic(
108 generic(
108 Addr_sz : integer := 8;
109 Addr_sz : integer := 8;
109 addr_max_int : integer := 256);
110 addr_max_int : integer := 256);
110 port(
111 port(
111 clk : in std_logic;
112 clk : in std_logic;
112 raz : in std_logic;
113 raz : in std_logic;
113 flag_RE : in std_logic;
114 flag_RE : in std_logic;
114 Waddr : in std_logic_vector(addr_sz-1 downto 0);
115 Waddr : in std_logic_vector(addr_sz-1 downto 0);
115 empty : out std_logic;
116 empty : out std_logic;
116 Raddr : out std_logic_vector(addr_sz-1 downto 0)
117 Raddr : out std_logic_vector(addr_sz-1 downto 0)
117 );
118 );
118 end component;
119 end component;
119
120
120
121
121 component Fifo_Write is
122 component Fifo_Write is
122 generic(
123 generic(
123 Addr_sz : integer := 8;
124 Addr_sz : integer := 8;
124 addr_max_int : integer := 256);
125 addr_max_int : integer := 256);
125 port(
126 port(
126 clk : in std_logic;
127 clk : in std_logic;
127 raz : in std_logic;
128 raz : in std_logic;
128 flag_WR : in std_logic;
129 flag_WR : in std_logic;
129 Raddr : in std_logic_vector(addr_sz-1 downto 0);
130 Raddr : in std_logic_vector(addr_sz-1 downto 0);
130 full : out std_logic;
131 full : out std_logic;
131 Waddr : out std_logic_vector(addr_sz-1 downto 0)
132 Waddr : out std_logic_vector(addr_sz-1 downto 0)
132 );
133 );
133 end component;
134 end component;
134
135
135
136
136 component Link_Reg is
137 component Link_Reg is
137 generic(Data_sz : integer := 16);
138 generic(Data_sz : integer := 16);
138 port(
139 port(
139 clk,raz : in std_logic;
140 clk,raz : in std_logic;
140 Data_one : in std_logic_vector(Data_sz-1 downto 0);
141 Data_one : in std_logic_vector(Data_sz-1 downto 0);
141 Data_two : in std_logic_vector(Data_sz-1 downto 0);
142 Data_two : in std_logic_vector(Data_sz-1 downto 0);
142 flag_RE : in std_logic;
143 flag_RE : in std_logic;
143 flag_WR : in std_logic;
144 flag_WR : in std_logic;
144 empty : in std_logic;
145 empty : in std_logic;
145 Data_out : out std_logic_vector(Data_sz-1 downto 0)
146 Data_out : out std_logic_vector(Data_sz-1 downto 0)
146 );
147 );
147 end component;
148 end component;
148
149
149 --===========================================================|
150 --===========================================================|
150 --===================== FIFOW SRAM ==========================|
151 --===================== FIFOW SRAM ==========================|
151 --===========================================================|
152 --===========================================================|
152
153
153 component APB_FifoWrite is
154 component APB_FifoWrite is
154 generic (
155 generic (
155 pindex : integer := 0;
156 pindex : integer := 0;
156 paddr : integer := 0;
157 paddr : integer := 0;
157 pmask : integer := 16#fff#;
158 pmask : integer := 16#fff#;
158 pirq : integer := 0;
159 pirq : integer := 0;
159 abits : integer := 8;
160 abits : integer := 8;
160 Data_sz : integer := 16;
161 Data_sz : integer := 16;
161 Addr_sz : integer := 8;
162 Addr_sz : integer := 8;
162 addr_max_int : integer := 256);
163 addr_max_int : integer := 256);
163 port (
164 port (
164 clk : in std_logic;
165 clk : in std_logic;
165 rst : in std_logic;
166 rst : in std_logic;
166 apbi : in apb_slv_in_type;
167 apbi : in apb_slv_in_type;
167 apbo : out apb_slv_out_type
168 apbo : out apb_slv_out_type
168 );
169 );
169 end component;
170 end component;
170
171
171
172
172 component Top_FifoWrite is
173 component Top_FifoWrite is
173 generic(
174 generic(
174 Data_sz : integer := 16;
175 Data_sz : integer := 16;
175 Addr_sz : integer := 8;
176 Addr_sz : integer := 8;
176 addr_max_int : integer := 256);
177 addr_max_int : integer := 256);
177 port(
178 port(
178 clk : in std_logic;
179 clk : in std_logic;
179 raz : in std_logic;
180 raz : in std_logic;
180 flag_RE : in std_logic;
181 flag_RE : in std_logic;
181 flag_WR : in std_logic;
182 flag_WR : in std_logic;
182 Data_in : in std_logic_vector(Data_sz-1 downto 0);
183 Data_in : in std_logic_vector(Data_sz-1 downto 0);
183 Raddr : in std_logic_vector(addr_sz-1 downto 0);
184 Raddr : in std_logic_vector(addr_sz-1 downto 0);
184 full : out std_logic;
185 full : out std_logic;
185 empty : out std_logic;
186 empty : out std_logic;
186 Waddr : out std_logic_vector(addr_sz-1 downto 0);
187 Waddr : out std_logic_vector(addr_sz-1 downto 0);
187 Data_out : out std_logic_vector(Data_sz-1 downto 0)
188 Data_out : out std_logic_vector(Data_sz-1 downto 0)
188 );
189 );
189 end component;
190 end component;
190
191
191 --===========================================================|
192 --===========================================================|
192 --===================== SRAM FIFOR ==========================|
193 --===================== SRAM FIFOR ==========================|
193 --===========================================================|
194 --===========================================================|
194
195
195 component APB_FifoRead is
196 component APB_FifoRead is
196 generic (
197 generic (
197 pindex : integer := 0;
198 pindex : integer := 0;
198 paddr : integer := 0;
199 paddr : integer := 0;
199 pmask : integer := 16#fff#;
200 pmask : integer := 16#fff#;
200 pirq : integer := 0;
201 pirq : integer := 0;
201 abits : integer := 8;
202 abits : integer := 8;
202 Data_sz : integer := 16;
203 Data_sz : integer := 16;
203 Addr_sz : integer := 8;
204 Addr_sz : integer := 8;
204 addr_max_int : integer := 256);
205 addr_max_int : integer := 256);
205 port (
206 port (
206 clk : in std_logic;
207 clk : in std_logic;
207 rst : in std_logic;
208 rst : in std_logic;
208 apbi : in apb_slv_in_type;
209 apbi : in apb_slv_in_type;
209 apbo : out apb_slv_out_type
210 apbo : out apb_slv_out_type
210 );
211 );
211 end component;
212 end component;
212
213
213
214
214 component Top_FifoRead is
215 component Top_FifoRead is
215 generic(
216 generic(
216 Data_sz : integer := 16;
217 Data_sz : integer := 16;
217 Addr_sz : integer := 8;
218 Addr_sz : integer := 8;
218 addr_max_int : integer := 256);
219 addr_max_int : integer := 256);
219 port(
220 port(
220 clk : in std_logic;
221 clk : in std_logic;
221 raz : in std_logic;
222 raz : in std_logic;
222 flag_RE : in std_logic;
223 flag_RE : in std_logic;
223 flag_WR : in std_logic;
224 flag_WR : in std_logic;
224 Data_in : in std_logic_vector(Data_sz-1 downto 0);
225 Data_in : in std_logic_vector(Data_sz-1 downto 0);
225 Waddr : in std_logic_vector(addr_sz-1 downto 0);
226 Waddr : in std_logic_vector(addr_sz-1 downto 0);
226 full : out std_logic;
227 full : out std_logic;
227 empty : out std_logic;
228 empty : out std_logic;
228 Raddr : out std_logic_vector(addr_sz-1 downto 0);
229 Raddr : out std_logic_vector(addr_sz-1 downto 0);
229 Data_out : out std_logic_vector(Data_sz-1 downto 0)
230 Data_out : out std_logic_vector(Data_sz-1 downto 0)
230 );
231 );
231 end component;
232 end component;
232
233
233 end;
234 end;
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