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Update MINI LFR constraint's files
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r638:905b2664a745 simu_with_Leon3
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1 1 ################################################################################
2 2 # SDC WRITER VERSION "3.1";
3 3 # DESIGN "LFR_EQM";
4 4 # Timing constraints scenario: "Primary";
5 5 # DATE "Fri Apr 24 16:02:16 2015";
6 6 # VENDOR "Actel";
7 7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 9 ################################################################################
10 10
11 11
12 12 set sdc_version 1.7
13 13
14 14
15 15 ######## Clock Constraints ########
16 16
17 17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18 18
19 19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20 20
21 21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22 22
23 23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24 24
25 25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26 26
27 27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28 28
29 29
30 30
31 31 ######## Generated Clock Constraints ########
32 32
33 33
34 34
35 35 ######## Clock Source Latency Constraints #########
36 36
37 37
38 38
39 39 ######## Input Delay Constraints ########
40 40
41 41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
42 42 set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
43 43 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
44 44 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
45 45 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
46 46 set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
47 47 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
48 48 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
49 49 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
50 50
51 51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54 54
55 55
56 56
57 57 ######## Output Delay Constraints ########
58 58
59 59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
60 60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
61 61 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
62 62 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
63 63 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
64 64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
65 65 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
66 66 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
67 67 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
68 68
69 69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }]
70 70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
71 71 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
72 72 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
73 73 address[7] SRAM_A[8] SRAM_A[9] }]
74 74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
75 75 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
76 76 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
77 77 address[7] SRAM_A[8] SRAM_A[9] }]
78 78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }]
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
82 82
83 83
84 84 ######## Delay Constraints ########
85 85
86 86 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87 87
88 88 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89 89
90 90
91 91 ######## Delay Constraints ########
92 92
93 93
94 94
95 95 ######## Multicycle Constraints ########
96 96
97 97
98 98
99 99 ######## False Path Constraints ########
100 100
101 101
102 102
103 103 ######## Output load Constraints ########
104 104
105 105
106 106
107 107 ######## Disable Timing Constraints #########
108 108
109 109
110 110
111 111 ######## Clock Uncertainty Constraints #########
112 112
113 113
114 114
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@@ -1,639 +1,639
1 ο»Ώ# Actel Physical design constraints file
1 # Actel Physical design constraints file
2 2 # Generated file
3 3
4 4 # Version: 9.1 SP3 9.1.3.4
5 5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
6 6 # Date generated: Tue Oct 18 08:21:45 2011
7 7
8 8
9 9 #
10 10 # IO banks setting
11 11 #
12 12
13 13
14 14 #
15 15 # I/O constraints
16 16 #
17 17
18 18 set_io clk100MHz \
19 19 -pinname F7 \
20 20 -fixed yes \
21 21 -DIRECTION Inout
22 22
23 23 set_io clk49_152MHz \
24 24 -pinname K14 \
25 25 -fixed yes \
26 26 -DIRECTION Inout
27 27
28 28 set_io reset \
29 29 -pinname T2 \
30 30 -fixed yes \
31 31 -DIRECTION Inout
32 32 #====================================================================
33 33 # BPs
34 34 #====================================================================
35 35 set_io BP0 \
36 36 -pinname L1 \
37 37 -fixed yes \
38 38 -DIRECTION Inout
39 39
40 40 set_io BP1 \
41 41 -pinname R1 \
42 42 -fixed yes \
43 43 -DIRECTION Inout
44 44
45 45 #====================================================================
46 46 # LEDs
47 47 #====================================================================
48 48
49 49 set_io LED0 \
50 50 -pinname V6 \
51 51 -fixed yes \
52 52 -DIRECTION Inout
53 53
54 54 set_io LED1 \
55 55 -pinname V5 \
56 56 -fixed yes \
57 57 -DIRECTION Inout
58 58
59 59 set_io LED2 \
60 60 -pinname T4 \
61 61 -fixed yes \
62 62 -DIRECTION Inout
63 63
64 64 #====================================================================
65 65 # UARTS
66 66 #====================================================================
67 67
68 68 set_io TXD1 \
69 69 -pinname N17 \
70 70 -fixed yes \
71 71 -DIRECTION Inout
72 72
73 73 set_io RXD1 \
74 74 -pinname N18 \
75 75 -fixed yes \
76 76 -DIRECTION Inout
77 77
78 78 set_io nCTS1 \
79 79 -pinname P18 \
80 80 -fixed yes \
81 81 -DIRECTION Inout
82 82
83 83 set_io nRTS1 \
84 84 -pinname P17 \
85 85 -fixed yes \
86 86 -DIRECTION Inout
87 87
88 88
89 89 set_io TXD2 \
90 90 -pinname P13 \
91 91 -fixed yes \
92 92 -DIRECTION Inout
93 93
94 94 set_io RXD2 \
95 95 -pinname T18 \
96 96 -fixed yes \
97 97 -DIRECTION Inout
98 98
99 99 set_io nCTS2 \
100 100 -pinname V17 \
101 101 -fixed yes \
102 102 -DIRECTION Inout
103 103
104 104 set_io nDTR2 \
105 105 -pinname L15 \
106 106 -fixed yes \
107 107 -DIRECTION Inout
108 108
109 109 set_io nRTS2 \
110 110 -pinname M15 \
111 111 -fixed yes \
112 112 -DIRECTION Inout
113 113
114 114 set_io nDCD2 \
115 115 -pinname N15 \
116 116 -fixed yes \
117 117 -DIRECTION Inout
118 118
119 119
120 120 #====================================================================
121 121 # EXT CONNECTOR
122 122 #====================================================================
123 123
124 124 set_io IO0 \
125 125 -pinname E4 \
126 126 -fixed yes \
127 127 -DIRECTION Inout
128 128
129 129 set_io IO1 \
130 130 -pinname D3 \
131 131 -fixed yes \
132 132 -DIRECTION Inout
133 133
134 134 set_io IO2 \
135 135 -pinname C2 \
136 136 -fixed yes \
137 137 -DIRECTION Inout
138 138
139 139 set_io IO3 \
140 140 -pinname D1 \
141 141 -fixed yes \
142 142 -DIRECTION Inout
143 143
144 144 set_io IO4 \
145 145 -pinname F2 \
146 146 -fixed yes \
147 147 -DIRECTION Inout
148 148
149 149 set_io IO5 \
150 150 -pinname F3 \
151 151 -fixed yes \
152 152 -DIRECTION Inout
153 153
154 154 set_io IO6 \
155 155 -pinname G2 \
156 156 -fixed yes \
157 157 -DIRECTION Inout
158 158
159 159 set_io IO7 \
160 160 -pinname H3 \
161 161 -fixed yes \
162 162 -DIRECTION Inout
163 163
164 164 set_io IO8 \
165 165 -pinname H4 \
166 166 -fixed yes \
167 167 -DIRECTION Inout
168 168
169 169 set_io IO9 \
170 170 -pinname J2 \
171 171 -fixed yes \
172 172 -DIRECTION Inout
173 173
174 174 set_io IO10 \
175 175 -pinname P1 \
176 176 -fixed yes \
177 177 -DIRECTION Inout
178 178
179 179 set_io IO11 \
180 180 -pinname N1 \
181 181 -fixed yes \
182 182 -DIRECTION Inout
183 183
184 184 #====================================================================
185 185 # SPACE WIRE
186 186 #====================================================================
187 187
188 188 set_io SPW_EN \
189 189 -pinname R12 \
190 190 -fixed yes \
191 191 -DIRECTION Inout
192 192
193 193 #================================
194 194 # NOMINAL LINK
195 195 #================================
196 196
197 197 set_io SPW_NOM_DIN \
198 198 -pinname R10 \
199 199 -fixed yes \
200 200 -DIRECTION Inout
201 201
202 202 set_io SPW_NOM_SIN \
203 203 -pinname R13 \
204 204 -fixed yes \
205 205 -DIRECTION Inout
206 206
207 207 set_io SPW_NOM_DOUT \
208 208 -pinname T13 \
209 209 -fixed yes \
210 210 -DIRECTION Inout
211 211
212 212 set_io SPW_NOM_SOUT \
213 213 -pinname T10 \
214 214 -fixed yes \
215 215 -DIRECTION Inout
216 216
217 217 #================================
218 218 # REDUNDANT LINK
219 219 #================================
220 220
221 221 set_io SPW_RED_DIN \
222 222 -pinname U18 \
223 223 -fixed yes \
224 224 -DIRECTION Inout
225 225
226 226 set_io SPW_RED_SIN \
227 227 -pinname T12 \
228 228 -fixed yes \
229 229 -DIRECTION Inout
230 230
231 231 set_io SPW_RED_DOUT \
232 232 -pinname U10 \
233 233 -fixed yes \
234 234 -DIRECTION Inout
235 235
236 236 set_io SPW_RED_SOUT \
237 237 -pinname P16 \
238 238 -fixed yes \
239 239 -DIRECTION Inout
240 240
241 241 #====================================================================
242 242 # MINI LFR ADC INPUTS
243 243 #====================================================================
244 244
245 245 set_io ADC_nCS \
246 246 -pinname K1 \
247 247 -fixed yes \
248 248 -DIRECTION Inout
249 249
250 250 set_io ADC_CLK \
251 251 -pinname T1 \
252 252 -fixed yes \
253 253 -DIRECTION Inout
254 254
255 255
256 256 #================================
257 257 # ADC DATA
258 258 #================================
259 259
260 260 set_io ADC_SDO\[0\] \
261 261 -pinname V4 \
262 262 -fixed yes \
263 263 -DIRECTION Inout
264 264
265 265 set_io ADC_SDO\[1\] \
266 266 -pinname V3 \
267 267 -fixed yes \
268 268 -DIRECTION Inout
269 269
270 270 set_io ADC_SDO\[2\] \
271 271 -pinname V2 \
272 272 -fixed yes \
273 273 -DIRECTION Inout
274 274
275 275 set_io ADC_SDO\[3\] \
276 276 -pinname U1 \
277 277 -fixed yes \
278 278 -DIRECTION Inout
279 279
280 280 set_io ADC_SDO\[4\] \
281 281 -pinname J1 \
282 282 -fixed yes \
283 283 -DIRECTION Inout
284 284
285 285 set_io ADC_SDO\[5\] \
286 286 -pinname H1 \
287 287 -fixed yes \
288 288 -DIRECTION Inout
289 289
290 290 set_io ADC_SDO\[6\] \
291 291 -pinname F1 \
292 292 -fixed yes \
293 293 -DIRECTION Inout
294 294
295 295 set_io ADC_SDO\[7\] \
296 296 -pinname E1 \
297 297 -fixed yes \
298 298 -DIRECTION Inout
299 299
300 300
301 301 #====================================================================
302 302 # SRAM
303 303 #====================================================================
304 304
305 305 #================================
306 306 # SRAM CTRL
307 307 #================================
308 308
309 309 set_io SRAM_nWE \
310 310 -pinname C13 \
311 311 -fixed yes \
312 312 -DIRECTION Inout
313 313
314 314 set_io SRAM_CE \
315 315 -pinname J14 \
316 316 -fixed yes \
317 317 -DIRECTION Inout
318 318
319 319 set_io SRAM_nOE \
320 320 -pinname B9 \
321 321 -fixed yes \
322 322 -DIRECTION Inout
323 323
324 324 set_io SRAM_nBE\[0\] \
325 325 -pinname H15 \
326 326 -fixed yes \
327 327 -DIRECTION Inout
328 328
329 329 set_io SRAM_nBE\[1\] \
330 330 -pinname C12 \
331 331 -fixed yes \
332 332 -DIRECTION Inout
333 333
334 334 set_io SRAM_nBE\[2\] \
335 335 -pinname A10 \
336 336 -fixed yes \
337 337 -DIRECTION Inout
338 338
339 339 set_io SRAM_nBE\[3\] \
340 340 -pinname A9 \
341 341 -fixed yes \
342 342 -DIRECTION Inout
343 343
344 344
345 345 #================================
346 346 # SRAM ADDRESS
347 347 #================================
348 348
349 349 set_io SRAM_A\[0\] \
350 350 -pinname C11 \
351 351 -fixed yes \
352 352 -DIRECTION Inout
353 353
354 354 set_io SRAM_A\[1\] \
355 355 -pinname C10 \
356 356 -fixed yes \
357 357 -DIRECTION Inout
358 358
359 359 set_io SRAM_A\[2\] \
360 360 -pinname C9 \
361 361 -fixed yes \
362 362 -DIRECTION Inout
363 363
364 364 set_io SRAM_A\[3\] \
365 365 -pinname C8 \
366 366 -fixed yes \
367 367 -DIRECTION Inout
368 368
369 369 set_io SRAM_A\[4\] \
370 370 -pinname C7 \
371 371 -fixed yes \
372 372 -DIRECTION Inout
373 373
374 374 set_io SRAM_A\[5\] \
375 375 -pinname A5 \
376 376 -fixed yes \
377 377 -DIRECTION Inout
378 378
379 379 set_io SRAM_A\[6\] \
380 380 -pinname A6 \
381 381 -fixed yes \
382 382 -DIRECTION Inout
383 383
384 384 set_io SRAM_A\[7\] \
385 385 -pinname B6 \
386 386 -fixed yes \
387 387 -DIRECTION Inout
388 388
389 389 set_io SRAM_A\[8\] \
390 390 -pinname B7 \
391 391 -fixed yes \
392 392 -DIRECTION Inout
393 393
394 394 set_io SRAM_A\[9\] \
395 395 -pinname A8 \
396 396 -fixed yes \
397 397 -DIRECTION Inout
398 398
399 399 set_io SRAM_A\[10\] \
400 400 -pinname B10 \
401 401 -fixed yes \
402 402 -DIRECTION Inout
403 403
404 404 set_io SRAM_A\[11\] \
405 405 -pinname A11 \
406 406 -fixed yes \
407 407 -DIRECTION Inout
408 408
409 409 set_io SRAM_A\[12\] \
410 410 -pinname B12 \
411 411 -fixed yes \
412 412 -DIRECTION Inout
413 413
414 414 set_io SRAM_A\[13\] \
415 415 -pinname A13 \
416 416 -fixed yes \
417 417 -DIRECTION Inout
418 418
419 419 set_io SRAM_A\[14\] \
420 420 -pinname B13 \
421 421 -fixed yes \
422 422 -DIRECTION Inout
423 423
424 424 set_io SRAM_A\[15\] \
425 425 -pinname C18 \
426 426 -fixed yes \
427 427 -DIRECTION Inout
428 428
429 429 set_io SRAM_A\[16\] \
430 430 -pinname C17 \
431 431 -fixed yes \
432 432 -DIRECTION Inout
433 433
434 434 set_io SRAM_A\[17\] \
435 435 -pinname B18 \
436 436 -fixed yes \
437 437 -DIRECTION Inout
438 438
439 439 set_io SRAM_A\[18\] \
440 440 -pinname C16 \
441 441 -fixed yes \
442 442 -DIRECTION Inout
443 443
444 444 set_io SRAM_A\[19\] \
445 445 -pinname D15 \
446 446 -fixed yes \
447 447 -DIRECTION Inout
448 448
449 449
450 450 #================================
451 451 # SRAM DATA
452 452 #================================
453 453
454 454 set_io SRAM_DQ\[0\] \
455 455 -pinname D16 \
456 456 -fixed yes \
457 457 -DIRECTION Inout
458 458
459 459 set_io SRAM_DQ\[1\] \
460 460 -pinname D18 \
461 461 -fixed yes \
462 462 -DIRECTION Inout
463 463
464 464 set_io SRAM_DQ\[2\] \
465 465 -pinname E15 \
466 466 -fixed yes \
467 467 -DIRECTION Inout
468 468
469 469 set_io SRAM_DQ\[3\] \
470 470 -pinname E18 \
471 471 -fixed yes \
472 472 -DIRECTION Inout
473 473
474 474 set_io SRAM_DQ\[4\] \
475 475 -pinname F15 \
476 476 -fixed yes \
477 477 -DIRECTION Inout
478 478
479 479 set_io SRAM_DQ\[5\] \
480 480 -pinname F18 \
481 481 -fixed yes \
482 482 -DIRECTION Inout
483 483
484 484 set_io SRAM_DQ\[6\] \
485 485 -pinname G15 \
486 486 -fixed yes \
487 487 -DIRECTION Inout
488 488
489 489 set_io SRAM_DQ\[7\] \
490 490 -pinname G17 \
491 491 -fixed yes \
492 492 -DIRECTION Inout
493 493
494 494 set_io SRAM_DQ\[8\] \
495 495 -pinname K15 \
496 496 -fixed yes \
497 497 -DIRECTION Inout
498 498
499 499 set_io SRAM_DQ\[9\] \
500 500 -pinname J18 \
501 501 -fixed yes \
502 502 -DIRECTION Inout
503 503
504 504 set_io SRAM_DQ\[10\] \
505 505 -pinname J15 \
506 506 -fixed yes \
507 507 -DIRECTION Inout
508 508
509 509 set_io SRAM_DQ\[11\] \
510 510 -pinname H18 \
511 511 -fixed yes \
512 512 -DIRECTION Inout
513 513
514 514 set_io SRAM_DQ\[12\] \
515 515 -pinname C3 \
516 516 -fixed yes \
517 517 -DIRECTION Inout
518 518
519 519 set_io SRAM_DQ\[13\] \
520 520 -pinname D4 \
521 521 -fixed yes \
522 522 -DIRECTION Inout
523 523
524 524 set_io SRAM_DQ\[14\] \
525 525 -pinname D5 \
526 526 -fixed yes \
527 527 -DIRECTION Inout
528 528
529 529 set_io SRAM_DQ\[15\] \
530 530 -pinname C6 \
531 531 -fixed yes \
532 532 -DIRECTION Inout
533 533
534 534 set_io SRAM_DQ\[16\] \
535 535 -pinname D14 \
536 536 -fixed yes \
537 537 -DIRECTION Inout
538 538
539 539 set_io SRAM_DQ\[17\] \
540 540 -pinname A15 \
541 541 -fixed yes \
542 542 -DIRECTION Inout
543 543
544 544 set_io SRAM_DQ\[18\] \
545 545 -pinname C15 \
546 546 -fixed yes \
547 547 -DIRECTION Inout
548 548
549 549 set_io SRAM_DQ\[19\] \
550 550 -pinname B17 \
551 551 -fixed yes \
552 552 -DIRECTION Inout
553 553
554 554 set_io SRAM_DQ\[20\] \
555 555 -pinname A17 \
556 556 -fixed yes \
557 557 -DIRECTION Inout
558 558
559 559 set_io SRAM_DQ\[21\] \
560 560 -pinname B16 \
561 561 -fixed yes \
562 562 -DIRECTION Inout
563 563
564 564 set_io SRAM_DQ\[22\] \
565 565 -pinname A16 \
566 566 -fixed yes \
567 567 -DIRECTION Inout
568 568
569 569 set_io SRAM_DQ\[23\] \
570 570 -pinname A14 \
571 571 -fixed yes \
572 572 -DIRECTION Inout
573 573
574 574 set_io SRAM_DQ\[24\] \
575 575 -pinname A4 \
576 576 -fixed yes \
577 577 -DIRECTION Inout
578 578
579 579 set_io SRAM_DQ\[25\] \
580 580 -pinname A3 \
581 581 -fixed yes \
582 582 -DIRECTION Inout
583 583
584 584 set_io SRAM_DQ\[26\] \
585 585 -pinname A2 \
586 586 -fixed yes \
587 587 -DIRECTION Inout
588 588
589 589 set_io SRAM_DQ\[27\] \
590 590 -pinname B1 \
591 591 -fixed yes \
592 592 -DIRECTION Inout
593 593
594 594 set_io SRAM_DQ\[28\] \
595 595 -pinname C1 \
596 596 -fixed yes \
597 597 -DIRECTION Inout
598 598
599 599 set_io SRAM_DQ\[29\] \
600 600 -pinname B2 \
601 601 -fixed yes \
602 602 -DIRECTION Inout
603 603
604 604 set_io SRAM_DQ\[30\] \
605 605 -pinname B3 \
606 606 -fixed yes \
607 607 -DIRECTION Inout
608 608
609 609 set_io SRAM_DQ\[31\] \
610 610 -pinname C4 \
611 611 -fixed yes \
612 612 -DIRECTION Inout
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