# HG changeset patch # User pellion # Date 2015-10-26 15:27:28 # Node ID 905b2664a7452390efda9ff74bc4a7b1485ba73c # Parent 0d81a266b9833577dbe7e6c5889542df03d8ddc5 Update MINI LFR constraint's files diff --git a/boards/MINI-LFR/MINI-LFR.sdc b/boards/MINI-LFR/MINI-LFR.sdc --- a/boards/MINI-LFR/MINI-LFR.sdc +++ b/boards/MINI-LFR/MINI-LFR.sdc @@ -76,9 +76,9 @@ address[11] SRAM_A[12] SRAM_A[13] SRAM_A address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \ address[7] SRAM_A[8] SRAM_A[9] }] -set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }] -set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }] -set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }] +set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }] +set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }] +set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }] ######## Delay Constraints ######## diff --git a/boards/MINI-LFR/default.pdc b/boards/MINI-LFR/default.pdc --- a/boards/MINI-LFR/default.pdc +++ b/boards/MINI-LFR/default.pdc @@ -1,4 +1,4 @@ -# Actel Physical design constraints file +# Actel Physical design constraints file # Generated file # Version: 9.1 SP3 9.1.3.4