HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r377:8f748b61300a

(LFR-EM) WFP_MS-1-1-16

pellion -

r377:8f748b61300a (LFR-EM) WFP_MS_1-1-16 JC

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r377:8f748b61300a

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designs/LFR-em-WFP_MS/LFR-em.vhd +2 -2

             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
-              lpp_lfr_1 : lpp_lfr_WFP_nMS
+              lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"00010B")  -- aa.bb.cc version
+                  top_lfr_version        => X"010110")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         -- 0 => MINI_LFR
                                                         -- 1 => EM

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"00010F")  -- aa.bb.cc version
+                  top_lfr_version        => X"000110")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => reset,

designs/Validation_LFR_SpectralMatrix/TB.vhd +50 -2

               SIGNAL error_input_fifo_write    :  STD_LOGIC_VECTOR(2 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL apbi :  apb_slv_in_type;
+              SIGNAL apbo :  apb_slv_out_type;
               SIGNAL status_full     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
+              --
+              SIGNAL ready_reg  : STD_LOGIC_VECTOR(5 DOWNTO 0);
+              SIGNAL irq_ongoing  : STD_LOGIC;
+              --
+              SIGNAL read_status : STD_LOGIC;
+              SIGNAL read_status_t : STD_LOGIC;
+              SIGNAL  observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
+              SIGNAL  observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
             BEGIN  -- beh
                   error_input_fifo_write                 => error_input_fifo_write,
                   debug_reg                              => debug_reg,
+                  --
+                  observation_vector_0 => observation_vector_0,
+                  observation_vector_1 => observation_vector_1,
+                  --
                   status_ready_matrix_f0               => status_ready_matrix_f0,
             --      status_ready_matrix_f0               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
-              apbi.psel(4) <= '0';
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   HCLK    => clk25MHz,
                   HRESETn => rstn,
                   apbi    => apbi,
-                  apbo    => OPEN,
+                  apbo    => apbo,
                   run_ms => OPEN,
+              read_status_t <= TRANSPORT apbo.pirq(0) AFTER 200 us;
+              PROCESS (clk25MHz, rstn)
+              BEGIN
+                IF rstn = '0' THEN
+                  ready_reg                 <= (OTHERS => '0');
+                  --read_status <= '0';
+                  apbi.psel(4)              <= '0';
+                  apbi.pwrite               <= '0';
+                  apbi.penable              <= '0';
+                  apbi.paddr(7 DOWNTO 2)    <= (OTHERS => '0');
+                ELSIF clk25MHz'event AND clk25MHz = '1' THEN
+                  apbi.psel(4)              <= '1';
+                  apbi.paddr(7 DOWNTO 2)    <= "000001";
+                  apbi.penable              <= '1';
+                  read_status <= apbo.pirq(0);
+                  IF read_status = '1' AND irq_ongoing = '0' THEN
+                    ready_reg   <= apbo.prdata(5 DOWNTO 0);
+                    irq_ongoing <= '1';
+                  END IF;
+                  IF read_status_t = '0' THEN
+                    apbi.pwrite <= '0';
+                  ELSE
+                    irq_ongoing <= '0';
+                    apbi.pwrite <= '1';
+                    apbi.pwdata(31 DOWNTO 6) <= (OTHERS => '0');
+                    apbi.pwdata(5 DOWNTO 0) <= ready_reg;
+                    ready_reg                <= (OTHERS => '0');
+                  END IF;
+                END IF;
+              END PROCESS;

designs/Validation_LFR_SpectralMatrix/wave.do +20 -2

             onerror {resume}
             quietly WaveActivateNextPane {} 0
+            add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
+            add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
+            add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
+            add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
+            add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
+            add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
+            add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
+            add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
+            add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
+            add wave -noupdate -expand -group debug -expand /tb/lpp_lfr_ms_1/debug_reg
+            add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
+            add wave -noupdate -expand -group debug -subitemconfig {/tb/lpp_lfr_apbreg_1/apbo.pirq {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/apbo
+            add wave -noupdate -expand -group debug /tb/ready_reg
+            add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
+            add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
+            add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
+            add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
+            add wave -noupdate -divider {New Divider}
             add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
             add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
             add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
             add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
             add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
             TreeUpdate [SetDefaultTree]
-            WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {30152624373 ps} 0} {{Cursor 3} {10666401890 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {87243365384 ps} 0}
+            WaveRestoreCursors {{Cursor 1} {123239471127 ps} 0}
             configure wave -namecolwidth 486
             configure wave -valuecolwidth 112
             configure wave -justifyvalue left
             configure wave -timeline 0
             configure wave -timelineunits ps
             update
-            WaveRestoreZoom {0 ps} {105000147 ns}
+            WaveRestoreZoom {124629370639 ps} {125891337681 ps}
             bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
             bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +20 -7

                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
+                --
+                observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+                observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 --debug
               SIGNAL error_input_fifo_write    :  STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
+              SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
                   addr_data_f1      => addr_data_f1,
                   addr_data_f2      => addr_data_f2,
                   addr_data_f3      => addr_data_f3,
-                  start_date        => start_date);
+                  start_date        => start_date,
+                  debug_signal      => debug_signal);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
                   error_input_fifo_write                 => error_input_fifo_write,
                   debug_reg                              => debug_ms,--observation_reg,
+                observation_vector_0 => observation_vector_0,
+                observation_vector_1 => observation_vector_1,
                   status_ready_matrix_f0                 => status_ready_matrix_f0,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   matrix_time_f2                         => matrix_time_f2);
               -----------------------------------------------------------------------------
-              observation_reg(31 DOWNTO 0) <= debug_ms(31-9 DOWNTO 0) &
-                                              dma_ms_ongoing &      -- 8
-                                              data_ms_done &        -- 7
+              observation_reg(31 DOWNTO 0) <=
-                                              dma_done &            -- 6
+                dma_sel(4) & -- 31
-                                              dma_sel &             -- 5 .. 1
+                dma_ms_ongoing &            -- 30
-                                              ms_softandhard_rstn;  -- 0
+                data_ms_done &              -- 29
+                dma_done &                  -- 28
+                ms_softandhard_rstn  &      --27
+                debug_ms(14 DOWNTO 12) &    -- 26 .. 24
+                debug_ms(11 DOWNTO 0) &     -- 23 .. 12
+                debug_signal(11 DOWNTO 0);  -- 11 .. 0
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +39 -17

                 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-                start_date   : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
+                start_date   : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
+                ---------------------------------------------------------------------------
+                debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 ---------------------------------------------------------------------------
                 );
               SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
               SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+              SIGNAL apbo_irq_ms : STD_LOGIC;
+              SIGNAL apbo_irq_wfp : STD_LOGIC;
             BEGIN  -- beh
                   prdata <= (OTHERS => '0');
-                  apbo.pirq <= (OTHERS => '0');
+                  apbo_irq_ms <= '0';
+                  apbo_irq_wfp <= '0';
                   status_full_ack <= (OTHERS => '0');
                         WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
                                          reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
                                          reg_sp.config_ms_run                      <= apbi.pwdata(2);
-                        WHEN "000001" => reg_sp.status_ready_matrix_f0_0               <= apbi.pwdata(0);
-                                         reg_sp.status_ready_matrix_f0_1               <= apbi.pwdata(1);
+                        WHEN "000001" =>
-                                         reg_sp.status_ready_matrix_f1_0               <= apbi.pwdata(2);
+                          reg_sp.status_ready_matrix_f0_0         <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0        ) OR reg0_ready_matrix_f0;
-                                         reg_sp.status_ready_matrix_f1_1               <= apbi.pwdata(3);
+                          reg_sp.status_ready_matrix_f0_1         <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1        ) OR reg1_ready_matrix_f0;
-                                         reg_sp.status_ready_matrix_f2_0               <= apbi.pwdata(4);
+                          reg_sp.status_ready_matrix_f1_0         <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0        ) OR reg0_ready_matrix_f1;
-                                         reg_sp.status_ready_matrix_f2_1           <= apbi.pwdata(5);
+                          reg_sp.status_ready_matrix_f1_1         <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1        ) OR reg1_ready_matrix_f1;
-                                         reg_sp.status_error_bad_component_error   <= apbi.pwdata(6);
+                          reg_sp.status_ready_matrix_f2_0         <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0        ) OR reg0_ready_matrix_f2;
-                                         reg_sp.status_error_buffer_full           <= apbi.pwdata(7);
+                          reg_sp.status_ready_matrix_f2_1         <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1        ) OR reg1_ready_matrix_f2;
-                                         reg_sp.status_error_input_fifo_write(0)   <= apbi.pwdata(8);
+                          reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
-                                         reg_sp.status_error_input_fifo_write(1)   <= apbi.pwdata(9);
+                          reg_sp.status_error_buffer_full         <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full        ) OR error_buffer_full;
-                                         reg_sp.status_error_input_fifo_write(2)   <= apbi.pwdata(10);
+                          reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
+                          reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
+                          reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
                           --2
                         WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
                         WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
                       END CASE;
                     END IF;
                   END IF;
+                  --apbo.pirq(pirq_ms) <=
-                  apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
+                  apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
                                                                                              ready_matrix_f1 OR
                                                                                              ready_matrix_f2)
                                           )
                                            OR error_input_fifo_write(1)
                                            OR error_input_fifo_write(2))
                                           ));
+                  -- apbo.pirq(pirq_wfp)
-                  apbo.pirq(pirq_wfp) <= ored_irq_wfp;
+                  apbo_irq_wfp<= ored_irq_wfp;
                 END IF;
               END PROCESS lpp_lfr_apbreg;
+              apbo.pirq(pirq_ms)  <= apbo_irq_ms;
+              apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
               apbo.pindex  <= pindex;
               apbo.pconfig <= pconfig;
               apbo.prdata  <= prdata;
                   addr_matrix         => addr_matrix_f2,
                   matrix_time         => matrix_time_f2);
+              -----------------------------------------------------------------------------
+              debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
+              debug_signal(11 DOWNTO  0) <= apbo_irq_ms &  --11
+                                           reg_sp.status_error_input_fifo_write(2) &--10
+                                           reg_sp.status_error_input_fifo_write(1) &--9
+                                           reg_sp.status_error_input_fifo_write(0) &--8
+                                           reg_sp.status_error_buffer_full         & reg_sp.status_error_bad_component_error & --7 6
+                                           reg_sp.status_ready_matrix_f2_1         & reg_sp.status_ready_matrix_f2_0 &--5 4
+                                           reg_sp.status_ready_matrix_f1_1         & reg_sp.status_ready_matrix_f1_0 &--3 2
+                                           reg_sp.status_ready_matrix_f0_1         & reg_sp.status_ready_matrix_f0_0; --1 0
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +13 0

                 error_input_fifo_write    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                --
+                observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+                observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 -- Reg In
                 status_ready_matrix_f0 : IN STD_LOGIC;
                   fft_data_valid => fft_data_valid,
                   fft_ready      => fft_ready);
+              observation_vector_0(5 DOWNTO 0) <= fft_ready &                         --5
+                                                  fft_data_valid &                    --4
+                                                  fft_pong &                          --3
+                                                  sample_load &                       --2
+                                                  fft_read &                          --1
+                                                  sample_valid;                       --0
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re);
+              -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               Mem_In_SpectralMatrix : lppFIFOxN

lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd +1 0

                     WHEN TRASH_FIFO =>
                       debug_reg_s(2 DOWNTO 0) <= "100";
+                      error_buffer_full             <= '0';
                       error_bad_component_error     <= '0';
                       IF fifo_empty = '1' THEN
                         state          <= IDLE;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +11 -1

                   error_buffer_full                      : OUT STD_LOGIC;
                   error_input_fifo_write                 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+                  --
+                  observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+                  observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+                  -------------------------------------------------------------------------
                   status_ready_matrix_f0               : IN  STD_LOGIC;
             --      status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
+                  --
+                  observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+                  observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                   observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;
                   addr_data_f1                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-                  start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
+                  start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
+                  debug_signal                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;

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