HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r465:8e656681264f

Correction du bugs (a confirmer) :...

pellion -

r465:8e656681264f (MINI-LFR) WFP_MS-0-1-35 JC

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r465:8e656681264f

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +80 -64

                SIGNAL rstn_50_d1 : STD_LOGIC;
                SIGNAL rstn_50_d2 : STD_LOGIC;
                SIGNAL rstn_50_d3 : STD_LOGIC;
+               SIGNAL lfr_debug_vector    : STD_LOGIC_VECTOR(11 DOWNTO 0);
+               SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
              BEGIN  -- beh
                -----------------------------------------------------------------------------
                    rstn_50_d2 <= '0';
                    rstn_50_d3 <= '0';
-                 ELSIF clk_50'event AND clk_50 = '1' THEN  -- rising clock edge
+                 ELSIF clk_50'EVENT AND clk_50 = '1' THEN  -- rising clock edge
                    clk_50_s  <= NOT clk_50_s;
                    rstn_50_d1 <= '1';
                    rstn_50_d2 <= rstn_50_d1;
                    rstn_25_d1 <= '0';
                    rstn_25_d2 <= '0';
                    rstn_25_d3 <= '0';
-                 ELSIF clk_50_s'event AND clk_50_s = '1' THEN  -- rising clock edge
+                 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN  -- rising clock edge
                    clk_25     <= NOT clk_25;
                    rstn_25_d1 <= '1';
                    rstn_25_d2 <= rstn_25_d1;
                BEGIN  -- PROCESS
                  IF reset = '0' THEN                 -- asynchronous reset (active low)
                    clk_24 <= '0';
-                 ELSIF clk_49'event AND clk_49 = '1' THEN  -- rising clock edge
+                 ELSIF clk_49'EVENT AND clk_49 = '1' THEN  -- rising clock edge
-                   clk_24 <= NOT clk_24;
                  END IF;
                END PROCESS;
                      dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
                END GENERATE spw_inputloop;
-               swni.rmapnodeaddr <= (others => '0');
+               swni.rmapnodeaddr <= (OTHERS => '0');
                -- SPW core
                sw0 : grspwm GENERIC MAP(
              -------------------------------------------------------------------------------
-               --LFR_rstn <= LFR_soft_rstn AND rstn_25;
-               LFR_rstn <= rstn_25;
+               LFR_rstn <= LFR_soft_rstn AND rstn_25;
+               --LFR_rstn <= rstn_25;
                lpp_lfr_1 : lpp_lfr
                  GENERIC MAP (
                    pirq_ms                => 6,
                    pirq_wfp               => 14,
                    hindex                 => 2,
-                   top_lfr_version        => X"000122")  -- aa.bb.cc version
+                   top_lfr_version        => X"000123")  -- aa.bb.cc version
                  PORT MAP (
                    clk             => clk_25,
                    rstn            => LFR_rstn,
                    ahbo            => ahbo_m_ext(2),
                    coarse_time     => coarse_time,
                    fine_time       => fine_time,
-                   data_shaping_BW => bias_fail_sw_sig);
+                   data_shaping_BW => bias_fail_sw_sig,
+                   debug_vector    => lfr_debug_vector,
+                   debug_vector_ms => lfr_debug_vector_ms
+                   );
-               observation_reg      <= (others => '0');
-               observation_vector_0 <= (others => '0');
-               observation_vector_1 <= (others => '0');
+               observation_reg(11 DOWNTO 0)      <= lfr_debug_vector;
+               observation_reg(31 DOWNTO 12)     <= (OTHERS => '0');
+               observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
+               observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
+               IO0                               <= rstn_25;
+               IO1                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT data_valid
+               IO2                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT ready
+               IO3                               <= lfr_debug_vector(0);  -- LFR APBREG error_buffer_full
+               IO4                               <= lfr_debug_vector(1);  -- LFR APBREG reg_sp.status_error_buffer_full
+               IO5                               <= lfr_debug_vector(8);  -- LFR APBREG  ready_matrix_f2
+               IO6                               <= lfr_debug_vector(9);  -- LFR APBREG reg0_ready_matrix_f2
+               IO7                               <= lfr_debug_vector(10);  -- LFR APBREG reg0_ready_matrix_f2
                all_sample: FOR I IN 7 DOWNTO 0 GENERATE
                  sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
                  GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                  PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
-               gpioi.sig_en <= (others => '0');
-               gpioi.sig_in <= (others => '0');
-               gpioi.din    <= (others => '0');
+               gpioi.sig_en <= (OTHERS => '0');
+               gpioi.sig_in <= (OTHERS => '0');
+               gpioi.din    <= (OTHERS => '0');
                --pio_pad_0 : iopad
                --  GENERIC MAP (tech => CFG_PADTECH)
                --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
                PROCESS (clk_25, rstn_25)
                BEGIN  -- PROCESS
-                 IF rstn_25 = '0' THEN                  -- asynchronous reset (active low)
-                   IO0  <= '0';
-                   IO1  <= '0';
-                   IO2  <= '0';
-                   IO3  <= '0';
-                   IO4  <= '0';
-                   IO5  <= '0';
-                   IO6  <= '0';
-                   IO7  <= '0';
+                   --    --IO0  <= '0';
+                   --    IO1  <= '0';
+                   --    IO2  <= '0';
+                   --    IO3  <= '0';
+                   --    IO4  <= '0';
+                   --    IO5  <= '0';
+                   --    IO6  <= '0';
+                   --    IO7  <= '0';
                    IO8  <= '0';
                    IO9  <= '0';
                    IO10 <= '0';
                    IO11 <= '0';
-                 ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
+                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                    CASE gpioo.dout(2 DOWNTO 0) IS
-                     WHEN "011" =>
-                       IO0  <= observation_reg(0 );
-                       IO1  <= observation_reg(1 );
-                       IO2  <= observation_reg(2 );
-                       IO3  <= observation_reg(3 );
-                       IO4  <= observation_reg(4 );
-                       IO5  <= observation_reg(5 );
-                       IO6  <= observation_reg(6 );
-                       IO7  <= observation_reg(7 );
+                       --        --IO0  <= observation_reg(0 );
+                       --        IO1  <= observation_reg(1 );
+                       --        IO2  <= observation_reg(2 );
+                       --        IO3  <= observation_reg(3 );
+                       --        IO4  <= observation_reg(4 );
+                       --        IO5  <= observation_reg(5 );
+                       --        IO6  <= observation_reg(6 );
+                       --        IO7  <= observation_reg(7 );
-                       IO8  <= observation_reg(8 );
-                       IO9  <= observation_reg(9 );
                        IO10 <= observation_reg(10);
                        IO11 <= observation_reg(11);
-                     WHEN "001" =>
-                       IO0  <= observation_reg(0  + 12);
-                       IO1  <= observation_reg(1  + 12);
-                       IO2  <= observation_reg(2  + 12);
-                       IO3  <= observation_reg(3  + 12);
-                       IO4  <= observation_reg(4  + 12);
-                       IO5  <= observation_reg(5  + 12);
-                       IO6  <= observation_reg(6  + 12);
-                       IO7  <= observation_reg(7  + 12);
+                       --        --IO0  <= observation_reg(0  + 12);
+                       --        IO1  <= observation_reg(1  + 12);
+                       --        IO2  <= observation_reg(2  + 12);
+                       --        IO3  <= observation_reg(3  + 12);
+                       --        IO4  <= observation_reg(4  + 12);
+                       --        IO5  <= observation_reg(5  + 12);
+                       --        IO6  <= observation_reg(6  + 12);
+                       --        IO7  <= observation_reg(7  + 12);
-                       IO8  <= observation_reg(8  + 12);
-                       IO9  <= observation_reg(9  + 12);
                        IO10 <= observation_reg(10 + 12);
                        IO11 <= observation_reg(11 + 12);
-                     WHEN "010" =>
-                       IO0  <= observation_reg(0  + 12 + 12);
-                       IO1  <= observation_reg(1  + 12 + 12);
-                       IO2  <= observation_reg(2  + 12 + 12);
-                       IO3  <= observation_reg(3  + 12 + 12);
-                       IO4  <= observation_reg(4  + 12 + 12);
-                       IO5  <= observation_reg(5  + 12 + 12);
-                       IO6  <= observation_reg(6  + 12 + 12);
-                       IO7  <= observation_reg(7  + 12 + 12);
+                       --        --IO0  <= observation_reg(0  + 12 + 12);
+                       --        IO1  <= observation_reg(1  + 12 + 12);
+                       --        IO2  <= observation_reg(2  + 12 + 12);
+                       --        IO3  <= observation_reg(3  + 12 + 12);
+                       --        IO4  <= observation_reg(4  + 12 + 12);
+                       --        IO5  <= observation_reg(5  + 12 + 12);
+                       --        IO6  <= observation_reg(6  + 12 + 12);
+                       --        IO7  <= observation_reg(7  + 12 + 12);
                        IO8  <= '0';
                        IO9  <= '0';
                        IO10 <= '0';
                        IO11 <= '0';
-                     WHEN "000" =>
-                       IO0  <= observation_vector_0(0 );
-                       IO1  <= observation_vector_0(1 );
-                       IO2  <= observation_vector_0(2 );
-                       IO3  <= observation_vector_0(3 );
-                       IO4  <= observation_vector_0(4 );
-                       IO5  <= observation_vector_0(5 );
-                       IO6  <= observation_vector_0(6 );
-                       IO7  <= observation_vector_0(7 );
+                       --        --IO0  <= observation_vector_0(0 );
+                       --        IO1  <= observation_vector_0(1 );
+                       --        IO2  <= observation_vector_0(2 );
+                       --        IO3  <= observation_vector_0(3 );
+                       --        IO4  <= observation_vector_0(4 );
+                       --        IO5  <= observation_vector_0(5 );
+                       --        IO6  <= observation_vector_0(6 );
+                       --        IO7  <= observation_vector_0(7 );
-                       IO8  <= observation_vector_0(8 );
-                       IO9  <= observation_vector_0(9 );
                        IO10 <= observation_vector_0(10);
                        IO11 <= observation_vector_0(11);
-                     WHEN "100" =>
-                       IO0  <= observation_vector_1(0 );
-                       IO1  <= observation_vector_1(1 );
-                       IO2  <= observation_vector_1(2 );
-                       IO3  <= observation_vector_1(3 );
-                       IO4  <= observation_vector_1(4 );
-                       IO5  <= observation_vector_1(5 );
-                       IO6  <= observation_vector_1(6 );
-                       IO7  <= observation_vector_1(7 );
+                       --        --IO0  <= observation_vector_1(0 );
+                       --        IO1  <= observation_vector_1(1 );
+                       --        IO2  <= observation_vector_1(2 );
+                       --        IO3  <= observation_vector_1(3 );
+                       --        IO4  <= observation_vector_1(4 );
+                       --        IO5  <= observation_vector_1(5 );
+                       --        IO6  <= observation_vector_1(6 );
+                       --        IO7  <= observation_vector_1(7 );
-                       IO8  <= observation_vector_1(8 );
-                       IO9  <= observation_vector_1(9 );
                        IO10 <= observation_vector_1(10);
                  END GENERATE ahbo_m_ext_not_used;
                END GENERATE all_ahbo_m_ext;
-             END beh;
  No newline at end of file
+             END beh;

designs/MINI-LFR_WFP_MS/testbench.vhd +12 -14

              USE lpp.lpp_lfr_apbreg_pkg.ALL;
              USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
-             LIBRARY postlayout;
-             USE postlayout.ALL;
              ENTITY testbench IS
              END;
                ADC_SDO      <= x"AA";
                SRAM_DQ      <= (OTHERS => 'Z');
-               IO0          <= 'Z';
-               IO1          <= 'Z';
-               IO2          <= 'Z';
-               IO3          <= 'Z';
-               IO4          <= 'Z';
-               IO5          <= 'Z';
-               IO6          <= 'Z';
-               IO7          <= 'Z';
-               IO8          <= 'Z';
-               IO9          <= 'Z';
-               IO10         <= 'Z';
-               IO11         <= 'Z';
+               --IO0          <= 'Z';
+               --IO1          <= 'Z';
+               --IO2          <= 'Z';
+               --IO3          <= 'Z';
+               --IO4          <= 'Z';
+               --IO5          <= 'Z';
+               --IO6          <= 'Z';
+               --IO7          <= 'Z';
+               --IO8          <= 'Z';
+               --IO9          <= 'Z';
+               --IO10         <= 'Z';
+               --IO11         <= 'Z';
                -----------------------------------------------------------------------------
                -- DUT

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +13 -3

                  coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                  fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                  --
-                 data_shaping_BW : OUT STD_LOGIC
+                 data_shaping_BW : OUT STD_LOGIC;
+                 --
+                 debug_vector    : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+                 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
-                 );
              END lpp_lfr;
                SIGNAL dma_buffer_full_err  : STD_LOGIC_VECTOR(4 DOWNTO 0);
                SIGNAL dma_grant_error      : STD_LOGIC;
+               SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
                -----------------------------------------------------------------------------
              --  SIGNAL run_dma : STD_LOGIC;
              BEGIN
+               debug_vector <= apb_reg_debug_vector;
+               -----------------------------------------------------------------------------
                sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
                sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
                    wfp_ready_buffer        => wfp_ready_buffer,-- TODO
                    wfp_buffer_time         => wfp_buffer_time,-- TODO
-                   wfp_error_buffer_full   => wfp_error_buffer_full -- TODO
+                   wfp_error_buffer_full   => wfp_error_buffer_full, -- TODO
+                   debug_vector => apb_reg_debug_vector
                    );
                -----------------------------------------------------------------------------
                    matrix_time_f0 => matrix_time_f0,
                    matrix_time_f1 => matrix_time_f1,
-                   matrix_time_f2 => matrix_time_f2);
+                   matrix_time_f2 => matrix_time_f2,
+                   debug_vector   => debug_vector_ms);
                -----------------------------------------------------------------------------
                --run_dma <= run_ms OR run;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +13 -2

                  wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                  wfp_ready_buffer        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                  wfp_buffer_time         : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
-                 wfp_error_buffer_full   : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
+                 wfp_error_buffer_full   : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+                 ---------------------------------------------------------------------------
+                 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                  );
              BEGIN  -- beh
+               debug_vector(0)          <= error_buffer_full;
+               debug_vector(1)          <= reg_sp.status_error_buffer_full;
+               debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
+               debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
+               debug_vector(8)          <= ready_matrix_f2;
+               debug_vector(9)          <= reg0_ready_matrix_f2;
+               debug_vector(10)         <= reg1_ready_matrix_f2;
+               debug_vector(11)         <= HRESETn;
              --  status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
              --  status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
              --  status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
              END beh;
-             -------------------------------------------------------------------------------
  No newline at end of file
+             ------------------------------------------------------------------------------

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +9 -3

                  matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                  matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
-                 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)  -- TODO
+                 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);  -- TODO
+                 ---------------------------------------------------------------------------
+                 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                  );
              END;
                    ReUse => (OTHERS => '0'),
                    run   => (OTHERS => '1'),
-                   wen         => sample_f2_wen,
+                   wen         => sample_f2_wen_s,
                    wdata       => sample_f2_wdata,
                    ren         => sample_f2_ren,
                    rdata       => sample_f2_rdata,
                    fft_data_valid => fft_data_valid,
                    fft_ready      => fft_ready);
+               debug_vector(0) <= fft_data_valid;
+               debug_vector(1) <= fft_ready;
+               debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
-               -----------------------------------------------------------------------------
                fft_ready_rising_down   <= fft_ready_reg AND NOT fft_ready;
                sample_load_rising_down <= sample_load_reg AND NOT sample_load;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +7 -3

                    length_matrix_f2       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                    matrix_time_f0         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                    matrix_time_f1         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
-                   matrix_time_f2         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
+                   matrix_time_f2         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+                   debug_vector           : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
                END COMPONENT;
                COMPONENT lpp_lfr_ms_fsmdma
                    ahbo            : OUT AHB_Mst_Out_Type;
                    coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                    fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
-                   data_shaping_BW : OUT STD_LOGIC
+                   data_shaping_BW : OUT STD_LOGIC ;
+                   debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+                   debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                    );
                END COMPONENT;
                    wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                    wfp_ready_buffer        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                    wfp_buffer_time         : IN  STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
-                   wfp_error_buffer_full   : IN  STD_LOGIC_VECTOR(3 DOWNTO 0));
+                   wfp_error_buffer_full   : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+                   debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
                END COMPONENT;
                COMPONENT lpp_top_ms

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